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Audio Player Verilog

This document describes a module that interfaces with various I/O components on the DE2-115 board including SDRAM, flash memory, Ethernet, USB, audio, and video ports. It instantiates a DE2_115_SOPC module which handles the core functionality and connections between the I/O ports and underlying system on a chip. The module allows some I/O ports to be reconfigured through GPIO and HSMC pins controlled by keyboard inputs.

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lizhi0007
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646 views12 pages

Audio Player Verilog

This document describes a module that interfaces with various I/O components on the DE2-115 board including SDRAM, flash memory, Ethernet, USB, audio, and video ports. It instantiates a DE2_115_SOPC module which handles the core functionality and connections between the I/O ports and underlying system on a chip. The module allows some I/O ports to be reconfigured through GPIO and HSMC pins controlled by keyboard inputs.

Uploaded by

lizhi0007
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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module DE2_115_SD_Card_Audio_Player(

//////// CLOCK //////////


CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
//////// Sma //////////
SMA_CLKIN,
SMA_CLKOUT,
//////// LED //////////
LEDG,
LEDR,
//////// KEY //////////
KEY,
//////// SW //////////
SW,
//////// SEG7 //////////
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
//////// LCD //////////
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
//////// RS232 //////////
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
//////// PS2 //////////
PS2_CLK,

PS2_DAT,
PS2_CLK2,
PS2_DAT2,
//////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
//////// VGA //////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
//////// Audio //////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
//////// I2C for EEPROM //////////
EEP_I2C_SCLK,
EEP_I2C_SDAT,
//////// I2C for Audio and Tv-Decode //////////
I2C_SCLK,
I2C_SDAT,
//////// Ethernet 0 //////////
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,

ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
//////// Ethernet 1 //////////
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
//////// TV Decoder //////////
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
/////// USB OTG controller
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
OTG_DREQ,
OTG_DACK_N,
OTG_FSPEED,
OTG_LSPEED,
//////// IR Receiver //////////
IRDA_RXD,
//////// SDRAM //////////
DRAM_ADDR,

DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////// SRAM //////////
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
//////// Flash //////////
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
//////// GPIO //////////
GPIO,
//////// HSMC (LVDS) //////////
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
HSMC_RX_D_P,
HSMC_TX_D_P,
//////// EXTEND IO //////////
EX_IO
);
//=======================================================
// PARAMETER declarations

//=======================================================

//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input
input
input
input

CLOCK_50;
CLOCK2_50;
CLOCK3_50;
ENETCLK_25;

//////////// Sma //////////


input
output

SMA_CLKIN;
SMA_CLKOUT;

//////////// LED //////////


output
[8:0]
output
[17:0]
//////////// KEY //////////
input
[3:0]

LEDG;
LEDR;

KEY;

//////////// SW //////////
input
[17:0]

SW;

//////////// SEG7 //////////


output
[6:0]
output
[6:0]
output
[6:0]
output
[6:0]
output
[6:0]
output
[6:0]
output
[6:0]
output
[6:0]

HEX0;
HEX1;
HEX2;
HEX3;
HEX4;
HEX5;
HEX6;
HEX7;

//////////// LCD //////////


output
inout
[7:0]
output
output
output
output

LCD_BLON;
LCD_DATA;
LCD_EN;
LCD_ON;
LCD_RS;
LCD_RW;

//////////// RS232 //////////


output
input

UART_CTS;
UART_RTS;

input
output

UART_RXD;
UART_TXD;

//////////// PS2 //////////


inout
inout
inout
inout

PS2_CLK;
PS2_DAT;
PS2_CLK2;
PS2_DAT2;

//////////// SDCARD //////////


output
inout
inout
[3:0]
input

SD_CLK;
SD_CMD;
SD_DAT;
SD_WP_N;

//////////// VGA //////////


output
[7:0]
output
output
output
[7:0]
output
output
[7:0]
output
output

VGA_B;
VGA_BLANK_N;
VGA_CLK;
VGA_G;
VGA_HS;
VGA_R;
VGA_SYNC_N;
VGA_VS;

//////////// Audio //////////


input
inout
inout
output
inout
output

AUD_ADCDAT;
AUD_ADCLRCK;
AUD_BCLK;
AUD_DACDAT;
AUD_DACLRCK;
AUD_XCK;

//////////// I2C for EEPROM //////////


output
EEP_I2C_SCLK;
inout
EEP_I2C_SDAT;
//////////// I2C for Audio and Tv-Decode //////////
output
I2C_SCLK;
inout
I2C_SDAT;
//////////// Ethernet 0 //////////
output
input
output
inout
output
input

ENET0_GTX_CLK;
ENET0_INT_N;
ENET0_MDC;
ENET0_MDIO;
ENET0_RST_N;
ENET0_RX_CLK;

input
input
input
input
input
input
output
output
output
input

[3:0]

[3:0]

ENET0_RX_COL;
ENET0_RX_CRS;
ENET0_RX_DATA;
ENET0_RX_DV;
ENET0_RX_ER;
ENET0_TX_CLK;
ENET0_TX_DATA;
ENET0_TX_EN;
ENET0_TX_ER;
ENET0_LINK100;

//////////// Ethernet 1 //////////


output
input
output
inout
output
input
input
input
input
[3:0]
input
input
input
output
[3:0]
output
output
input

ENET1_GTX_CLK;
ENET1_INT_N;
ENET1_MDC;
ENET1_MDIO;
ENET1_RST_N;
ENET1_RX_CLK;
ENET1_RX_COL;
ENET1_RX_CRS;
ENET1_RX_DATA;
ENET1_RX_DV;
ENET1_RX_ER;
ENET1_TX_CLK;
ENET1_TX_DATA;
ENET1_TX_EN;
ENET1_TX_ER;
ENET1_LINK100;

//////////// TV Decoder 1 //////////


input
input
[7:0]
input
output
input

TD_CLK27;
TD_DATA;
TD_HS;
TD_RESET_N;
TD_VS;

//////////// USB OTG controller //////////


inout
[15:0] OTG_DATA;
output
[1:0] OTG_ADDR;
output
OTG_CS_N;
output
OTG_WR_N;
output
OTG_RD_N;
input
[1:0] OTG_INT;
output
OTG_RST_N;
input
[1:0] OTG_DREQ;
output
[1:0] OTG_DACK_N;
inout
OTG_FSPEED;
inout
OTG_LSPEED;

//////////// IR Receiver //////////


input

IRDA_RXD;

//////////// SDRAM //////////


output
[12:0]
output
[1:0]
output
output
output
output
inout
[31:0]
output
[3:0]
output
output

DRAM_ADDR;
DRAM_BA;
DRAM_CAS_N;
DRAM_CKE;
DRAM_CLK;
DRAM_CS_N;
DRAM_DQ;
DRAM_DQM;
DRAM_RAS_N;
DRAM_WE_N;

//////////// SRAM //////////


output
[19:0]
output
inout
[15:0]
output
output
output
output

SRAM_ADDR;
SRAM_CE_N;
SRAM_DQ;
SRAM_LB_N;
SRAM_OE_N;
SRAM_UB_N;
SRAM_WE_N;

//////////// Flash //////////


output
[22:0]
output
inout
[7:0]
output
output
input
output
output

FL_ADDR;
FL_CE_N;
FL_DQ;
FL_OE_N;
FL_RST_N;
FL_RY;
FL_WE_N;
FL_WP_N;

//////////// GPIO //////////


inout
[35:0]
//////////// HSMC (LVDS) //////////
input
input
input
output
output
output
inout
[3:0]
input
[16:0]
output
[16:0]

GPIO;

HSMC_CLKIN_P1;
HSMC_CLKIN_P2;
HSMC_CLKIN0;
HSMC_CLKOUT_P1;
HSMC_CLKOUT_P2;
HSMC_CLKOUT0;
HSMC_D;
HSMC_RX_D_P;
HSMC_TX_D_P;

//////// EXTEND IO //////////


inout
[6:0]

EX_IO;

//=======================================================
// REG/WIRE declarations
//=======================================================
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
wire HEX6P;
wire HEX7P;

//=======================================================
// Structural coding
//=======================================================
wire reset_n;
assign reset_n = 1'b1;
DE2_115_SOPC DE2_115_SOPC_inst(
// 1) global signals:
.clk_50(CLOCK_50),
.reset_n(reset_n),
.altpll_25(VGA_CLK),
.altpll_io(),
.altpll_sdram(DRAM_CLK),
.altpll_sys(),
// the_audio
.avs_s1_export_ADCDAT_to_the_audio(AUD_ADCDAT),
.avs_s1_export_ADCLRC_to_the_audio(AUD_ADCLRCK),
.avs_s1_export_BCLK_to_the_audio(AUD_BCLK),
.avs_s1_export_DACDAT_from_the_audio(AUD_DACDAT),
.avs_s1_export_DACLRC_to_the_audio(AUD_DACLRCK),
.avs_s1_export_XCK_from_the_audio(AUD_XCK),
// the_eep_i2c_scl
.out_port_from_the_eep_i2c_scl(EEP_I2C_SCLK),
// the_eep_i2c_sda
.bidir_port_to_and_from_the_eep_i2c_sda(EEP_I2C_SDAT),

// the_i2c_scl
.out_port_from_the_i2c_scl(I2C_SCLK),
// the_i2c_sda
.bidir_port_to_and_from_the_i2c_sda(I2C_SDAT),
// the_key
.in_port_to_the_key(KEY),
// the_lcd
.LCD_E_from_the_lcd(LCD_EN),
.LCD_RS_from_the_lcd(LCD_RS),
.LCD_RW_from_the_lcd(LCD_RW),
.LCD_data_to_and_from_the_lcd(LCD_DATA),
// the_ledg
.out_port_from_the_ledg(LEDG),
// the_ledr
.out_port_from_the_ledr(LEDR),
// the_rs232
.cts_n_to_the_rs232(UART_CTS),
.rts_n_from_the_rs232(UART_RTS),
.rxd_to_the_rs232(UART_RXD),
.txd_from_the_rs232(UART_TXD),

// the_seg7
.SEG7_from_the_seg7({
HEX7P, HEX7, HEX6P, HEX6,
HEX5P, HEX5, HEX4P, HEX4,
HEX3P, HEX3, HEX2P, HEX2,
HEX1P, HEX1, HEX0P, HEX0}),
// the_sma_in
.in_port_to_the_sma_in(SMA_CLKIN),
// the_sma_out
.out_port_from_the_sma_out(SMA_CLKOUT),
// the_sw
.in_port_to_the_sw(SW),
// the_tri_state_bridge_flash_avalon_slave
.address_to_the_cfi_flash(FL_ADDR),
.read_n_to_the_cfi_flash(FL_OE_N),
.select_n_to_the_cfi_flash(FL_CE_N),

.tri_state_bridge_flash_data(FL_DQ),
.write_n_to_the_cfi_flash(FL_WE_N),
// sdcard
.out_port_from_the_sd_clk(SD_CLK),
.bidir_port_to_and_from_the_sd_cmd(SD_CMD),
.bidir_port_to_and_from_the_sd_dat(SD_DAT),
.in_port_to_the_sd_wp_n(SD_WP_N),
// the_usb
.USB_INT1_to_the_usb(OTG_INT[1]),
.USB_ADDR_from_the_usb(OTG_ADDR),
.USB_CS_N_from_the_usb(OTG_CS_N),
.USB_DATA_to_and_from_the_usb(OTG_DATA),
.USB_INT0_to_the_usb(OTG_INT[0]),
.USB_RD_N_from_the_usb(OTG_RD_N),
.USB_RST_N_from_the_usb(OTG_RST_N),
.USB_WR_N_from_the_usb(OTG_WR_N),
//IrDA
.ir_to_the_Terasic_IrDA_0(IRDA_RXD)
);

// Flash Config
assign
FL_RST_N = reset_n;
assign
FL_WP_N = 1'b1;
///////////////////////////////////////////
// LCD config
assign LCD_BLON = 0; // not supported
assign LCD_ON = 1'b1; // alwasy on
wire io_dir;
wire action;
assign io_dir = KEY[0] & action;
///////////////////////////////////////////
// GPIO
assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;
///////////////////////////////////////////
// HSMC
assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;

assign HSMC_TX_D_P = HSMC_RX_D_P;


assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;
///////////////////////////////////////////
// NET
assign ENET0_GTX_CLK = ENET0_INT_N;
assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;
assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;
assign ENET1_GTX_CLK = ENET1_INT_N;
assign ENET1_MDC = ENET1_RX_COL;
assign ENET1_RST_N = ENET1_RX_CRS;
assign ENET1_TX_DATA = ENET1_RX_DATA;
assign ENET1_TX_EN = ENET1_RX_ER;
assign ENET1_TX_ER = ENET1_TX_CLK;
///////////////////////////////////////////
// USB OTG
assign OTG_DACK_N = OTG_DREQ;
assign OTG_FSPEED = 1'b1;
assign OTG_LSPEED = 1'b0;
///////////////////////////////////////////
// TV
assign TD_RESET_N = TD_VS;
assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);
///////////////////////////////////////////
// ps2
assign PS2_CLK = PS2_DAT;
assign PS2_CLK2 = PS2_DAT2;
endmodule

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