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Midterm Exam Architecture

The document contains 4 problems related to computer architecture. It provides the questions and answers. Problem 1 asks about the hardware structure used to commit instructions in order in an out-of-order processor, to which the answer is reorder buffer. Problem 2 asks about which data hazards can be overcome by register renaming, and the answer is WAR and WAW hazards. Problem 3 asks about the number of SRAM bits needed for an 8KB, 2-way set associative cache with a 64B block size, and provides the calculation to get the answer of 68,288 bits. Problem 4 asks which of two processors would execute a given instruction mix faster, and shows the calculation that Processor B would be faster.

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Sparśa Roychowdhury
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1K views2 pages

Midterm Exam Architecture

The document contains 4 problems related to computer architecture. It provides the questions and answers. Problem 1 asks about the hardware structure used to commit instructions in order in an out-of-order processor, to which the answer is reorder buffer. Problem 2 asks about which data hazards can be overcome by register renaming, and the answer is WAR and WAW hazards. Problem 3 asks about the number of SRAM bits needed for an 8KB, 2-way set associative cache with a 64B block size, and provides the calculation to get the answer of 68,288 bits. Problem 4 asks which of two processors would execute a given instruction mix faster, and shows the calculation that Processor B would be faster.

Uploaded by

Sparśa Roychowdhury
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Problem 1: What Out-Of-Order processor hardware structure can be used to enforce that instructions commit in order?

Ans: Reorder Buffer is used to enforce Out-of-order processor hardware structure to commit instruction in order. Problem2: Register renaming is able overcome which of the three data hazards? Ans: Register renaming is able to overcome WAR (Write After Read) and WAW (Write After Write) hazards. Problem 3: How many SRAM bits are needed to implement an 8KB two-way set associative cache with 64B block size? Assume that each line (entry) has a single valid bit and no dirty bits. There is one bit per set for true LRU. Assume that the address size of the machine is 32-bits and that the machine allows for byte addressing. Ans: Total no of cache blocks = 8KB/64B = 128. And No of sets = 128/2 = 64. Hence total bit required to implement Valid bit and true LRU is 64 + 128 =192 bits. As we can see 6 bit is required for selecting the set and another 6 bit for selecting the byte in the block making total of 12 bits, the rest of the 32 bits is managed for tags which is required for each block. Hence for tag total bit is required is 20 * 128 bits = 2560 bits And total bit to manage memory = 8 * 1024 * 8 = 65536 bits Making total of 68288 bits of SRAM Bits. Problem 4: Which of the following two processors will execute a program with the given instruction mix faster? Name Frequency CPI for ALU instructions CPI for branch instructions CPI for memory instructions Instruction Mix: 50% ALU Instructions 10% Branch Instructions 40% Memory Instructions Ans: For Processor A , One Clock Cycle = 1/1GHz = 1nano seconds Now the average time to execute one instruction on processor A is 0.5(1 * 1) + 0.1(2 * 1) + 0.4(1 * 1) = 0.5 + 0.2 + 0.4 = 1.1 nano seconds. Now for processor B, Processor A 1GHz 1 2 1 Processor B 2GHz 1.5 3 2

One clock Cycle = 1 / 2GHz = .5 nano seconds Now the average time to execute one instruction on processor B is, 0.5(.5 * 1.5) + 0.1 (.5 * 3) + 0.4 ( .5 * 2) = 0.925 nano seconds. As we see that the average time of Processor B < Average time of processor A hence we can say that the processor B is faster to execute a program than Processor A.

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