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Cad For Vlsi Circuits

The document is an exam for a Masters level VLSI Design course. It contains 15 questions testing knowledge of topics related to VLSI CAD tools and design processes. These include general purpose integrated circuits, integer linear programming, symbolic layout editors, partitioning problems, sizing algorithms, local routing parameters, static vs dynamic partitioning, two level logic synthesis, ASAP scheduling, and supervertices. Additional questions cover design domains, verification methods, graph representations, minimum spanning trees, placement constraints, floorplanning concepts, channel routing algorithms, gate-level simulation issues, ROBDD principles and manipulation, data flow types, and assignment problem optimization.

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logarasu
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101 views

Cad For Vlsi Circuits

The document is an exam for a Masters level VLSI Design course. It contains 15 questions testing knowledge of topics related to VLSI CAD tools and design processes. These include general purpose integrated circuits, integer linear programming, symbolic layout editors, partitioning problems, sizing algorithms, local routing parameters, static vs dynamic partitioning, two level logic synthesis, ASAP scheduling, and supervertices. Additional questions cover design domains, verification methods, graph representations, minimum spanning trees, placement constraints, floorplanning concepts, channel routing algorithms, gate-level simulation issues, ROBDD principles and manipulation, data flow types, and assignment problem optimization.

Uploaded by

logarasu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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com

M.E. DEGREE EXAMINATION, JUNE 2012 Second Semester VLSI Design VL9221/252204/VL 921CAD FOR VLSI CIRCUITS (Common to M.E. Applied Electronics) (Regulation 2009)

Time : Three hours Answer ALL Questions PART A (10 2 = 20 Marks)

Maximum : 100 Marks

1. List out the general-purpose integrated circuits. 2. Define integer linear programming. 3. What is the job of symbolic layout editor? 4. What does the partitioning problem deal with? 5. Formulate the sizing algorithm for slicing floor plans. 6. List the parameters characterizing the local routing problem. 7. Compare static partitioning and dynamic partitioning. 8. Write the problem definition for two level logic synthesis. 9. Write the demerit and ASAP scheduling. 10. Define supervertices.

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PART B (5 16 = 80 Marks)

11. (a)

(i) (ii)

Explain the design domains to describe the VLSI design process.

(8)

What are the ways of checking the correctness of an IC without actually (8) Or

fabricating it?

(b)

(i) (ii)

Explain a suitable data structure to represent a graph. Write the Prims algorithm for minimum spanning trees.

(8) (8)

12. (a)

(i) (ii)

With diagram explain the minimum distance design rules. List the types of placement problem and explain. Or

(8) (8)

(b)

Write the algorithms for constraint-graph compaction.

(16)

13. (a)

Describe the concepts of floorplanning. Or

(16)

(b)

Write the algorithms used for channel routing.

(16)

14. (a)

Explain the various issues related to gate-level simulation. Or

(16)

(b)

Explain the principle, construction and manipulation of ROBDD.

(16)

15. (a)

With suitable diagrams explain the types of data flow. Or

(16)

(b)

Explain the optimization issues and formulation of assignment problem.

(16)

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