Zynq-7000 All Programmable SoC

Technical Reference Manual

UG585 (v1.5) March 7, 2013

Notice of Disclaimer The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. Copyright 20122013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. CPRI is a trademark of Siemens AG. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Revision History
The following table shows the revision history for this document. Change bars indicate the latest revisions. Date
04/08/2012 06/25/2012

Version
1.0 1.1 Xilinx initial release.

Revision
Removed Chapter 30, Board Design (now part of UG933, Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide).

Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.5) March 7, 2013

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Date
08/08/2012

Version
1.2

Revision
Added information about the 7z010 CLG225 device and references to section 2.5.4 MIO-at-a-Glance Table throughout document. Added section headings 1.1.1 Block Diagram and 1.1.2 Documentation Resources, added sections 1.1.3 Notices and TrustZone Capabilities, and clarified PS MIO I/Os in Chapter 1. Updated Table 2-1. Changed 2.4.2 MIO-EMIO Connections heading to 2.5.2 IOP Interface Connections and clarified first paragraph. Updated Table 2-4. Added section 2.7.1 Clocks and Resets and Table 2-7, and updated Table 2-13 PS MIO I/Os in Chapter 2. Added note under Branch Prediction and Table 3-8 in Chapter 3. Updated Table 4-1 in Chapter 4. Added section 5.1.7 Read/Write Request Capability in Chapter 5. Updated NAND MIO pin assignments and Table 6-6 in Chapter 6. Updated section 7.2 Functional Description in Chapter 7. Added section heading 10.1.1 Features and added section 10.1.3 Notices in Chapter 10. Updated Parallel (SRAM/NOR) Interface features list and added section 11.1.3 Notices in Chapter 11. Reorganized, clarified, and expanded Chapter 12 to include programming models (added sections 12.1.4 Notices, 12.3 Programming Guide, and 12.5.2 MIO Programming). Added last note in section 13.3.4 Using ADMA in Chapter 13. Added Restrictions in Chapter 14. Clarified first paragraph, added section 15.1.3 Notices, and clarified Figure 15-7 through Figure 15-17 in Chapter 15. Added section 16.1.4 Notices in Chapter 16. Clarified sections 17.2.5 SPI FIFOs, 17.2.6 SPI Clocks, and 17.2.7 SPI EMIO Considerations in Chapter 17. Reorganized, clarified, and expanded Chapter 18 to include programming models (added sections 18.1.4 Notices and 18.5.1 MIO Programming). Reorganized, clarified, and expanded Chapter 19 to include programming models (added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in Chapter 25. Updated Table 26-4 in Chapter 26. Clarified section 27.3 I/O Signals in Chapter 27. Added section 28.1.2 Notices in Chapter 28. Clarified Mapping Summary and updated Table 29-1, Table 29-3, and Table 29-5 in Chapter 29. Added section 30.1.3 Notices in Chapter 30. Updated data sheet references in section A.3.1 Zynq-7000 AP SoC Documents of Appendix A. Updated register database in sections B.3 Module Summary through B.34 USB Controller (usb) in Appendix B. Changed product name from Extensible Processing Platform (EPP) to All Programmable SoC (AP SoC) throughout document. Added Table 1-1. Added 2.1.1 Notices, 2.4 PSPL Voltage Level Shifter Enables, 7z010 CLG225 Device Notice, VREF Source Considerations, updated Table 2-2, and added warning to 2.5.7 MIO Pin Electrical Parameters. Added Initialization of L1 Caches, 3.2.4 Memory Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown by Way Sequence and 3.9 CPU Initialization Sequence. Added Zynq-7000 AP SoC 7z010 CLG225 Device Notice and expanded Table 4-7. Updated and expanded tables in 6.3.4 Boot Devices through 6.3.8 Post Boot ROM State, reworked 6.3.6 Debug Status, and added 6.3.7 Accessible Addresses for Boot Image Address-Data Writes and DMA Done Status. Reworked Table 7-3. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and Reset. Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices, expanded 10.1.6 I/O Signals, added 10.6.11 DRAM Write Latency Restriction, 10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes. Added 12.2.4 I/O Mode Issues and updated 12.3.5 Rx/Tx FIFO Response to I/O Command Sequences. Reworked 16.3.3 I/O Configuration, added 16.4 IEEE 1588 Time Stamping and 16.6.7 MIO Pin Considerations. Added 18.2.7 CAN0-to-CAN1 Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UART0-to-UART1 Connection and 19.2.10 Status and Interrupts, expanded 19.2.11 Modem Control, reworked 19.3 Programming Guide and 19.4.2 Resets. Added 20.2.7 I2C0-to-I2C1 Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and reorganized content of Chapter 21, Programmable Logic Description. Added 25.7.1 Clock Throttle. Expanded 26.4.1 PL General Purpose User Resets. Updated register database in sections B.3 Module Summary through B.34 USB Controller (usb) in Appendix B.

10/30/2012

1.3

Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.5) March 7, 2013

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Date
11/16/2012 03/07/2013

Version
1.4 1.5

Revision
Changed second bullet under NAND Flash Interface from Up to a 4 GB device to Up to a 1 GB device in Chapter 11, Static Memory Controller. Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect. Clarified section 6.1 Introduction and other sections, and added PS Independent JTAG Non-Secure Boot section in Chapter 6, Boot and Configuration. Made minor clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller, Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in Chapter 12, Quad-SPI Flash Controller. Made minor clarifications to Chapter 13, SD/SDIO Controller. Made major clarifications/updates to Chapter 14, General Purpose I/O (GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controllers. Made minor clarifications to Chapter 16, Gigabit Ethernet Controller. Reworked and expanded Chapter 17, SPI Controller. Made minor clarifications to Chapter 18, CAN Controller, and Chapter 19, UART Controller. Made major clarifications/updates to Chapter 20, I2C Controller (added new sections, 20.3 Programmers Guide, 20.4 System Functions, and 20.5 I/O Interface). Made minor clarifications to Chapter 21, Programmable Logic Description and added new sections 21.1.2 PL Resources by Device Type and 21.1.3 Notices. Made minor clarifications to Chapter 22, Programmable Logic Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and expanded Chapter 24, Power Management. Made minor clarifications to Chapter 25, Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28, System Test and Debug, and Chapter 29, On-Chip Memory (OCM). Reworked and expanded Chapter 30, XADC Interface. Made minor clarifications to Chapter 31, PCI Express. Reworked and expanded Chapter 32, Device Secure Boot. Updated Appendix A, Additional Resources. Updated register database in sections B.3 Module Summary through B.34 USB Controller (usb) in Appendix B.

Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.5) March 7, 2013

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.1.2 Documentation Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

1.2 Processing System (PS) Features and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.2.1 Application Processor Unit (APU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.2.2 Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.2.3 I/O Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

1.3 Programmable Logic Features and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.4 Interconnect Features and Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.4.1 PS Interconnect Based on AXI High Performance Data Path Switches. . . . . . . . . . . . . . . . . . . . . . . . . .38 1.4.2 PS-PL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.5 System Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 2: Signals, Interfaces, and Pins

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.1 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.2 2.3 2.4 2.5

Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSPL Voltage Level Shifter Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS-PL MIO-EMIO Signals and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7

43 44 45 45

I/O Peripheral (IOP) Interface Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 IOP Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 MIO Pin Assignment Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 MIO-at-a-Glance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 MIO Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Default Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 MIO Pin Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.6 PSPL AXI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.7 PSPL Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Event Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 DMA Req/Ack Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.8 PL I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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Chapter 3: Application Processing Unit

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.1.1 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.1.2 System-level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.2 Cortex A9 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Level 1 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 NEON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Performance Monitoring Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

3.3 Snoop Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.3.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 3.3.2 Address Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 3.3.3 SCU Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.4 L2-Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 3.4.2 Exclusive L2-L1 Cache Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 3.4.3 Cache Replacement Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3.4.4 Cache Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3.4.5 Enabling and Disabling the L2 Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 3.4.6 RAM Access Latency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.4.7 Store Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.4.8 Optimizations Between Cortex-A9 and L2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3.4.9 Pre-fetching Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 3.4.10 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

3.5 APU Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.5.1 PL Co-processing Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 3.5.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

3.6 Support for TrustZone Within the APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8 CPU Security Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CP15 Register Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 MMU Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 L-1 Cache Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Security Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CPU Debug TrustZone Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 SCU Register Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 TrustZone Support in the L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

3.7 Application Processing Unit (APU) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.7.1 Reset Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 3.7.2 APU State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

3.8 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 3.8.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 3.8.3 Dynamic Clock Gating in the L2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

3.9 CPU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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Chapter 4: System Addresses

4.1 4.2 4.3 4.4 4.5 4.6 4.7 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Private Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMC Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS I/O Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous PS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 116 116 117 117 118 118

Chapter 5: Interconnect
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AXI ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Read/Write Request Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.2 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.2.1 Basic Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5.2.2 Advanced QoS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5.2.3 DDR Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

5.3 AXI_HP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Bandwidth Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Command Interleaving and Re-Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Performance Optimization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

5.4 AXI_ACP Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.5 AXI_GP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 5.5.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

5.6 PS-PL AXI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.6.1 AXI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 5.6.2 AXI Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Chapter 6: Boot and Configuration

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.1.1 Boot-up Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

6.2 External Startup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 6.2.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

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6.2.3 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 6.2.4 Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 6.2.5 Mode Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

6.3 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 Introduction and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Boot ROM Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Boot Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Boot ROM MultiBoot and Boot Partition Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Debug Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Accessible Addresses for Boot Image Address-Data Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Post Boot ROM State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Device Configuration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 PL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

6.4 Device Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Chapter 7: Interrupts
7.1 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.1.1 7.1.2 7.1.3 7.1.4 7.2.1 7.2.2 7.2.3 7.2.4 Private, Shared and Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Generic Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Resets and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Software Generated Interrupts (SGI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 CPU Private Peripheral Interrupts (PPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Shared Peripheral Interrupts (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 Wait for Interrupt Event Signal (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.3 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

7.3.1 Write Protection Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

7.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.4.1 7.4.2 7.4.3 7.4.4 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 ARM Programming Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 Legacy Interrupts and Security Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Chapter 8: Timers
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8.1.1 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 8.1.2 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

8.2 CPU Private Timers and Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

8.2.1 8.2.2 8.2.3 8.2.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Interrupt to PS Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

8.3 Global Timer (GT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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8.3.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 8.3.2 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

8.4 System Watchdog Timer (SWDT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

8.5 Triple Timer Counters (TTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Chapter 9: DMA Controller

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
9.1.1 9.1.2 9.1.3 9.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

9.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

9.2.1 DMA Transfers on the AXI Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 9.2.2 AXI Transaction Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 9.2.3 DMA Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 9.2.4 Multi-channel Data FIFO (MFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 9.2.5 Memory-to-Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 9.2.6 PL Peripheral AXI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 9.2.7 PL Peripheral Request Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 9.2.8 PL Peripheral - Length Managed by PL Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 9.2.9 PL Peripheral - Length Managed by DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 9.2.10 Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 9.2.11 Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 9.2.12 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 9.2.13 IP Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

9.3 Programming Guide for DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9.3.1 9.3.2 9.3.3 9.3.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Execute a DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 Write Microcode to Program CCRx for AXI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Memory-to-Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 PL Peripheral DMA Transfer Length Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 Restart Channel using an Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Interrupting a Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

9.4 Programming Guide for DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

9.5 Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

9.5.1 Updating Channel Control Registers During a DMA Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

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9.6 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

9.6.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 9.6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 9.6.3 Reset Configuration of Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

9.7 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

9.7.1 AXI Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 9.7.2 Peripheral Request Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Chapter 10: DDR Memory Controller

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.2.1 10.2.2 10.2.3 10.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 DDR Memory Types, Densities, and Data Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 AXI Feature Support and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 TrustZone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

10.2 AXI Memory Port Interface (DDRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

10.3 DDR Core and Transaction Scheduler (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

10.3.1 Row/Bank/Column Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

10.4 DDRC Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

10.4.1 Priority, Aging Counter and Urgent Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 10.4.2 Page-Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 10.4.3 Aging Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 10.4.4 Stage 1 AXI Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 10.4.5 Stage 2 Read Versus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 10.4.6 High Priority Read Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 10.4.7 Stage 3 Transaction State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 10.4.8 Read Priority Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 10.4.9 Write Combine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 10.4.10 Credit Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

10.5 Controller PHY (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 10.6 Initialization and Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
10.6.1 DDR Clock Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 10.6.2 DDR IOB Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 10.6.3 DDR IOB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 10.6.4 DDR Controller Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 10.6.5 DRAM Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 10.6.6 DRAM Input Impedance (ODT) Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 10.6.7 DRAM Output Impedance (RON) Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 10.6.8 DRAM Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 10.6.9 Write Data Eye Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 10.6.10 Alternatives to Automatic DRAM Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 10.6.11 DRAM Write Latency Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

10.7 Register Overviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.7.1 DDRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 10.7.2 DDRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

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10.7.3 DDRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

10.8 Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

10.8.1 10.8.2 10.8.3 10.8.4 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 ECC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 ECC Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Data Mask During ECC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 ECC Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 Changing Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Deep Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282

10.9 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Chapter 11: Static Memory Controller

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 11.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

11.2 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 Boot Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 PL353 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

11.3 11.4 11.5 11.6

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

288 289 290 291

Chapter 12: Quad-SPI Flash Controller

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
12.1.1 12.1.2 12.1.3 12.1.4 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 I/O Mode Transmit Registers (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 I/O Mode Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Linear Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Unsupported Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Linear Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 Configure I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 I/O Mode Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Rx/Tx FIFO Response to I/O Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

12.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

12.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

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12.3.6 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

12.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

12.4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 12.4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

12.5 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

12.5.1 Wiring Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 12.5.2 MIO Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 12.5.3 MIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

Chapter 13: SD/SDIO Controller

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
13.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 13.1.2 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.2.9 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 AHB Interface and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 SD/SDIO Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 Command and Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 Stream Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Soft Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 FIFO Overrun and Underrun Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Data Transfer Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 Data Transfers Without DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 Using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 Using ADMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 Abort Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 External Interface Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 Supported Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Bus Voltage Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330

13.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

13.4 SDIO Controller Media Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

13.4.1 SDIO EMIO Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

Chapter 14: General Purpose I/O (GPIO)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 14.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 14.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

14.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

14.2.1 14.2.2 14.2.3 14.2.4 GPIO Control of Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 EMIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 Bank0, Bits[8:7] are Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

14.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

14.3.1 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 14.3.2 GPIO Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 14.3.3 Writing Data to GPIO Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

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14.3.4 Reading Data from GPIO Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 14.3.5 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

14.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

14.4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 14.4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 14.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

14.5 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

14.5.1 MIO Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341

Chapter 15: USB Host, Device, and OTG Controllers

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 15.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 15.1.3 Hardware System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 15.1.4 Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 15.1.5 Configuration, Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348 15.1.6 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348 15.1.7 Implementation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 15.1.8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 15.1.9 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 15.1.10 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

15.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 Controller Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 ULPI Link Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 Hardware/Software System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Operational Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Interrupt and Status Bits Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 OTG Status/Interrupt and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

15.3 Programming Overview and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

15.4 Device Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

15.4.1 Controller State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 15.4.2 USB Bus Reset Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

15.5 Device Endpoint Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

15.5.1 15.5.2 15.5.3 15.5.4 15.6.1 15.6.2 15.6.3 15.6.4 15.6.5 Link-list Endpoint Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 Manage Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 Endpoint Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 Prime Transmit Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 Prime Receive Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 Interrupt and Bulk Endpoint Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 Isochronous Endpoint Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 Control Endpoint Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376

15.6 Device Endpoint Packet Operational Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

15.7 Device Endpoint Descriptor Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

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15.7.1 Endpoint Queue Head Descriptor (dQH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 15.7.2 Endpoint Transfer Descriptor (dTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 15.7.3 Endpoint Transfer Overlay Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

15.8 Programming Guide for Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

15.8.1 Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 15.8.2 USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 15.8.3 Register Controlled Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

15.9 Programming Guide for Device Endpoint Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . 384

15.9.1 15.9.2 15.9.3 15.9.4 Device Controller Initialization Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 Manage Transfer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 Manage Transfers with Transfer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 Service Device Mode Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

15.10 Host Mode Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

15.10.1 Host Controller Transfer Schedule Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 15.10.2 Periodic Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 15.10.3 Asynchronous Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

15.11 EHCI Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

15.11.1 15.11.2 15.11.3 15.11.4 15.11.5 15.11.6 15.11.7 15.11.8 15.12.1 15.12.2 15.12.3 15.12.4 15.12.5 15.12.6 15.12.7 15.12.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 Embedded Transaction Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 EHCI Functional Changes for the TT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 Port Reset Timer Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 Port Speed Detection Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 FS/LS Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 Operational Model of the TT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400 Port Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Descriptor Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Transfer Descriptor Type (TYP) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Isochronous (High Speed) Transfer Descriptor (iTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403 Split Transaction Isochronous Transfer Descriptor (siTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 Queue Element Transfer Descriptor (qTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 Queue Head (QH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 Transfer Overlay Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 Periodic Frame Span Traversal Node (FSTN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420

15.12 Host Data Structures Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

15.13 Programming Guide for Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

15.13.1 Controller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421 15.13.2 Run/Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

15.14 OTG Description and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

15.14.1 Hardware Assistance Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 15.14.2 OTG Interrupt and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423

15.15 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

15.15.1 15.15.2 15.15.3 15.15.4 15.15.5 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 PS Interrupts to GIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 APB Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 AHB Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426

15.16 I/O Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

15.16.1 Wiring Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 15.16.2 MIO-EMIO Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 15.16.3 MIO-EMIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428

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Chapter 16: Gigabit Ethernet Controller

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16.1.1 16.1.2 16.1.3 16.1.4 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 16.2.7 16.2.8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 MAC Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434 MAC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435 MAC Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435 Wake on LAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438 DMA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 Checksum Offloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449 IEEE 1588 Time Stamp Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 MAC 802.3 Pause Frame Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454

16.2 Functional Description and Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

16.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

16.3.1 Initialize the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458 16.3.2 Configure the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459 16.3.3 I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 16.3.4 Configure the PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461 16.3.5 Configure the Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .462 16.3.6 Configure Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464 16.3.7 Enable the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464 16.3.8 Transmitting Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465 16.3.9 Receiving Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465 16.3.10 Debug Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466

16.4 IEEE 1588 Time Stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468 Controller Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 Best Master Clock Algorithm (BMCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471 PTP Packet Handling at the Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472 PTP Packet Handling at the Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474

16.5 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

16.5.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 16.5.2 Status and Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

16.6 Signals and I/O Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

16.6.1 16.6.2 16.6.3 16.6.4 16.6.5 16.6.6 16.6.7 MIOEMIO Interface Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 Precision Time Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 Programmable Logic (PL) Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 RGMII Interface via MIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 GMII/MII Interface via EMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479 MDIO Interface Signals via MIO and EMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .480 MIO Pin Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481

Chapter 17: SPI Controller

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.1.1 17.1.2 17.1.3 17.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486

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17.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 Multi-Master Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .490 FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 Interrupt Register Bits, Logic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 SPI-to-SPI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 Master Mode Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493 Slave Mode Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .496

17.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

17.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

17.4.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .497 17.4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .497

17.5 I/O Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .498 Back-to-Back Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 MIO/EMIO Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501 Wiring Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .502 MIO/EMIO Signal Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505

Chapter 18: CAN Controller

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
18.1.1 18.1.2 18.1.3 18.1.4 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.3.7 18.3.8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509 Controller Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510 Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513 Message Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517 Rx Message Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522 CAN0-to-CAN1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 Configuration Mode State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525 Start-up Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .526 Change Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .526 Write Messages to TxFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 Write Messages to TxHPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 Read Messages from RxFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528

18.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

18.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

18.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

18.4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 18.4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530

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18.5 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

18.5.1 MIO Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 18.5.2 MIO-EMIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531

Chapter 19: UART Controller

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533 19.1.2 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534 19.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534

19.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

19.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535 19.2.2 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535 19.2.3 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535 19.2.4 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537 19.2.5 Transmitter Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537 19.2.6 Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 19.2.7 Receiver Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 19.2.8 I/O Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 19.2.9 UART0-to-UART1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541 19.2.10 Status and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541 19.2.11 Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .543

19.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 Configure Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548 RxFIFO Trigger Level Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549

19.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

19.4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 19.4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551

19.5 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

19.5.1 MIO Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551 19.5.2 MIO EMIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553

Chapter 20: I2C Controller

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .554 20.1.2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555 20.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555

20.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.2.8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 Slave Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 I2C Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .560 Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 I2C0-to-I2C1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 Status and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561

20.3 Programmers Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

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20.3.1 20.3.2 20.3.3 20.3.4 20.3.5

Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562 Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562 Configure Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566

20.4 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

20.4.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566 20.4.2 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567

20.5 I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

20.5.1 Pin Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567 20.5.2 MIO-EMIO Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568

Chapter 21: Programmable Logic Description

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569 21.1.2 PL Resources by Device Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .571 21.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572

21.2 PL Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

21.2.1 21.2.2 21.2.3 21.2.4 21.3.1 21.3.2 21.3.3 21.3.4 CLBs, Slices, and LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574 Digital Signal Processing DSP Slice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575 PS-PL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576 SelectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577 Low-Power Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578 Integrated I/O Block for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580

21.3 Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

21.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

Chapter 22: Programmable Logic Design Guide

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 22.2 Programmable Logic for Software Offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.2.6 22.3.1 22.3.2 22.3.3 22.3.4 22.4.1 22.4.2 22.4.3 22.4.4 22.4.5 Benefits of Using PL to Implement Software Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 Designing PL Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 PL Acceleration Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .584 Power Offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .584 Real Time Offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585 Reconfigurable Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586 Theoretical Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587 DDR Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588 OCM Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .589 Interconnect Throughput Bottlenecks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .589 PL Interface Comparison Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590 Cortex-A9 CPU via General Purpose Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590 PS DMA Controller (DMAC) via General Purpose Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .591 PL DMA via AXI High-Performance (HP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592 PL DMA via AXI ACP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593

22.3 PL and Memory System Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

22.4 Choosing a Programmable Logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

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22.4.6 PL DMA via General Purpose AXI Slave (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .594

Chapter 23: Programmable Logic Test and Debug

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .595 23.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .596 23.1.3 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597

23.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

23.2.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597 23.2.2 Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598 23.2.3 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600

23.3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

23.3.1 General-Purpose Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602 23.3.2 Trigger Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603 23.3.3 Trace Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603

23.4 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 23.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

23.5.1 FTM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

Chapter 24: Power Management

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
24.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605

24.2 System Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

24.2.1 24.2.2 24.2.3 24.2.4 24.2.5 24.2.6 24.2.7 Device Technology Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 PL Power-down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 APU Maximum Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 DDR Memory Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 DDR Memory Controller Modes and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 Boot Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 PS Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607

24.3 Programming Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

24.3.1 System Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 24.3.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609 24.3.3 I/O Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611

24.4 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

24.4.1 Setup Wake-up Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612 24.4.2 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612

24.5 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Chapter 25: Clocks

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
25.1.1 25.1.2 25.1.3 25.1.4 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .616 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618

25.2 CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 25.3 System-wide Clock Frequency Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

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25.4 Clock Generator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 25.5 DDR Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 25.6 IOP Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
25.6.1 25.6.2 25.6.3 25.6.4 25.6.5 USB Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .625 Ethernet Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626 SDIO, SMC, SPI, Quad-SPI and UART Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .627 CAN Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .627 GPIO and I2C Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .628

25.7 PL Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

25.7.1 Clock Throttle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629 25.7.2 Clock Throttle Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630

25.8 Trace Port Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 25.9 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 25.10 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
25.10.1 25.10.2 25.10.3 25.10.4 Branch Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633 DDR Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634 Digitally Controlled Impedance (DCI) Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634

Chapter 26: Reset System

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
26.1.1 26.1.2 26.1.3 26.1.4 26.2.1 26.2.2 26.2.3 26.2.4 26.2.5 26.2.6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637 Reset Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638 Boot Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639 Power-on Reset (PS_POR_B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640 External System Reset (PS_SRST_B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641 System Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641 Watchdog Timer Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641 Secure Violation Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641 Debug Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641

26.2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

26.3 Reset Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

26.3.1 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .642

26.4 PL Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

26.4.1 PL General Purpose User Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643

26.5 Register Overviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

26.5.1 Reset Subsystem Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643 26.5.2 System Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644 26.5.3 Peripheral Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644

Chapter 27: JTAG and DAP Subsystem

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
27.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .646 27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .648

27.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 27.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 27.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

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27.4.1 Use Case I: Software Debug with Trace Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .652 27.4.2 Use Case II: PS and PL Debug with Trace Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .652

27.5 ARM DAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 27.6 Trace Port Interface Unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 27.7 Xilinx TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Chapter 28: System Test and Debug

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
28.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657 28.1.2 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .658

28.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

28.2.1 28.2.2 28.2.3 28.2.4 28.2.5 28.2.6 28.2.7 Debug Access Port (DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .659 Embedded Cross Trigger (ECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .660 Program Trace Macrocell (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 Instrumentation Trace Macrocell (ITM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 Funnel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 Embedded Trace Buffer (ETB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 Trace Packet Output (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663

28.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 28.4 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

28.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .665 28.4.2 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .666

28.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

28.5.1 Authentication Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .669

Chapter 29: On-Chip Memory (OCM)

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672 29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672 29.1.3 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673

29.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

29.2.1 29.2.2 29.2.3 29.2.4 29.2.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674 Optimal Transfer Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674 Arbitration Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679

29.3 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 29.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

29.4.1 Changing Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680 29.4.2 AXI Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .681

Chapter 30: XADC Interface

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
30.1.1 30.1.2 30.1.3 30.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .683 System Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .684 PS-XADC Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .685 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .686

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30.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

30.2.1 30.2.2 30.2.3 30.2.4 30.3.1 30.3.2 30.3.3 30.3.4 30.3.5 30.3.6 30.4.1 30.4.2 30.4.3 30.4.4 Interface Arbiter (PL-JTAG and PS-XADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687 Serial Communication Channel (PL-JTAG and PS-XADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687 Analog-to-Digital Converter (All) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688 Sensor Alarms (PS-XADC and DRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688 Serial Channel Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .689 Command and Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .690 Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .691 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .691 Min/Max Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .692 Critical Over-temperature Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .692 Read and Write to the FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .693 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .694 Command Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .695 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .695

30.3 PS-XADC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

30.4 Programming Guide for the PS-XADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

30.5 Programming Guide for the DRP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 30.6 Programming Guide for the PL-JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 30.7 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
30.7.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .696 30.7.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697

Chapter 31: PCI Express

31.1 31.2 31.3 31.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint Use Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 699 699 700

Chapter 32: Device Secure Boot

32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
32.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701 32.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701

32.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

32.2.1 32.2.2 32.2.3 32.2.4 32.2.5 32.2.6 32.2.7 32.2.8 32.2.9 32.3.1 32.3.2 32.3.3 32.3.4 Master Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703 External Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .705 Secure Boot Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .705 eFuse Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .707 RSA Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708 Boot Image and Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708 Boot Image and Bitstream Decryption and Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709 HMAC Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709 AES Key Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709 Non-Secure Boot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709 Secure Boot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710 Security Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710 Golden Image Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710

32.3 Secure Boot Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

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32.3.5 JTAG and Debug Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710 32.3.6 Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711 32.3.7 Secure Boot Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

32.4 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Appendix A: Additional Resources

A.1 Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 A.2 Solution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 A.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
A.3.1 A.3.2 A.3.3 A.3.4 A.3.5 A.3.6 A.3.7 A.3.8 Zynq-7000 AP SoC Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .714 PL Documents Device and Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .714 Advanced eXtensible Interface (AXI) Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715 Software Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715 git Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715 Design Tool Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715 EDK Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716 Third-Party IP and Standards Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716

Appendix B: Register Details

B.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 B.2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 B.3 Module Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 B.4 AXI_HP Interface (AFI) (axi_hp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 B.5 CAN Controller (can). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 B.6 DDR Memory Controller (ddrc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 B.7 CoreSight Cross Trigger Interface (cti). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 B.8 Performance Monitor Unit (cortexa9_pmu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 B.9 CoreSight Program Trace Macrocell (ptm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 B.10 Debug Access Port (dap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 B.11 CoreSight Embedded Trace Buffer (etb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 B.12 PL Fabric Trace Monitor (ftm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 B.13 CoreSight Trace Funnel (funnel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 B.14 CoreSight Intstrumentation Trace Macrocell (itm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 B.15 CoreSight Trace Packet Output (tpiu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 B.16 Device Configuration Interface (devcfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 B.17 DMA Controller (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102 B.18 Gigabit Ethernet Controller (GEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206 B.19 General Purpose I/O (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 B.20 Interconnect QoS (qos301) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314 B.21 NIC301 Address Region Control (nic301_addr_region_ctrl_registers) . . . . . . . . . . . . . . . . 1320 B.22 I2C Controller (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322 B.23 L2 Cache (L2Cpl310) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333 B.24 Application Processing Unit (mpcore). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372

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B.25 B.26 B.27 B.28 B.29 B.30 B.31 B.32 B.33 B.34

On-Chip Memory (ocm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad-SPI Flash Controller (qspi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD Controller (sdio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Level Control Registers (slcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller (pl353) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Controller (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Watchdog Timer (swdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple Timer Counter (ttc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Controller (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Controller (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1427 1431 1448 1489 1633 1660 1672 1676 1697 1717

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Chapter 1

Introduction
1.1 Overview
The Zynq-7000 family is based on the Xilinx All Programmable SoC (AP SoC) architecture. These products integrate a feature-rich dual-core ARM Cortex-A9 MPCore based processing system (PS) and Xilinx programmable logic (PL) in a single device, built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, and high-k metal gate (HKMG) process technology. The ARM Cortex-A9 MPCore CPUs are the heart of the PS which also includes on-chip memory, external memory interfaces, and a rich set of I/O peripherals. The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including: Automotive driver assistance, driver information, and infotainment Broadcast camera Industrial motor control, industrial networking, and machine vision IP and Smart camera LTE radio and baseband Medical diagnostics and imaging Multifunction printers Video and night vision equipment

The Zynq-7000 architecture conveniently maps the custom logic and software in the PL and PS respectively. It enables the realization of unique and differentiated system functions. The integration of the PS with the PL provides levels of performance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, loose-coupling and power budgets. Xilinx and the Xilinx Alliance partners offer a large number of soft IP modules for the Zynq-7000 family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL from Xilinx and additional OSes and board support packages (BSPs) from partners. The award-winning ISE Design Suite: Embedded Edition development environment enables a rapid product development for software, hardware, and systems engineers. Many third-party software development tools are also available.

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The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed. This latter capability is analogous to the dynamic loading and unloading of software modules. The PL configuration data is referred to as a bitstream.

1.1.1 Block Diagram

Figure 1-1 illustrates the functional blocks of the Zynq-7000 AP SoC. The PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for power management if required.
X-Ref Target - Figure 1-1

Zynq-7000 AP SoC
I/O Peripherals USB USB GigE GigE SD SDIO SD SDIO GPIO UART UART CAN CAN I2C I2C SPI SPI Memory Interfaces SRAM/ NOR ONFI 1.0 NAND Q-SPI CTRL

Processing System
Clock Generation 2x USB 2x GigE 2x SD IRQ Reset SWDT TTC System Level Control Regs MMU 32 KB I-Cache GIC DMA 8 Channel OCM Interconnect Central Interconnect CoreSight Components

Application Processor Unit

FPU and NEON Engine ARM Cortex-A9 CPU 32 KB D-Cache FPU and NEON Engine MMU 32 KB I-Cache ARM Cortex-A9 CPU 32 KB D-Cache

Snoop Controller, AWDT, Timer 512 KB L2 Cache & Controller

MIO

256K SRAM Memory Interfaces DDR2/3,3L, LPDDR2 Controller

DAP DevC Programmable Logic to Memory Interconnect

EMIO

XADC 12 bit ADC

General-Purpose Ports

DMA Sync

IRQ

Config AES/ SHA

High-Performance Ports

ACP

Programmable Logic
SelectIO Resources

Notes: 1) Arrow direction shows control (master to slave) 2) Data flows in both directions: AXI 32bit/64bit, AXI 64bit, AXI 32bit, AHB 32bit, APB 32bit, Custom

DS190_01_030713

Figure 1-1:

Zynq-7000 AP SoC Overview

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The Zynq-7000 AP SoC is composed of the following major functional blocks: Processing System (PS)

Application processor unit (APU) Memory interfaces I/O peripherals (IOP) Interconnect

Programmable Logic (PL)

1.1.2 Documentation Resources

Table 1-1 identifies the versions of third-party IP used in the Zynq-7000 AP SoC devices. Table 1-1: Vendor IP Versions Unit
Cortex-A9 MPCore AMBA Level 2 Cache Controller (PL310) PrimeCell Static Memory Controller (PL353) PrimeCell DMA Controller (PL330) CoreLink Network Interconnect (NIC-301) DesignWare Cores IntelliDDR Multi Protocol Memory Controller USB 2.0 High Speed Atlantic Controller Watchdog Timer Inter Intergrated Circuit Gigabit Ethernet MAC Serial Peripheral Interface Universal Asynchronous Receiver Transmitter Triple Timer Counter SD2.0/SDIO2.0/MMC3.31 AHB Host Controller

Supplier
ARM ARM ARM ARM ARM Synopsys Synopsys Cadence Cadence Cadence Cadence Cadence Cadence Arasan r3p0

Version
r3p2-50rel0 r2p1 r1p1 r2p2 A07 2.20a Rev 07 r1p10 r1p23 r1p06 r1p08 Rev 06 8.9A_apr02nd_2010

The PL is derived from Xilinxs 7 Series FPGA technology (Artix-7 for the 7z010/7z020 and Kintex-7 for the 7z030/7z045/7z100). The PL is used to extend the functionality to meet specific application requirements. The PL includes many different types of resources including configurable logic blocks (CLBs), port and width configurable block RAM (BRAM), DSP slices with 25 x 18 multiplier, 48-bit accumulator and pre-adder (DSP48E1), a user configurable analog to digital convertor (XADC), clock management tiles (CMT), a configuration block with 256b AES for decryption and SHA for authentication, configurable SelectIO and optionally GTX multi-gigabit transceivers and integrated PCI Express (PCIe) block. To learn more about the PL resources, refer to the following Xilinx 7 Series FPGA User Guides: UG471, 7 Series FPGAs SelectIO Resources User Guide UG472, 7 Series FPGAs Clocking Resources User Guide

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UG473, 7 Series FPGAs Memory Resources User Guide UG474, 7 Series FPGAs Configurable Logic Block User Guide UG476, 7 Series FPGAs GTX Transceiver User Guide UG477, 7 Series FPGAs Integrated Block v1.3 for PCI Express User Guide UG479, 7 Series FPGAs DSP48E1 User Guide UG480, 7 Series FPGAs XADC User Guide

The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals that have a combined total of over 3,000 connections. This enables the designer to effectively integrate user-created hardware accelerators and other functions in the PL fabric that are accessible to the processors and can also access memory resources in the processing system. The PS I/O peripherals, including the static/flash memory interfaces share a multiplexed I/O (MIO) of up to 54 MIO pins. Zynq-7000 AP SoC devices also include the capability to utilize the I/Os that are part of the PL domain for many of the PS I/O Peripherals. This is done through an extended multiplexed I/O interface (EMIO). The system includes many types of security, test and debug features. The Zynq-7000 AP SoC can be booted securely or non-securely. The PL configuration bitstream can be applied securely or non-securely. Both of these use the 256b triple-des AES decryption and SHA authentication blocks that are part of the PL. Therefore, to use these security features, the PL must be powered on. The boot process is multi-stage and minimally includes the Boot ROM and the first-stage boot loader (FSBL). The Zynq-7000 AP SoC includes a factory-programmed Boot ROM that is not user accessible. The boot ROM determines whether the boot is secure or non-secure, performs some initialization of the system and clean-ups, reads the mode pins to determine the primary boot device and finishes once it is satisfied it can execute the FSBL. After a system reset, the system automatically sequences to initialize the system and process the first stage boot loader from the selected external boot device. The process enables the user to configure the AP SoC platform as needed, including the PS and the PL. Optionally, the JTAG interface can be enabled to give the design engineer access to the PS and the PL for test and debug purposes. Power to the PL can be optionally shut off to reduce power consumption. In addition, the clocks in the PS can be dynamically slowed down or gated off to reduce power further. Zynq-7000 AP SoC devices support ARMs standby mode to obtain minimal power drain, but still are able to start up when certain events occur. Elements of the Zynq-7000 AP SoC are described from the point of view of the PS. For example, a general purpose slave interface on the PS to the PL means that the master resides in the PL. A high performance slave interface means the high performance master resides in the PL. A general purpose master interface means the PS is the master and the slave resides in the PL.

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1.1.3 Notices
Zynq-7000 AP SoC Device Family
The PS structure for all Zynq-7000 AP SoC devices is the same except for the following: 7z010 CLG225 Device The 7z010 CLG225 device (225 pin package) has a limited number of pins that reduces the capability of the MIO, DDR and XADC subsystems. 32 MIO pins, see section 2.5.3 MIO Pin Assignment Considerations 16 DDR data, see section 10.1.3 Notices in Chapter 10, DDR Memory Controller Four pairs of XADC signals, see Notices in Chapter 30, XADC Interface

Device Revisions
The visual markings are shown in UG865, Zynq-7000 All Programmable SoC Packaging and Pinout Advance Product Specification. Software can read the following registers in all Zynq-7000 AP SoC devices to determine silicon revision: devcfg.PS_VERSION slcr.PSS_IDCODE[IDCODE]

The JTAG interface also includes the IDCODE revision content.

TrustZone Capabilities
TrustZone is hardware that is built into all Zynq-7000 AP SoC devices. The Technical Reference Manual includes TrustZone hardware descriptions. Please contact your Xilinx Sales Representative about obtaining detailed information related to operating the system in a secure mode.

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1.2 Processing System (PS) Features and Descriptions

1.2.1 Application Processor Unit (APU)
The application processor unit (APU) provides an extensive offering of high-performance features and standards-compliant capabilities.

Dual ARM Cortex-A9 MPCore CPUs with ARM v7

Run-time options allow single processor, asymmetrical (AMP) or symmetrical multiprocessing (SMP) configurations ARM Version 7 ISA: Standard ARM instruction set and Thumb-2, Jazelle RCT and Jazelle DBX Java acceleration NEON 128b SIMD coprocessor and VFPv3 per MPCore 32 KB instruction and 32 KB data L1 caches with parity per MPCore 512 KB of shareable L2 cache with parity Private timers and watchdog timers

System Features
System-Level Control Registers (SLCRs)

A group of various registers that are used to control the PS behavior The register map is located in Chapter 4, System Addresses The SLCR registers related to a specific chapter are listed in the register overview table of that chapter and detailed in Appendix B, Register Details

Snoop control unit (SCU) to maintain L1 and L2 coherency Accelerator coherency port (ACP) from PL (master) to PS (slave)

64b AXI slave port Can access the L2 and the OCM Transactions are data coherent with L1 and L2 caches Dual ported Accessible by the CPUs, PL and central interconnect At level of L2, but is not cacheable Four channels for PS (memory copy to/from any memory in system) Four channels for PL (memory to PL, PL to memory)

256 KB of on-chip SRAM (OCM) with parity

DMA controller

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General interrupt controller (GIC)

Individual interrupt masks and interrupt prioritization Five CPU-private peripheral interrupts (PPI) Sixteen CPU-private software generated interrupts (SGI) Distributes shared peripheral interrupts (SPI) from the rest of the system, PS and PL 20 from the PL Wait for interrupt (WFI) and wait for event (WFE) signals from CPU sent to PL Enhanced security features to support TrustZone technology

Watchdog timer, triple counter/timer

1.2.2 Memory Interfaces

The memory interfaces includes multiple memory technologies.

DDR Controller
Supports DDR3, DDR3L, DDR2, LPDDR-2

Rate is determined by speed and temperature grade of the device ECC on 16b

16b or 32b wide

Uses up to 73 dedicated PS pins Modules (no DIMMs)

32b wide: 4 x 8b, 2 x 16b, 1 x 32b 16b wide: 2 x 8b, 1 x 16b

Autonomous DDR power down entry and exit based on programmable idle periods Data read strobe auto-calibration Write data byte enables supported for each data beat Low latency read mechanism using HPR queue Special urgent signaling to each port TrustZone regions programmable on 64 MB boundaries Exclusive accesses for two different IDs per port (locked transactions are not supported)

DDR Controller Core and Transaction Scheduler

Transaction scheduling is done to optimize data bandwidth and latency Advanced re-ordering engine to maximize memory access efficiency with target of 90% efficiency with continuous read and write and 80% efficiency with random read and write Write-read address collision checking that flushes the write buffer Obeys AXI ordering rules

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Quad-SPI Controller
Key features of the linear Quad-SPI Controller are: Single or dual 1x and 2x read support 32-bit APB 3.0 interface for I/O mode that allows full device operations including program, read and configuration 32-bit AXI linear address mapping interface for read operations Single chip select line support Supports write protection signal Four-bit bidirectional I/O signals Read speed of x1, x2 and x4 Write speed of x1 and x4 Maximum Quad-SPI clock at master mode is 100 MHz 252-byte entry FIFO depth to improve Quad-SPI read efficiency Supports Quad-SPI device up to 128 Mb density Supports dual Quad-SPI with two quad-SPI devices in parallel

In addition, the linear address mapping mode features include: Supports regular read-only memory access through the AXI interface Up to two SPI flash memories Up to 16 MB addressing space for one memory and 32 MB for two memories AXI read acceptance capability of 4 Both AXI incrementing and wrapping-address burst read Automatically converts normal memory read operation to SPI protocol, and vice versa Serial, Dual and Quad-SPI modes

Static Memory Controller (SMC)

Either of the following can be the primary boot device: NAND controller

8/16-bit I/O width with one chip select signal ONFI specification 1.0 16-word read and 16-word write data FIFOs 8-word command FIFO Programmable I/O cycle timing ECC assist Asynchronous memory operating mode

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Parallel SRAM/NOR controller

8-bit data bus width One chip select with up to 26 address signals (64 MB) Two chip selects with up to 25 address signals (32 MB + 32 MB) 16-word read and 16-word write data FIFOs 8-word command FIFO Programmable I/O cycle timing on a per chip select basis Asynchronous memory operating mode

1.2.3 I/O Peripherals

The I/O Peripherals (IOP) are a collection of industry-standard interfaces for external data communication:

GPIO
Up to 54 GPIO signals for device pins routed through the MIO

Outputs are 3-state capable 64 Inputs, 128 outputs (64 true outputs and 64 output enables) Enable, bit or bank data write, output enable and direction controls Status read of raw and masked interrupt Positive edge, negative edge, either edge, high level, low level sensitivities

192 GPIO signals between the PS and PL via the EMIO

The function of each GPIO can be dynamically programmed on an individual or group basis

Programmable Interrupts on individual GPIO basis

Gigabit Ethernet Controllers (Two)

RGMII interface using MIO pins and external PHY Additional interface using PL SelectIO and external PHY with additional soft IP in the PL
SGMII interface using PL GTX transceivers

Built-in DMA with scatter-gather IEEE 802.3-2008 and IEEE 1588 revision 2.0 Wake-on capability

USB Controllers: Each as Host, Device or OTG (Two)

USB 2.0 high speed on-the-go (OTG) dual role USB host controller or USB device controller operation using the same hardware MIO pins only (one USB controller is available in the 7x010 device)

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Built-in DMA USB 2.0 high speed device USB 2.0 high speed host controller The USB host controller registers and data structures are EHCI compatible Direct support for USB transceiver low pin interface (ULPI). The ULPI module supports 8 bits External PHY required Support up to 12 endpoints

SD/SDIO Controllers (Two)

Bootable SD Card mode (option) Built-in DMA Host mode support only Support for version 2.0 of SD specification Full speed and low speed support 1-bit and 4-bit data interface support Low speed clock 0400 KHz Support for high speed interface Full speed clock 0-50 MHz with maximum throughput at 25 MB/s Support for memory, I/O, and combination cards Support for power control modes Support for interrupts 1 KB Data FIFO interface

SPI Controllers (Two): Master or Slave

Four wire bus: MOSI, MISO, SCLK, SS Full-duplex operation offers simultaneous receive and transmit Master mode

Manual or auto start transmission of data Manual or auto slave select (SS) mode Supports up to three slave select lines Allows the use of an external peripheral select 3-to-8 decode Programmable delays for data transmission Programmable start detection mode Drives into three-state if not enabled

Slave mode

Multi-master environment

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Identifies an error condition if more than one master detected 25 MHz maximum via EMIO to PL SelectIO pins

Supports 50 MHz maximum external SPI clock rate via MIO

Selectable master clock reference Programmable master baud rate divisor Supports 128-byte read and 128-byte write FIFOs

Each FIFO is 8-bit wide

Programmable FIFO thresholds Supports programmable clock phase and polarity Supports manual or auto start transmission of data Software can poll for status or function as interrupt-driven Programmable interrupt generation

CAN Controllers (Two)

Conforms to the ISO 11898 -1, CAN 2.0A, and CAN 2.0B standards Supports both standard (11-bit identifier) and extended (29-bit identifier) frames Supports bit rates up to 1 Mb/s Transmit message FIFO with a depth of 64 messages Transmit prioritization through one high-priority transmit buffer Support of watermark interrupts for TxFIFO and RxFIFO Automatic re-transmission on errors or arbitration loss in normal mode Receive message FIFO with a depth of 64 messages Acceptance filtering of four acceptance filters Sleep mode with automatic wakeup Snoop mode Loopback mode for diagnostic applications Maskable error and status interrupts 16-bit time stamping for receive messages Readable error counters

UART Controllers (Two)

Programmable baud rate generator 64-byte receive and transmit FIFOs 6, 7, or 8 data bits 1, 1.5, or 2 stop bits Odd, even, space, mark, or no parity

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Parity, framing and overrun error detection Line-break generation and detection Automatic echo, local loopback, and remote loopback channel modes Interrupts generation Rx and Tx signals are on the MIO and EMIO interfaces Modem control signals: CTS, RTS, DSR, DTR, RI, and DCD are available on the EMIO interface

I2C Controllers (two)

Supports 16-byte FIFO I2C bus specification version 2 Programmable normal and fast bus data rates Master mode

Write transfer Read transfer Extended address support Support HOLD for slow processor service Supports TO interrupt flag to avoid stall condition

Slave monitor mode Slave mode

Slave transmitter Slave receiver Extended address support Fully programmable slave response address Supports HOLD to prevent overflow condition Supports TO interrupt flag to avoid stall condition

Software can poll for status or function as interrupt-driven device Programmable interrupt generation

PS MIO I/Os
The PS MIO I/O buffers are split into two voltage domains. Within each domain, each MIO is independently programmable. Two I/O voltage banks

Bank 0 voltage bank consists of pins 0:15 Bank 1 voltage bank consists of pins 16:53 1.8 and 2.5/3.3 volts

MIO voltage levels can be programmed per bank.

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CMOS single ended or HSTL differential receiver mode

1.3 Programmable Logic Features and Descriptions

The PL provides a rich architecture of user-configurable capabilities. Configurable logic blocks (CLB)

6-input look-up tables (LUTs) Memory capability within the LUT Register and shift register functionality Cascadeable adders Dual port Up to 72-bits wide Configurable as dual 18 Kb Programmable FIFO logic Built-in error correction circuitry 25 18 two's complement multiplier/accumulator high-resolution (48 bit) signal processor Power saving 25-bit pre-adder to optimize symmetrical filter applications Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading High-speed buffers and routing for low-skew clock distribution Frequency synthesis and phase shifting Low-jitter clock generation and jitter filtering High-performance SelectIO technology High-frequency decoupling capacitors within the package for enhanced signal integrity Digitally controlled impedance that can be 3-stated for lowest power, high-speed I/O operation High range (HR) IOs support 1.2 V to 3.3 V High performance (HP) IOs support 1.2 V to 1.8 V (7z030, 7z045, and 7z100 devices) High-performance transceivers capable of up to 12.5 Gb/s (GTX) Low-power mode optimized for chip-to-chip interfaces Advanced transmit pre- and post-emphasis, and receiver linear (CTLE) and decision feedback equalization (DFE), including adaptive equalization for additional margin

36 Kb block RAM

Digital signal processing DSP48E1 Slice

Clock management

Configurable I/Os

Low-power gigabit transceivers (7z030, 7z045, and 7z100 devices)

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Analog-to-digital converter (XADC)

Dual 12-bit 1 MSPS analog-to-digital converters (ADCs) Up to 17 flexible and user-configurable analog inputs On-chip or external reference option On-chip temperature (4C max error) and power supply (1% max error) sensors Continuous JTAG access to ADC measurements Compatible to the PCI Express base specification 2.1 with Endpoint and Root Port capability Supports Gen1 (2.5 Gb/s) and Gen2 (5.0 Gb/s) speeds Advanced configuration options, advanced error reporting (AER), and end-to-end CRC (ECRC) advanced error reporting and ECRC features

Integrated interface blocks for PCI Express designs (7z030, 7z045, and 7z100 devices)

1.4 Interconnect Features and Description

Zynq-7000 AP SoC devices uses a variety of interconnect technologies, optimized to the specific communication needs of the functional blocks. For more information, refer to the block diagram in Figure 1-1 or a more detailed diagram in Figure 5-1.

1.4.1 PS Interconnect Based on AXI High Performance Data Path Switches

OCM interconnect

Provides access to the 256 KB memory from the central interconnect and the PL CPUs and ACP interfaces have the lowest latency access to OCM via the SCU The central interconnect is 64-bits, connecting the IOP and DMA controller to the DDR memory controller, on-chip RAM, and the AXI_GP interfaces (via their switches) for the PL logic Connects the local DMA units in the Ethernet, USB and SD/SDIO controllers to the central interconnect Connects masters in the PS to the IOP

Central interconnect

1.4.2 PS-PL Interfaces

The PS-PL interface contains all the signals available to the PL designer for integrating the PL-based functions and the PS. There are two types of interfaces between the PL and the PS. 1. Functional interfaces which include AXI interconnect, extended MIO interfaces (EMIO) for most of the I/O peripherals, interrupts, DMA flow control, clocks, and debug interfaces. These signals are available for connecting with user-designed IP blocks in the PL.

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2.

Configuration signals which include the processor configuration access port (PCAP), configuration status, single event upset (SEU) and Program/Done/Init. These signals are connected to fixed logic within the PL configuration block, providing PS control.

AXI functional interfaces: AXI_ACP

One 64-bit cache coherent master port in the PL Connects to the snoop control unit for cache coherency between the CPUs and the PL 32-bit or 64-bit data master interfaces (independently programmed) Efficient resizing in 32-bit slave interface configuration mode Efficient upsizing to 64-bits for aligned 32-bit transfers in 32-bit slave interface configuration mode Automatic expansion to 64-bits for unaligned 32-bit transfers in 32-bit slave interface configuration mode Dynamic command upsizing translation between 32-bit and 64-bit interfaces, controllable via AxCACHE[1] Separate R/W programmable issuing capability for read and write commands Programmable release threshold of write commands Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS Smoothing out of long-latency transfers using 1 KB (128 by 64 bit) data FIFOs for both reads and writes QoS signaling available from PL ports Command and data FIFO fill-level counts available to the PL Standard AXI 3.0 interfaces supported Large slave interface read acceptance capability in the range of 14 to 70 commands (burst length dependent) Large slave interface write acceptance capability in the range of 8 to 32 commands (burst length dependent) Two, 32-bit master interfaces Two, 32-bit slave interfaces Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS Standard AXI 3.0 interfaces supported

AXI_HP, four high performance/bandwidth master ports in the PL

AXI_GP, four general purpose ports

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1.5 System Software

Xilinx provides device drivers for all of the I/O peripherals. These device drivers are provided in source format and support bare-metal or stand alone and Linux. An example first-stage boot loader (FSBL) is also provided in source code format. The source drivers for stand alone and FSBL are provided as part of the Xilinx IDE Design Suite Embedded Edition. The Linux drivers are provided via the Xilinx Open Source Wiki at http://wiki.xilinx.com Refer to UG821, Zynq-7000 Software Developers Guide for additional information. In addition, Xilinx Alliance Program partners provide system software solutions for IP, middleware, operation systems, etc. Please refer to the Zynq-7000 landing page at http://www.xilinx.com/zynq for the latest information.

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Signals, Interfaces, and Pins

2.1 Introduction
This chapter identifies the user visible signals and interfaces in Zynq-7000 AP SoC devices. The interfaces and signals are organized into major groups as shown in Figure 2-1. The Zynq-7000 AP SoC devices consist of a Processing System (PS) with a Xilinx Artix-7 or Kintex-7 based Programmable Logic (PL) block.

2.1.1 Notices
7z010 CLG225 Device
This device supports 32 MIO pins and at most one Ethernet interface through the MIO pins. This is shown in the MIO table in 2.5.4 MIO-at-a-Glance Table. One or both of the Ethernet controllers can interface to logic in the PL.

PS-PL Voltage Level Shifters

All of the signals and interfaces that go between the PS and PL traverse a voltage boundary. These input and output signals are routed through voltage level shifters that must be enabled and disabled during the power-up and power-down sequences of the PL. For more information on the voltage level shifters, refer to section 2.7.1 Clocks and Resets.

Pin Timing and Voltage Specifications

Refer to the Zynq-7000 AP SoC Data Sheet for timing and pin voltage information.

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X-Ref Target - Figure 2-1

Zynq 7000 Device Boundary

Processing System (PS)

AXI Interfaces M_AXI_GP x2 S_AXI_GP x2 S_AXI_HP x4 S_AXI_ACP x1

Programmable Logic (PL)

PS Signals and Interfaces PS_CLK, POR_RST_N, SRST_N DDR Memory

Misc. PL Signals FCLKs IRQ, Event, Standby DMA Req/Ack

PL Signals User SelectIO XADC Zynq 7z030, 7z045, & 7z100

Multi-gigabit Serial Transceivers (MGTX)

USB Quad-SPI NAND, NOR/SRAM DDR Arb, AXI Idle, SRAM Int FTMD Trace, FTMT Trigs

MIO Pins, EMIO Signals, JTAG GigE, SDIO, SPI, I2C, CAN, UART, GPIO, TTC, SWDT

PS Power Pins
Boot Mode

EMIO MIO JTAG

PL Power Pins

UG585_c2_01_021413

Figure 2-1:

Signals, Interfaces, and Pins

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2.2 Power Pins

The PS and PL power supplies are fully independent, however the PS power supply must be present whenever the PL power supply is active. The PS includes an independent power supply for the DDR I/O and two independent voltage banks for MIO. The power pins are summarized in Table 2-1. The voltage sequencing and electrical specifications are shown in the applicable Zynq-7000 AP SoC data sheet. Also refer to the Zynq-7000 AP SoC packaging and pin documents for more information. Table 2-1: Type Power Pins Pin Name
VCCPINT VCCPAUX PS Power VCCO_DDR VCCO_MIO0 VCCO_MIO1 VCCPLL VCCINT VCCAUX PL Power VCCO_# VCC_BATT VCCBRAM VCCAUX_IO_G# XADC Ground VCCADC, GNDADC GND

Nominal Voltage
1.0V 1.8V 1.2V to 1.8V 1.8V to 3.3V 1.8V to 3.3V 1.8V 1.0V 1.8V 1.8V to 3.3V 1.5V 1.0V 1.8V to 2.0V N/A Ground Internal logic

Power Pin Description

I/O buffer pre-driver DDR memory interface MIO bank 0, pins 0:15 MIO bank 1, pins 16:53 Three PLL clocks, analog Internal core logic I/O buffer pre-driver I/O buffers drivers (per bank) PL decryption key memory backup PL block RAM PL auxiliary I/O circuits Analog power and ground. Digital and analog grounds

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2.3 PS I/O Pins

A summary of the dedicated PS signal pins is shown in Table 2-2. Refer to the applicable Zynq-7000 AP SoC data sheet.

7z010 CLG225 Device Notice

The 7z010 CLG225 device has fewer pins than the other Zynq-7000 AP SoC devices as shown in Table 2-2. Details for DDR and MIO pins can be found in their respective chapters, Chapter 10, DDR Memory Controller and section 2.5.3 MIO Pin Assignment Considerations. There is more information about the 7z010 CLG225 device in section 1.1.3 Notices.

Warning: For MIO pins, the allowable Vin High level voltage depends on the settings of the

slcr.MIO_PIN_xx[IO_Type] and [DisableRcvr] bits. These restrictions and the restrictions for all I/O pins are defined in the Zynq-7000 AP SoC data sheets. Damage to the input buffer can occur when the limits are exceeded. PS Signal Pins Name Type
I I I I/O I/O Ref I/O N/A

Table 2-2: Group

Clock

7z010 Zynq-7000 CLG225 Family Voltage Node Pin Count Pin Count
1 1 1 16 32 1 73 2 1 1 1 16 16 0 51 1 VCCO_MIO0 VCCO_MIO0 VCCO_MIO1 VCCO_MIO0 VCCO_MIO1 VCCO_MIO1 VCCO_DDR ~

Description
System reference clock. See Chapter 25, Clocks. Power on reset, active low. See Chapter 26, Reset System. Debug system reset, active Low. Forces the system to enter a reset sequence. See Chapter 26, Reset System. Refer to section 2.5 PS-PL MIO-EMIO Signals and Interfaces and UG865 Zynq-7000 AP SoC Package and Pinout Guide. Voltage reference for RGMII differential input receivers, refer to UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide. See Chapter 10, DDR Memory Controller. DDR DCI voltage reference pins, refer to UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide . Voltage reference for DDR DQ and DQS differential input receivers, refer to UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide.

PS_CLK PS_POR_B

Reset PS_SRST_B PS_MIO[15:0] MIO PS_MIO[53:16] PS_MIO_VREF PS_DDR_xxx PS_DDR_VR[N,P]

DDR

PS_DDR_VREF

Ref

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2.4 PSPL Voltage Level Shifter Enables

All of the signals and interfaces that go between the PS and PL traverse a voltage boundary. These input and output signals are routed through voltage level shifters that are enabled by the slcr.LVL_SHFTR_EN register. This enable must be managed during the PL power-up and power-down sequences so that they are disabled whenever the PL is powered-down and enabled before the signals are used. The PS must always be powered on when the PL is powered on.

Example: Power-up Sequence

1. 2. 3. 4. 5. Power-up the PL . Refer to the data sheet for voltage sequencing requirements. The slcr.LVL_SHFTR_EN register should be equal to 0x0 . Program the PL . Keep the slcr.LVL_SHFTR_EN register = 0x0 . Wait for the PL to be programmed . Read devcfg.INT_STS [PCFG_DONE_INT] until = 1 to indicate that the DONE signals has asserted. Enable the level shifters . Write 0x0F to the slcr.LVL_SHFTR_EN register. Begin to use the signals and interfaces between the PS and PL.

Example: Power-down Sequence

1. 2. 3. 4. Stop using the signals and interfaces between the PS and PL . Disable the voltage level shifters . Write 0x0 to the slcr.LVL_SHFTR_EN register. Power-down the PL . Refer to the data sheet for voltage sequencing requirements. Leave the slcr.LVL_SHFTR_EN register = 0x0 when the PL is powered down .

Note: Functionally, there is no reason to enable the voltage level shifters until the PL is fully

configured. The PS does not allow the voltage level shifters to be enabled until the PL global signal, GHIGH, is High. The PL is fully programmed when the PL DONE signal is High. Both GHIGH and DONE are tracked as interrupts in the DevC subsystem.

2.5 PS-PL MIO-EMIO Signals and Interfaces

The MIO is fundamental to the I/O peripheral connections due to the limited number of MIO pins. Software programs the routing of the I/O signals to the MIO pins. The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface. This is useful to gain access to more device pins (PL pins) and to allow an I/O peripheral controller to interface to user logic in the PL. See Figure 2-2.

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X-Ref Target - Figure 2-2

EMIO
Interface

PS PL

PL
AHB Masters

PL User Pins

AHB Slaves

APB Slaves

MIO Multiplexer

UG585_c2_02_101612

Figure 2-2:

MIO-EMIO Overview

2.5.1 I/O Peripheral (IOP) Interface Routing

The I/O multiplexing of the I/O controller signals differs; that is, some IOP signals are solely available on the MIO pin interface. Most of the signals are available via MIO or EMIO. Some of the interface signals are only accessible via EMIO. The routing capabilities for each I/O peripheral is shown in Table 2-3, The MIO pin assignment possibilities are illustrated in section 2.5.4 MIO-at-a-Glance Table. Table 2-3: I/O Peripheral MIO-EMIO Interface Routing MIO Routing
Clock In, Wave Out. One pair of signals from each counter. Clock In, Reset Out Parallel NOR/SRAM and NAND Flash Serial, dual and quad modes 50 MHz Up to 54 I/O channels (GPIO Banks 0 and 1)

Peripheral
TTC [0,1] SWDT SMC Quad-SPI [0,1] SDIO [0,1] GPIOs

EMIO Routing
Clock In, Wave Out. Three pairs of signals from each counter. Clock In, Reset Out Not available Not available 25 MHz 64 GPIO channels with input, output, 3-state control (GPIO banks 2 and 3)

Cross Reference
See Chapter 8, Timers See Chapter 8, Timers See Chapter 11, Static Memory Controller See Chapter 12, Quad-SPI Flash Controller See Chapter 13, SD/SDIO Controller See Chapter 14, General Purpose I/O (GPIO)

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PS I/O Peripherals (IOP)

PS MIO Pins

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Table 2-3:

I/O Peripheral MIO-EMIO Interface Routing (Contd) MIO Routing

Host, device, and OTG RGMII v2.0 50 MHz ISO 11898 -1, CAN 2.0A/B Simple UART: Two pins (TX/RX) SCL, SDA {0, 1} TCK, TMS, TDI, TDO Up to 16-bit data

Peripheral
USB [0,1] Ethernet [0,1] SPI [0,1] CAN [0,1] UART [0,1] I2C [0,1] PJTAG Trace Port IU Notes:

EMIO Routing
Not available MII/GMII (1) Available Available TX, RX, DTR, DCD, DSR, RI, RTS and CTS SCL, SDA {0, 1} TCK, TMS, TDI, TDO, 3-state for TDO Up to 32-bit data

Cross Reference
See Chapter 15, USB Host, Device, and OTG Controllers See Chapter 16, Gigabit Ethernet Controller See Chapter 17, SPI Controller See Chapter 18, CAN Controller See Chapter 19, UART Controller See Chapter 20, I2C Controller See Chapter 27, JTAG and DAP Subsystem See Chapter 28, System Test and Debug

1. When the Ethernet MII/GMII interface is routed through EMIO, other MII interfaces (e.g., RMII, RGMII, and SGMII) can be derived using appropriate shim logic in the PL that attaches to PL pins.

2.5.2 IOP Interface Connections

For most peripherals, there is flexibility in where the I/O signals can be mapped. The routing capabilities are shown in Figure 2-4. For example, the XPS design software includes up to 12 possible MIO port mappings for CAN, or, if selected, a path to the EMIO interface. The peripheral system connection diagram is shown in Figure 2-3. The majority of the I/O signals for PS peripherals, other than USB, can be routed to either the PS pins through the MIO, or to the PL pins through the EMIO. Most peripherals also maintain the same protocol between MIO and EMIO, except Gigabit Ethernet. To reduce pin count, a 4-bit RGMII interface runs through the MIO at a 250 MHz data rate (125 MHz clock with a double data rate). The route through the EMIO includes an 8-bit GMII interface running at a 125 MHz data rate. The USB, Quad-SPI, and SMC interfaces are not available to the EMIO interface to the PL. On the interconnect side, the USB, Ethernet and SDIO peripherals are connected to the central interconnect to service the six DMA masters. Software accesses the slave-only Quad-SPI and SMC peripherals via the AHB interconnect. The GPIO, SPI, CAN, UART, and I2C save-only controllers are accessed via the APB bus. All control and status registers are also accessed via the APB interconnect except for the SDIO controllers which each have two AHB interfaces. This architecture is designed to balance the bandwidth needs of each controller interface.

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X-Ref Target - Figure 2-3

WAVE_OUT

SWDT

TTC 1, 0

CLK_IN RESET_OUT CLK_IN

IOPs PS
S
AHB 32 APB AHB 32 APB

MIO
MIO [0]

DMA Regs DMA Regs

USB 0

to EMIO

ULPI 0 ULPI 1 MDIO 0

USB 1

MIO [1]
Boot Devices PLL VMODE

Central Interconnect
AXI 32

AHB 32 APB AHB 32 APB AHB 32

DMA Regs DMA Regs DMA Regs

GigE 0

Comm Port Comm Port

RGMII 0

MIO [2]

Boot Mode Pins:

MIO[5:2] Flash/JPEG

RGMII 1

GigE 1

GMII via EMIO

MIO [6]

MIO[6] PLL Bypass

S S

SDIO 0

SDIO 0 SDIO 1

AHB 32

DMA Regs DMA

MIO [7]

AHB 32 AHB 32 AXI 32 AXI 32 APB AXI 32

SDIO 1
to EMIO QSPI 0

MIO[8:7] Voltage Mode

Slave Interconnect
AXI 32

M S M M

MIO [8]

APB

Regs DMA Regs Data Path Regs

Quad SPI 0

Quad SPI 1 NAND NOR/SRAM

ONFi Parallel

QSPI 1

MIO [9]

Zynq Device Pins

APB

SMC

MIO [10]

To APB slave ports for Regs

M M

APB

Control, Status Regs

GPIO Banks 0 & 1 GPIO Banks 2 & 3 SPI {0, 1}

GPIO

MIO [51]

Slave
AXI 32

M S M M M

APB APB APB APB

CAN {0, 1} UART {0, 1} I2C {0, 1}

MIO [52]

MIO [53]
Dervice Boundary

EMIO

Programmable Logic (PL)

Figure 2-3: I/O Peripherals System Diagram

UG585_c2_03_071012

2.5.3 MIO Pin Assignment Considerations

Normally, each pin is assigned to one function. One exception to this is the dual use boot mode strapping resistors (MIO [2:8]). There are several important MIO pin assignment considerations. The MIO-at-a-Glance table, the interface routing table, and these pin assignment considerations are helpful when doing pin planning.

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Interface Frequencies: The clocking frequency for an interface usually depends on device speed grade and whether the interface is routed via MIO or EMIO. The possible routing paths for each interface are listed in Table 2-3, page 46. The maximum clock frequency that can be used for each speed grade and routing path are defined in the Zynq-7000 AP SoC data sheets. Two MIO Voltage Banks: The MIO pins are split across two independently configured sets of I/O buffers: Bank 0, MIO[15:0] and Bank 1, MIO[53:16]. The signalling voltage is initially configured using the VMODE boot mode strapping pins. Each bank can be configure for 1.8V signalling or 2.5V/3.3V. Boot Mode Strapping Pins: These pins can be assigned to I/O peripherals in addition to functioning as boot mode pins. MIO pins [8:2], define the boot device, the initial PLL clock bypass mode, and the voltage mode (VMODE) for the MIO banks. The strapping pins are sampled a few PS_CLK clock cycles after the PS_POR_B reset signal de-asserts. The board design ties these signals to VCC or ground using 20 K pull-up and pull-down resisters. More information about the boot mode pin settings is provided in Chapter 6, Boot and Configuration. I/O Buffer Output Enable Control: The output enable for each MIO I/O buffer is controlled by a combination of the setting of the three-state override control bit, the selected signal type (input-only or not), and the state of the peripheral controller. The three-state override bit can be controlled from either of two places: the slcr.MIO_PIN[TRI_ENABLE] register bit or the slcr.MIO_MST_TRI register bits. These bits control the same flip-flop to help control the three-state signal of the I/O buffer. The I/O buffer output is enabled when the three-state flip-flop control = 0 and the signal is an output-only or the I/O peripheral desires to drive a signal configured as I/O. Boot from SD Card: The BootROM expects the SD card to be connected to MIO pins 40 through 45 (SDIO 0 interface). Static Memory Controller (SMC) Interface: Only one SMC memory interface can be used in a design. The SMC controller consumes many of the MIO pins and neither of the SMC memory interfaces can be routed to the EMIO. For example, if an 8-bit NAND Flash is implemented, then Quad-SPI, is not available and the test port is limited to 8-bits. If a 16-bit NAND Flash is implemented, then additional pins are consumed. Ethernet 0 is not available. The SRAM/NOR interface consumes up to 70% of the MIO pins, eliminating Ethernet and USB 0. The SRAM/NOR upper address pins are optional, as appropriate for the attached device. Also note that the SMC interface straddles the two MIO voltage banks. Quad-SPI Interface: The lower memory Quad-SPI interface (QSPI_0) must be used if the Quad-SPI memory subsystem is to be used. The upper interface (QSPI_1) is optional and is only used for a two-memory arrangement (parallel or stacked). Do not use the Quad-SPI 1 interface alone. MIO Pins [8:7] are Outputs: These MIO pins are available as output only. GPIO channels 7 and 8 can only be configured as outputs. MIO Pins in 7z010 CLG225 Device: This device has 32 MIO pins, 0:15, 28:39, 48, 49, 52, and 53. All other Zynq-7000 AP SoC devices include all 54 MIO pins and all devices have the same EMIO interface functionality. Refer to section 1.1.3 Notices. The 32 MIO pins available in the 7z010 CLG225 device restrict the functionality of the PS:

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Either one USB or one Ethernet controller via MIO No boot from SD Card No NOR/SRAM interfacing Width of NAND Flash limited to 8 bits

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2.5.4 MIO-at-a-Glance Table

Table 2-4 presents MIO information in a compact format for easy reference; the gray boxes represent signals that are not usable in the 7z010 CLG225 device. Refer to section PS-PL MIO-EMIO Signals and Interfaces for background information. This section also includes important pin assignment considerations. Table 2-4: MIO-at-a-Glance MIO Bank 0
0 1 2 3 4 5 6 7 8 9 BOOT_MODE
Device pll V

MIO Bank 1

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
Pins not available in 7z010 CLG225. Not in CLG225.

The 20k ohm Boot Mode pull-up/down resistors tx are sampled at Reset.

Ethernet 0
tx data tx rx ctl ck rx data rx tx ctl ck

Ethernet 1
tx data tx rx ctl ck rx data rx ctl

MDIO ck d

ck

Quad SPI 0
cs cs io io io io s 1 0 0 1 2 3 clk

Quad SPI 1
fb s io io io io ck clk 0 1 2 3 1, 0 da st nx dir ta p t

USB 0
data ck data da st nx dir ta p t

USB 1
data ck data

SPI SDIO

SPI 1 SDIO 1

SPI 0 SDIO 0

SPI 1 SDIO 1

SPI 0 SDIO 0

SPI 1 SDIO 1

SPI 0 SDIO 0

SPI 1 SDIO 1

mo mi ss ss ss mi ss ss ss mo mo mi ss ss ss mi ss ss ss mo mo mi ss ss ss mi ss ss ss mo mo mi ss ss ss ck ck ck ck ck ck ck si so 0 1 2 so 0 1 2 si si so 0 1 2 so 0 1 2 si si so 0 1 2 so 0 1 2 si si so 0 1 2 1, 0 c c c c c c c io io io io io io io io io io io io io io io io io io io io io io io io io io io io ck m ck m ck m m ck m ck m ck m ck 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d d d d d d d

SD Card Detect and Write Protect are available in any of the shaded positions in any combination of the four signals.
0 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

SD Card Power Controls are available on an odd/even pin basis that corresponds to SDIO controllers 0 and 1.
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

SMC interface choice: NOR/SRAM or NAND Flash

cs no 0 te cs alewe data oe we data io 4 ~ 7 io io io cle rd 2 0 1 da ta io bu 3 sy address [0:24] io 8 ~ 15

NOR/SRAM NAND Flash

MIO Pin 1 is optional: addr 25, cs 1 or gpio

0 1 2 3 4 5 6 7 8 9

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
rx tx rx tx tx rx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx rx tx tx rx

CAN

0 1

tx rx

CAN External Clocks are optionally available on any pin in any combination

UART I2C System Timers

0 1 0 1 TTC 0 TTC 1 SWDT

rx tx tx rx ck d ck d Clk In, Wave Out Clk In, Wave Out tx rx

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d w ck w ck

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d w ck w ck

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d w ck w ck

rx tx tx rx ck d ck d

rx tx tx rx ck d ck d

Clk In, Reset Out ck r

ck r

ck r

ck r ck r

GPIOs are available for each MIO pin. Pins 0 ~ 31 are controlled by GPIO bank 0. Pins 32 ~ 53 are controlled by GPIO bank 1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 t t t t t t t t t t t t t t t t PJTAG Interface di do ck ms di do ck ms di do ck ms di do ck ms ck ctl 8 9 10 11 12 13 14 15 2 3 0 1 4 5 6 7 2 3 ck ctl 0 1

Clock and Control Data

Trace Port User Interface

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2.5.5 MIO Signal Routing

Signal routing through the MIO is controlled by the MIO_PIN_[53:0] configuration registers located in the slcr registers set. The MIO multiplexes and de-multiplexes the various input and output signals to the MIO pins using four stages of multiplexing, as shown in Figure 2-4. The high-speed data signals (such as RGMII for Gigabit Ethernet and ULPI for USB) are routed through only one multiplexer stage. The slower signals (such as the UART and I2C ports) are routed through all four multiplexer stages. The routing for each MIO pin is independently controlled by multiple bit fields in each MIO_PIN register.
X-Ref Target - Figure 2-4

Level 3 Muxing
0 1 2 3 4 5 6 7 Input Tie-Offs To Program Muxing Levels, refer to the select fields in Registers MIO_PIN_[53:00] EMIO Other MIO Pins

Inputs to Controllers Controller Input

Controller Outputs

Level 2 Muxing

Controller Outputs

0 1 2 3

Level 1 Muxing

Outputs from Controllers

Controller Output

0 1

Level 0 Muxing

MIO Pin Controller Output

0 1

Notice: Not all mux inputs are populated with controller outputs.

UG585_c2_04_042312

Figure 2-4:

MIO Signal Routing

Any of the MIO pins can be programmed to be an external CAN controller reference clock using the CAN_MIOCLK_CTRL register.

2.5.6 Default Logic Levels

The inputs to the I/O peripherals are driven with default values when another source is not routed to either the MIO or the EMIO. If an input is routed to EMIO, but the PL is powered down, then the same default value is driven to the I/O peripheral. (See Figure 2-5.) For MIO-only signals, the default signal input is driven when the MIO multiplexer does not route the signal to an MIO pin. For MIO-EMIO signals, the default signal input is driven when the MIO multiplexer does not route the signal to an MIO pin (the signal defaults to the EMIO interface) and when the signal is programmed to be routed through the EMIO, but the PL either does not drive the signal (not configured) or is not able to drive it (powered down).

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The default input signal logic levels are designed to be benign to the I/O peripheral. As a precaution, the related peripheral core should also be disabled when not in use. The logic levels are shown in the signal tables in each chapter for each I/O peripheral.
X-Ref Target - Figure 2-5

Programmable Logic EMIO Input

EMIO Output

Input Signal Tie-Offs

Voltage translation and drives a default value to the MIO mux.

MIO Mux Subsystems With MIO And EMIO Routing

EMIO Inputs

MIO Pins
0 1

Subsystems With MIO-only Routing

Hardcoded Tie-Offs No Interface Selected

UG585_c2_05_042312

Figure 2-5:

Non-selected Controller Inputs

2.5.7 MIO Pin Electrical Parameters

The MIO_PIN registers include bit fields to control the electrical pin characteristics of each I/O Buffer (GPIOB). This includes I/O buffer signaling voltage, drive strength, 3-state control, pull-up resistor, and HSTL enable. These are summarized in Table 2-5. Refer to the applicable Zynq-7000 AP SoC data sheet for electrical specifications. Table 2-5: MIO I/O Buffer Programmable Parameters MIO_PIN Register Bit Field
I/O_Type DisableRcvr Speed 3-State Control Pull-up

I/O Buffer Parameter

Signaling HSTL Receiver Drive Strength 3-State Control Pull-up

Selections
LVCMOS (18, 25, 33), HSTL Enable, Disable Fast, Slow Enable, Disable Enable, Disable

Comments
Selects the drive and receiver type Enable when IO_Type = HSTL Selects edge rate for all I/O types Enables 3-state for all I/O types Enables pull-up for all I/O types

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WARNING! The allowable Vin High level voltage depends on the settings of the

slcr.MIO_PIN_xx[IO_Type] and [DisableRcvr] bits. The restrictions are defined in the Zynq-7000 AP SoC data sheets. Damage to the input buffer can occur when the limits are exceeded.

VREF Source Considerations

The VREF pins for HSTL signaling can be from an internal or external source. The user should choose based system design needs. The reference source is selected using the slcr.GPIOB_CTRL [VREF_SW_EN] register bit.

2.6 PSPL AXI Interfaces

The PS side of the AXI interfaces are based on the AXI 3 interface specification. Each interface consists of multiple AXI channels. The interfaces are summarized in Table 2-6. Over a thousand signals are used to implement these nine PL AXI interfaces.

Note: The PL level shifters must be enabled via LVL_SHFTR_EN before PL logic communication can
occur, refer to section 2.7.1 Clocks and Resets. PL AXI Interfaces Interface Description
General Purpose (AXI_GP) General Purpose (AXI_GP) Accelerator Coherency Port, cache-coherent transaction (ACP) High Performance ports (AXI_HP) with read/write FIFOs and two dedicated memory ports on DDR controller and a path to the OCM. The AXI_HP interfaces are known also as AFI.

Table 2-6: Interface Name

Master
PS PS PL PL PL PL PL PL PL

Slave
PL PL PS PS PS PS PS PS PS

Signals
Chapter 5, Interconnect has a section to describe each of these interfaces. The AXI signals are listed individually in section 5.6 PS-PL AXI Interface Signals. The AXI_ACP interface is also described in multiple places in Chapter 3, Application Processing Unit, including section 3.5.1 PL Co-processing Interfaces. The PS interconnect is shown in Figure 5-1.

M_AXI_GP0 M_AXI_GP1 S_AXI_GP0 S_AXI_GP1 S_AXI_ACP S_AXI_HP0 S_AXI_HP1 S_AXI_HP2 S_AXI_HP3

2.7 PSPL Miscellaneous Signals

The programmable logic interface group contains miscellaneous interfaces between PS and the PL. An input is driven by the PL and an output is driven by the PS. Signals might have suffixes where an 'N' suffix indicates an active Low signal; otherwise the signal is active High. A 'TN suffix indicates an active Low 3-state enable signal and is an output to the PL. Output signals to the PL are always driven to either a High or Low level state.

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PS-PL signal groups are identified in Table 2-7. Table 2-7: PS-PL Signal Groups Signal Name
FCLKx IRQF2Px and IRQP2Fx EVENTx FPGA, DDR, EMIO DMACx EMIOx

PS-PL Signal Group

PL Clocks and Resets Interrupts Events IdleAXI, DDR ARB, SRAM Interrupt, FPGA DMA Controller EMIO Signals

Reference
2.7.1 Clocks and Resets 2.7.2 Interrupt Signals 2.7.3 Event Signals 2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals 2.7.5 DMA Req/Ack Signals Table 2-3

Note: The PL level shifters must be enabled via the slcr.LVL_SHFTR_EN register before PL logic
communication can occur, refer to section 2.7.1 Clocks and Resets.

2.7.1 Clocks and Resets

Clocks
The PS clock module provides four frequency-programmable clocks (FCLKs) to the PL that are physically spread out along the PSPL boundary. The clocks can also be individually controlled. The FCLK clocks can be routed to PL clock buffers to serve as a frequency source.

Note: There is no guaranteed timing relationship between any of the four PL clocks and between

any of the other PS-PL signals. Each clock is independently programmed and operated. The FCLKCLKTRIGN[3:0] signals are currently not supported. They must be tied to ground in the PL. The FCLK clocks are described in Chapter 25, Clocks.

Resets
The PS reset subsystem provides four programmable reset signals to the PL. The reset signals are controlled by writing to the slcr.FPGA_RST_CTRL SLCR[FPGA[3:0]_OUT_RST] bit fields. The resets are independently programmed and are completely independent of the PL clocks and all other PS-PL signals. The PS reset subsystem is described in Chapter 26, Reset System. The PL clocks and resets are summarized in Table 2-8. Table 2-8:
PL Clocks PL Clock Throttle Control PL Resets

PL Clock and Reset Signals Type PL Signal Name

FCLKCLK[3:0] FCLKCLKTRIG [3:0] FCLKRESETN [3:0]

I/O
O I O

Reference
Chapter 25, Clocks Chapter 26, Reset System

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2.7.2 Interrupt Signals

The interrupts from the processing system I/O peripherals (IOP) are routed to the PL and assert asynchronously to the FCLK clocks. In the other direction, the PL can asynchronously assert up to 20 interrupts to the PS. Sixteen of these interrupt signals are mapped to the interrupt controller as a peripheral interrupt where each interrupt signal is set to a priority level and mapped to one or both of the CPUs. The remaining four PL interrupt signals are inverted and routed to the nFIQ and nIRQ interrupt directly to the signals to the private peripheral interrupt (PPI) unit of the interrupt controller. There is an nFIQ and nIRQ interrupt for each of two CPUs. The PS to PL and PL to PS interrupts are listed in Table 2-9. Details of the interrupt signals are described in Chapter 7, Interrupts. Table 2-9: Type
PL to PS Interrupts PS to PL Interrupts

PL Interrupt Signals PL Signal Name I/O

IRQF2P[7:0] IRQF2P[15:8] IRQF2P[19:16] IRQP2F[27:0] I I I O SPI: Numbers [68:61]. SPI: Numbers [91:84]. PPI: nFIQ, nIRQ (both CPUs). Pl Logic. These signals are received from the I/O peripherals and are forwarded to the interrupt controller. These signals are also provided as outputs to the PL.

Destination

2.7.3 Event Signals

The PS supports processor events to and from the PL (see Table 2-10). These signals are asynchronous to the PS and FCLK clocks. For details on these signals, see Chapter 3, Application Processing Unit. Table 2-10: Type
Events

PL Event Signals PL Signal Name

EVENTEVENTI EVENTEVENTO EVENTSTANDBYWFE[1:0]

I/O
I O O O

Description
Causes one or both CPUs to wakeup from a WFE state. Asserted when one of the CPUs has executed the SEV instruction. CPU standby mode: asserted when a CPU is waiting for an event. CPU standby mode: asserted when a CPU is waiting for an interrupt.

Standby

EVENTSTANDBYWFI[1:0]

2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals

The idle AXI signal to the PS is used to indicate that there are no outstanding AXI transactions in the PL. Driven by the PL, this signal is one of the conditions used to initiate a PS bus clock shut-down by ensuring that all PL bus devices are idle. The DDR urgent/arb signal is used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller.

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Table 2-11:

PL AXI Idle, DDR Urgent/Arb and SRAM Interrupt Signals PL Signal Name
FPGAIDLEN DDRARB[3:0] EMIOSRAMINTIN

Type
Idle PL AXI interfaces DDR Urgent Signal SRAM

I/O
I I I

Destination
Central interconnect clock disable logic DDR memory controller

Reference

Chapter 10, DDR Memory Controller

2.7.5 DMA Req/Ack Signals

There are four sets of DMA controller flow control signals for use by up to four PL slaves connected via the M_AXI_GP interfaces (see Table 2-11). These four sets of flow control signals correspond to DMA channels 4 through 7, see Chapter 9, DMA Controller. Table 2-12: Type
Clock and Reset

PL DMA Signals Signal

Clock Ready Valid Type Last Ready

PL Signal Name
DMA[3:0]ACLK DMA[3:0]DRREADY DMA[3:0]DRVALID DMA[3:0]DRTYPE[1:0] DMA[3:0]DRLAST DMA[3:0]DAREADY DMA[3:0]DAVALID DMA[3:0]DATYPE[1:0]

I/O
I O I I I I O O

Reference
9.2.7 PL Peripheral Request Interface

Request

Chapter 9, DMA Controller

Acknowledge

Valid Type

2.8 PL I/O Pins

A summary of the PL I/O pins is shown in Table 2-13. Refer to the applicable Zynq-7000 AP SoC data sheet and Zynq-7000 AP SoC packaging and pin documents for more information. For more information on multi-gigabit serial transceivers pins, see the Pin Description and Design Guidelines section in UG476, 7 Series FPGAs GTX Transceivers User Guide. (Four to sixteen transceivers are available in the Kintex-based Zynq 7z030, 7z045, and 7z100 devices.)

7z010 CLG225 Device Notice

The 7z010 CLG225 device has fewer pins than the other Zynq-7000 AP SoC devices. For the 7z010 CLG225, DXN is tied to ground, Bank 34 has 8 I/Os, and Bank 35 has 46 I/Os. There are also only four pairs of XADC signals.

Warning: The allowable Vin High level voltages are defined in the Zynq-7000 AP SoC data sheets.
Damage to the input buffer can occur when the limits are exceeded.

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Table 2-13: Group

PL Pin Summary Name

IO_LXXY_#, IO_XX_# MGTXRX[P,N] MGTXTX[P,N] MGTAVCC_G#

Type
I/O I O I I I I I I I/O I/O I I I

Description
Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended. Differential receive and transmit ports. Multi-Gigabit Serial Transceiver pins. Four transceivers are available in the Zynq-7000 AP SoC 7z030 device and 16 in the 7z045 and 7z100 devices. 1.0V analog power-supply pin for receiver and transmitter internal circuits. 1.2V analog power-supply pin for the transmit driver. 1.8V auxiliary analog Quad PLL voltage supply for the transceivers. Positive differential reference clock for the transceivers. Negative differential reference clock for the transceivers. Precision reference resistor pin for internal calibration termination. See Chapter 27, JTAG and DAP Subsystem. Refer to the 7-series documentation. Pre-configuration I/O standard type for the dedicated configuration bank 0. Active Low input enables internal pull-ups during configuration on all SelectIO pins. Dedicated differential analog inputs.

User I/O Pins

Multi-Gigabit Serial Transceivers

MGTAVTT_G# MGTVCCAUX_G# MGTREFCLK0/1P MGTREFCLK0/1N MGTAVTTRCAL MGTRREF PL_TCK, PL_TMS, PL_TDI, PL_TDO DONE, INIT_B, PROGRAM_B

N/A Precision reference resistor pin for internal calibration termination.

PL JTAG

Configuration

CFGBVS PUDC_B VP, VN

XADC

VREFP, VREFN AD[15:0]P, AD[15:0]N MRCC

N/A Reference input (1.25V) and ground. I 16 differential auxiliary analog inputs. Clock capable I/Os driving BUFRs, BUFIOs, BUFGs and MMCMs/PLLs. In addition, these pins can drive the BUFMR for multi-region BUFIO and BUFR support. These pins become regular user I/Os when not needed as a clock. Clock capable I/Os driving BUFRs, BUFIOs and MMCMs/PLLs. These pins become regular user I/Os when not needed for clocks. Four memory byte groups. DDR DQS strobe pin that belongs to the memory byte group T0-T3. Temperature-sensing diode pins. Tie to VCCO. Tie to ground.

Multi-function

SRCC T[3:0] T[3:0]_DQS

I I I I I I

Temperature Reserved

DXP, DXN RSVDVCC RSVDGND

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Chapter 3

Application Processing Unit

3.1 Introduction
3.1.1 Basic Functionality
The application processing unit (APU), located within the PS, contains two ARM Cortex A9 processors with NEON co-processors that are connected in an MP configuration sharing a 512 KB L2 cache. Each processor is a high-performance and low-power core that implements two separate 32 KB L1 caches for instruction and data. The Cortex-A9 processor implements the ARMv7-A architecture with full virtual memory support and can execute 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in the Jazelle state. The NEON coprocessor's media and signal processing architecture adds instructions that target audio, video, image and speech processing, and 3D graphics. These advanced single instruction multiple data (SIMD) instructions are available in both ARM and Thumb states. A block diagram of the APU is shown in Figure 3-1. The two Cortex A9 processors within the APU are organized in an MP configuration with a snoop control unit (SCU) responsible for maintaining L1 cache coherency between the two processors and the ACP interface from the PL. To increase performance, there is a shared unified 512 KB level-two (L2) cache for instruction and data. In parallel to the L2 cache, there is a 256 KB on-chip memory (OCM) module that provides a low-latency memory. An accelerator coherency port (ACP) facilitates communication between the programmable logic (PL) and the APU. This 64-bit AXI interface allows the PL to implement an AXI master that can access the L2 and OCM while maintaining memory coherency with the CPU L1 caches. The unified 512 KB L2 cache is 8-way set-associative and allows users to lock the cache content on a line, way, or master basis. All accesses through the L2 cache controller can be routed to the DDR controller or can be sent to other slaves in the PS or PL depending on their address. To reduce latency to the DDR memory, there is a dedicated port from the L2 controller to the DDR controller. Debug and trace capability is built into the two processor cores and interconnects as a part of the CoreSight debug and trace system. The user can control and interrogate both processors and the memory through the debug access port (DAP). Furthermore, 32-bit AMBA trace bus (ATB) masters from the two processors are funneled with other ATB masters, such as Instrumentation Trace Macrocell (ITM) and Fabric Trace Monitor (FTM), to generate the unified PS trace through the on-chip embedded trace buffer (ETB) or the trace-port interface units (TPIU).

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X-Ref Target - Figure 3-1

APU

Accelerator Coherency Port (ACP)

PL Fabric M
Read/Write Requests

CPUs
Snoopable Data buffers and caches
L1 Cache Line Updates

Cache Coherent Transactions S S

Maintain L1 Cache Coherency

SCU

Flush Cache Line to Memory Cache Tag RAM Update

Tag RAM

M0
Cacheable and Noncacheable Accesses

M1 System Interconnect

Cacheable and Noncacheable Accesses to DDR, PL, Peripherals, and PS registers

S OCM M0

Tag RAM

L2 Cache

Data RAM

M1

DDR

System Interconnect
UG585_c3_01_100812

Figure 3-1:

APU Block Diagram

ARM architecture supports multiple operating modes including supervisor, system, and user modes to provide different levels of protection at the application level. The architecture support for TrustZone technology helps to create a secure environment to run applications and protect their contents. TrustZone built into the ARM CPU processor and many peripherals enable a secure system to handle keys, private data, and encrypted information without allowing these secrets to leak to non-trusted programs or users. The APU contains a 32-bit watchdog timer and a 64-bit global timer with auto-decrement features that can be used as general-purpose timers and also as a mechanism to start up the processors from standby mode.

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3.1.2 System-level View

The APU is the most critical component of the system that comprises the PS, the IPs implemented in the PL, and board-level devices such as the external memories and the peripherals. The main interfaces through which the APU communicates to the rest of the system are two interfaces through the L2 controller and an interface to the OCM that is parallel to the L2 cache. See Figure 3-1. All accesses from the dual Cortex-A9 MP system go through the SCU and all accesses from any other master that requires coherency with the Cortex-A9 MP system also need to be routed through the SCU using the ACP Port. All accesses that are not routed through the SCU are non-coherent with the CPU and software has to explicitly handle the synchronization and coherency. Accesses from the APU can target the OCM, DDR, PL, IOP slaves, or registers within the PS sub-blocks. In order to minimize the latency to the OCM, a dedicated master port from the SCU provides direct access by the processors and the ACP to the OCM, offering a latency that is even less than the L2 cache. All APU accesses to the DDR are routed through the L2 cache controller. To improve the latencies of the DDR accesses, there is a dedicated master port from the L2 cache controller to the DDR memory controller that allows all APU-DDR transactions to bypass the main interconnects which is shared with the other masters. All other accesses from the APU that are neither OCM-bound nor DDR-bound go through the L2 controller and are routed through the main interconnect using a second port. The accesses that pass through the L2 cache controller do not have to be cacheable. As shown in Figure 3-2, the APU and its sub-blocks all operate in the CPU_6x4x clock domain. The interfaces from the APU to the OCM and to the main interconnects are all synchronous. The main interconnects can run at 1/2 or 1/3 of the frequency of the CPU. The DDR block is on the DDR_3x clock domain and operates asynchronously to the APU. The ACP port to the APU block includes a synchronizer and the PL master that uses this port can have a clock that is asynchronous to the APU.

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X-Ref Target - Figure 3-2

High Performance AXI Controllers (AXI_HP)

PL Clocks M0
32-/ 64-bit

Cache Coherent ACP Port

M3 M

PL Fabric

General Purpose AXI Masters

M0 M1 ASYNC

General Purpose AXI Slaves

S0 S1

M1
32-/ 64-bit

M2
32-/ 64-bit

32-/ 64-bit

ASYNC

ASYNC

Application Processing Unit

ASYNC

DevC

ASYNC ASYNC DAP ASYNC 4 8 8 1

Cortex-A9
NEON MMU L1 I/D Caches
Instruction Data Snoop

ASYNC

ASYNC

FIFO

FIFO

FIFO

FIFO

Slave Interconnect Switch

AXI_HP to DDR Interconnect

Snoop Control Unit

CPU_6x4x

CPU_2x

L2 Cache
512 KB QoS
64-bit

DMA Controller
M1 CPU_2x

QoS
64-bit

M0

IOP Masters
M

IOP Slave
Reg & Data

OCM Interconnect

QoS

8 QoS

16

IOP
QoS CPU_1x
64-bit 64-bit

8
Read/Write Requests (e.g., 8 reads, 8 writes)

64-bit

On-chip RAM
256 kB

Central Interconnect

ASYNC QoS
32-bit 32-bit

ASYNC ASYNC
Clock Synchronizer

16

DDR Controller

DDR_3x 1 4

8 M1

8 M0

QoS
Quality of Service Priority Clock Domains are specified within Some Blocks

Master Interconnect

M3

M2

CPU_2x
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Figure 3-2:

APU System View Diagram

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3.2 Cortex A9 Processors

3.2.1 Summary
The APU implements a dual-core Cortex A9 MP configuration. Each processor has its own SIMD media processing engine (NEON), memory management unit (MMU), and separate 32 KB level-one (L1) instruction and data caches. Each Cortex-A9 processor provides two 64-bit AXI master interfaces for independent instruction and data transactions to the SCU. Depending on the address and attributes, these transactions are routed to the OCM, L2 cache, DDR memory, or, through the PS interconnect, to other slaves in the PS, or to the PL. Each processor's interface with the SCU includes the required snoop signals to provide coherency between the L1 data caches within the processors and the shared L2 cache for shareable memory. The Cortex A9 and its subsystem also provide complete Trustzone extension, necessary for user security. The Cortex-A9 processor implements the necessary hardware features for program debug and trace generation support. The processor also provides hardware counters to gather statistics on the operation of the processor and memory system. The major sub-blocks within the Cortex-A9 are the central processing unit (CPU), the L1 instruction and data caches, the memory management unit (MMU), the NEON coprocessor, and the core interfaces. Their functions are explained in the following subsections.

3.2.2 Central Processing Unit (CPU)

Each Cortex A9 CPU can issue two instructions in one cycle and execute them out of order. The CPU implements dynamic branch prediction and with its variable length pipeline can deliver 2.5 DMIPs/MHz. The Cortex-A9 processor implements the ARMv7-A architecture with full virtual memory support and can execute 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in the Jazelle hardware acceleration state. Figure 3-3 shows the architecture of the Cortex A9 processor.

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X-Ref Target - Figure 3-3

Cortex A9 Processor
Coresight Debug CoreSight Debug Access Port Profiling Monitor Block Register Rename Stage Program Trace Unit Virtual to Physical Register Pool Dual Instruction Decode Stage Branches Out of Order Multi-issue with Speculation Address Instruction Queue & Dispatch ALU Out of Order Write-back Stage 3 + 1 Dispatch Stage ALU/MUL

Coresight Trace

FPU/NEON

Instruction Queue

Prediction Queue

MemorySystem Instruction Pre-fetch Stage

Fast Loop Mode Branch Prediction Global History Buffer Branch Target Address Cache (BTAC) Return Stack Auto Pre-fetcher TLB MMU

Load-Store Unit Data Cache Store Buffer

Instruction Cache

Instruction Interface

Data Interface
UG585_c3_04_030712

Figure 3-3:

Cortex A9 Architecture

Pipeline
The pipeline implemented in the Cortex-A9 CPU employs advanced fetching of instructions and branch prediction that decouples the branch resolution from potential memory latency-induced instruction stalls. In the Cortex-A9 CPU, up to four instruction-cache lines are pre-fetched to reduce the impact of memory latency on the instruction throughput. The CPU fetch unit can continuously forward two to four instructions per cycle to the instruction decode buffer to ensure efficient superscalar pipeline utilization. The CPU implements a superscalar decoder capable of decoding two full instructions per cycle, and any of the four CPU pipelines can select instructions from the issue queue. The parallel pipelines support concurrent execution across full dual arithmetic units, load-store unit, plus resolution of any branch each cycle. The Cortex-A9 CPU employs speculative execution of instructions enabled by dynamic renaming of physical registers into an available pool of virtual registers. The CPU employs this virtual register renaming to eliminate dependencies across registers without jeopardizing the correct execution of programs. This feature allows code acceleration through an effective hardware based unrolling of

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loops, and increases the pipeline utilization by removing data dependencies between adjacent instructions which also indirectly reduces interrupt latency. In the Cortex-A9 CPU, dependent load-store instructions can be forwarded for resolution within the memory system to further reduce pipeline stalls. The core supports up to four data cache line fill requests that can be through automatic or user-driven pre-fetching. A key feature of this CPU is the out-of-order write back of instructions that enables the pipeline resources to be released independent of the order in which the system provides the required data. Load/store instructions can be issued speculatively before condition of instruction or a preceding branch has been resolved or before data to be written has become available. If the condition required for the execution of the load/store fails, any of the side-effects, such as the action to modify registers, are flushed.

Branch Prediction
To minimize the branch penalty in its highly pipelined CPU, the Cortex A9 implements both static and dynamic branch prediction. Static branch prediction is provided by the instructions and is decided during compilation. Dynamic branch prediction uses the outcome of the previous executions of a specific branch to determine whether the branch should be taken or not. The dynamic branch prediction logic employs a global branch history buffer (GHB) which is a 4096-entry table holding 2-bit prediction information for specific branches and is updated every time a branch gets executed. The branch execution and the overall instruction throughput also benefit greatly from the implementation of a branch target address cache (BTAC) which holds the target addresses of the recent branches. This 512-entry address cache is organized as 2-way 256 entries and provides the target address for a specific branch to the pre-fetch unit before the actual target address is generated based on the calculation of the effective address and its translation to the physical address. Additionally, if an instruction loop fits in four BTAC entries, instruction cache accesses are turned off to lower power consumption.

Note: Both GHB and BTAC RAMs implement parity for protection; however, this support has limited

diagnostic value. Corruption in GHB data or BTAC data does not generate functional errors in the Cortex-A 9 processor. Corruption in GHB data or BTAC data results in a branch misprediction, that is, detected and corrected when the branch gets executed. The Cortex-A9 CPU can predict conditional branches, unconditional branches, indirect branches, PC-destination data-processing operations, and branches that switch between ARM and Thumb states. However, the following branch instructions are not predicted: Branches that switch between states (except ARM to Thumb transitions, and Thumb to ARM transitions). Instructions with the S suffix are not predicted as they are typically used to return from exceptions and have side effects that can change privilege mode and security state. All mode-changing instructions.

Users can enable program flow prediction by setting the Z bit in the CP15 c1 Control register to 1 . Refer to the System Control Register in the ARM Cortex-A9 Technical Reference Manual (see Appendix A, Additional Resources). Before switching the program flow prediction on, a BTAC flush operation must be performed which has the additional effect of setting the GHB into a known state.

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Cortex-A9 also employs an 8-entry return stack cache that holds the 32-bit subroutine return addresses. This feature greatly reduces the penalty of executing subroutine calls and can address nested routines up to eight levels deep.

Instruction and Data Alignment

ARM architecture specifies the ARM instructions as being 32-bits wide and requires them to be word-aligned. Thumb instructions are 16-bits wide and are required to be half-word aligned. Thumb-2 instructions which are 16- or 32-bits wide are also required to be half-word aligned. Data accesses can be unaligned and the load/store unit within the CPU breaks them up to aligned accesses. The data from these accesses are merged and sent to the register file within the CPU as had been requested.

Note: The application processing unit (APU), and the PS as a whole, support only little-endian
architecture for both instruction and data.

Trace and Debug

The Cortex-A9 processor implements the ARMv7 debug architecture as described in the ARM Architecture Reference Manual. In addition, the processor supports a set of Cortex-A9 processor-specific events and system-coherency events. For more information, see Chapter 11, Performance Monitoring Unit in the ARM Cortex-A9 Technical Reference Manual. The debug interface of the processor consists of: A baseline CP14 interface that implements the ARMv7 debug architecture and the set of debug events as described in the ARM Architecture Reference Manual. An extended CP14 interface that implements a set of debug events specific to this processor (explained in the ARM Architecture Reference Manual). An external debug interface connected to an external debugger through a debug access port (DAP).

The Cortex-A9 includes a program trace module that provides ARM CoreSight technology compatible program-flow trace capabilities for either of the Cortex-A9 processors and provides full visibility into the processor's actual instruction flow. The Cortex-A9 PTM includes visibility over all code branches and program flow changes with cycle-counting enabling profiling analysis. The PTM block in conjunction with the CoreSight Design Kit provides the software developer the ability to non-obtrusively trace the execution history of multiple processors and either store this, along with time stamped correlation, into an on-chip buffer, or off chip through a standard trace interface so as to have improved visibility during development and debug. The Cortex A9 processor also implements program counters and event monitors that can be configured to gather statistics on the operation of the processor and the memory system.

3.2.3 Level 1 Caches

Each of the two Cortex-A9 processors has separate 32 KB level-1 instruction and data caches. Both L1 caches have common features that include:

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Each cache can be disabled independently, using the system control coprocessor. Refer to the System Control Register in the ARM Cortex-A9 Technical Reference Manual . The cache line lengths for both L1 caches are 32 bytes. Both caches are 4-way set-associative. L1 caches support 4 KB, 64 KB, 1 MB, and 16 MB virtual memory page. Neither of the two L1 caches supports the lock-down feature. The L1 caches have 64-bit interfaces to the integer core and AXI master ports. Cache replacement policy is either pseudo round-robin or pseudo random. The victim counter is read at time of miss, not allocation and it is incremented on allocation. An invalid line in the set is replaced in preference to using the victim counter. On a cache miss, critical word first filling of the cache is performed. To reduce power consumption, the number of full cache reads is reduced by taking advantage of the sequential nature of many cache operations. If a cache read is sequential to the previous cache read, and the read is within the same cache line, only the data RAM set that was previously read is accessed. Both L1 caches support parity. All memory attributes are exported to external memory systems. Support for TrustZone security exports the secure or non-secure status to the caches and memory system. Upon reset, the contents of both L1 caches are cleared to comply with security requirements

Note: The user must invalidate the instruction cache, the data cache, and BTAC before using them.

It is not required to invalidate the main TLB, even though it is recommended for safety reasons. This ensures compatibility with future revisions of the processor.

The L1 instruction-side cache (I-Cache) is responsible for providing an instruction stream to the Cortex-A9 processor. The L1 I-Cache interfaces directly to the pre-fetch unit which contains a two-level prediction mechanism as described in the Branch Prediction section of this chapter. The L1 instruction cache is virtually indexed and physically tagged. The L1 data-side cache (D-Cache) is responsible for holding the data used by the Cortex-A9 processor. Key features of the L1 D-Cache include: Data cache is physically indexed and physically tagged. D-Cache is non-blocking and therefore, load/store instructions can continue to hit the cache while it is performing allocations from external memory due to prior read/write misses. The data cache supports four outstanding reads and four outstanding writes. The CPU can support up to four outstanding preload (PLD) instructions. However, explicit load/store instructions have higher priority. The Cortex-A9 load/store unit supports speculative data pre-fetching which monitors sequential accesses made by program and starts fetching the next expected line before it has been requested. This feature is enabled in the cp15 Auxiliary Control register (DP bit). The pre-fetched lines can be dropped before allocation, and PLD instruction has higher priority. The data cache supports two 32-byte line-fill buffers and one 32-byte eviction buffer. The Cortex-A9 CPU has a store buffer with four 64-bit slots with data merging capability.

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Both data cache read misses and write misses are non-blocking with up to four outstanding data cache read misses and up to four outstanding data cache write misses being supported. The APU data caches offer full snoop coherency control utilizing the MESI algorithm. The data cache in Cortex-A9 contains local load/store exclusive monitor for LDREX/STREX synchronizations. These instructions are used to implement semaphores. The exclusive monitor handles one address only, with eight 8 words or one cache line granularity. Therefore, avoid interleaving LDREX/STREX sequences and always execute a CLREX instruction as part of any context switch. D-Cache only supports write-back/write-allocate policy. Write-through and write-back/no write-allocate policies are not implemented. L1 D-Cache offers support for exclusive operation with respect to the L2 cache. Exclusive operation implies that a cache line is valid only in L1 or L2 cache and never in both at the same time. A line-fill into L1 causes the line to be marked invalid in L2. At the same time, eviction of a line from L1 causes the line to be allocated in L2, even if it is not dirty. A line-fill into L1 from dirty L2 line forces eviction of the line to external memory. The exclusive operation, disabled by default, increases cache utilization and reduces power consumption.

Initialization of L1 Caches
Before using the L1 caches, the user must invalidate the instruction cache, the data cache, and the BTAC. It is not required to invalidate the main TLB, even though it is recommended for safety reasons. This ensures compatibility with future revisions of the processor. Steps to initialize L1 Caches: 1. Invalidate TLBs: mcr 2. p15, 0, r0, c8, c7, 0 (r0 = 0 )

Invalidate I-Cache: mcr p15, 0, r0, c7, c5, 0 (r0 = 0 )

3.

Invalidate Branch Predictor Array: mcr p15, 0, r0, c7, c5, 6 (r0 = 0 )

4.

Invalidate D-Cache: mcr p15, 0, r11, c7, c14, 2 (should be done for all the sets/ways)

5. 6.

Initialize MMU. Enable I-Cache and D-Cache: mcr p15, 0, r0, c1, c0, 0 (r0 = 0x1004 )

7.

Synchronization barriers: dsb isb (Allows MMU to start) (Flushes pre-fetch buffer)

(Refer to Memory Barriers, page 71 for more details on memory barriers.)

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3.2.4 Memory Ordering

Memory Ordering Model
The Cortex-A9 architecture defines a set of memory attributes with the characteristics required to support all memory and devices in the system memory map. The following mutually-exclusive main memory type attributes describe the memory regions: Normal Device Strongly-ordered

Device and Strongly-ordered

Accesses to Strongly-ordered and Device memory have the same memory-ordering model. System peripherals come under strongly ordered and device memory. Access rules for this memory are as follows: The number and size of accesses are preserved. Accesses are atomic, and will not be interrupted part way through. Both read and write accesses can have side-effects on the system. Accesses are never cached. Speculative accesses are never be performed. Accesses cannot be unaligned. The order of accesses arriving at Device memory is guaranteed to correspond to the program order of instructions which access Strongly-ordered or device memory. This guarantee applies only to accesses within the same peripheral or block of memory. The Cortex-A9 processor can re-order normal memory accesses around Strongly-ordered or Device memory accesses.

The only difference between Device and Strongly-ordered memory is that: A write to Strongly-ordered memory can complete only when it reaches the peripheral or memory component accessed by the write. A write to Device memory is permitted to complete before it reaches the peripheral or memory component accessed by the write.

Normal Memory
Normal memory is used to describe most parts of the memory system. All ROM and RAM devices are considered to be Normal memory. All code to be executed by the processor must be in Normal memory. Code is not architecturally permitted to be in a region of memory which is marked as Device or Strongly-ordered. The properties of Normal memory are as follows: The processor can repeat read and some write accesses. The processor can pre-fetch or speculatively access additional memory locations, with no side-effects (if permitted by MMU access permission settings). The processor does perform speculative writes.

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Unaligned accesses can be performed. Multiple accesses can be merged by processor hardware into a smaller number of accesses of a larger size. Multiple byte writes could be merged into a single double-word write, for example.

Memory Attributes
In addition to memory types, the ordering of accesses for regions of memory is also defined by the memory attributes. The following sub-sections discuss these attributes.

Shareability
Shareability domains define zones within the bus topology within which memory accesses are to be kept consistent (taking place in a predictable way) and potentially coherent (with hardware support). Outside of this domain, masters might not see the same order of memory accesses as inside it. The order of memory accesses takes place in these defined domains. Table 3-1 shows the different shareability options available in a Cortex A9 system: Table 3-1: Shareability Domains Abbreviation
NSH

Domain
Non-Shareable

Description
A domain consisting only of the local master. Accesses that never need to be synchronized with other cores, processors or devices. Not normally used in SMP systems. A domain (potentially) shared by multiple masters, but usually not all masters in the system. A system can have multiple inner shareable domains. An operation that affects one inner shareable domain does not affect other inner shareable domains in the system. A domain almost certainly shared by multiple masters, and quite likely consisting of several inner shareable domains. An operation that affects an outer shareable domain also implicitly affects all inner shareable domains within it. An operation on the full system affects all masters in the system; all non-shareable regions, all inner shareable regions and all outer shareable regions.

Inner Shareable

ISH

Outer Shareable

OSH

Full System

SY

Shareability only applies to Normal memory, and to Device memory in an implementation that does not include the large physical address extensions (LPAE). In an implementation that includes the LPAE Device memory is always outer shareable. For more information on LPAE, please refer to the ARM Technical Reference Manual.

Cacheability
Cacheable attributes apply only for the Normal memory type. These attributes provide a mechanism of coherency control with masters that lie outside the shareability domain of a region of memory. Each region of Normal memory is assigned a cacheable attribute that is one of: Write-back cacheable Write-through cacheable Non-cacheable

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Please go through the Cache Policies of ARM architecture, for information on these attributes. The Cortex-A9 CPU also provides independent cacheability attributes for Normal memory for two conceptual levels of cache, the inner and the outer cacheable. Inner refers to the innermost caches, and always includes the lowest level of cache i.e. L1 Cache. Outer cache refers to L2 Cache. No cache controlled by the inner cacheability attributes can lie outside a cache controlled by the outer cacheability attributes.

Memory Barriers
A memory barrier is an instruction or sequence of instructions that forces synchronization events by a processor with respect to retiring load/store instructions. Cortex A9 CPU requires three explicit memory barriers to support the memory order model. They are: Data memory barrier Data synchronization barrier Instruction synchronization barrier

These barriers provide the functionality to order and complete load/store instructions. This also helps in context synchronization.

Data Memory Barrier (DMB)

This instruction ensures that all memory accesses in program order before the barrier are observed in the system before any explicit memory accesses that appear in program order after the barrier. It does not affect the ordering of any other instructions executing on the processor, or of instruction fetches.

Example: Weakly Ordered Message Passing Problem

Consider the following instructions executing on processor P1 and P2: P1: STR R5, [R1] STR R0, [R2] P2: WAIT ([R2]==1) LDR R5, [R1] ; wait on flag ; set new data ; send flag indicating data ready

; read new data

Here, the order of memory accesses seen by the other processor might not be the order that appears in the program, for either loads or stores. The addition of barriers ensures that the observed order of both the reads and the writes allow transfer of data correctly. P1: STR R5, [R1] ; set new data

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DMB

; ensure that all observers see data before the flag ; send flag indicating data ready

STR R0, [R2] P2:

WAIT ([R2]==1) ; wait on flag DMB ; ensure that the load of data is after the flag has been observed

LDR R5, [R1]

Data Synchronization Barrier (DSB)

The DSB instruction has the same effect as the DMB, but in addition to this, it also synchronizes the memory accesses with the full instruction stream, not just other memory accesses. This means that when a DSB is issued, execution stalls until all outstanding explicit memory accesses have completed. When all outstanding reads have completed and the write buffer is drained, execution resumes as normal. There is no effect on pre-fetching of instructions. Example usage of DSB is discussed in the following section.

Example: Instruction Cache Maintenance Operations

The multiprocessing extensions require that a DSB is executed by the processor which issued an instruction cache maintenance instruction to ensure its completion; this also ensures that the maintenance operation is completion on all cores within the shareable, not outer-shareable domain. ISB is not broadcast, and so does not have an effect on other cores. This requires that other cores perform their own ISB synchronization once it is known that the update is visible, if it is necessary to ensure the synchronization of those other cores. P1: STR R11, [R1] DSB ICIMVAU R1 BPIMVA R1 DSB STR R0, [R2] ISB BX R1 P2: WAIT ([R2] == 1) ISB BX R1 ; wait for flag signaling completion ; synchronize context on this processor ; branch to new code ; ensure completion of the ICache and branch predictor ; Invalidation on all processors ; set flag to signal completion ; synchronize context on this processor ; branch to new code ; R11 contains a new instruction to be stored in program memory ; ensure completion of the clean on all processors ; ensure instruction cache/branch predictor discard stale data DCCMVAU R1 ; clean to PoU (Point of Unification) makes it visible to instruction cache

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Instruction Synchronization Barrier (ISB)

This flushes the pipeline and pre-fetch buffer(s) in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has completed. This ensures that the effects of context altering operations (for example, CP15 or ASID changes or TLB or branch predictor operations), executed before the ISB instruction are visible to any instructions fetched after the ISB. This does not in itself cause synchronization between data and instruction caches, but is required as a part of such an operation.

Mismatched Memory Attributes

A physical memory location is accessed with mismatched attributes if all accesses to the location do not use a common definition of all of the following attributes of that location: Memory types - Strongly-ordered, Device, or Normal Shareability Cacheability

The following rules apply when a physical memory location is accessed with mismatched attributes: 1. When a memory location is accessed with mismatched attributes the only software visible effects are one or more of the following:

Uni-processor semantics for reads and writes to that memory location might be lost. This means: A read of the memory location by a thread of execution might not return the value most recently written to that memory location by that thread of execution. Multiple writes to the memory location by a thread of execution, which use different memory attributes, might not be ordered in program order.

There might be a loss of coherency when multiple threads of execution attempt to access a memory location. There might be a loss of properties derived from the memory type.

2.

If the mismatched attributes for a location mean that multiple cacheable accesses to the location might be made with different shareability attributes, then coherency is guaranteed only if each thread of execution that accesses the location with a cacheable attribute performs a clean and invalidate of the location. The possible loss of properties caused by mismatched attributes for a memory location are defined more precisely if all of the mismatched attributes define the memory location as one of:

3.

Strongly-ordered memory Device memory Normal inner non-cacheable, outer non-cacheable memory.

In these cases, the only possible software-visible effects of the mismatched attributes are one or more of:

Possible loss of properties derived from the memory type when multiple threads of execution attempt to access the memory location.

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Possible re-ordering of memory transactions to the memory location that use different memory attributes, potentially leading to a loss of coherency or uni-processor semantics. Any possible loss of coherency or uniprocessor semantics can be avoided by inserting DMB barrier instructions between accesses to the same memory location that might use different attributes.

4.

If the mismatched attributes for a memory location all assign the same shareability attribute to the location, any loss of coherency within a shareability domain can be avoided. To do so, software must use the techniques that are required for the software management of the coherency of cacheable locations between threads of execution in different shareability domains. This means:

If any thread of execution might have written to the location with the write-back attribute, before writing to the location not using the write-back attribute, a thread of execution must invalidate, or clean, the location from the caches. This avoids the possibility of overwriting the location with stale data. After writing to the location with the write-back attribute, a thread of execution must clean the location from the caches, to make the write visible to external memory. Before reading the location with a cacheable attribute, a thread of execution must invalidate the location from the caches, to ensure that any value held in the caches reflects the last value made visible in external memory.

In all cases:

Location refers to any byte within the current coherency granule. A clean and invalidate operation can be used instead of a clean operation, or instead of an invalidate operation. To ensure coherency, all cache maintenance and memory transactions must be completed, or ordered by the use of barrier operations.

5.

If all aliases of a memory location that permit write access to the location assign the same shareability and cacheability attributes to that location, and all these aliases use a definition of the shareability attribute that includes all the threads of execution that can access the location, then any thread of execution that reads the memory location using these shareability and cacheability attributes accesses it coherently, to the extent required by that common definition of the memory attributes.

3.2.5 Memory Management Unit (MMU)

The MMU in the ARM architecture involves both memory protection and address translation. The MMU works closely with the L1 and L2 memory systems in the process of translating virtual addresses to physical addresses. It also controls accesses to and from the external memory. The MMU is compatible with the Virtual Memory System Architecture version 7 (VMSAv7) requirements supporting 4 KB, 64 KB, 1 MB, and 16 MB page table entries and 16 access domains. The unit provides global and application-specific identifiers to remove the requirement for context switch TLB flushes and has the capability for extended permission checks. Please see the ARM Architecture Reference Manual for a full architectural description of the VMSAv7. The processor implements the ARMv7-A MMU enhanced with security extensions and multiprocessor extensions to provide address translation and access permission checks. The MMU controls table-walk hardware that accesses translation tables in main memory. The MMU enables

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fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in instruction and data translation look-aside buffers (TLBs). In summary, the MMU is responsible for the following operations: Checking of Virtual Address and ASID (address space identifier) Checking of domain access permissions Checking of memory attributes Virtual-to-physical address translation Support for four page (region) sizes Mapping of accesses to cache, or external memory Four entries in the main TLB are lockable

MMU Functional Description

The key feature of MMU is the address translation. It translates addresses of code and data from the virtual view of memory to the physical addresses in the real system. It enables tasks or applications to be written in a way which requires them to have no knowledge of the physical memory map of the system, or about other programs which may be running at the same time. This makes programming of applications much simpler, as it enables to use the same virtual memory address space for each. This virtual address space is separate from the actual physical map of memory in the system. The translation process is based on translation entries stored in the translation table. Refer to Translation Tables for more details. The two major functional units, shown in Figure 3-4, exist in the MMU to provide address translation automatically based on the table entries: The table walker automatically retrieves the correct translation table entry for a requested translation. The Translation Look-Aside Buffer (TLB) stores recently used translation entries, acting like a cache of the translation table.
Virtual Memory Space MMU Physical Memory Space

X-Ref Target - Figure 3-4

Process

TLB

Page Table Walk Logic

Translation Tables

UG585_c3_05_102112

Figure 3-4:

MMU Architecture Block Diagram

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Translation Tables
The translation of virtual to physical addresses is based on entries in translation tables; they are often called as page tables. These contain a series of entries, each of which describes the physical address translation for part of the memory map. Translation table entries are organized by virtual address. Each virtual address corresponds to exactly one entry in the translation table. In addition to describing the translation of that virtual page to a physical page, they also provide access permissions and memory attributes for that page or block. A single set of translation tables is used to give the translations and memory attributes which apply to instruction fetches and to data reads or writes. The process in which the MMU accesses page tables to translate addresses is known as page table walking. When developing a table-based address translation scheme, one of the most important design parameters is the memory page size described by each translation table entry. MMU instances support 4 KB and 64 KB pages, a 1 MB section, and a 16 MB super-section. Using bigger page sizes means a smaller translation table. Using a smaller page size, 4 KB, greatly increases the efficiency of dynamic memory allocation and defragmentation, but it would require one million entries to span the entire 4 GB address range. To reconcile these two requirements, the Cortex-A9 Processor MMU supports multi-level page table architecture with two levels of page table: level 1 (L1) and level 2 (L2), which are discussed in the following sub-sections.

Level 1 Page Tables

Level 1 page table sometimes called as a master page table, which divides the full 4 GB address space into 4,096 equally sized 1 MB sections. The L1 page table therefore contains 4,096 entries, each entry being word sized. Each entry can either hold a pointer to the base address of a level 2 page table or a page table entries for translating a 1 MB section. If the page table entry is translating a 1 MB section, it gives the base address of the 1 MB page in physical memory. The base address of the L1 page table is known as the Translation Table Base Address (TTB) and is held within a register in CP15 c2. It must be aligned to a 16 KB boundary. An L1 page table entry can be one of four possible types; the least significant two bits [1:0] in the entry define which one of these the entry contains: A fault entry that generates an abort exception. This can be either a pre-fetch or data abort, depending on the type of memory access. This effectively indicates virtual addresses which are unmapped. A 1 MB section translation entry. An entry that points to an L2 page table. This enables a 1 MB piece of memory to be further sub-divided into smaller pages. A 16 MB super-section. This is a special kind of 1 MB section entry, which requires 16 entries in the page table.

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X-Ref Target - Figure 3-5

14 31 24 Fault 23 23 19 18 17 16 15 13 12 IGNORE 11 10 9

8 7 6 5

Page Table

Page Table Base Address, bits [31:10]

IMP

Domain

SBZ NS SBZ

Section Base Address, PA [31:20]

TEX[2:0]

NS

nG

IMP

Supersection Base Address PA[31:24]

Extended Base Address PA[35:32]

NS

nG

IMP

Extended Base Address PA[39:36]

Supersection

TEX[2:0]

AP[1:0]

AP[2]

Domain

Section

AP[1:0]

AP[2]

XN

Reserved

Reserved

UG585_c3_06_1022112

Figure 3-5:

L1 Page Table Entry Format

The page table entry for a section (or super-section) contains the physical base address used to translate the virtual address. Many other bits listed in the page-table entry, including the access permissions (AP) and memory region attributes TEX, cacheable (C) or bufferable (B) types are examined in the next section.

Example: Generation of a Physical Address from a L1 Page Table Entry

Assume an L1 page table is placed at address 0x12300000 . The processor core issues virtual address 0x00100000 . The top 12 bits [31:20] define which 1 MB of virtual address space is being accessed. In this case 0x001 , so we need to read table entry [1]. Each entry is one word (4 bytes). To get the offset into the table we must multiply the entry number by entry size: 0x001 * 4 = address offset of 0x004 . The address of the entry is 0x12300000 + 0x004 = 0x12300004 . So, upon receiving this virtual address from the processor, the MMU reads the word from address 0x12300004 .

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X-Ref Target - Figure 3-6

Translation Table Base Address

31

14 13

Virtual Address

31

20 19

31

14 13

2 10

Level 1 Table

First Level Descriptor Address

0 31 20 19 18 17

10 2 10

Section Base Address Descriptor

31

20 19

Physical Address
UG585_c3_07_102112

Figure 3-6:

Generating a Physical Address from an L1 Page Table Entry

Level 2 Page Tables

An L2 page table has 256 word-sized entries, requires 1KB of memory space and must be aligned to a 1KB boundary. Each entry translates a 4KB block of virtual memory to a 4KB block in physical memory. A page table entry can give the base address of either a 4KB or 64KB page. There are three types of entry used in L2 page tables, identified by the value in the two least significant bits of the entry: A large page entry points to a 64 KB page. A small page entry points a 4 KB page. A fault page entry generates an abort exception if accessed.

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X-Ref Target - Figure 3-7

31 Fault Large Page

16 15 14 13 12 11 10 9 IGNORE Large Page Base Address TEX [2:0] S APX XN nG

1 0

0 0 1

SBZ

AP

Small Page

Small Page Base Address

TEX [2:0]

APX

nG

AP

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Figure 3-7:

L2 Page Table Entry Format

The fields mentioned in the above page table entries are discussed in Description of Page Table Entry Fields. Figure 3-8 summarizes the address translation process when using two layers of page tables. The bits [31:20] of the virtual address are used to index into the 4096-entry L1 page table, where the base address is given by the CP15 TTB register The L1 page table entry points to an L2 page table, which contains 256 entries. Bits [19:12] of the virtual address are used to select one of those entries which then gives the base address of the page. The final physical address is generated by combining that base address with the remaining bits of the physical address.

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XN

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X-Ref Target - Figure 3-8

Translation Table Base Address

31

14 13

Virtual Address

31

20 19

12 11

31

14 13

2 10

Level 1 Table TTB

31

Level 1 Descriptor Address

01 10 9 2 10

Level 2 Table Base Address

Level 2 Table 2TB

31

10 9

2 10

Level 2 Descriptor Address

10 31 12 11 2 10

Small Page Base Address

31

12 11

Physical Address
UG585_c3_09_102112

Figure 3-8:

Generating a Physical Address from an L2 Page Table Entry

Description of Page Table Entry Fields

Memory Access Permissions (AP and APx)
The access permission (AP and APX) bits in the page table entry give the access permission for a page. An access which does not have the necessary permission (or which faults) is aborted. On a data access, this results in a precise data abort exception. On an instruction fetch, the access is marked as aborted and if the instruction is not subsequently flushed before execution, a pre-fetch abort exception is taken. Information about the address of the faulting location and the reason for the fault is stored in CP15 (the fault address and fault status registers). The abort handler can then take appropriate action. Table 3-2 lists the access permission encodings.

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Table 3-2: APX

0 0 0 0 1 1 1 1

Access Permission Encodings AP1

0 0 1 1 0 0 1 1

AP0
0 1 0 1 0 1 0 1

Privileged
No access Read/Write Read/Write Read/Write ~ Read Read ~

Unprivileged
No access No access Read Read/Write ~ No access Read ~~

Description
Permission fault Privileged access only No user-mode write Full access Reserved Privileged Read only Read only Reserved

Memory Attributes (TEX, C and B bits)

TEX, C, and B bits within the page table entry are used to set the memory attributes of a page and also the cache policies to be used. Memory attributes are discussed in 3.2.4 Memory Ordering, and for various cache policies please refer to the ARM Technical Reference Manual. Table 3-3 and Table 3-4 summarizes these memory attributes. Table 3-3: TEX [2:0]
0 0 0 0 1 1 10 10 11 1XX

Memory Attributes Encodings C

0 0 1 1 0 1 Y

B
0 1 0 1 0 0 Y Strongly-ordered shareable device

Description

Memory Type
Strongly ordered Device Normal Normal Normal Device Normal

Outer and Inner write-through, no allocate on write Outer and Inner write-back, no allocate on write Outer and Inner non-cacheable Reserved Non-Shareable device Reserved Reserved Cached memory XX - Outer Policy YY - Inner Policy

Table 3-4:

Memory Attributes Encodings Cache Attribute

Non-Cacheable Write-Back, Write-Allocate Write-Through, no Write-Allocate Write-Back, no Write-Allocate

Encoding Bits C
0 0 1 1

B
0 1 0 1

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Domains
A domain is a collection of memory regions. Domains are only valid for L1 Page table entries. The L1 page table entry format supports 16 domains, and requires the software that defines a translation table to assign each memory region to a domain. The domain field specifies which of the 16 domains the entry is in, and a two-bit field in the Domain Access Control Register (DACR) defines the permitted access for each domain. The possible settings for each domain are: No access - Any access using the translation table descriptor generates a Domain fault. Clients - On an access using the translation table descriptor, the access permission attributes are checked. Therefore, the access might generate a Permission fault. Managers - On an access using the translation table descriptor, the access permission attributes are not checked. Therefore, the access cannot generate a Permission fault.

Shareable bit (S)

This bit determines whether the translation is for sharable memory. S = 0 , the memory location is non-shareable and S = 1, it is sharable. For more information please refer to shareable attributes in section 3.2.4 Memory Ordering.

Non-Global Region Bit (nG)

The nG bit in the translation table entry permits the virtual memory map to be divided into global and non-global regions. Each non-global region (nG = 1 ) has an associated address space identifier (ASID), which is a number assigned by the OS to each individual task. If the nG bit is set for a particular page, that page is associated with a specific application and is not global. This means that when the MMU performs a translation, it uses both the virtual address and an ASID values. When a page table walk occurs and the TLB is updated and the entry is marked as non-global, the ASID value is stored in the TLB entry in addition to the normal translation information. Subsequent TLB look-ups only match on that entry if the current ASID matches with the ASID that is stored in the entry. This means that we can have multiple valid TLB entries for a particular page (marked as non-global), but with different ASID values. This significantly reduces the software overhead of context switches, as it avoids the need to flush the on-chip TLBs.

Execute Never bit (xN)

A memory location marked as Execute Never, when it has its XN attribute set to 1 in a Client domain, instructions are not allowed to fetch/prefetch. Any region of memory that is read-sensitive must be marked as Execute Never, to avoid the possibility of a speculative prefetch accessing the memory region. For example, any memory region that corresponds to a read-sensitive peripheral must be marked as Execute Never.

TLB Organization
The Cortex-A9 MMU includes two levels of TLBs which include a unified TLB for both instruction and data and separate micro TLBs for each. The micro TLBs act as the first level TLBs and each have 32 fully associative entries. If an instruction fetch or a load/store address misses in the corresponding micro TLB, the unified or main TLB is accessed. The unified main TLB provides a 2-way associative 2x64 entry table (128 entries) and supports 4 lockable entries using the lock-by-entry model. The TLB

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uses a pseudo round-robin replacement policy to determine which entry in the TLB should be replaced in the case of a miss. Unlike some other RISC processors that require software to manage the updates of the TLB from the page table that resides in the memory, the main TLB in Cortex-A9 supports hardware page table walks to perform look-ups in the L1 data cache. This allows the page tables to be cached. The MMU can be configured to perform hardware translation table walks in cacheable regions by setting the IRGN bits in the Translation Table Base registers. If the encoding of the IRGN bits is write-back, then an L1 data cache look-up is performed and data is read from the data cache. If the encoding of the IRGN bits is write-through or non-cacheable, then an access to external memory is performed. TLB entries can be global, or can be assigned to particular processes or applications using the ASIDs associated with those processes. ASIDs enable TLB entries remain resident during context switches, avoiding the requirement of reloading them subsequently. a per-CPU basis. The ASID is incremented for each new process. When the ASID rolls over (ASID = 0 ,) a TLB flush request is sent to both CPUs. However, only the CPU that is in the middle of a context switch immediately updates its current ASID context. The other CPU continues to run using its current pre-rollover ASID until a scheduling interval occurs and then it context switches to a new process. TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated within the core. This coprocessor provides a standard mechanism for configuring the level one memory system.

Note: The ARM Linux kernel manages the 8-bit TLB ASID space globally across all CPUs instead of on

Micro TLB
The first level of caching for the page table information is a micro TLB of 32 entries implemented on each of the instruction and data sides. These blocks provide a fully associative look-up of the virtual addresses in a cycle. The micro TLB returns the physical address to the cache for the address comparison, and also checks the protection attributes to signal either a pre-fetch abort or a data abort. All main TLB related operations affect both the instruction and data micro TLBs, causing them to be flushed. In the same way, any change of the Context ID register causes the micro TLBs to be flushed. The main or unified TLB, explained in the next section, should be invalidated after reset and before the MMU is enabled.

Main TLB
The main TLB is the second layer in the TLB structure that catches the misses from the Micro TLBs. It also provides a centralized source for lockable translation entries. Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the main TLB take a variable number of cycles, according to competing requests from each of the micro TLBs and other implementation-dependent factors.

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Entries in the lockable region of the main TLB are lockable at the granularity of a single entry. As long as the lockable region does not contain any locked entries, it can be allocated with non-locked entries to increase overall main TLB storage size.

Translation Table Base Register 0 and 1

When managing multiple applications with their individual page tables, there is a need to have multiple copies of the L1 page table, one for each application. Each of these are 16 KB in size. Most of the entries are identical in each of the tables, as typically only one region of memory is task-specific, with the kernel space being unchanged in each case. Furthermore, if there is a need to modify a global page table entry, the change is needed in each of the tables. To help reduce the effect of these problems, a second page table base register can be used. CP15 contains two page table base registers, TTBR0 and TTBR1. A control register (the TTB Control register) is used to program a value in the range 0 to 7. This value (denoted by N) tells the MMU how many upper bits of the virtual address it should check to determine which of the two TTB registers to use. When N is 0 (the default), all virtual addresses are mapped using TTBR0. With N in the range 1-7, the hardware looks at the most significant bits of the virtual address. If the N most significant bits are all zero, TTBR0 is used, otherwise TTBR1 is used. TTBR0 is used typically for process-specific addresses. On a context switch, TTBR0 is updated to point to the first-level translation table for the new context and TTBCR is updated if this change changes the size of the translation table. This table ranges in size from 128 bytes to 16 KB. TTBR1 is used for operating system and I/O addresses that do not change on a context switch. The size of this table is always 16 KB.

TLB Match Process

Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each is marked as being associated with a particular application space, or as global for all application spaces. A TLB entry matches if bits [31: N] of the modified virtual address (MVA) match, where N is log2 of the page size for the TLB entry. It is either marked as global, or the ASID matched the current ASID. A TLB entry matches when these conditions are true: Its virtual address matches that of the requested address Its non-secure TLB ID (NSTID) matches the secure or non-secure state of the MMU request Its ASID matches the current ASID or is global

The operating system must ensure that, at most, one TLB entry matches at any time. A TLB can store entries based on the following block sizes: Supersections: Sections : Large pages : Small pages : 16 MB blocks of memory 1 MB blocks of memory 64 KB blocks of memory 4 KB blocks of memory

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Supersections, sections, and large pages are supported to permit mapping of a large region of memory while using only a single entry in a TLB. If no mapping for an address is found within the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB. (The translation table entries are discussed in detail in Translation Table Base Register 0 and 1, page 84)

Memory Access Sequence

When the processor generates a memory access, the MMU: 1. 2. 3. Performs a look-up for the requested virtual address and current ASID and security state in the relevant instruction or data micro TLB. If there is a miss in the micro TLB, performs a look-up for the requested virtual address and current ASID and security state in the main TLB. If there is a miss in main TLB, performs a hardware translation table walk.

The MMU might not find a global mapping or a mapping for the currently selected ASID with a matching non-secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the TTB Control register. If translation table walks are disabled, the processor returns a section translation fault. If the MMU finds a matching TLB entry, it uses the information in the entry as follows: 1. The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual for a description of access permission bits, abort types and priorities, and for a description of the Instruction Fault Status register (IFSR) and Data Fault Status register (DFSR). The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers control the cache and write buffer, and determine if the access is: a. c. 3. Secure or non-secure Normal memory, device, or strongly-ordered b. Shared or not The MMU translates the virtual address to a physical address for the memory access.

2.

If the MMU does not find a matching entry, a hardware table walk occurs.

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X-Ref Target - Figure 3-9

Translation Request

Is the translation in TLB?

Yes

Perform Translation

Translation Result

No

TLB Update

Yes

Table walking enabled?

Yes

Entry exists in Page Table?

No

No

Translation Fault
UG585_c3_10_102112

Figure 3-9:

Translation Process

TLB Maintenance Operations

The following rules describe the TLB maintenance operations: A TLB invalidate operation is complete when all memory accesses using the TLB entries that have been invalidated have been observed by all observers to the extent that those accesses are required to be observed, as determined by the shareability and cacheability of the memory locations accessed by the accesses. In addition, once the TLB invalidate operation is complete, no new memory accesses that can be observed by those observers using those TLB entries will be performed. A TLB maintenance operation is only guaranteed to be complete after the execution of a DSB instruction. An ISB instruction, or a return from an exception, causes the effect of all completed TLB maintenance operations that appear in program order before the ISB or return from exception to be visible to all subsequent instructions, including the instruction fetches for those instructions. An exception causes all completed TLB maintenance operations that appear in the instruction stream before the point where the exception was taken to be visible to all subsequent instructions, including the instruction fetches for those instructions. All TLB Maintenance operations are executed in program order relative to each other. The execution of a Data or Unified TLB maintenance operation is guaranteed not to affect any explicit memory access of any instruction that appears in program order before the TLB maintenance operation. This means no memory barrier instruction is required. This ordering is guaranteed by the hardware implementation. The execution of a Data or Unified TLB maintenance operation is only guaranteed to be visible to a subsequent explicit load or store operation after both:

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The execution of a DSB instruction to ensure the completion of the TLB operation. A subsequent ISB instruction, or taking an exception, or returning from an exception.

The execution of an Instruction or Unified TLB maintenance operation is only guaranteed to be visible to subsequent instruction fetch after both:

The execution of a DSB instruction to ensure the completion of the TLB operation. A subsequent ISB instruction, or taking an exception, or returning from an exception.

The following rules apply when writing translation table entries. They ensure that the updated entries are visible to subsequent accesses and cache maintenance operations. A write to the translation tables, after it has been cleaned from the cache if appropriate, is only guaranteed to be seen by a translation table walk caused by an explicit load or store after the execution of both a DSB and an ISB. However, it is guaranteed that any writes to the translation tables are not seen by any explicit memory access that occurs in program order before the write to the translation tables. If the translation tables are held in write-back cacheable memory, the caches must be cleaned to the point of unification after writing to the translation tables and before the DSB instruction. This ensures that the updated translation table is visible to a hardware translation table walk. A write to the translation tables, after it has been cleaned from the cache if appropriate, is only guaranteed to be seen by a translation table walk caused by the instruction fetch of an instruction that follows the write to the translation tables after both a DSB and an ISB.

TLB Lockdown
The TLB supports the TLB lock-by-entry model as described in the ARM Architecture Reference Manual. See TLB Lockdown Register description in the ARM Cortex-A9 Technical Reference Manual.

3.2.6 Interfaces
AXI and Coherency Interfaces
Each Cortex-A9 processor provides two 64-bit pseudo AXI master interfaces for independent instruction fetch and data transactions. These interfaces operate at the speed of the processor cores (CPU_6x4x clock) and are capable of sustaining four double-word writes every five processor cycles when copying data across a cached region of memory. The instruction side interface is a read-only interface and does not have the write channel. These interfaces implement an extended version of the AXI protocol that also provides multiple optimizations to the L2 cache including support for L2 pre-fetch hints and speculative memory accesses. These optimizations are explained in more detail in the L2-Cache section of this chapter. The AXI transactions are all routed through the SCU to the OCM or the L2 cache controller based on their addresses. Each Cortex-A9 also provides a cache coherency bus (CCB) to the SCU to provide the information required for coherency management between the L1 and L2 caches.

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Debug and Trace Interfaces

Each Cortex-A9 processor has a standard 32-bit APB slave port that operates at the CPU_1x clock frequency and is accessed through the debug APB bus master in the SOC debug block. The operation of this block is explained in the corresponding chapter of this document. The Cortex-A9 processors also include a pair of interfaces for trace generation and cross trigger control. The trace source interface from each core is a 32-bit CoreSight standard ATB master port that operates at the speed of the PS interconnect (CPU_2x clock), and is connected to the funnel in the SOC debug block. Each core also has a 4-bit standard CoreSight cross trigger interface that operates at the interconnect frequency (CPU_2x clock) and is connected to the cross trigger matrix (CTM) in the SOC debug block.

Other Interfaces
Each Cortex-A9 processor has multiple control bits that are driven through the System-Level Control register (SLCR). This includes a 4-bit interface that drives the CoreSight standard security signals and also static configuration signals for controlling CP15 and SW programmability. There are also other interfaces including the event and interrupt interfaces that are explained later in this chapter.

3.2.7 NEON
The Cortex-A9 NEON MPE extends the Cortex-A9 functionality to provide support for the ARM v7 advanced SIMD and vector floating-point v3 (VFPv3) instruction sets. The Cortex-A9 NEON MPE supports all addressing modes and data-processing operations described in the ARM Architecture Reference Manual.

The Cortex-A9 NEON MPE features are: SIMD vector and scalar single-precision floating-point computation

Unsigned and signed integers Single bit coefficient polynomials Single-precision floating-point values Addition and subtraction Multiplication with optional accumulation Maximum or minimum value driven lane selection operations Inverse square-root approximation Comprehensive data-structure load instructions, including register-bank-resident table lookup.

The operations supported by the NEON co-processor include:

Scalar double-precision floating-point computation SIMD and scalar half-precision floating-point conversion 8, 16, 32, and 64-bit signed and unsigned integer SIMD computation

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8 or 16-bit polynomial computation for single-bit coefficients Structured data load capabilities Dual issue with Cortex-A9 processor ARM or Thumb instructions Independent pipelines for VFPv3 and advanced SIMD instructions Large, shared register file, addressable as:

Thirty-two 32-bit S (single) registers Thirty-two 64-bit D (double) registers Sixteen 128-bit Q (quad) registers

See the ARM Architecture Reference Manual for details of the advanced SIMD instructions and the NEON MPE operation.

3.2.8 Performance Monitoring Unit

The Cortex-A9 processor includes a performance monitoring unit (PMU) which provides six counters to gather statistics on the operation of the processor and memory system. Each counter can count any of 58 events available in the Cortex-A9 processor. The PMU counters, and their associated control registers, are accessible from the internal CP15 interface as well as from the DAP interface. For details, refer to the Performance Monitoring Unit in the ARM Cortex-A9 Technical Reference Manual.

3.3 Snoop Control Unit (SCU)

3.3.1 Summary
The SCU block connects the two Cortex A9 processors to the memory subsystem and contains the intelligence to manage the data cache coherency between the two processors and the L2 cache. This block is responsible for managing the interconnect arbitration, communication, cache and system memory transfers, and cache coherence for the Cortex A9 processors. The APU also exposes the capabilities of the SCU to system accelerators that are implemented in the PL through the accelerator coherency port (ACP) interface that is explained later. This interface allows PL masters to share and access the processor's cache hierarchy. The offered system coherence here not only improves performance but also reduces the software complexity involved in otherwise maintaining software coherency within each OS driver. The SCU block communicates with each of the Cortex-A9 processors through a cache coherency bus (CCB) and manages the coherency between the L1 and the L2 caches. The SCU supports MESI snooping which provides increased power efficiency and performance by avoiding unnecessary system accesses. The block implements duplicated 4-way associative tag RAMs acting as a local directory that lists coherent cache lines held in the CPU L1 data caches. The directory allows the SCU to check if data is in the L1 data caches with great speed and without interrupting the processors. Also, accesses can be filtered only to the processor that is sharing the data.

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The SCU can also copy clean data from one processor cache to another and eliminate the need for main memory accesses to perform this task. Furthermore, it can move dirty data between the processors, skipping the shared state and avoiding the latency associated with the write-back. It is important to note that the Cortex A9 does not guarantee coherency between the L1 instructions caches as the processor is not capable of modifying the L1 contents directly.

3.3.2 Address Filtering

One of the functions of the SCU is to filter transactions that are generated by the processors and the ACP based on their addresses and route them accordingly to the OCM or L2 controller. The granularity of the address filtering within the SCU is 1 MB; therefore, all accesses by the processors or through the ACP whose addresses are within a 1 MB window can only target the OCM or L2 controller. The default setting of the address filtering within the SCU routes all the upper and lower 1M addresses within the 4G address space to the OCM and the rest of the addresses are routed to the L2 controller. Refer to the SCU Address Filtering section of Chapter 29, On-Chip Memory (OCM) for more information on the SCU address filtering.

3.3.3 SCU Master Ports

Each of the SCU AXI master ports to the L2 or OCM has the following write and read issuing capabilities: Write issuing capability:

10 write transactions per processor: 8 non-cacheable writes 2 evictions from L1

2 additional writes for eviction traffic from the SCU 3 more write transactions from the ACP 14 read transactions per processor: 4 instruction reads 6 linefill reads 4 non-cacheable read

Read issuing capability:

7 more read transactions from the ACP

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3.4 L2-Cache
3.4.1 Summary
The L2 cache controller is based on the ARM PL310 and includes an 8-way set-associative 512 KB cache for dual Cortex-A9 cores. The L2 cache is physically addressed and physically tagged and supports a fixed 32-byte line size. These are the main features of the L2 cache: Supports snoop coherency control utilizing MESI algorithm Offers parity check for L2 cache memory Supports speculative read operations in the SMP mode Provides L1/L2 exclusive mode (i.e., data exists in either, but not both) Can be locked down by master, line, or way per master Implements 16-entry deep preload engine for loading data into L2 cache memory To improve latency, critical-word-first line-fill is supported Implements pseudo-random victim selection policy with deterministic option

Write-through and write-back Read allocate, write allocate, read and write allocate

The contents of the L2 data and tag RAMS are cleared upon reset to comply with security requirements The L2 controller implements multiple 256-bit line buffers to improve cache efficiency

Line fill buffers (LFBs) for external memory access to create a complete cache line into L2 cache memory. Four LFBs are implemented for AXI read interleaving support Two 256-bit line read buffers for each slave port. These buffers hold a line from the L2 cache in case of cache hit Three 256-bit eviction buffers hold evicted lines from the L2 cache, to be written back to main memory Three 256-bit store buffers hold bufferable writes before their draining to main memory, or L2 cache. They enable multiple writes to the same line to be merged

The controller implements selectable cache pre-fetching within 4k boundaries. The L2 cache controller forwards exclusive requests from L1 to DDR, OCM, or external memory

Note: The SCU does not maintain coherency between instruction and data L1 caches, so this
coherency must be maintained by software. The L2 Cache implements TrustZone security extension to offer enhanced OS security. The non-secure (NS) tag bit is added in tag RAM and is used for lookup in the same way as an address bit. The NS-tag bit is also added in all of the buffers. The NS bit in tag RAM is used to determine the security level of evictions to DDR and OCM. The controller restricts non-secure accesses for control, configuration, and maintenance registers to restrict access to secure data.

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Cache Response
This section describes the general behavior of the cache controller depending on the Cortex A9 transactions. These are the descriptions for the different type of transactions: Bufferable The transaction can be delayed by the interconnect or any of its components for an arbitrary number of cycles before reaching its final destination. This is usually only relevant to writes. The transaction at the final destination does not have to present the characteristics of the original transaction. For writes this means that a number of different writes can be merged together. For reads this means that a location can be pre-fetched or can be fetched just once for multiple read transactions. To determine if a transaction should be cached, this attribute should be used in conjunction with the read allocate and write allocate attributes. If the transfer is a read and it misses in the cache then it should be allocated. This attribute is not valid if the transfer is not cacheable. If the transfer is a write and it misses in the cache then it should be allocated. This attribute is not valid if the transfer is not cacheable.

Cacheable

Read Allocate Write Allocate

In the ARM architecture, the inner attributes are used to control the behavior of the L1 caches and write buffers. The outer attributes are exported to the L2 or an external memory system. In the Cortex A9 processing system (similar to most modern processors), to improve performance and power, many optimizations are performed at many levels of the system which cannot be completely hidden from the outside world and might cause the violation of the expected sequential execution model. Examples of these optimizations are: Multi-issue speculative and out-of-order execution Usage of load/store merging to minimize the latency of load/stores In a multi-core processor, hardware-based cache coherency management can cause cache lines to migrate transparently between cores causing different cores to see updates to cached memory locations in different orders External system characteristics might create additional challenges when external masters are included in the coherent system through the ACP

Therefore, it is vital to define certain rules to constrain the order in which the memory accesses of one core relate to the surrounding instructions, or could be observed by other cores within a multi-core processor system. Typically the memory can be categorized into Normal, Strongly Ordered and Device regions. For more information please refer to section 3.2.4 Memory Ordering.

Table 3-5 shows the general behavior of the L2 cache controller in response to ARMv7 load/store transaction types that are supported by Cortex-A9.

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Table 3-5:

Cache Controller Behavior for SCU Requests L2 Cache Controller Behavior

Read: Not cached in L2, results in memory access. Write: Not buffered, results in memory access. Read: Not cached in L2, results in memory access. Write: Placed in store buffer, not merged, immediately drained to memory. Read: Not cached in L2, results in memory access. Write: Placed in store buffer, write to memory when store buffer is drained. Read hit: Read from L2. Read miss: Line fill to L2. Write hit: Put in store buffer, write to L2 and memory when store buffer is drained. Write miss: Put in store buffer, write to memory when store buffer is drained. Read hit: Read from L2. Read miss: Line fill to L2. Write hit: Put in store buffer, write to L2 when store buffer is drained and mark line as dirty. Write miss: Put in store buffer, write to L3 when store buffer is drained. Read hit: Read from L2. Read miss: Not cached in L2, causes memory access. Write hit: Put in store buffer, write to L2 and memory when store buffer is drained. Write miss: Put in store buffer. When buffer is drained, check if it is full. If not full, request word or line to memory before allocating buffer to L2. Allocation to L2. Write to memory. Read hit: Read from L2. Read miss: Not cached in L2, causes memory access. Write hit: Put in store buffer, write to L2 when store buffer is drained, and mark line as dirty. Write miss: Put in store buffer. When buffer has to be drained, check if it is full. If it is not full then request word or line to memory before allocating the buffer to L2. Allocation to L2. Strongly ordered

Transaction Type ARMv7 Equivalent

Non-cacheable and non-bufferable Bufferable only

Device

Cacheable but do not allocate Cacheable write-through, allocate on read

Outer non-cacheable Outer write-through, no write allocate

Cacheable write-back, allocate on read

Outer write-back, no write allocate

Cacheable write-through, allocate on write -

Cacheable write-back, allocate on write -

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Table 3-5:

Cache Controller Behavior for SCU Requests (Contd) L2 Cache Controller Behavior
Read hit: Read from L2. Read miss: Line fill to L2. Write hit: Put in store buffer, write to L2 and memory when store buffer is drained. Write miss: Put in store buffer. When buffer has to be drained, check whether it is full. If it is not full then request word or line to memory before allocating the buffer to the L2. Allocation to L2. Write to memory. Read hit: Read from L2. Read miss: Line fill to L2. Write hit: Put in store buffer, write to L2 when store buffer is drained, and mark line as dirty. Write miss: Put in store buffer. When buffer has to be drained, check if it is full. If it is not full then request word or line to memory before allocating the buffer to L2. Allocation to L2. Outer write-through, allocate on both reads and writes

Transaction Type ARMv7 Equivalent

Cacheable write-through, allocate on read and write

Cacheable write-back, allocate on read and write

Outer write-back, write allocate

3.4.2 Exclusive L2-L1 Cache Configuration

In the exclusive cache configuration mode, the L1 data cache of the Cortex-A9 processor and the L2 cache are exclusive. At any time, a given address is cached in either L1 data cache or in the L2 cache, but not in both. This has the effect of increasing the usable space and efficiency of the L2 cache. When exclusive cache configuration is selected: Data cache line replacement policy is modified so that the victim line in the L1 always gets evicted to the L2, even if it is clean. If a line is dirty in the L2 cache, a read request to this address from the processor causes write-back to external memory and a line-fill to the processor.

Both L1 and L2 caches have to be configured for exclusive caching. Setting the exclusive cache configuration bit 12 in the Auxiliary Control register for L2 and bit 7 of the ACTLR register in Cortex-A9 configure the L2 and L1 caches to operate exclusive to one another. For reads, the behavior is as follows: For a hit, the line is marked as non-valid (the tag RAM valid bit is reset,) and the dirty bit is unchanged. If the dirty bit is set, future accesses can still hit in this cache line but the line is part of the preferred choice for future evictions. For a miss, the line is not allocated into the L2 cache.

For writes, the behavior depends on the value of attributes from the SCU to indicate if the write transaction is an eviction from the L1 memory system and whether it is a clean eviction. AWUSERS[8] attribute indicates an eviction and AWUSERS[9] indicates a clean eviction. The behavior is summarized as follows: For a hit, the line is marked dirty unless the AWUSERS[9:8] = b11 . In this case, the dirty bit is unchanged.

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For a miss, if the cache line is evicted (AWUSERS[8] is 1 ,) the cache line is allocated and its dirty status depends on if it is evicted dirty or not. If the cache line is evicted dirty (AWUSERS[8] is 0 ,) the cache line is allocated only if it is write allocate.

3.4.3 Cache Replacement Strategy

Bit [25] of the Auxiliary Control register configures the replacement strategy. It can be either round-robin or pseudo-random. The round-robin replacement strategy fills invalid and unlocked ways first; for each line, when ways are all valid or locked, the victim is chosen as the next unlocked way. The pseudo-random replacement strategy fills invalid and unlocked ways first; for each line, when ways are all valid or locked, the victim is chosen randomly between unlocked ways. When a deterministic replacement strategy is required, the lockdown registers are used to prevent ways from being allocated. For example, since L2 cache is 512 KB and is 8-way set-associative, each way is 64 KB. If a piece of code is required to reside in two ways (128 KB,) with a deterministic replacement strategy, ways 1-7 must be locked before the code is filled into the L2 cache. If the first 64 KB of code is allocated into way 0 only, then way 0 must be locked and way 1 unlocked so that the second half of the code can be allocated in way 1. There are two lockdown registers, one for data and one for instructions. If required, one can separate data and instructions into separate ways of the L2 cache.

3.4.4 Cache Lockdown

The L2 cache controller allows locking down entries by line, by way, or by master (includes both CPU and ACP masters.) Lockdown by line and lockdown by way can be used at the same time; lockdown by line and lockdown by master can also be used at the same time. However, lockdown by master and lockdown by way are exclusive, because lockdown by way is a subset of lockdown by master.

Lockdown by Line
When enabled, all newly allocated cache lines get marked as locked. The controller then considers them as locked and does not naturally evict them. It is enabled by setting bit [0] of the lockdown by the Line Enable register. Bit [21] of the tag RAM shows the locked status of each cache line.

Note: An example of when the lockdown by line feature might be enabled is during the time when
a critical piece of software code is loaded into the L2 cache. The unlock all lines background operation enables the unlocking of all lines marked as locked by the lockdown by line mechanism. The status of this operation can be checked by reading the Unlock All Lines register. While an unlock all lines operation is in progress, the user cannot launch a background cache maintenance operation. If attempted, a SLVERR error is returned.

Lockdown by Way
The L2 cache is 8-way set-associative and allows users to lock the replacement algorithm on a way basis, enabling the set count to be reduced from 8-way all the way down to direct mapped. The 32-bit cache address consists of the following fields:

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[Tag Field], [Index Field], [Word Field], [Byte Field] When a cache lookup occurs, the index defines where to look in the cache ways. The number of ways defines the number of locations with the same index referred to as a set. Therefore, an 8-way set associative cache has eight locations where an address with Index A can exist. There are 2 11 or 2,024 indices in the 512K L2 cache. Lockdown format C, as the ARM Architecture Reference Manual describes, provides a method to restrict the replacement algorithm used for allocations of cache lines within a set. This method enables: Fetch of code or load data into the L2 cache Protection from being evicted because of other accesses This method can also be used to reduce cache pollution

The Lockdown register in the L2 cache controller is used to lock any of the eight ways in the L2 cache. To apply lockdown, the user sets each bit to 1 to lock each respective way. For example, set Bit [0] for Way 0, Bit [1] for Way 1.

Lockdown by Master
The lockdown by master feature is a superset of the lockdown by way feature. It enables multiple masters to share the L2 cache and makes the L2 cache behave as though these masters have dedicated smaller L2 caches. This feature enables the user to reserve ways of the L2 cache to specific master IDs. The L2 cache controller lockdown by master is only able to distinguish up to eight different masters. However, there are up to 64 AXI master IDs from the Cortex-A9 MP core. Table 3-6 shows how the 64 master ID values are grouped into eight lockable groups. Table 3-6:
A9 Core 0 A9 Core 1 A9 Core 2 A9 Core 3 ACP Group0 ACP Group1 ACP Group2 ACP Group3

Lockdown by Master ID Group Comment

All 8 read/write request from Core 0 All 8 read/write request from Core 1 Reserved for future Reserved for future ACP ID = { 000 , 001 } ACP ID = { 010 , 011 } ACP ID = { 100 , 101 } ACP ID = { 110 , 111 }

ID Group

3.4.5 Enabling and Disabling the L2 Cache Controller

The L2 cache is disabled by default and can be enabled by setting Bit 0 of the L2 Cache Control register independently of the L1 caches. When the cache controller block is not enabled, depending on their addresses, transactions pass through to the DDR memory or the main interconnect on the

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cache controller master ports. The address latency introduced by the disabled cache controller is one cycle in the slave port from the SCU plus one cycle in the master ports.

3.4.6 RAM Access Latency Control

The L2 cache data and tag RAMs use the same clock as the Cortex-A9 processors; however, it is not feasible to access these RAMs in a single cycle when the clock runs at its maximum speed. To address this issue, the L2-cache controller provides a mechanism to adjust the latencies for the write access, read access, and setup of both RAM arrays by respectively setting bits [10:8], [6:4], and [2:0] of its Tag RAM and Data RAM Latency Control registers. The default value for these fields is 3'b111 for both registers which corresponds to the maximum latency of eight CPU_6x4x cycles for the three attributes of each RAM array. Because these large latencies result in very poor cache performance, the software should reset the attributes as follows: Set the latencies for the three tag RAM attributes to 2 by writing 3'b001 to bits [10:8], [6:4], and [2:0] of the Tag RAM Latency Control register. Set the latencies for the write access and setup of the data RAM to 2 by writing 3'b001 to bits [10:8] and [2:0] of the Data RAM Latency Control register. Set the read access latency of the data RAM to 3 by writing 3'b010 to bits [6:4] of the Data RAM Latency Control register.

3.4.7 Store Buffer Operation

Two buffered write accesses to the same address and the same security bit cause the first write access to be overridden if the controller does not drain the store buffer after the first access. The store buffer has merging capabilities, so it merges successive writes to the same line address into the same buffer slot. This means that the controller does not drain the slots as soon as they contain data, but rather waits for other potential accesses that target the same cache line. The store buffer draining policy is as follows. Slave port refers to the port from the SCU to the L2 cache controller: Store buffer slot is immediately drained if targeting device memory area Store buffer slots are drained as soon as they are full Store buffer is drained at each strongly-ordered read occurrence in the slave port Store buffer is drained at each strongly ordered write occurrence in the slave port If the three slots of the store buffer contain data, the least recently accessed slot is drained If a hazard is detected with one store buffer slot, it is drained to resolve the hazard. Hazards can occur when data is present in the cache buffers, but not yet present in the cache RAM or external memory Store buffer slots are drained when a locked transaction is received by the slave port Store buffer slots are drained when a transaction targeting the configuration registers is received by the slave port

Merging condition is based on address and security attribute. Merging takes place only when data is in the store buffer and it is not draining.

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When a write-allocate cacheable slot is drained, misses in the cache, and is not full, the store buffer sends a request via the master ports to the main interconnects or DDR to complete the cache line. The corresponding master port sends a read request through the interconnects and provides data to the store buffer in return. When the slot is full, it can be allocated into the cache.

3.4.8 Optimizations Between Cortex-A9 and L2 Controller

To improve performance, the SCU interface to the L2 controller and partially the interface to the on-chip memory controller (OCM), implement several optimizations: Early write response Pre-fetch hints Full line of zero write Speculative reads of the Cortex-A9 MPCore processor

These optimizations apply to the transfers from the processor and do not include the ACP.

Early Write Response

During the write transaction from the Cortex-A9 to the L2 cache controller, the write response from the L2 controller is normally returned to the SCU only when the last data beat has arrived at the L2 controller. This optimization enables the L2 controller to send the write response of certain write transactions as soon as the store buffer accepts the write address and allows the Cortex-A9 processor to provide a higher bandwidth for writes. This feature is disabled by default and the user can enable it by setting the Early BRESP enable bit in the Auxiliary Control register for the L2 controller. The Cortex-A9 does not require any programming to enable this feature. OCM does not support this feature and its write responses are generated normally.

Pre-fetch Hints
When the Cortex-A9 processor is configured to run in SMP mode, the automatic data pre-fetchers implemented in the CPUs issue special read accesses to the L2 cache controller. These special reads are called pre-fetch hints. When the L2 controller receives such pre-fetch hints, it allocates the targeted cache line into the L2 cache for a miss without returning any data back to the Cortex-A9 processor. The user can enable the pre-fetch hint generation by the Cortex-A9 processors through one of the two following methods: 1. Enabling the L2 pre-fetch hint feature by setting bit [1] of the ACTLR register. When enabled, this feature sets the Cortex-A9 processor to automatically issue L2 pre-fetch hint requests when it detects regular fetch patterns on a coherent memory. Use of PLE (pre-load engine) operations. When this feature is used in the Cortex-A9 processor, the PLE issues a series of L2 pre-fetch hint requests at the programmed addresses.

2.

No additional programming of the L2 Controller is required. Application of the pre-fetch hints to the OCM memory space does not cause any action because, unlike caches, transfer of data into OCM RAM requires explicit operations by software.

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Full Line of Zero Write

When this feature is enabled, the Cortex-A9 processor can write entire non-coherent cache lines of zeroes to the L2 cache, using a single write command cycle. This provides a performance improvement as well as some power savings. The Cortex-A9 processor is likely to use this feature when a CPU is executing a memset routine to initialize a particular memory area. This feature is disabled by default and can be enabled by setting the Full Line of Zero enable bit of the Auxiliary Control register for the L2 controller and the enable bit in the Cortex-A9 ACTLR register. Care must be taken if this feature is enabled because correct behavior relies on consistent enabling in both the Cortex-A9 processor and the controller. To enable this feature, the following steps must be performed: 1. 2. 3. Enable Full line of zero feature in the L2 controller Enable L2 cache controller Enable Full line of zero feature in A9

The cache controller does not support strongly-ordered write accesses with this feature. The feature is also supported by the OCM if it is enabled in the Cortex-A9

Speculative Reads of the Cortex-A9

This is a feature unique to the Cortex-A9 MP configuration and can be enabled using a dedicated software control bit in the SCU Control register. For this feature, the Cortex-A9 has to be in the SMP mode through the use of the SMP bit in the ACTLR register; however, the L2 controller does not require any specific settings. When the speculative read feature is enabled, on coherent line fills, the SCU speculatively issues read transactions to the controller in parallel with its tag lookup. The controller does not return data on these speculative reads and only prepares data in its line read buffers. If the SCU misses, it issues a confirmation line fill to the controller. The confirmation is merged with the previous speculative read in the controller and enables the controller to return data to the L1 cache sooner than a L2 cache hit. If the SCU hits, the speculative read is naturally terminated in the L2 controller, either after a certain number of cycles, or when a resource conflict exists. The L2 controller informs the SCU when a speculative read ends, either by confirmation or termination.

3.4.9 Pre-fetching Operation

The pre-fetch operation is the capability of attempting to fetch cache lines from memory in advance, to improve system performance. To enable the pre-fetch feature, the user sets bit 29 or 28 of the Auxiliary or Pre-fetch Control register. When enabled, if the slave port from the SCU receives a cacheable read transaction, a cache lookup is performed on the subsequent cache line. Bits [4:0] of the Pre-fetch Control register provide the address of the subsequent cache line. If a miss occurs, the cache line is fetched from external memory, and allocated to the L2 cache. By default, the pre-fetch offset is 5'b00000 . For example, if S0 receives a cacheable read at address 0x100 , the cache line at address 0x120 is pre-fetched. Pre-fetching the next cache line might not necessarily result in optimal performance. In some systems, it might be better to pre-fetch more in

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advance to achieve better performance. The pre-fetch offset enables this by setting the address of the pre-fetched cache line to Cache Line + 1 + Offset. The optimal value of the pre-fetch offset depends on the external memory read latency and on the L1 read issuing capability. The pre-fetch mechanism is not launched for a 4 KB boundary crossing. Pre-fetch accesses can use a large number of the address slots in the controller master ports. This prevents non-prefetch accesses being serviced and affects performance. To counter this effect, the controller can drop pre-fetch accesses. This can be controlled using bit 24 of the Pre-fetch Control register. When enabled, if a resource conflict exists between pre-fetch and non-pre-fetch accesses in the controller master ports, pre-fetch accesses are dropped. When data corresponding to these dropped pre-fetch accesses returns from the external memory, it is discarded and is not allocated into the L2 cache.

3.4.10 Programming Model

The following applies to the registers used in the L2 cache controller: The cache controller is controlled through a set of memory-mapped registers. The memory region for these registers must be defined with strongly-ordered or device memory attributes in the L1 page tables. The reserved bits in all registers must be preserved; otherwise, unpredictable behavior of the device might occur. All registers support read and write accesses unless otherwise stated in the relevant text. A write updates the contents of a register and a read returns the contents of the register. All writes to registers automatically perform an initial cache sync operation before proceeding.

Initialization Sequence
As an example, a typical cache controller start-up programming sequence consists of the following register operations: Write 0x020202 to the register at 0xF8000A1C . This is a mandatory step. Write to the auxiliary, tag RAM latency, data RAM latency, pre-fetch, and Power Control registers using a read-modify-write to set up global configurations:

Associativity and way size Latencies for RAM accesses Allocation policy Pre-fetch and power capabilities Write 0xFFFF to 0x77C Poll cache maintenance register until invalidate operation is complete

Secure write to invalidate by way, offset 0x77C , to invalidate all entries in cache:

If required, write to register 9 to lockdown D and lockdown I. Write to the Interrupt Clear register to clear any residual raw interrupts set. Write to the interrupt mask register if it is desired to enable interrupts.

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Write to Control register 1 with the LSB set to 1 to enable the cache.

If a write is performed to the Auxiliary, Tag RAM latency, or Data RAM Latency Control register with the L2 cache enabled, a SLVERR (error) results. The L2 cache must be disabled by writing to the Control register before writing to these registers.

Cache Lockdown by Way Sequence

These are the steps to be followed for locking code by way: 1. 2. Ensure the code to be locked is in cacheable memory region. This can be done by programming page table entry for the region with appropriate memory attributes. Refer to Memory Attributes. Ensure the code to lockdown is in non-cacheable memory region. For example, the region can be marked as Strongly Ordered region.

The following is the sequence that needs to be implemented in lockdown routine: 3. 4. 5. 6. Disable the Interrupts. Clean and Invalidate entire L2 cache. This step is for ensuring that the code to be locked is not loaded into L2 cache. Find the number of ways required for loading code based on the code size. Unlock the calculated ways and lock all the ways remaining. This is done by writing into Data LockDown registers. Please refer to the PL310 L2 Cache Controller Document for information on these registers. Load the code into the L2 cache using PLD instruction. PLD instruction always generates data references, this is the reason for using Data Lockdown registers. For more information on PLD instruction, please refer to the ARMv7 TRM. This step loads the code into unlocked ways. Lock the loaded ways and unlock the remaining ways by writing into Data Lockdown registers. Enable Interrupts.

7.

8. 9.

To check for whether the code is really locked into L2 cache, generate more references to the code that has been locked. These references can be monitored by L2 Cache Instruction Hit event. For more information on the available events of L2 cache and their initialization, please refer to the PL310 L2 Cache Controller Document. This event initialization should be done prior to code locking. So more the references to code, more the instruction hits. For example, the code that is locked can be called from a Timer Interrupt Handler which generates references as per the number of interrupts programmed.

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3.5 APU Interfaces

3.5.1 PL Co-processing Interfaces
ACP Interface
The accelerator coherency port (ACP) is a 64-bit AXI slave interface on the SCU that provides an asynchronous cache-coherent access point directly from the PL to the Cortex-A9 MP-Core processor subsystem. A range of system PL masters can use this interface to access the caches and the memory subsystem exactly the way the APU processors do to simplify software, increase overall system performance, or improve power consumption. This interface acts as a standard AXI slave and supports all standard read and write transactions without any additional coherency requirements placed on the PL components. Therefore, the ACP provides cache-coherent access from the PL to ARM caches while any memory local to the PL are non-coherent with the ARM. Any read transactions through the ACP to a coherent region of memory interact with the SCU to check whether the required information is stored within the processor L1 caches. If it is, the data is returned directly to the requesting component. If it misses in the L1 cache, then there is also the opportunity to hit in L2 cache before finally being forwarded to the main memory. For write transactions to any coherent memory region, the SCU enforces coherence before the write is forwarded to the memory system. The transaction can also optionally allocate into the L2 cache, removing the power and performance impact of writing through to the off-chip memory.

ACP Requests
The read and write requests performed on the ACP behave differently depending on whether the request is coherent or not. This behavior is as follows: ACP coherent read requests: An ACP read request is coherent when ARUSER[0] = 1 and ARCACHE[1] = 1 alongside ARVALID. In this case, the SCU enforces coherency. When the data is present in one of the Cortex-A9 processors, the data is read directly from the relevant processor, and returned to the ACP port. When the data is not present in any of the Cortex-A9 processors, the read request is issued on one of the SCU AXI master ports, along with all its AXI parameters, with the exception of the locked attribute. ACP non-coherent read requests: An ACP read request is non-coherent when ARUSER[0] = 0 or ARCACHE[1] = 0 alongside ARVALID. In this case, the SCU does not enforce coherency, and the read request is directly forwarded to one of the available SCU AXI master ports to the L2 cache controller or OCM. ACP coherent write requests: An ACP write request is coherent when AWUSER[0] = 1 and AWCACHE[1] = 1 alongside AWVALID. In this case, the SCU enforces coherency. When the data is present in one of the Cortex-A9 processors, the data is first cleaned and invalidated from the relevant CPU. When the data is not present in any of the Cortex-A9 processors, or when it has been cleaned and invalidated, the write request is issued on one of the SCU AXI master ports, along with all corresponding AXI parameters with the exception of the locked attribute.

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Note: The transaction can optionally allocate into the L2 cache if the write parameters are set accordingly.
ACP non-coherent write requests: An ACP write request is non-coherent when AWUSER[0] = 0 or AWCACHE[1] = 0 alongside AWVALID. In this case, the SCU does not enforce coherency, and the write request is forwarded directly to one of the available SCU AXI master ports.

ACP Usage
The ACP provides a low latency path between the PS and the accelerators implemented in the PL when compared with a legacy cache flushing and loading scheme. Steps that must take place in an example of a PL-based accelerator are as follows: 1. 2. 3. 4. The CPU prepares input data for the accelerator within its local cache space. The CPU sends a message to the accelerator using one of the general purpose AXI master interfaces to the PL. The accelerator fetches the data via the ACP, processes the data, and returns the result via the ACP. The accelerator sets a flag by writing to a known location to indicate that the data processing is complete. Status of this flag can be polled by the processor or could generate an interrupt.

Table 3-7 shows ACP read and write behavior based on current cache status. Clearly, access latency is small when cache hits occur. When compared to a tightly-coupled coprocessor, ACP access latencies are relatively long. Therefore, ACP is not recommended for fine-grained instruction level acceleration. On the other hand, for coarse-grain acceleration such as video frame-level processing, ACP does not have a clear advantage over traditional memory-mapped PL acceleration because the transaction overhead is small relative to the transaction time, and might potentially cause undesirable cache thrashing. ACP is therefore optimal for medium-grain acceleration such as block-level crypto accelerator, video macro-block level processing, etc. Table 3-7: ACP Read and Write Behavior Action
ACP Read - I (Invalid)

Description
SCU fetches data from external memory through one of two AXI master interfaces. Data is forwarded to the ACP directly. It does not affect the CPU L1 cache state. SCU fetches data from L1 cache with M status. It does not affect the L1 cache state. SCU fetches data from any L1 cache with S status. It does not affect the L1 cache state. SCU fetches data from the L1 cache with E status. It does not affect the L1 cache state. Data is written to external memory through one of two AXI master interfaces. It does not affect the CPU L1 cache state. Data in L1 cache with M status is flushed out to external memory first. After that, ACP data is written into external memory interface. L1 cache previously with M status is changed to I status. If the SCU overwrites the entire cache line, L1 cache flush is skipped.

ACP Read - M (Modified) ACP Read - S (Shared) ACP Read - E (Exclusive) ACP Write - I (Invalid) ACP Write - M (Modified)

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Table 3-7:

ACP Read and Write Behavior (Contd) Action Description

Data is written to external memory through one of two AXI master interfaces. L1 cache previously with S status is changed to I state Data is written to external memory through one of two AXI master interfaces. Any L1 cache previously with S status is changed to I status.

ACP Write - S (Shared) ACP Write - E (Exclusive)

ACP Limitations
The accelerator coherency port (ACP) has these limitations: Exclusive access is not allowed for coherent memory. Locked access is not allowed for coherent memory. Write transactions with AWLEN = 3, AWSIZE = 3, and WSTRB line in the CPUs to get corrupted.

11111111 can cause the cache

Continuous access to the OCM over the ACP can starve accesses from other AXI masters. To allow access from other masters, the ACP bandwidth to OCM should be moderated to less than the peak OCM bandwidth. This can be accomplished by regulating burst sizes to less than eight 64-bit words. Blocks such as PCIe which prioritize write requests over read requests should not be connected to the ACP port as they might create deadlock. Connecting these devices to the other the GP and HP AXI ports does not manifest the mentioned deadlock issue.

Note: The Xilinx HDL wrapper around the PS7 primitive provides a function to flag the third

limitation (cache lines being corrupted). If enabled, the Xilinx ACP adapter watches for transactions that could potentially corrupt the cache and generate an error response to the master that is requesting the write request. The write transaction is allowed to proceed to the ACP interface, so the possibility of cache corruption is NOT eliminated. The master is notified of the possible problem in order to take the appropriate action. The ACP adapter can also generate an interrupt signal to the CPUs, which can be used by the software to detect such a situation.

Event Interface
The event bus provides a low-latency and direct mechanism to transfer status and implement a wake mechanism between the APU and the PL. The event input and output signals on this interface use toggle signaling in which an event is communicated by toggling the signal to the opposite logic level on both edges. The event bus includes these signals: EVENTEVENTO EVENTEVENTI EVENTSTANDBYWFE[1:0] A toggle output signal indicating that either CPU is executing the SEV instruction. A toggle input signal that wakes up either one or both CPUs if they are in a standby state initiated by the WFE instruction. 2-level output signals indicating the state of the two CPUs. A bit is asserted if the corresponding CPU is in standby state following the execution of the WFE (wait for event) instruction. 2-level output signals indicating the state of the two CPUs. A bit is asserted if the corresponding CPU is in standby state following the execution of the WFI (wait for interrupt) instruction.

EVENTSTANDBYWFI[1:0]

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The event bus can be used to implement PL-based accelerators. The event output can be used to trigger an ACP accelerator to read from a predefined address. Further on in the process, the event input can be used to communicate that the data has been written back over the ACP and is ready to be consumed by a CPU. A detailed description of this example follows: 1. 2. 3. 4. CPU0 generates the data that is required by the accelerator in the L1/L2 cache. This data can contain both commands and information to be processed. CPU0 issues an SEV (send event) instruction, causing EVENTEVENTO to toggle to the PL. The signal is connected to an accelerator IP implemented in the PL. CPU0 next issues a WFE (wait For event) instruction, placing the CPU in a lower-power standby state. This is reflected in the EVENTSTANDBYWFE[0] status output to the PL. The accelerator notices the toggled EVENTEVENTO signal and realizes that CPU0 is waiting. The accelerator fetches data from a prearranged address and data format via the ACP interface and begins processing. After writing the result data back via the ACP, the accelerator asserts the EVENTEVENTI input to indicate that processing is complete and wakes up CPU0. CPU0 wakes from its standby state, which is reflected in the EVENTSTANDBYWFE[0] output, and CPU0 continues execution using the processed data.

5. 6.

3.5.2 Interrupt Interface

The PS general interrupt controller (GIC) supports 64 interrupt input lines that are driven from other blocks within the PS or the PL. Six of the 64 interrupt inputs are driven from within the APU. These include the L1 parity fail, L2 interrupt (all reasons), and PMU (performance monitor unit) interrupt. The interrupt output of the GIC drives either the IRQ or FIQ inputs of each of the Cortex-A9 processors. The selection as to which processor is interrupted is accomplished via an SCU register within the APU. Table 3-8 defines the interrupts specific to the APU. Table 3-8: Interrupt
32 33 34 92 37 38

APU Interrupts Description

Any of the L1 instruction cache, L1 data cache, TLB, GHB, and BTAC parity errors from CPU 0 Any of the L1 instruction cache, L1 data cache, TLB, GHB, and BTAC parity errors from CPU 1 Any errors including parity errors from L2 controller Any of the parity errors from SCU generate a third interrupt Performance monitor unit (PMU) of CPU0 Performance monitor unit (PMU) of CPU1

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3.6 Support for TrustZone Within the APU

For the system to transition from power-on reset to a stable state with both secure and non-secure applications running simultaneously, it must go through the steps depicted in Figure 3-10.
X-Ref Target - Figure 3-10

Boot Running

POR

Permanent Residence

ROM Secure Boot

Secure Boot Loader (FSBL)

Non Secure Boot Loader

Secure OS (Monitor) Boot

Secure Monitor

Non Secure OS Boot

UG585_c3_03_022212

Figure 3-10:

TrustZone Boot Sequence

In Figure 3-10, it is assumed that the device security is on; however, this is not a necessary requirement to enable TrustZone security. In this figure, solid lines are used to show the boot flow and dotted lines are used to indicate processing transition after the system is running. The shaded blocks are software functional blocks that remain running after the system boots. In the TrustZone boot flow, Secure OS boots first and initiates a secure monitor as a secure gateway between the secure and non-secure operating systems. After the secure monitor starts, it can spawn a non-secure boot loader which in turn starts a non-secure OS. Before non-secure OS initiates, secure OS defines a set of events to force transition from non-secure OS to secure monitor. The possible events include SMC instruction, IRQ, FIQ, and data abort.

3.6.1 CPU Security Transition

Secure monitor call (SMC) causes a secure monitor exception which is available only in privileged modes. An attempt to execute this instruction in user mode causes an undefined instruction exception. Other than entering the monitor mode through an SMC call, there are a few additional methods to allow users to switch back-and-forth between secure and non-secure worlds via the secure monitor, which acts as a gate-keeper between these two domains. These are all of the possible methods to enter the monitor mode:

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External abort handler FIQ handler IRQ handler

In the secure monitor mode, the processor is always in the secure state independent to the SCR.NS bit. trigger erroneous asynchronous aborts in secure world. For example, a secure hypervisor runs some code with SCR.NS= 1 and the mask asynchronous abort bit CPSR.A= 1 . This non-secure code attempts to read and write memory that is marked as secure-only, and receives AXI DECERR. At that time, no exceptions occur because CPSR.A= 1 and the exceptions are masked. Once secure mode is re-entered, the hypervisor switches to other code, performs DSB/ISB, and clears CPSR.A= 0 . In this case, the Cortex-A9 processor still remembers the pending asynchronous external abort and takes an exception as soon as CPSR.A= 0 . In addition, the non-secure code might have done multi-word stores to secure memory, causing data to be modified in the L1 cache. When this data is eventually cast out, an asynchronous external abort might also be taken in the secure mode.

Note: Under certain circumstances, there is a possibility that Cortex-A9 TrustZone violations might

3.6.2 CP15 Register Access Control

There are a group of banked registers under CP15 which means that the same register has two physical copies for secure and non-secure modes. The physical register is automatically selected based on the SCR.NS bit when system is not in the secure monitor mode. In the secure monitor mode, a secure version of the physical register is always selected. Table 3-9 shows part of the CP15 registers. (Users should refer to the ARM Architecture Reference document for the entire list of the registers.) Table 3-9:
c0 c1 c2

Typical CP15 Registers Banked Register

CSSELR, Cache Size Selection register SCTLR, System Control register ACTLR, Auxiliary Control register TTBR0, Translation Table Base 0 TTBR0, Translation Table Base 1 TTBCR, Translation Table Base Control

CP15 Register

Permitted Accesses
Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only

c3 c5

DACR, Domain Access Control register DFSR, Data Fault Status register IFSR, Instruction Fault Status register ADFSR, Auxiliary Data Fault Status register AIFSR, Auxiliary Instruction Fault Status register

c6 c7

DFAR, Data Fault Address register IFAR, Instruction Fault Address register PAR, Physical Address register (VA to PA translation)

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Table 3-9:
c10 c12

Typical CP15 Registers (Contd) Banked Register

PRRR, Primary Region Remap register NMRR, Normal Memory Remap register VBAR Vector Base Address register

CP15 Register

Permitted Accesses
Read/write in privileged modes only Read/write in privileged modes only Read/write in privileged modes only

Table 3-10 shows additional registers with access control at secure and non-secure states. Table 3-10:
c1

CP15 State Control Registers Secure Register

NSACR, Non-Secure Access Control register SCR, Secure Configuration register SDER, Secure Debug Enable register

CP15 Register

Permitted Accesses
Read/write in privileged modes Read-only in non-secure privileged modes Read/write in privileged modes Read/write in privileged modes Read/write in privileged modes

c12

MVBAR, Monitor Vector Base Address register

3.6.3 MMU Security

The MMU in Cortex A9 is enhanced with TrustZone features to provide access permission checks in addition to address translation. In each of the secure and non-secure worlds, a single set of two-level page tables stored in main memory controls the contents of the instruction- and data-side translation look-aside buffers (TLBs). The calculated physical address associated with the virtual address is placed in the TLB, accompanied by an NSTID (non-secure table identifier) that allows secure and non-secure entries to co-exist. The TLBs are enabled in each world through a single bit in CP15 Control register c1, providing a single address translation and protection scheme for software. This is how the TLB and BTAC state is handled when transitioning between secure and non-secure worlds: BPIALL, when executed from the secure state, might or might not invalidate BTAC entries in the non-secure state. TLBIALL, when executed from the secure state, does not invalidate BTAC entries from the non-secure state. Writing to CONTEXTIDR from the secure state, but with SCR.NS=1, does invalidate BTC entries in the non-secure state.

Because any context switch writes to CONTEXTIDR and causes the non-secure BTAC entries to be invalidated, BPIALL from secure state not affecting non-secure BTAC entries is not going to be a problem.

3.6.4 L-1 Cache Security

Each cache line can contain secure or non-secure data. The effect of an access attempting to violate data security causes a cache miss. On a miss, the next step is to go to the external memory which returns an abort if the NS attribute does not match access permissions.

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3.6.5 Security Exception Control

When an exception is taken, processor execution is forced to an address that corresponds to the type of exception. These addresses are called the exception vectors. By default, the exception vectors are eight consecutive word-aligned memory addresses, starting at an exception base address as follows: There are three exception base addresses for Zynq-7000 AP SoC devices: The non-secure exception base address is used for all exceptions processed in non-secure state. The secure exception base address is used for all exceptions processed in secure state, but not in monitor mode. The monitor exception base address is used for all exceptions processed in monitor mode.

3.6.6 CPU Debug TrustZone Access Control

Four control signals control CPU debug status: DBGEN, NIDEN, SPIDEN, and SPNIDEN. These four control signals are part of a secure and protected register within the device configuration interface module. The most important modes supported are identified in Table 3-11. Table 3-11: Mode
No Debug Non-Secure Non Invasive Debug Non-Secure Invasive Debug Secure Non Invasive Debug Secure Invasive Debug

CPU Debug TrustZone Access Control DBGEN

0 1 1 1 1

NIDEN SPIDEN SPNIDEN

0 1 1 1 1 0 0 0 0 1 0 0 0 1 1

Comment
No CPU debug at all Allow non-invasive debug, such as Trace and Performance Monitor, in Non-Secure mode Allow invasive debug, such as stop processor, in Non-Secure mode This allow CPU Trace and Profile under secure condition This allows Invasive debug for secure mode

3.6.7 SCU Register Access Control

The SCU non-secure Access Control register (SNACR) controls the global non-secure accesses for each major component within the SCU. The Interrupt Controller Distributor Control register (ICDDCR) is a banked register for controlling secure and non-secure accesses.

3.6.8 TrustZone Support in the L2 Cache

The cache controller attaches an NS bit to all data stored in the L2 cache and in internal buffers. A non-secure transaction cannot access secure data. Therefore the controller treats secure and non-secure data as being part of two different memory spaces. The controller treats a non-secure access to secure data in the L2 cache as a miss. For a read transfer, the cache controller sends a line fill command to external memory, propagates any security errors from external memory to the processor, and does not allocate the line in L2.

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These are a few notes about the Trustzone support in L2: The L2 Control register can only be written to with an access tagged as secure, to enable or disable the L2 cache. The Auxiliary Control register can only be written to with an access tagged as secure. Bit [26] in the Auxiliary Control register is for NS lockdown enable. This bit should be used to determine whether non-secure accesses can modify a lockdown register. Non-Secure maintenance operations do not clean or invalidate secure data.

3.7 Application Processing Unit (APU) Reset

3.7.1 Reset Functionality
The APU supports different reset modes that enable the user to reset different parts of the block independently. Applicable resets and their functions are as follows: Power-on Reset The power-on reset or cold reset is applied when the power is first applied to the system or through the PS_POR_B device pin. In this reset mode, both CPUs, the NEON coprocessors, and the debug logic is reset. A system reset initializes the Cortex-A9 processor and the NEON coprocessors, apart from the debug logic. Break points and watch points are retained during this reset. This reset is applied through the PS_SRST_B device pin. A software or warm reset initializes the Cortex-A9 processor and the NEON coprocessors, apart from the debug logic. Break points and watch points are retained during this reset. Processor reset is typically used for resetting a system that has been operating for some time. This reset is applied through the A9_CPU_RST_CTRL.A9_RSTx register. This reset is similar to the software reset; however, it is triggered through the JTAG interface. This reset initializes the debug logic in a Cortex-A9 processor, including break point and watch point values. It is triggered through the JTAG interface.

System Reset

Software Reset

System Debug Reset Debug Reset

Note: The APU in Zynq-7000 AP S0C devices does not support an independent reset for the NEON
coprocessors. the user must stop the associated clock, de-assert the reset, and then restart the clock. During a system or POR reset, hardware automatically takes care of this. Assuming the user wants to reset CPU0, the user must to set the following fields in the SLCR.A9_CPU_RST_CTRL (address 0X000244 ) register in the order listed: 1. 2. A9_RST0 = 1 to assert reset to CPU0 A9_CLKSTOP0 = 1 to stop clock to CPU0

Note: Unlike the POR or system resets, when the user applies a software reset to a single processor,

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3. 4.

A9_RST0 = 0 to release reset to CPU0 A9_CLKSTOP0 = 0 to restart clock to CPU0

3.7.2 APU State After Reset

Table 3-12 summarizes the state of the APU after the reset. Table 3-12:
CPU1 L1 Caches Validation MMUs SCU Address Filtering L2 Cache L2 wait-states Validation

APU State after Reset State after Reset

Kept in a WFE state while executing code located at address 0xFFFFFE00 to 0xFFFFFFF0 Disabled Unknown (requires invalidation prior to usage) Disabled Disabled Upper and lower 1M addresses within the 4G address space are mapped to OCM and the rest of the addresses are routed to the L2 Disabled Tag RAM and Data RAM wait states are both 7-7-7 for setup latency, write access latency, and read access latency Unknown (requires invalidation prior to usage)

Function

3.8 Power Considerations

3.8.1 Introduction
The APU incorporates many features to improve its dynamic power efficiency: Either of the CPUs can be put in the standby mode and started up when a event or interrupt is detected. The L2 cache can be put in the standby mode when the CPUs are in that mode. Clock gating is extensively used in all the sub-blocks within the module. Accurate branch and return prediction reduces the number of incorrect instruction fetch and decode operations. Physically-addressed caches reduce the number of cache flushes and refills, saving energy in the system. The CPUs implement micro TLBs for local address translation which reduces the power consumed in translation and protection look-ups. The tag RAMs and data RAMs are accessed sequentially to eliminate accesses to the unwanted data RAMs and thus minimize unnecessary power consumption.

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To reduce power consumption in the L1 caches, the number of full cache reads is reduced by taking advantage of the sequential nature of memory accesses. If a cache read is sequential to the previous cache read, and the address is within the same cache line, only the data RAM set that was previously read is accessed. If an instruction loop fits in four BTAC entries, then instruction cache accesses are turned off in order to lower power consumption. The clock to the NEON Engine is dynamically controlled by the CPU and the engine gets clocked only when a NEON instruction is issued.

Note: Power to the APU or any of its sub-blocks cannot be turned off while the PS is powered on.

3.8.2 Standby Mode

In the standby mode of operation, the device is still powered-up, but most of its clocks are gated off. This means that the processor is in a static state and the only power drawn is due to leakage currents and the clocking of the small amount of logic which looks out for the wakeup condition. This mode is entered using either the WFI (wait for interrupt) or WFE (wait for event) instructions. It is recommended that a DSB memory barrier be used before WFI or WFE, to ensure that pending memory transactions complete. The processor stops execution until a wake up event is detected. The wake up condition is dependent on the entry instruction. For WFI, an interrupt or external debug request wakes the processor. For WFE, a number of specified events exist, including another processor in an MP system executing the SEV instruction. A request from the SCU can also wake up the clock for a cache coherency operation in an MP system. This means that the cache of a processor which is in standby state continues to be coherent with caches of other processors. A processor reset always forces the processor to exit from the standby condition. The standby mode of the L2 cache controller can be enabled by setting bit 0 of the L2 controller Power Control register. This mode is used in conjunction with the wait state (WFI/WFE) of the processor that drives the controller. Before entering the wait state, the Cortex-A9 processor must set its status field in the CPU Power Status register of the SCU to signal its entering standby mode. The Cortex-A9 processor then executes a WFI or WFE entry instruction. The SCU CPU Power Status register bits can also be read by a Cortex-A9 processor exiting low-power mode to determine its state before executing its reset setup. If the MP system is in the standby mode, the SCU signals to the L2 cache controller to gate its clock and the controller honors that when the L2 becomes idle. Any transaction from the SCU to the L2 restarts the clock and triggers a response with 2-3 clock cycles of delay.

3.8.3 Dynamic Clock Gating in the L2 Controller

Bit 1 of the L2 Controller Power Control register enables the dynamic clock gating feature within the controller. If this feature is enabled, the cache controller stops its clock when it is idle for 32 clock cycles. The controller stops the clock until there is a transaction on its slave interface from the SCU. If this interface detects a transaction, it restarts its clock and accepts the new transaction with 2-3 cycles of delay.

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3.9 CPU Initialization Sequence

Typically, these are the following steps to initialize CPU: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set the Vector Base Address register (refer to section 3.6.2 CP15 Register Access Control). Invalidate L1Caches, TLB, Branch Predictor Array (refer to Initialization of L1 Caches). Invalidate L2 Cache. Prepare page tables and load into physical memory. (For more information on page tables please refer to Translation Table Base Register 0 and 1.) Setup the Stack. Load the Page Table Base Address into Translation Table Base Register (refer to Translation Table Base Register 0 and 1). Set the MMU enable bit of the System Control register (refer to section 3.6.2 CP15 Register Access Control). Initialize and enable L2 cache (refer to section L2 Cache: Programming Model 3.4.10 Programming Model). Enable L1 Caches by writing to System Control register (refer to section 3.6.2 CP15 Register Access Control).

10. Jump to entry of application.

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System Addresses
4.1 Address Map
The comprehensive system level address map is shown in Table 4-1. The shaded entries indicate that the address range is reserved and should not be accessed. Table 4-2 identifies reserved address ranges. Table 4-1: System-Level Address Map CPUs and ACP
OCM DDR 0000_0000 to 0003_FFFF (2) DDR

Address Range

AXI_HP
OCM OCM

Other Bus Masters(1)

OCM OCM

Notes
Address not filtered by SCU and OCM is mapped low Address filtered by SCU and OCM is mapped low Address filtered by SCU and OCM is not mapped low Address not filtered by SCU and OCM is not mapped low

0004_0000 to 0007_FFFF 0008_0000 to 000F_FFFF 0010_0000 to 3FFF_FFFF 4000_0000 to 7FFF_FFFF 8000_0000 to BFFF_FFFF E000_0000 to E02F_FFFF E100_0000 to E5FF_FFFF F800_0000 to F800_0BFF F800_1000 to F880_FFFF F890_0000 to F8F0_2FFF FC00_0000 to FDFF_FFFF(4) FFFC_0000 to FFFF_FFFF (2)

DDR DDR DDR PL PL IOP SMC SLCR PS CPU Quad-SPI OCM OCM Quad-SPI OCM DDR DDR DDR DDR DDR DDR PL PL IOP SMC SLCR PS

Address filtered by SCU Address not filtered by SCU Address filtered by SCU Address not filtered by SCU(3) Accessible to all interconnect masters General Purpose Port #0 to the PL, M_AXI_GP0 General Purpose Port #1 to the PL, M_AXI_GP1 I/O Peripheral registers, see Table 4-6 SMC Memories, see Table 4-5 SLCR registers, see Table 4-3 PS System registers, see Table 4-7 CPU Private registers, see Table 4-4 Quad-SPI linear address for linear mode OCM is mapped high OCM is not mapped high

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Notes:
1. The other bus masters include the S_AXI_GP interfaces, Device configuration interface (DevC), DAP controller, DMA controller and the various controllers with local DMA units (Ethernet, USB and SDIO). 2. The OCM is divided into four 64 KB sections. Each section is mapped independently to either the low or high addresses ranges, but not both at the same time. In addition, the SCU can filter addresses destined for the OCM low address range to the DDR DRAM controller instead. A detailed discussion of the OCM is explained in Chapter 29, On-Chip Memory (OCM). 3. For each 64 KB section mapped to the high OCM address range via slcr.OCM_CFG[RAM_HI] which is not also part of the SCU address filtering range will be aliased for CPU and ACP masters at a range of (0x000C_0000 to 0x000F_FFFF ). See Chapter 29, On-Chip Memory (OCM) for more information. 4. When a single device is used, it must be connected to QSPI 0. In this case, the address map starts at FC00_0000 and goes to a maximum of FCFF_FFFF (16 MBs). When two devices are used, both devices must be the same capacity. The address map for two devices depends on the size of the devices and their connection configuration. For the shared 4-bit parallel I/O bus, the QSPI 0 device starts at FC00_0000 and goes to a maximum of FCFF_FFFF (16 MBs). The QSPI 1 device starts at FD00_0000 and goes to a maximum of FDFF_FFFF (another 16 MBs). If the first device is less than 16 MBs in size, then there will be a memory space hole between the two devices. For the 8-bit dual stacked mode (8-bit bus), the memory map is continuous from FC00_0000 to a maximum of FDFF_FFFF (32 MBs).

Table 4-2:

System-Level Address Map (Reserved Addresses) CPUs and ACP AXI_HP Other Bus Masters(1)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Address Range
C000_0000 to DFFF_FFFF E030_0000 to E0FF_FFFF E600_0000 to F7FF_FFFF F800_0C00 to F800_0FFF F801_0000 to F88F_FFFF F8F0_3000 to FBFF_FFFF FE00_0000 to FFFB_FFFF

Notes

PL AXI Interface Note

There are two general purpose interconnect ports that go to the PL, M_AXI_GP{1,0}. Each port is addressable by masters in the PS and each port occupies 1 GB of system address space in the ranges specified in Table 4-1. The M_AXI_GP addresses are directly from the PS; they are not remapped on their way to the PL. The addresses outside of these ranges are not presented to the PL.

Execute-In-Place Capable Devices

The following devices are execute-in-place capable: DDR OCM SMC SRAM/NOR Quad-SPI (linear addressing mode) M_AXI_GP{1, 0} (PL block RAM or external memory with a suitable PL slave controller)

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4.2 System Bus Masters

The CPUs and AXI_ACP see the same memory map, except the CPUs have a private bus to access their private timer, interrupt controller, and shared L2 cache / SCU registers. The AXI_HP interfaces provide high bandwidth to the DDR DRAM and OCM. The other system bus masters include: DMA controller, see Chapter 9, DMA Controller Device configuration interface (DevC), see Chapter 6, Boot and Configuration Debug access port (DAP), see Chapter 28, System Test and Debug PL bus master controllers attached to AXI general purpose ports (S_AXI_GP[1:0]), see Chapter 5, Interconnect and Chapter 21, Programmable Logic Description AHB bus master ports with local DMA units (Ethernet, USB, and SDIO)

4.3 SLCR Registers

The System-Level Control registers (SLCR) consist of various registers that are used to control the PS behavior. These registers are accessible via the central interconnect using load and store instructions. The detailed descriptions for each register can be found in Appendix B, Register Details. A summary of the SLCR registers with their base addresses is shown in Table 4-3. Table 4-3: SLCR Register Map Description
SLCR write protection lock and security Clock control and status Reset control and status APU control TrustZone control CoreSight SoC debug control DDR DRAM controller MIO pin configuration MIO parallel access Miscellaneous control On-chip memory (OCM) control I/O buffers for MIO pins (GPIOB) and DDR pins (DDRIOB) See Chapter 28, System Test and Debug See Chapter 10, DDR Memory Controller See Chapter 2, Signals, Interfaces, and Pins See Chapter 2, Signals, Interfaces, and Pins See Chapter 29, On-Chip Memory (OCM) See Chapter 29, On-Chip Memory (OCM) See Chapter 2, Signals, Interfaces, and Pins See Chapter 25, Clocks See Chapter 26, Reset System See Chapter 3, Application Processing Unit

Register Base Address

F800_0000 F800_0100 F800_0200 F800_0300 F800_0400 F800_0500 F800_0600 F800_0700 F800_0800 F800_0900 F800_0A00 F800_0B00

Reference

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4.4 CPU Private Bus Registers

The registers shown in Table 4-4 are only accessible by the CPU on the CPU private bus. The accelerator coherency port (ACP) cannot access any of the private CPU registers. The private CPU registers are used to control subsystems in the APU. Table 4-4: CPU Private Register Map Description
Top-level interconnect configuration and Global Programmers View (GPV) SCU control and status Interrupt controller CPU Global timer Private timers and private watchdog timers Interrupt controller distributor L2-cache controller

Register Base Address

F890_0000 to F89F_FFFF F8F0_0000 to F8F0_00FC F8F0_0100 to F8F0_01FF F8F0_0200 to F8F0_02FF F8F0_0600 to F8F0_06FF F8F0_1000 to F8F0_1FFF F8F0_2000 to F8F0_2FFF

4.5 SMC Memory

The SMC memories are accessed via a 32-bit AHB bus (see Table 4-5). The SMC control registers are listed in Table 4-6. Refer to Chapter 11, Static Memory Controller for information on the functionality of the NAND and SRAM/NOR controllers. Table 4-5: SMC Memory Address Map Description
SMC NAND Memory address range SMC SRAM/NOR CS 0 Memory address range SMC SRAM/NOR CS 1 Memory address range

Register Base Address

E100_0000 E200_0000 E400_0000

Zynq-7000 AP SoC 7z010 CLG225 Device Notice

This device has a limited number of PS pins. The SMC controller supports the 8-bit NAND interface. The controller does not support the NOR/SRAM interfaces or the 16-bit NAND interface.

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4.6 PS I/O Peripherals

The I/O Peripheral registers are accessed via a 32-bit APB bus, shown in Table 4-6. Table 4-6: I/O Peripheral Register Map Description
UART Controllers 0, 1 USB Controllers 0, 1 I2C Controllers 0, 1 SPI Controllers 0, 1 CAN Controllers 0, 1 GPIO Controller Ethernet Controllers 0, 1 Quad-SPI Controller Static Memory Controller (SMC) SDIO Controllers 0, 1

Register Base Address

E000_0000, E000_1000 E000_2000, E000_3000 E000_4000, E000_5000 E000_6000, E000_7000 E000_8000, E000_9000 E000_A000 E000_B000, E000_C000 E000_D000 E000_E000 E010_0000, E010_1000

4.7 Miscellaneous PS Registers

The PS system registers are accessed via a 32-bit AHB bus (see Table 4-7). Table 4-7: PS System Register Map Description (Acronym)
Triple timer counter 0, 1 (TTC 0, TTC 1) DMAC when secure (DMAC S) DMAC when non-secure (DMAC NS) System watchdog timer (SWDT) DDR memory controller Device configuration interface (DevC) AXI_HP 0 high performance AXI interface w/ FIFO AXI_HP 1 high performance AXI interface w/ FIFO AXI_HP 2 high performance AXI interface w/ FIFO AXI_HP 3 high performance AXI interface w/ FIFO On-chip memory (OCM) Reserved CoreSight debug control

Register Base Address

F800_1000, F800_2000 F800_3000 F800_4000 F800_5000 F800_6000 F800_7000 F800_8000 F800_9000 F800_A000 F800_B000 F800_C000 F800_D000 F880_0000

Register Set
ttc. dmac. dmac. swdt. ddrc. devcfg. afi. afi. afi. afi. ocm. reserved. cti.

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Interconnect
5.1 Introduction
The interconnect, located within the PS, comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug and test monitoring. The interconnect manages multiple outstanding transactions and is architected for low-latency paths for the ARM CPUs and, for the PL master controllers, a high-throughput and cache coherent data paths.

5.1.1 Features
The interconnect is the primary mechanism for data communications. The following summarizes the interconnect features: The interconnect is based on AXI high performance datapath switches:

Snoop control unit L2 cache controller Interconnect switches based on ARM NIC-301 Central interconnect Master interconnect Slave interconnect Memory interconnect OCM interconnect AHB and APB bridges

PS-PL Interfaces

AXI_ACP, one cache coherent master port for the PL AXI_HP, four high performance/bandwidth master ports for the PL AXI_GP, four general purpose ports (two master ports and two slave ports)

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5.1.2 Block Diagram

Figure 5-1 shows the block diagram for the interconnect.

Interconnect Masters
The interconnect masters are shown at the top of Figure 5-1. The interconnect masters include: CPUs and accelerator coherency port (ACP) High performance PL Interfaces, AXI_HP{3:0} General purpose PL interfaces, AXI_GP{1:0} DMA controller AHB masters (I/O peripherals with local DMA units) Device configuration (DevC) and debug access port (DAP)

Snoop Control Unit (SCU)

The functionality of the snoop control unit is described in Chapter 3, Application Processing Unit. The address filtering feature of the SCU makes the SCU function like a switch from the perspective of the traffic from its AXI slave ports to its AXI master ports.

Central Interconnect
The central interconnect is the core of the ARM NIC301-based interconnect switches.

Master Interconnect
The master interconnect switches the low-to-medium speed traffic from AXI_GP ports, DevC and DAP to the central interconnect.

Slave Interconnect
The slave interconnect switches the low-to-medium speed traffic from the central interconnect to AXI_GP, I/O peripherals (IOP) and other blocks.

Memory Interconnect
The memory interconnect switches the high speed traffic from the AXI_HP ports to DDR DRAM and on-chip RAM (via another interconnect).

OCM Interconnect
The OCM interconnect switches the high speed traffic from the central interconnect and the memory interconnect.

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X-Ref Target - Figure 5-1

Synchronous CPU clock domain Asynchronous to is asynchronous to all else. all else.
CPU, L1 Clock cpu_6x4x AHB/APB Clock cpu_1x OCM Clock cpu_2x DDR Clock ddr_3x

Each of the eight AXI interfaces are asynchronous to all else.

Async crossing ASYNC

Read/Write Request Capability 8 7,3 (e.g. 1 number: 8 reads, 8 writes) (e.g. 2 numbers: 7 reads, 3 writes)

PL DDR Clock ddr_2x

PL Fabric

PL Fabric

Cortex A9
NEON/FPU Jazelle, Thumb-2, MMUs, L1 i/dCaches CPU_6x4x

PL Logic

High Performance AXI Controllers

(AXI_HP[3:0]) PL clocks M0 M1 32- / 64-bit
ASYNC ASYNC ASYNC

Cache Coherent ACP port

(S_AXI_ACP) M

General Purpose AXI Controllers

(S_AXI_GP[1:0]) M0 ASYNC DevC M 4 8 8 M1 ASYNC

Masters Data
32-bit CPU_1x M

DMA Controller
64-bit CPU_2x M

M2

M3

ASYNC 7,3

DAP M 1

ASYNC

FIFO

FIFO

FIFO

FIFO

S0

S1

S2

S3 32-bit

Snoop Control Unit (SCU) CPU_6x4x M0

Cache Tag RAM M1 8,3

Master Interconnect
CPU_2x

S0

S1

S2

S3 4,4 QoS 64-bit QoS

Memory Interconnect
DDR_2x M0 M1

64-bit

64-bit

M2

S1 512 kB CPU_6x4x M1 8

S0

S2

L2 Cache Controller
8 ASYNC 8 ASYNC ASYNC M0 8

Central Interconnect
M0

64-bit M1

CPU_2x M2

64-bit S0 S0 S1 S1

OCM Interconnect
CPU_2x QoS 64-bit M 4 ASYNC S1 256 kB CPU_6x4x CPU_2x S0

32-bit M0 8 ASYNC M1 8

Slave Interconnect
M2 4 ASYNC 32-bit

CPU_2x

ASYNC

M3 1 32-bit

On-chip RAM

S0 General Purpose AXI Controllers (M_AXI_GP[1:0])

S1

S APB Slaves Registers CPU_1x

PL Logic

Slaves Reg & Data CPU_1x

64-bit S3 S2 DDR DRAM S0

64-bit

64-bit S1 DDR_3x

UG585_c5_01_050212

Figure 5-1:

Interconnect Block Diagram

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L2 Cache Controller
The functionality of the L2 cache controller is described in Chapter 3, Application Processing Unit. The address filtering feature of the L2 cache controller makes the L2 cache controller function like a switch from the perspective of the traffic from its AXI slave ports to its AXI master ports.

Interconnect Slaves
The interconnect slaves are shown toward the bottom of Figure 5-1. The Interconnect slaves include: On-chip RAM (OCM) DDR DRAM General purpose PL interfaces, M_AXI_GP{1:0} AHB slaves (IOP with local DMA units) APB slaves (programmable registers in various blocks) GPV (programmable registers of the interconnect, not shown in the figure)

5.1.3 Datapaths
Table 5-1 lists the major datapaths used by the PS interconnect. Table 5-1: Source
CPU AXI_ACP AXI_HP S_AXI_GP DevC DAP AHB masters DMA Controller Master IC. FIFO SCU Memory IC. Central IC. L2 Cache Central IC.

Interconnect Datapaths Destination

SCU SCU FIFO Master IC. Master IC. Master IC. Central IC. Central IC. Central IC. Memory IC. L2 Cache OCM IC. OCM IC. Slave IC. Slave IC.

Type
AXI AXI AXI AXI AXI AHB AXI AXI AXI AXI AXI AXI AXI AXI AXI

Clock at source
CPU_6x4x SAXIACPACLK SAXIHPnACLK SAXIGPnACLK CPU_1x CPU_1x CPU_1x CPU_2x CPU_2x DDR_2x CPU_6X4x DDR_2x CPU_2x CPU_6x4x CPU_2x

Clock at destination
CPU_6x4x CPU_6x4x DDR_2x CPU_2x CPU_2x CPU_2x CPU_2x CPU_2x CPU_2x DDR_2x CPU_6x4x CPU_2x CPU_2x CPU_2x CPU_2x

Sync or Async(1)
Sync Async Async Async Sync Sync Sync Sync Sync Sync Sync Async Sync Sync Sync

Data width
64 64 32/64 32 32 32 32 64 64 64 64 64 64 64 64

R/W Advanced Request QoS Capability

7, 12 7, 3 14-70, 8-32(2) 8, 8 8, 4 1, 1 8, 8 8, 8 8, 8 8, 3 8, 8 X X -

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SCU OCM IC. Slave IC. Slave IC. Slave IC. L2 Cache Central IC. Memory IC. Slave IC. Notes:
1. Each asynchronous path includes an asynchronous bridge for clock domain crossing. 2. Burst-length dependent (see AXI_HP Interfaces). 3. The path from the slave interconnect to GPV is an internal path within the entire interconnect structure. When accessing GPV, ensure that all clocks are on.

Interconnect Datapaths (Contd) Destination

On-chip RAM On-chip RAM APB slaves AHB slaves AXI_GP DDR Controller DDR Controller DDR Controller GPV

Type
AXI AXI APB AXI AXI AXI AXI AXI - (3)

Clock at source
CPU_6x4x CPU_2x CPU_2x CPU_2x CPU_2x CPU_6x4x CPU_2x DDR_2x CPU_2x

Clock at destination
CPU_2x CPU_2x CPU_1x CPU_1x MAXIGPnACLK DDR_3x DDR_3x DDR_3x (multiple)

Sync or Async(1)
Sync Sync Sync Sync Async Async Async Async -

Data width
64 64 32 32 32 64 64 64 -

R/W Advanced Request QoS Capability

4, 4 4, 4 1, 1 4, 4 8, 8 8, 8 8, 8 8, 8 X -

5.1.4 Clock Domains

The interconnect, masters, and slaves use these clocks: CPU_6x4x: CPU_2x: CPU_1x: DDR_3x: DDR_2x: SAXIACPACLK: SAXIHP0ACLK: SAXIHP1ACLK: SAXIHP2ACLK: SAXIHP3ACLK: SAXIGP0ACLK: SAXIGP1ACLK: MAXIGP0ACLK: MAXIGP1ACLK: CPUs, SCU, L2 cache controller, on-chip RAM Central interconnect, master interconnect, slave interconnect, OCM interconnect AHB masters, AHB slaves, APB slaves, DevC, DAP DDR Memory Controller Memory interconnect, FIFOs AXI_ACP slave port AXI_HP0 slave port AXI_HP1 slave port AXI_HP2 slave port AXI_HP3 slave port AXI_GP0 slave port AXI_GP1 slave port AXI_GP0 master port AXI_GP1 master port

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Except for CPU_6X4X, CPU_2X, and CPU_1X, which are synchronous clocks with a ratio of 6:2:1 or 4:2:1, all clocks in the above list are asynchronous to one another, as shown in Figure 5-2.
X-Ref Target - Figure 5-2

High Performance AXI Controllers

(AXI_HP)

Cache Coherent AXI P port (AXI_ACP) Async

M_AXI_GP

Async

Async
DevC DAP

CPUs
CPU_6x4x

Snoop Control Unit (SCU)

CPU_6x4x

Master Interconnect
CPU_2x 6:2:1 or 4:2:1 Ratio

Masters
CPU_1x

DMA Controller
CPU_2x

AXI_HP to DDR Interconnect

DDR_2x

CPU_6x4x CPU_2x

CPU_6x4x

On-chip RAM

L2 Cache

Central Interconnect

CPU_2x

Async

OCM Interconnect
CPU_2x

Slave Interconnect

CPU_2x

Slaves
CPU_1x

APB Slaves
CPU_1x

Async

Async

Async

DDR DRAM

DDR_3x

S_AXI_GP

UG585_c5_02_012813

Figure 5-2:

Interconnect Clock Domains

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5.1.5 Connectivity
The interconnect is not a full cross-bar structure. Table 5-2 shows which master can access which slave. Table 5-2: Master - Slave Access Slave On-chip RAM
X X X X X X X X X X X X X X X X X X X X X X X X X

Master CPUs AXI_ACP AXI_HP{0,1} AXI_HP{2,3} S_AXI_GP{0,1} DMA Controller AHB Masters DevC, DAP

DDR Port 0
X X

DDR Port 1

DDR Port 2

DDR Port 3

M_AXI _GP
X X

AHB Slaves
X X

APB Slaves
X X

GPV
X X

5.1.6 AXI ID
The interconnect uses 13-bit AXI IDs, consisting of (from MSB to LSB): 3 bits that identify the interconnect (central, master, slave, etc.) 8 bits supplied by the master; width is determined by the largest AXI ID width among all masters 2 bits that identify the slave interface of the identified interconnect

Table 5-3 lists all possible AXI ID values that a slave can observe. Table 5-3: Slave Visible AXI ID Values Master
AXI_HP0 AXI_HP1 AXI_HP2 AXI_HP3 DMAC controller AHB masters DevC DAP

Master ID width
6 6 6 6 4 3 0 0

AXI ID (as seen by the slaves)

13b00000xxxxxx00 13b00000xxxxxx01 13b00000xxxxxx10 13b00000xxxxxx11 13b0010000xxxx00 13b00100000xxx01 13b0100000000000 13b0100000000001

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Table 5-3:

Slave Visible AXI ID Values (Contd) Master

S_AXI_GP0 S_AXI_GP1

Master ID width
6 6 8 8

AXI ID (as seen by the slaves)

13b01000xxxxxx10 13b01000xxxxxx11 13b011xxxxxxxx00 13b100xxxxxxxx00

CPUs, AXI_ACP via L2 M1 port CPUs, AXI_ACP via L2 M0 port Notes:

x, which can be either 0 or 1 , originates from the requesting master.

5.1.7 Read/Write Request Capability

The R/W Request Capability shown in Figure 5-1 and in Table 5-1 describes the maximum number of requests that the master of a datapath can issue. This does not mean the master can always issue that maximum number of requests under any circumstances or scenarios. There are conditions where other limiting factors can be active to reduce the number of requests. One particular example is the extended write rule in the deadlock avoidance scheme, which ensures the network only issues a write transaction (on the AW channel) if all the outstanding write transactions have had the last write data beat transmitted (on the W channel). Under this rule, if the number of write data beats is large, preventing a second write request from being issued in a certain spot in the network, because the network must wait until the last beat of write data of the first write is transmitted, then only a single write request can be issued by a master.

5.1.8 Register Overview

Table 5-4 provides an overview of the GPV registers. Table 5-4:
Function TrustZone

GPV Register Overview

Name security_gp0_axi security_gp1_axi qos_cntl, max_ot, max_comb_ot, aw_p, aw_b, aw_r, ar_p, ar_b, ar_r Overview Control boot secure settings for the slave ports of the slave interconnect. Control advanced QoS features, maximum number of outstanding transactions, AW and AR channel peak rates, burstiness, average rates.

Advanced QoS

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5.2 Quality of Service

5.2.1 Basic Arbitration
Each interconnect (central, master, slave, memory) uses a two-level arbitration scheme to resolve contention. The first-level arbitration is based on the priority indicated by the AXI QoS signals from the master or programmable registers. The highest QoS value has the highest priority. The second-level arbitration is based on a least recently granted (LRG) scheme and is used when multiple requests are pending with the same QoS signal value. Information on OCM arbitration can be found in Chapter 10, DDR Memory Controller.

5.2.2 Advanced QoS

In addition to the basic arbitration, the interconnect provides an advanced QoS control mechanism. This programmable mechanism influences interconnect arbitration for requests from these masters: CPUs and ACP requests to DDR (via L2 cache controller port M0) DMA controller requests to DDR and OCM (via the central interconnect) AMBA master requests to DDR and OCM (via the central interconnect)

In the PS, advanced QoS modules exist on the following paths: Path from L2 cache to DDR Path from DMA controller to the central interconnect Path from AHB masters to the central interconnect

The QoS module is based on ARMs QoS-301, which is an extension to the NIC-301 network interconnect. They provide facilities to regulate transactions as follows: Maximum number of outstanding transactions Peak rates, Average rates Burstiness

For more information, refer to CoreLink QoS-301 Network Interconnect Advanced Quality of Service Technical Reference Manual. The usage of QoS arbitration for all slave interfaces should be used with careful deliberation, as fixed priority arbitration leads to starvation issues if not used properly. By default, all ports have equal priority so starvation is not an issue.

Rationale
The user is expected to create well behaved masters in the PL, which sufficiently throttle their rate of command issuance, or use the AXI_HP issuance capability settings. However, traffic from CPUs

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(through L2 cache), the DMA controller, and the IOP masters can interfere with traffic from the PL. The QoS modules allow users to throttle these PS masters to ensure expected/consistent throughput and latency for the user design in the PL or specific PS masters. This is especially useful for video,

which requires guaranteed maximum latency. By regulating the irregular masters like CPUs, the DMA controller, and IOP masters, it is possible to guarantee max latency for PL-based video.

5.2.3 DDR Port Arbitration

The PS interconnect uses all four QoS signals except where it attaches to the DDR memory controller, which takes only the most significant QoS signal. A 3-input mux selects among this QoS signal, another signal from the SLCR.DDR_URGENT register, and a DDRARB signal directly from the PL to determine if a request is urgent. Refer to the DDR memory controller chapter for more details.

5.3 AXI_HP Interfaces

The four AXI_HP interfaces provide PL bus masters with high bandwidth datapaths to the DDR and OCM memories. Each interface includes two FIFO buffers for read and write traffic. The PL to memory interconnect routes the high-speed AXI_HP ports to two DDR memory ports or the OCM. The AXI_HP interfaces are also referenced as AFI (AXI FIFO interface), to emphasize their buffering capabilities. The PL level shifters must be enabled via LVL_SHFTR_EN before PL logic communication can occur.

5.3.1 Features
The interfaces are designed to provide a high throughput data path between PL masters and PS memories including the DDR and on-chip RAM. The main features include: 32- or 64-bit data wide master interfaces (independently programmed per port) Efficient dynamic upsizing to 64-bits for aligned transfers in 32-bit interface mode, controllable via AxCACHE[1] Automatic expansion to 64-bits for unaligned 32-bit transfers in 32-bit interface mode Programmable release threshold of write commands Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS Smoothing out of long-latency transfers using 1 KB (128 by 64 bit) data FIFOs for both reads and writes QoS signaling available from PL ports Command and Data FIFO fill-level counts available to the PL Standard AXI 3.0 interfaces supported Programmable command issuance to the interconnect, separately for read and write commands Large slave interface read acceptance capability in the range of 14 to 70 commands (burst length dependent)

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Large slave interface write acceptance capability in the range of 8 to 32 commands (burst length dependent)

5.3.2 Block Diagram

Figure 5-3 shows the block diagram for the AXI_HP interfaces.
X-Ref Target - Figure 5-3

64-bit PS AXI Channels

RdAddr

RdData APB I/F

WrAddr

WrData

BResp

Read Channel

Write Channel

RdAddr Channel Q

RdData Channel FIFO

WrAddr Channel Q

WrData Channel FIFO

BResp Channel Q

Registers

QoS en Issue Capability

FIFO Levels

QoS en Issue Capability WrAddr

FIFO Levels

32/64-bit PL AXI Channels

RdAddr

RdData

WrData

BResp
UG585_c5_03_072412

Figure 5-3:

AXI_HP Block Diagram

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5.3.3 Functional Description

There are two sets of AXI ports, one set connecting directly to the PL and the other connecting to the AXI interconnect matrix, allowing access to DDR and OCM memory (see Figure 5-4).
X-Ref Target - Figure 5-4

High Performance AXI Controllers

(AXI_HP) M0
FIFO

M1
FIFO

M2
FIFO

M3
FIFO

S0

S1

S2

S3

Memory Interconnect
M0 M1 M2

Central Interconnect

S0 M

S1

OCM Interconnect

SCU
S1 S0

L2-cache

On-chip RAM

S3

S2

S1

S0

DDR Memory Controller

UG585_c5_04_050212

Figure 5-4:

High Performance (AXI_HP) Connectivity

5.3.4 Performance
See Chapter 22, Programmable Logic Design Guide for more information.

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5.3.5 Register Overview

A partial list of registers related to the high performance AXI port is listed in Table 5-5 Table 5-5: High Performance (AFI) AXI Register Overview Register Name
AFI_RDCHAN_CTRL AFI_WRCHAN_CTRL AFI_RDCHAN_ISSUINGCAP AFI_WRCHAN_ISSUINGCAP AFI_RDQOS AFI_WRQOS AFI_RDDATAFIFO_LEVEL AFI_WRDATAFIFO_LEVEL

Module

Overview
Select 64- or 32-bit interface width mode. Various bandwidth management control settings. Maximum outstanding read/write commands. Read/write register-based Quality of Service (QoS) priority value. Read/write data FIFO register occupancy. Change arbitration priority of HP (and central interconnect) accesses at OCM with respect to SCU writes. Various priority settings for arbitration at DDR controller for AXI_HP (AFI) ports 2 and 3. Various priority settings for arbitration at DDR controller for AXI_HP (AFI) ports 0 and 1. Level shifters. Must be enabled before using any of the PL AXI interfaces.

AXI_HP

OCM

OCM_CONTROL axi_priority_rd_port2 axi_priority_wr_port2 axi_priority_rd_port3 axi_priority_wr_port3 LVL_SHFTR_EN

DDRC

SLCR

5.3.6 Bandwidth Management Features

For applications requiring multiple programmable logic masters on multiple high performance AXI interface ports simultaneously, and in the presence of a medium or heavily loaded PS system, the management of the bandwidth per programmable logic port or thread becomes more difficult. For example, if real-time type traffic is required on one thread, possibly mixed with non real-time traffic on other threads/ports, the standard AXI 3.0 bus protocol does not explicitly provide methods to manage priority. The high performance AXI interface module does provide several functions to assist priority and queue management. The majority of management functions are provided to both the programmable logic design as PL signals and the PS as registers, as performance optimization is application dependent. This allows maximum flexibility, while simplifying the high performance AXI interface requirements. The additional signals provided to the PL, in addition to standard AXI3 signals are provided in Table 5-6. The priority and occupancy management functions provided are discussed in the following sections.

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Table 5-6:

Additional per-port HP PL Signals PS-PL Signal Name

SAXIHP{0-3}RCOUNT[7:0] SAXIHP{0-3}WCOUNT[7:0] SAXIHP{0-3}RACOUNT[2:0] SAXIHP{0-3}WACOUNT[5:0] SAXIHP{0-3}AWQOS[3:0]

Type

I/O
O O O O I I I

Description
Fill level of the RdData Channel FIFO Fill level of the WrData Channel FIFO Fill level of the RdAddr Channel FIFO Fill level of the WrAddr Channel FIFO WrAddr Channel QOS input. Qualified by SAXIHP{0-3}AWVALID RdAddr Channel QOS input. Qualified by SAXIHP{0-3}ARVALID When asserted (1), indicates that the Maximum Outstanding Read Commands (Issuing Capability) should be derived from the rdIssueCap1 register. When asserted (1), indicates that the Maximum Outstanding Write Commands (Issuing Capability) should be derived from the wrIssueCap1 register.

FIFO Occupancy

Quality of Service SAXIHP{0-3}ARQOS[3:0] SAXIHP{0-3}RDISSUECAP1EN

Interconnect Issuance Throttling

SAXIHP{0-3}WRISSUECAP1EN

QoS Priority
The AXI QoS input signals can be used to assign an arbitration priority to the read and write commands. Note that the PS interconnect allows either master control or programmable (register) control as a configuration option. For the AFI, it is desirable to have the ability for masters to dynamically change the QOS inputs. However, to provide flexibility, the register field AFI_RDCHAN_CTRL.FabricQosEn is provided. This allows a static QoS value to be programmed via the high performance AXI interface port, ignoring the PL AXI QoS inputs.

FIFO Occupancy
The level of the data and command FIFOs for both read and write are exported to the PL allowing the user to take advantage of the QOS feature supported by the top-level interconnect. Based on the relative levels of these FIFOs, a PL controller could dynamically change the priority of the individual read and write requests into the high performance AXI interface block(s). If, for instance, a particular PL master read data FIFO is getting too empty, the priority of the read requests could be increased. The filling of this FIFO now takes priority over the other three FIFOs. When the FIFO reaches an acceptable fill-level, the priority typically is reduced again. The exact scheme used to control the relative priorities is flexible as it must be performed in the programmable logic. Note that the FIFO Level should be used as a relative level as opposed to an exact level, because clock domain crossing is involved. Another possible application of the FIFO levels is using them to look-ahead at the data fill level to determine if data can be read or written without having to use the AXI RVALID/WREADY handshake signals. This could potentially simplify the AXI interface design logic, enabling higher speeds of operation.

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Interconnect Issuance Throttling

To optimize the latency or throughput of other masters in the system such as the CPUs, it might be desirable to constrain the number of outstanding transactions that a high-performance port requests to the system interconnect. Issuing capability is the maximum number of outstanding commands that a HP can request at any one time. Control of the read and write command issuing capability of the high performance AXI interface is available as a primary input from the logic. This option can be enabled via the DDRC.AFI_XXCHAN_CTRL FabricOutCmdEn registers. The logic signals, SAXIHP{0-3}RDISSUECAP1_EN and SAXIHP{0-3}WRISSUECAP1_EN allow the user to change the issuing capability of the AFI block to the PS dynamically between two levels.

Write FIFO Store and Forward

The write channels can be configured to store-and-forward write commands or allow them to pass through with no storage. The following two registers control the mode of write store and forward: AFI_WRCHAN_CTRL.[WrCmdReleaseMode] AFI_WRCHAN_CTRL.[WrDataThreshold]

The Mode register selects between a complete AXI burst store-and-forward, a partial AXI burst store-and-forward, or a pass through (no store at all). If absolute minimum latency for write commands is required, the pass-through mode could be selected. However, in cases where multiple masters are competing for the system slaves, better system performance can likely be achieved using at least the partial AXI burst store-and-forward mode. This is because once an AXI write is committed at each point throughout the PS, the entire burst must be processed before any other write data from other write commands can be processed. For example, using pass-through mode, if one HP port with a slow clock rate issues a long burst, a second port with a faster clock rate might need to wait until the entire slower write data burst has been transferred, even if all of the write data on the fast clock is available. This is different from the case of reads, where read data interleaving is permitted.

32-bit Interface Considerations

Each physical high performance PL AXI interface is programmable to be either a 32-bit or 64-bit interface through the register field AFI.AFI_xxCHAN_CTRL.[32BitEn]. Note that the read and write channels have separate enables and can therefore be configured differently.

Upsizing and Expansion

In 32-bit mode, some form of translation between the 32-bit port and the 64-bit port is required. For write data, the 32-bit data (and write strobes) must be aligned correctly onto the appropriate lanes in the 64-bit domain. For read data, the appropriate lanes of the 64-bit data must be aligned onto the 32-bit data bus. This data alignment between different width interfaces ware automatically dealt with by the high performance AXI interface module.

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For the 32-bit mode, an expansion or upsizing must be performed to the 64-bit bus. These are defined as follows: Expansion. The AxSIZE[] and AxLEN[] fields remain unchanged on the 64-bit bus. The number of data beats in the 64-bit domain is therefore the same as the number of data beats in the 32-bit domain. This is the simplest option but also the most inefficient in terms of bandwidth utilization. Upsizing. This is an optimization that makes better use of the 64-bit bus available bandwidth. The AxSIZE[] field can be changed to `64-BIT (expansion case it is `32-BIT or less) and the AxLEN[] field can potentially be adjusted to make use of the 64-bit bus. For a full width transfer, the number of data beats in the 64-bit domain is now, at best, half the number of data beats in the 32-bit domain. For example, a burst of 16x32-bit is upsized to a burst of 864-bit.

Note: Upsizing only occurs if the AxCACHE[1] bit is set. If it is not, expansion of the command
occurs. This means that the user can dynamically control, on a per-command basis, whether to expand or upsize.

internal 64-bit PS transactions. Whatever appears at the PL port is passed as is to the PS port. In 64-bit mode no upsizing or expansion is performed. This also applies to narrow transactions in the 64-bit mode.

Note: In 64-bit mode, there is no translation between the programmable logic transactions and the

32-bit Interface Limitations

The high performance AXI interface imposes the following constraints: 1. In 32-bit mode, only burst multiples of 2, incremental burst read commands, aligned to 64-bit boundaries are upsized. All other 32-bit commands are expanded. These include all narrow transactions (wrap as well as fixed burst types). Whenever an expanded read command is accepted from the programmable logic by the AFI, this command is blocked until all outstanding high performance AXI interface read commands in the pipeline are flushed. The flushing occurs automatically under control of the AFI.

2.

The implication of the above is that for expanded commands, performance is very limited, as command pipelining is essentially disabled.

Note: All valid AXI command are still supported, just not optimized to take advantage of the 64-bit
bus bandwidth. In the case of write commands completing out-of-order, no performance penalty is incurred because the BRESP can be issued in any order directly back to the PL ports. To be symmetric across read and write operations, the high performance AXI interface also only upsizes 64-bit aligned burst multiples of 2, incremental burst write commands, in 32-bit mode. In the case of writes however, no blocking of expanded commands occur. Write performance for expanded commands in 32-bit mode is therefore much higher than read performance.

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5.3.7 Transaction Types

Table 5-7summarizes the different command types issued to the high performance AXI interface from the PL and the command modifications that occur. Table 5-7: No.
1 2 3 4 5 6 7 8

High Performance AXI Interface Command Types Mode

64-bit 64-bit 64-bit 64-bit 32-bit 32-bit 32-bit 32-bit

Command Type
64-bit Reads All Burst types Narrow Read 64-bit Write All Burst types Narrow Write 32-bit INCR Read Aligned to 64-bits Even burst multiples All other 32-bit Read Commands 32-bit INCR Write Aligned to 64-bits Even burst multiples All other 32-bit Write Commands

Translation
None None None None Upsized to 64-bits Expanded to 64-bits Upsized to 64-bits Expanded to 64-bits

Comments
Best optimization possible. Because no upsizing is performed, the narrower the width, the more inefficient the transaction. Best optimization possible. Because no upsizing is performed, the narrower the width, the more inefficient the transaction. Best 32-bit mode optimization possible. Each read command is blocked until all previous read commands are completed. Extremely inefficient. Best 32-bit mode optimization possible. Relatively inefficient because no upsizing is performed. No blocking occurs for writes.

5.3.8 Command Interleaving and Re-Ordering

When multi-threaded commands are used in AXI, there is the potential for commands being processed out-of-order as well as interleaving of data beats. The DDR controller guarantees that all read commands are completed continuously, that is, it does not interleave read data onto its external AXI ports. It does however take advantage of re-ordering of read and write commands, to perform internal optimizations. It is therefore expected that read and write commands issued to the DDR controller are sometimes completed in a different order from which they were issued. Read data interleaving is not supported by either the DDR or the OCM. However, the interconnect might introduce read data interleaving into the system when a single PL port issues multi-threaded read commands to both the DDR and OCM memories. From the high performance AXI interface's perspective: Both read and write commands can be re-ordered. Read data interleaving might occur.

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5.3.9 Performance Optimization Summary

This section summarizes the most important considerations when using the high performance AXI interface module from a software or user perspective. For general purpose AXI transfers, use the general purpose PS AXI ports and not these ports. These ports are optimized for high throughput applications, but have various limitations. Table 5-5 summarizes the different command types issued to the high performance AXI interface module from the PL and the way in which they are dealt with. When using 32-bit mode, it is strongly recommended not to use commands of the type shown in line 6 of Table 5-5, as this impacts performance significantly. The QoS PL inputs can be controlled from physical programmable logic signals or statically configured in APB registers. The signals allow QoS values to be changed on a per-command basis. The register control is static for all commands. The AxCACHE[1] must be set for upsizing to occur. If this bit is not set, expansion always occurs. If the PL design demands a continuous read data flow after the first data beat has been read, the design must first allow the read data FIFO to fill with the complete transaction data before popping the first data beat out. The FIFO level is exported to the PL for this purpose. This behavior might be useful if the PL master is not able to be throttled by RVALID after the first data exits the read FIFO. Wait-states can be inserted if write commands are not asserted at least one cycle ahead of the corresponding first write data beat in 32-bit AXI channel slave interface mode. The PL masters should be able to handle read data interleaving. If it is desired that they not deal with this issue, they should not issue multi-threaded read commands to both the OCM and DDR from the same port by using the same ARID value for all outstanding read requests. The relationship of write FIFO occupancy to the write data ready to accept signal (WREADY) varies as follows:

In 64-bit AXI mode: FIFO not full (SAXIHP0WCOUNT << 128) always implies WREADY=1 . In 32-bit AXI mode: There is a dependency between the write address (AWVALID) and the write data (WVALID). If the write address is presented at least one cycle before the first beat of any given write data burst, then the FIFO not full (SAXIHP0WCOUNT << 128) implies WREADY= 1 . If not, then WREADY is de-asserted until the write address is produced. The reason for this back pressure is that in 32-bit mode, expansion/upsizing is performed on the data into the write data FIFO.

Write response (BVALID) latency is dependent on many factors, such as DDR latency, DDR transaction reordering, and other conflicting traffic (including higher-priority transactions). Write commands and data are sent the entire path to the slave (DDR or OCM) and the response is issued by the slave to return to the high performance AXI interface. Transactions issued after reception of the write response is guaranteed to be committed later at the slave than the responded write transaction.

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5.4 AXI_ACP Interface

The accelerator coherency port provides low-latency access to programmable logic masters, with optional coherency with L1 and L2 cache. From a system perspective, the ACP interface has similar connectivity as the APU CPUs. Due to this close connectivity, the ACP directly competes with them for resource access outside of the APU block. Figure 5-5 gives an overview of the ACP connectivity. The PL level shifters must be enabled via LVL_SHFTR_EN before PL logic communication can occur. For more information about the ACP interface, including its limitations, see Chapter 3, Application Processing Unit.
X-Ref Target - Figure 5-5

APU
PL Logic

Accelerator Coherency Port (ACP)

CPUs
Snoopable Data Buffers And Caches L1 Cache Read/Write Line Updates Requests

Cache Coherent Transactions S S Flush Cache Line to Memory Cache Tag RAM Update

Maintain L1 Cache Coherency M0

SCU
M1

Tag RAM

Cacheable and Noncacheable Accesses

System Interconnect

Cacheable and Non-cacheable Accesses to DDR, PL, Peripherals, and PS Registers

OCM
M0

Tag RAM

L2 Cache

Data RAM M1

DDR

System Interconnect
UG585_c5_05_101212

Figure 5-5:

ACP Connectivity Diagram

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5.5 AXI_GP Interfaces

5.5.1 Features
AXI_GP features include: Standard AXI protocol Data bus width: 32 Master port ID width: 12 Master port issuing capability: 8 reads, 8 writes Slave port ID width: 6 Slave port acceptance capability: 8 reads, 8 writes

5.5.2 Performance
These interfaces are connected directly to the ports of the master interconnect and the slave interconnect, without any additional FIFO buffering, unlike the AXI_HP interfaces which has elaborate FIFO buffering to increase performance and throughput. Therefore, the performance is constrained by the ports of the master interconnect and the slave interconnect. These interfaces are for general-purpose use only and are not intended to achieve high performance. The PL level shifters must be enabled via LVL_SHFTR_EN before PL logic communication can occur.

5.6 PS-PL AXI Interface Signals

5.6.1 AXI Signals
AXI signals are identified in Table 5-8. The PL level shifters must be enabled via the LVL_SHFTR_EN register before PL logic communication can occur, refer to section 2.4 PSPL Voltage Level Shifter Enables. Table 5-8: AXI Signals Summary AXI PS Masters AXI Channel M_AXI_GP{0,1} I/O AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP
SAXIGP{0,1}ACLK SAXIHP{0:3}ACLK SAXIACPACLK

I/O

Clock, Reset
MAXIGP{0,1}ACLK I I

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Table 5-8:

AXI Signals Summary (Contd) AXI PS Masters AXI PS Slaves I/O S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP
SAXIGP{0,1}ARESETN SAXIHP{0:3}ARESETN SAXIACPARESETN

AXI Channel

M_AXI_GP{0,1}
MAXIGP{0,1}ARESETN

I/O

Read Address
MAXIGP{0,1}ARADDR[31:0] O SAXIGP{0,1}ARADDR[31:0] SAXIHP{0:3}ARADDR[31:0] SAXIACPARADDR[31:0] SAXIGP{0,1}ARVALID SAXIHP{0:3}ARVALID SAXIACPARVALID SAXIGP{0,1}ARREADY SAXIHP{0:3}ARREADY SAXIACPARREADY SAXIGP{0,1}ARID[5:0] SAXIHP{0:3}ARID[5:0] SAXIACPARID[2:0] SAXIGP{0,1}ARLOCK[1:0] SAXIHP{0:3}ARLOCK[1:0] SAXIACPARLOCK[1:0] SAXIGP{0,1}ARCACHE[3:0] SAXIHP{0:3}ARCACHE[3:0] SAXIACPARCACHE[3:0] SAXIGP{0,1}ARPROT[2:0] SAXIHP{0:3}ARPROT[2:0] SAXIACPARPROT[2:0] SAXIGP{0,1}ARLEN[3:0] SAXIHP{0:3}ARLEN[3:0] SAXIACPARLEN[3:0] SAXIGP{0,1}ARSIZE[1:0] SAXIHP{0:3}ARSIZE[2:0] SAXIACPARSIZE[2:0] SAXIGP{0,1}ARBURST[1:0] SAXIHP{0:3}ARBURST[1:0] SAXIACPARBURST[1:0] SAXIGP{0,1}ARQOS[3:0] SAXIHP{0:3}ARQOS[3:0] SAXIACPARQOS[3:0] ~ ~ SAXIACPARUSER[4:0] I

MAXIGP{0,1}ARVALID

MAXIGP{0,1}ARREADY I MAXIGP{0,1}ARID[11:0]

MAXIGP{0,1}ARLOCK[1:0] O MAXIGP{0,1}ARCACHE[3:0] O MAXIGP{0,1}ARPROT[2:0] O MAXIGP{0,1}ARLEN[3:0] O MAXIGP{0,1}ARSIZE[1:0] O MAXIGP{0,1}ARBURST[1:0] O MAXIGP{0,1}ARQOS[3:0] O ~

Read Data

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Table 5-8:

AXI Signals Summary (Contd) AXI PS Masters AXI PS Slaves I/O S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP
SAXIGP{0,1}RDATA[31:0] SAXIHP{0:3}RDATA[63:0] SAXIACPRDATA[63:0] SAXIGP{0,1}RVALID SAXIHP{0:3}RVALID SAXIACPRVALID SAXIGP{0,1}RREADY SAXIHP{0:3}RREADY SAXIACPRREADY SAXIGP{0,1}RID[5:0] SAXIHP{0:3}RID[5:0] SAXIACPRID[2:0] SAXIGP{0,1}RLAST SAXIHP{0:3}RLAST SAXIACPRLAST SAXIGP{0,1}RRESP[2:0] SAXIHP{0:3}RRESP[2:0] SAXIACPRRESP[2:0] ~ SAXIHP{0:3}RCOUNT[7:0] ~ ~ SAXIHP{0:3}RACOUNT[2:0] ~ ~ SAXIHP{0:3}RDISSUECAP1EN ~

AXI Channel

M_AXI_GP{0,1}
MAXIGP{0,1}RDATA[31:0]

I/O

I MAXIGP{0,1}RVALID I MAXIGP{0,1}RREADY O MAXIGP{0,1}RID[11:0] I MAXIGP{0,1}RLAST I MAXIGP{0,1}RRESP[1:0] I ~

Write Address
MAXIGP{0,1}AWADDR[31:0] O SAXIGP{0,1}AWADDR[31:0] SAXIHP{0:3}AWADDR[31:0] SAXIACPAWADDR[31:0] SAXIGP{0,1}AWVALID SAXIHP{0:3}AWVALID SAXIACPAWVALID SAXIGP{0,1}AWREADY SAXIHP{0:3}AWREADY SAXIACPAWREADY SAXIGP{0,1}AWID[5:0] SAXIHP{0:3}AWID[5:0] SAXIACPAWID[2:0] I

MAXIGP{0,1}AWVALID

MAXIGP{0,1}AWREADY I MAXIGP{0,1}AWID[11:0]

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Table 5-8:

AXI Signals Summary (Contd) AXI PS Masters AXI PS Slaves I/O S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP
SAXIGP{0,1}AWLOCK[1:0] SAXIHP{0:3}AWLOCK[1:0] SAXIACPAWLOCK[1:0] SAXIGP{0,1}AWCACHE[3:0] SAXIHP{0:3}AWCACHE[3:0] SAXIACPAWCACHE[3:0] SAXIGP{0,1}AWPROT[2:0] SAXIHP{0:3}AWPROT[2:0] SAXIACPAWPROT[2:0] SAXIGP{0,1}AWLEN[3:0] SAXIHP{0:3}AWLEN[3:0] SAXIACPAWLEN[3:0] SAXIGP{0,1}AWSIZE[1:0] SAXIHP{0:3}AWSIZE[2:0] SAXIACPAWSIZE[2:0] SAXIGP{0,1}AWBURST[1:0] SAXIHP{0:3}AWBURST[1:0] SAXIACPAWBURST[1:0] SAXIGP{0,1}AWQOS[3:0] SAXIHP{0:3}AWQOS[3:0] SAXIACPAWQOS[3:0] ~ ~ SAXIACPAWUSER[4:0]

AXI Channel

M_AXI_GP{0,1}
MAXIGP{0,1}AWLOCK[1:0]

I/O

O MAXIGP{0,1}AWCACHE[3:0] O MAXIGP{0,1}AWPROT[2:0] O MAXIGP{0,1}AWLEN[3:0] O MAXIGP{0,1}AWSIZE[1:0] O MAXIGP{0,1}AWBURST[1:0] O MAXIGP{0,1}AWQOS[3:0] O ~

Write Data
MAXIGP{0,1}WDATA[31:0] O MAXIGP{0,1}WVALID O MAXIGP{0,1}WREADY I MAXIGP{0,1}WID[11:0] O MAXIGP{0,1}WLAST O SAXIGP{0,1}WDATA[31:0] SAXIHP{0:3}WDATA[63:0] SAXIACPWDATA[63:0] SAXIGP{0,1}WVALID SAXIHP{0:3}WVALID SAXIACPWVALID SAXIGP{0,1}WREADY SAXIHP{0:3}WREADY SAXIACPWREADY SAXIGP{0,1}WID[5:0] SAXIHP{0:3}WID[5:0] SAXIACPWID[2:0] SAXIGP{0,1}WLAST SAXIHP{0:3}WLAST SAXIACPWLAST I

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Table 5-8:

AXI Signals Summary (Contd) AXI PS Masters AXI PS Slaves I/O S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP
SAXIGP{0,1}WSTRB[3:0] SAXIHP{0:3}WSTRB[7:0] SAXIACPWSTRB[7:0] ~ SAXIHP{0:3}WCOUNT[7:0] ~ ~ SAXIHP{0:3}WACOUNT[5:0] ~ ~ SAXIHP{0:3}WRISSUECAP1EN ~

AXI Channel

M_AXI_GP{0,1}
MAXIGP{0,1}WSTRB[3:0]

I/O

O ~

Write Response
MAXIGP{0,1}BVALID I MAXIGP{0,1}BREADY O MAXIGP{0,1}BID[11:0] I MAXIGP{0,1}BRESP[1:0] I SAXIGP{0,1}BVALID SAXIHP{0:3}BVALID SAXIACPBVALID SAXIGP{0,1}BREADY SAXIHP{0:3}BREADY SAXIACPBREADY SAXIGP{0,1}BID[5:0] SAXIHP{0:3}BID[5:0] SAXIACPBID[2:0] SAXIGP{0,1}BRESP[1:0] SAXIHP{0:3}BRESP[1:0] SAXIACPBRESP[1:0] O

5.6.2 AXI Clocks and Resets

Each interface has a single clock for all five channels that make up an interface. This clock is provided by the PL. All clocks must be active and all resets must be inactive on all PS-PL AXI interfaces for the GPV to function properly. The entire PS might hang if this condition is not satisfied and a GPV access is attempted. Therefore, no GPV access should be attempted if not all of the clocks for the PS-PL AXI interfaces are connected and operating.

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Boot and Configuration

6.1 Introduction
The boot ROM is responsible for the power on boot up process. Based on the boot mode strapping pins on the hardware board, the boot mode is selected. After a power-on, the boot ROM reads the boot mode register to determine the user-configured boot mode.The boot mode is sampled only on POR and not in soft reset. The user selectable boot modes can be Quad-SPI, SD card, NAND Flash, NOR Flash or JTAG. Post power-on, the boot ROM configures the required sections of the PS to read the images from the selected boot device. The boot ROM first reads the boot header and based on the configuration parameters set in the header, performs the authentication of the image, loads the FSBL image from Flash to OCM, and hands over the control to the FSBL. In addition to the four boot modes listed above, the boot ROM also supports JTAG boot mode. The boot ROM can also operate in secure or non-secure mode depending on the configuration set by the user in the boot header. All boot modes, except the JTAG boot mode, execute code within the CPUs to configure both the PS and PL sections of the Zynq-7000 AP SoC device. JTAG boot mode has control flexibility for a development environment, but can only be used in a non-secure operating mode. When the system boots in non-secure JTAG mode, the primary CPU halts execution by executing a WFE instruction. The JTAG connections are explained in Chapter 27, JTAG and DAP Subsystem. The FSBL normally contains CPU instructions to further configure the PS using register reads/writes and to configure the PL using the device configuration unit (DevC). This interface supports decryption of the FSBL and bitstream for the PL. This chapter describes the following topics: External Startup Requirements

Power, resets , boot mode pins , and clocks Hard-coded CPU instructions to configure the PS for the boot device PCAP/HMAC/AES

Boot ROM

Device Configuration Interface

The device configuration unit (DevC) includes all the methods and procedures for initializing and configuring the PL under software control.

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The DevC uses the Advanced Encryption Standard (AES) and Hash-based Message Authentication Code (HMAC) for decryption of the FSBL and PL bitstream. These are accessed via the DevC and the Processor Configuration Access Port (PCAP).

6.1.1 Boot-up Stages

Stage 0
Hard-coded boot ROM executes on the primary CPU after power-on reset, system, or software reset. Resets are explained in Chapter 26, Reset System.

Stage 1
This is generally the FSBL, but it can be any user-controlled code. Please refer to UG821, Zynq-7000 Software Developer s Guide for details about the FSBL.

Stage 2
This is generally the user processing system design , but it could also be a second stage boot loader (SSBL) . This stage is completely within user control and is not described further in this chapter. Please refer UG821, Zynq-7000 Software Developer s Guide for details about FSBL and stage 2 images.

6.2 External Startup Requirements

6.2.1 Introduction
Zynq-7000 AP SoC devices have power, clock, and reset requirements that must be met for successful boot ROM execution. This section describes those requirements.

6.2.2 Power Requirements

The requirements for the PS and PL are shown in Table 6-1. These power requirements are only for the boot ROM. In stage 1 the PL requires power to configure. For further details on the required power rails refer to Chapter 24, Power Management. Table 6-1: PS and PL Power Requirements Boot Option
Configuration via NAND, NOR, SD card, or Quad-SPI Note: Secure JTAG configuration is not supported

Secure
Yes

Processing System Power

Required

Programmable Logic Power

Required

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Table 6-1:

PS and PL Power Requirements (Contd) Boot Option Secure

No No

Processing System Power

Required Required

Programmable Logic Power

Not Required Required

Configuration via NAND, NOR, SD card, or Quad-SPI Configuration via JTAG

6.2.3 Clock Requirements

PS_CLK must be present and within required operating ranges as specified in the AP SoC devices applicable data sheet. For more information on the PS_CLK refer to Chapter 25, Clocks. PS_CLK must be present before PS_POR_B is de-asserted.

6.2.4 Reset Requirements

There are two main external reset sources that impact the execution of the boot ROM. The resets are: PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal. PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS supply power ramps.

Note: This signal cannot be asserted while the boot ROM is executing from a POR reset. If

PS_SRST_B is asserted while the boot ROM is running through a POR reset sequence it will trigger a lock-down event preventing the boot ROM from completing. To recover from lockdown the device either needs to be power cycled or PS_POR_B needs to be asserted.

Both of these external resets result in the following device flow: If power-on reset (POR) is issued, the BOOT_MODE register is updated If PLL is enabled (not bypass), device waits for the PLL to lock Debug reset (for CPU and DAP) is de-asserted Device enters same path as for a warm reset (see below)

There are also internal warm reset signals that result in the boot ROM executing again. When these reset sources are triggered the following steps occur in the device:

RAM memory clear

All functional clocks are stopped All CPU and peripheral clocks are de-asserted CPU0 starts to execute from the boot ROM

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6.2.5 Mode Pin Settings

Five mode pins, mode[4:0], are used to indicate the boot source, JTAG mode, and PLL bypass selection. Two voltage mode signals, VMODE[1:0], are used to indicate the voltage mode of the multiplexed I/O banks. The mode[4:0] and VMODE[1:0] signals should be connected using pull-up or pull-down 20 K resistors. A pull-up resistor to VCCO_MIO0 specifies a 1 and a pull-down resistor to ground specifies a 0 . The VMODE signals are used to set the individual MIO_PIN registers to the appropriate LVCMOS18 or LVCMOS33 IO standard for all MIO pins while the ROM is running. After the boot ROM completes, the FSBL can change the I/O standard from LVCMOS to HSTL as needed. The VMODE[0] pin is used to set the I/O standard on Bank 0 and VMODE[1] is used to set the I/O standard on Bank 1. The BOOT_MODE and VMODE signals are sampled 50 PS_CLK clocks after the Low-to-High transition of the PS_POR_B reset pin. After being sampled on POR, the BOOT_MODE values are stored in the slcr.BOOT_MODE register. The VMODE values are stored in the slcr.GPIOB_DRVR_BIAS_CTRL register. The BOOT_MODE pins are MIO[6:2] and the VMODE pins are MIO[8:7]. The pins are used as follows: MIO[2] selects the JTAG mode MIO[5:3] selects the boot mode MIO[6] enables the PLLs MIO[8:7] configures the I/O bank voltage

The PS boot mode selections are shown in Table 6-2. The BOOT_MODE bits correspond to the associated register. Table 6-2: Boot_Mode Strapping MIO Pins VMODE[1] VMODE[0] MIO[8] Cascaded JTAG Independent JTAG Boot Devices JTAG NOR NAND
Reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0

BOOT_MODE BOOT_MODE BOOT_MODE BOOT_MODE BOOT_MODE [4] [0] [2] [1] [3] MIO[6] MIO[5] MIO[4] MIO[3] MIO[2]
0 1

MIO[7]

Quad-SPI
Reserved SD Card Reserved

PLL Mode

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Table 6-2:

Boot_Mode Strapping MIO Pins (Contd) VMODE[1] VMODE[0] BOOT_MODE BOOT_MODE BOOT_MODE BOOT_MODE BOOT_MODE [4] [0] [2] [1] [3] MIO[8] MIO[7] MIO[6] 0 1 MIO Bank 0 Voltage MIO[5] MIO[4] MIO[3] MIO[2]

PLL Used PLL Bypassed

2.5 V, 3.3 V 1.8 V

0 1

MIO Bank 1 Voltage 2.5 V, 3.3 V 1.8 V

0 1

6.3 Boot ROM

6.3.1 Introduction and Features
The boot ROM provides the following configuration features: Three different PS configuration methods, including two master modes and one slave mode:

Secure, encrypted image, master mode Non-secure master mode Non-secure slave mode via JTAG Quad-SPI flash NAND flash NOR flash SD card

Four master boot sources:

PS secure configuration using AES-256 and HMAC (SHA-256) SoC debug security Execute-in-place from NOR and QSPI

PS configuration starts after power-on reset. The ARM CPU starts executing code from the on-chip boot ROM with JTAG disabled. The boot ROM contains code for base drivers for NAND, NOR, Quad-SPI, SD card, and PCAP. DDR and other peripheral initializations are not performed from the boot ROM and must be done in the stage 1 image or later. For security reasons, the CPU is always the first device out of reset among all master modules within the PS. While the boot ROM is running, JTAG is disabled to ensure security.

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The boot ROM code is also responsible for loading the stage 1 boot image. AP SoC hardware supports multi-stage user boot image loading; any further user boot image loading after stage 1 is the user's responsibility. When the boot ROM releases control to stage 1, user software assumes full control of entire system. The only way to execute the boot ROM again is by performing a reset. The PS boot source is selected via the BOOT_MODE signals (indicated by a weak pull-up or pull-down applied to specific pins), which are sampled once during power-on reset. The sampled value is stored in the slcr.BOOT_MODE register. The boot ROM supports encrypted and unencrypted images referred to as secure boot and non-secure boot , respectively. Additionally the boot ROM supports beginning execution of the stage 1 image directly from linear flash (NOR or QSPI) when using the execute-in-place (XIP) feature, only for non secure boot images. XIP is possible only for NOR and QSPI modes. In secure boot, the CPU, running from secure boot ROM code, decrypts and authenticates the incoming user PS image, stores it in the OCM RAM, and then branches into it. In non-secure boot, the CPU, running from boot ROM code, disables all secure boot features including the AES engine within the PL before branching to the user image in the OCM RAM or flash (if XIP is used). The PS boot image is limited to 192 KB unless booting with XIP. Any subsequent boot stages for either the PS or the PL are the user's responsibility and are under the user's control. The boot ROM code is not accessible to the user. Following a stage 1 secure boot, the user can proceed with either secure or non-secure subsequent boot stages. Following a non-secure first stage boot, only non-secure subsequent boots stages are possible. For decryption and authentication, the PS uses the hard-wired AES-256 and HMAC (SHA-256) modules within the PL. For this reason, the PL must be powered up during any secure boot, even if only the PS is configured. The device encryption key is user-selectable from either the on-chip eFUSE unit or the on-chip BBRAM. There are five possible boot sources: NAND, NOR, SD card, Quad-SPI, and JTAG. The first four boot sources are used in master boot methods in which the CPU loads the external boot image from non-volatile memory into the PS. JTAG can only be used in slave boot mode, and only supports a non-secure boot. An external host computer acts as the master to load the boot image into the OCM via a JTAG connection. The PS CPU remains in idle mode as the boot image is loaded. The high-level configuration flow for the boot ROM is shown in Figure 6-1.

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X-Ref Target - Figure 6-1

OUT-OF-POWER-ON-RESET-STATE 1. All JTAG Debug Modes are Disabled (SPIDEN, SPNIDEN, DBGEN, NIDEN) 2. ROM Code Access is Disabled 3. Boot Mode Pins are Latched in Power-on-Reset Only.

OUT-OF-SOFTWARE-RESET-STATE (Reset by WDT, SW, JTAG etc) 1. All JTAG Debug Modes are disabled (SPIDEN, SPNIDEN, DBGEN, NIDEN) 2. ROM Code Access is aDisabled Note: DAP Controller is Disabled in a Soft reset.

eFUSE Scan

PLL_BYPASS?

Wait PLL Lock

BIST Clear. ARM Out-Of-Reset and starts executing code from ROM.

Error Lock Down

CPU Initialization

A
PLL Initialization if SW RST If Time Out No Yes

Non Secure Setup

Default Memory Map @ ROM Code Exit

Yes

A
No SEC_EN == 1 192K OCM Boot Secure Feature Disable
1. Set PCFG_AES_EN = 0 2. Set SEC_En = 0 3. Set USER_MODE = 1 4. Lock SEC_LOCK, AES_EN_LOCK, AES_FUSE_LOCK

ROM Default Register Initialization BootStrap Detection By ROM Code. Non Secure Setup Yes No BootStrap == JTAG? Secure Lockdown
Clean PS and PL. Force FORCE_RST Signal to Clean All Internal RAMs

Empty

1M
DDR

Non Secure Setup

Initialize the boot device depending on the Boot Mode.

DAP-AP Enable

1GB

CPU0 & CPU1 are in WFE state. JTAG acess is enabled.

System is Under Reset

1. Set DAP_EN[2:0] = 111 2. Set all ARM DBGEN to 1 2. CPU enter idle mode 3. Enable JTAG_CHAIN_DIS = 0

Peripheral

CPU0 & CPU1 are in WFE state. JTAG acess is enabled.

Start ImageHeader Search

No

Valid Header Found? Yes Load Boot image header from selected boot device.

Exit from this state is POR ONLY.

Disable ROM Code Access

Empty 64K OCM

Boot Header == (BRAM EFUSE) Key

=

Yes

Check if PL is Powered Up

Non Secure Register Pair Initialization

If Time Out No

Yes

Yes XIP_Boot? No

Secure Register Pair Initialization

Yes XIP_Boot? No PSS Boot Code Load

1. Load Pss boot image from select boot devices (NOR, NAND, SD and QSI) into On-Chip RAM.

Secure Featuer Enable

1. Set SEC_EN = 1 2. Set AES_En = 1 3. Set PCFG_AES_FUSE = Header_AES_EFUSE 4. Enable AES_FUSE_LOCK

Non Secure Setup

Non Secure Setup PSS Image Decryption

Branch to External Flash (QSPI or NOR only)

Branch to User Code

CPU Load endrypted PSS Image Through PCAP Interface. PSS Image will be push into a special PCAP register within FPGA configuration logic. FPGA configuration will decrypt incoming image and loop back the decrypted image in parallel with encrypted image loading, Return decrypted image will be written into on-chip RAM within PSS.

Exit to User Code in QSPI/ NOR Flash

Exit to User Code in OCM RAM

Pass HMAC? Yes ROM Code access is disabled. DAP JTAG access is disabled. Branch to User Code.

No

Exit to User Code in OCM RAM

UG585_c6_01_021213

Figure 6-1:

Boot ROM Configuration Flow

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6.3.2 Boot ROM Header

The boot ROM requires a header for all configuration interfaces except JTAG. The boot ROM header format is shown in Table 6-3. For non-secure mode, the PS image is either retrieved from flash and loaded into on-chip RAM directly, or the processor jumps directly to the start location in the NOR/Quad-SPI flash memory (if XIP). For secure mode, the PS image is retrieved from flash, decrypted, and authenticated using the AES and HMAC hardware within the PL. The header controls these boot ROM features: Execute-in-place (length and start of execution fields) Encryption key source (encryption status field) Dual Quad-SPI parallel configuration (width detection field) boot ROM Header Format Fields
Reserved for Interrupts Width Detection Image Identification Encryption Status User Defined Source Offset Length of Image Reserved Start of Execution Total Image Length Reserved Header Checksum Unused Register Initialization Unused FSBL Image

Table 6-3:

Header Word Offset

0x00 - 0x01F 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C - 0x09C 0x0A0 - 0x89C 0x8A0-0x8BF 0x8C0

Table 6-3 shows the layout of the flash boot ROM header with offsets relative from the beginning of the flash ROM. Each word is 32 bits in size. The header between 0 and 0x8C0 is always in clear non-encrypted form regardless of the state of the encryption status word. Default values, usage, and behavior are described in the following sections.

Reserved for Interrupts Byte Offset 0x0

Thirty two (32) 32-bit words from 0 to 0x1F are reserved for interrupts. This is useful for execute-in-place for NOR and QSPI devices. It allows the vector table to be managed in two ways. The first is to use the MMU to remap the flash linear address space to 0x0 . The second method to

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manage the vector table location is to use the coprocessor VBAR register. For more information on setting this register refer to the ARM v7-AR Architecture Reference Manual (see Appendix A, Additional Resources).

Width Detection Byte Offset 0x20

This word has a mandatory value of 0xAA995566 . This value allows the boot ROM to determine data width of a single Quad-SPI device and optional presence of a second parallel Quad-SPI device at power-up. Based on the data read, the boot ROM reconfigures the flash interface so that the flash ROM can be read by the CPU as a linear address space. If this value cannot be found, the boot ROM device performs a lockdown.

Image Identification Byte Offset 0x24

This word has a mandatory value of 0x584C4E58,'XLNX' . This value allows the boot ROM (along with the header checksum field) to determine that a valid flash ROM boot header is present. If the value is not matched, the boot ROM does a lockdown.

Encryption Status Byte Offset 0x28

If the boot image is encrypted, valid values for this field are: 0xA5C3C5A3 (E-Fuse key source) 0x3A5C3C5A (Battery-backed RAM key source)

A value of 0 (zero) indicates a non-encrypted boot image. Any other value causes the boot ROM to do a lockdown.

User Defined Byte Offset 0x2C

This word is user-defined and can be any value. The boot ROM does not interpret or use this field.

Source Offset Byte Offset 0x30

This word contains the number of bytes from the beginning of the flash image where the boot image load image resides. This value is relative to the beginning of the boot ROM header. This offset must be aligned to a 64-byte boundary and must be at or above address offset 0x8C0.

Length of Image Byte Offset 0x34

This word contains the byte count of the load image to transfer to OCM memory. The maximum image length is 0x3000 0 . A value of zero with NOR or QSPI flash causes the boot ROM to execute the FSBL from the associated flash device without copying the image to OCM (XIP).

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Reserved Byte Offset 0x38

This word region is reserved for future use and must be initialized to 0x0 .

Start of Execution Byte Offset 0x3C

This word has different valid values depending on whether execute-in-place is being used. If execute-in-place is not used:

This word must contain the start address relative to the OCM. For non-secure mode the address must be equal to or greater than 0x0 and less than 0x30000 . For secure mode the address must equal 0x0 . Execution attempts outside of the OCM memory space cause a security lockup. This word contains the start address within the Flash device (NOR or QSPI). The address must be within the first 32 MB of the NOR or QSPI linear address space.

If execute-in-place is used:

Total Image Length Byte Offset 0x40

This word contains the total number of bytes loaded by the boot ROM from flash. For non-secure boot this field should equal Length of Image. For secure images this field is larger than Length of Image.

Reserved Byte Offset 0x44

This word region is reserved for future use and must be initialized to 0x0 .

Header Checksum Byte Offset 0x48

The word contains the checksum value of the header which is checked prior to using the data within the header. The checksum is calculated by summing the words from 0x20 to 0x44 and inverting the result.

Unused Byte Offset 0x4C to 0x9F

This area is unused and is available for FSBL or other application utilization.

Register Initialization Byte Offset 0xA0 to 0x89F

This word region contains a simple system to initialize PS registers for the MIO multiplexer and flash clocks. This allows the MIO multiplexer to be fully configured before the stage 1 image is copied into OCM or executed from flash with XIP, and allows for flash device clocks to be set to maximum bandwidth speeds.

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A register initialization appears as two words, first a register address, then a register value. Register initializations can be in any order, and the same register can be initialized with different values as many times as needed. The register initialization is performed prior to copying the stage 1 image allowing modification of the default system setup for maximum configuration performance. The allowable address range depends on whether the image is secure or non-secure: Secure mode allows addresses from 0xF8000100 to 0xF80001AF For non-secure mode refer to 6.3.7 Accessible Addresses for Boot Image Address-Data Writes.

The boot ROM stops register initialization when either 0xFFFFFFFF register address is encountered or after the last register initialization pair ( 0x898 - 0x89F ). Register address values equal to 0xFFFFFFFF or out of the allowed address range cause the boot ROM to perform a security lockup.

FSBL Image Byte Offset 0x8C0

The FSBL image must start at or above this location.

6.3.3 Boot Performance

Various factors determine the PS configuration time in the boot ROM. Those factors include power supply ramp time, configuration mode selected, external non-volatile device used, PS boot image size, and whether the PL is powered. The boot ROM does not configure the PL so additional boot time calculations are needed for the stage 1 image. This section only covers the startup time requirements for the boot ROM to load an image to the OCM and begin execution. This section makes the following assumptions: The boot timer starts when the user turns on the power switch. The boot timer stops when the boot ROM branches to the stage 1 image. All times assume default system values.

The boot timeline is divided into five stages: 1. 2. 3. 4. 5. Power ramp time PLL lock time (TPSPLLLOCK) PL clear time (TPOR) Register initialization Stage 1 image copy/execution

Power supply ramp times can be long. For boot-time critical applications, the user should consider using a high-performance power supply to reduce power ramp time. PLL lock time could vary from 1,000 reference clock cycles to 10,000 reference clock cycles, but it is relatively small compared to the other boot stages. Additionally, register initialization takes a negligible amount of time, but can have a drastic effect on the stage 1 image copy when XIP is not used.

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The PL clear time is variable depending on whether the PL is powered while the boot ROM is running. Secure boot mode and JTAG boot mode require the PL to be powered while the boot ROM is running. If the PL is powered while the boot ROM is running the startup time is extended by TPOR. Given the high internal bandwidth of the DevC DMA module (100 MB/s secure, 400 MB/s non-secure) image load time is typically limited by the non-volatile RAM bus bandwidth. The stage 1 image copy and execute time varies greatly depending on the configuration interface. For specific numbers refer to the applicable Zynq 7000 data sheet. As this is the default stage 1 startup time these numbers can be significantly reduced using the register initialization table in the boot ROM header.

6.3.4 Boot Devices

The boot ROM supports configuration from four different slave interfaces: Quad-SPI NAND NOR flash SD card

Additionally Zynq-7000 devices can be programmed via a JTAG. This section details features of each configuration interface. For details on the specific devices Xilinx recommends for each boot interface please refer to AR 50991 http://www.xilinx.com/support/answers/50991.htm.

Quad-SPI Flash
Quad-SPI booting has these features: x1, x2, and x4 single device configuration Dual x4 device configuration Execute-in-place

The boot ROM uses the width-detection word in the boot header to determine whether configuration is taking place from a single Quad-SPI device or dual parallel Quad-SPI devices. The boot ROM starts Quad-SPI configuration by enabling the single device pins and then attempts to read the width-detection word. If it sees the expected value it continues with the appropriate x4 , x2, or x1 setup . If the boot ROM reads the flash device and sees a value of 0xACCA50AF it sets the controller up for dual x4 Quad-SPI configuration. If the BootROM does not find a value of 0xAA995566 or 0xACCA50AF then it continues searching for an image header to allow for width-detection until the 32 MB address limit. The values loaded in to MIO_PIN registers during the Quad-SPI boot mode are shown in Table 6-4. Initially, the boot ROM enables 4-bit mode and then reads the width-detection word register in the device. If the width indicates an 8-bit data width, then additional MIO pins are enabled as shown in Table 6-4.

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Table 6-4:

Boot ROM Quad-SPI Boot MIO Register Settings MIO Pin Number MIO_PIN Register Setting Pin State I/O I/O Buffer Output, Pull-up
Enabled Enabled Enabled 3-state 3-state 3-state

Quad-SPI I/O Interface Signal Name

External Connection
~ Pull up/down Pull up/down Pull up/down Pull up/down ~

Quad-SPI Boot
QSPI_CS0 QSPI_IO{0:3} QSPI_SCLK0 not Quad-SPI QSPI_SCLK_FB_OUT (not used for boot) not Quad-SPI MIO 1 MIO 2 to 5 MIO 6 MIO 7 MIO 8 MIO 14 to 53 0x0602 0x0602 0x0602 reset value reset value reset value O IO O I I I

4-bit Quad-SPI Boot

QSPI_CS1 QSPI_SCLK1 QSPI_IO{4:7} MIO 0 MIO 9 MIO 10 to 13 reset value reset value reset value I I I 3-state 3-state 3-state ~ ~ ~

8-bit Quad-SPI Boot

QSPI_CS1 QSPI_SCLK1 QSPI_IO{4:7} MIO 0 MIO 9 MIO 10 to 13 0x0602 0x0602 0x1602 O O IO Enabled Enabled Enabled, Pull-up ~ ~ ~

The boot ROM uses the linear addressing feature of the Quad-SPI controller, so only the first 32 MB are accessible for storing the stage 1 image. Memory above the first 32 MB is available after the boot ROM passes execution to the stage 1 image. The boot ROM sets QSPI.LQSPI_CFG to use these settings: CLK_POL: 0 CLK_PH: 0 BAUD_RATE_DIV: 1 (by 4) INST_CODE is set as:

In x1 mode: 0x03 In x2 mode: 0x3B In x4 mode: 0x6B In x1 mode: 0 In x2 and x4 mode: 1

DUMMY_BYTE is set as:

SEP_BUS and TWO_MEM are set if a dual x4 configuration is used

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NAND
NAND boot has these features: 8-bit or 16-bit NAND flash devices Supports ONFI 1.0 device protocol Bad block support 1-Bit hardware ECC support

The boot ROM reads the ONFI compliant parameter information in 8-bit mode to determine the device width. The boot image must be located within 4 GB address space of the NAND flash device. If the device is 16 bits wide, then the boot ROM enables the upper eight I/O signals for a 16-bit data bus. The MIO pin assignments for 8- and 16-bit boot modes are listed in Table 6-5.

Note: The 16-bit NAND interface is not available in the 7z010 CLG225 device.
Table 6-5: Boot ROM NAND Flash Boot MIO Register Settings MIO Pin Number MIO_PIN Register Setting NAND Boot
SMC_NAND_CS_B Addr25, CS1 or other SMC_NAND_ALE SMC_NAND_WE_B SMC_NAND_DATA2 SMC_NAND_DATA0 SMC_NAND_DATA1 SMC_NAND_CLE SMC_NAND_RD_B SMC_NAND_DATA{4:7} SMC_NAND_DATA3 SMC_NAND_WAIT not NAND not NAND MIO 0 MIO 1 MIO 2 MIO 3 MIO 4 MIO 5 MIO 6 MIO 7 MIO 8 MIO 9 to 12 MIO 13 MIO 14 MIO 15 MIO 24 to 53 0x0610 reset value 0x0610 0x0610 0x0610 0x0610 0x0610 0x0610 0x0610 0x1610 0x1610 0x0610 reset value reset value IO I O O IO IO IO O O IO IO I I I Enabled 3-state Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled, Pull-up Enabled, Pull-up 3-state 3-state 3-state ~ Pull up/down Pull up/down Pull up/down Pull up/down Pull up/down Pull up/down Pull up/down ~ ~ ~ ~ ~

NAND Flash I/O Interface Signal Name

Pin State I/O I/O Buffer Output, Pull-up External Connection

8-bit NAND Boot

SMC_NAND_DATA{8:15} MIO 16 to 23 reset value I 3-state ~

16-NAND Boot
SMC_NAND_DATA{8:15} MIO 16 to 23 0x1610 IO Enabled, Pull-up ~

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When working with NAND there are three primary considerations that must be made from the boot ROM standpoint: Bad Blocks: How to read and write RAW data reliably. ECC: Recovering from bit disturbances. Partitioning Memory: dividing flash memory into logical sections (partitions) with consideration for bad blocks.

The BootROM manages bad blocks in the following way: It looks for a bad block table (BBT) in the last four blocks of the NAND flash device. It supports a primary and secondary BBT with versioning allowing safe software updates. If a BBT is not present the boot ROM scans the flash reading the Out-Of-Band (OOB) information to determine the locations of bad blocks. The boot ROM only performs read operations it does not write to flash.

While reading from NAND the boot ROM skips blocks that are marked as bad in the BBT or in the OOB information if a BBT does not exist. For example: consider a flash device has bad blocks located at block 1, 3, and 5 (seeFigure 6-2): When writing the image to flash, blocks 1, 3, and 5 must be skipped. When reading, the boot ROM reads the full user data from the good blocks as they are encountered.

The Zynq NAND controller can manage 1-bit of ECC in hardware. For more details on the ECC capabilities of the controller please refer to chapter 11. The boot ROM is aware of on-die ECC devices and automatically setups the controller so that ECC is disabled on it allowing the NAND device to take care of ECC. The BootROM treats NAND flash as one continuous partition. From a user perspective, this only affects the Multiboot register. The Multiboot register value written is offset by the number of bad blocks leading up to the target address. Consider the following example: Image with two multiboot sections Image is 1 MB in size. Block size is 128 KB. Second multiboot section starts at 512 KB. Bad blocks are located at 128 KB and 256 KB offsets.

In this scenario, the image should be programed as one partition which results in the second multiboot section being offset by 256 KB total (2 blocks worth). When the multiboot register is written it can be set to 512 KB offset and the boot ROM take cares of calculating the new start address based on where the bad blocks reside.

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X-Ref Target - Figure 6-2

User Image

User Image as Programmed

0x00000000 User Data Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10

Key:
User Data Unused Bad Block

0x00000000 Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10

UG585_c6_10_021213

Figure 6-2:

Flash Device with Bad Blocks Example

The boot ROM uses the following NAND timing values: t_rr = 0x02 t_ar = 0x02 t_clr = 0x01 t_wp = 0x03 t_rea = 0x02 t_wc = 0x05 t_rc = 0x05

NOR
NOR boot has these features: Execute-in-place Support for asynchronous flash Supports x8 flash devices

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Densities up to 256 Mb

The boot ROM does not try to perform any configuration detection of NOR flash devices. When NOR is selected for configuration the boot ROM enables the pins in Table 6-6.

Note: The NOR and SRAM interfaces are not available in the 7z010 CLG225 device.
Table 6-6: Boot ROM NOR/SRAM Flash Boot MIO Register Settings MIO Pin Number
MIO 0 MIO 1 MIO 2 MIO 3 to 6 MIO 7 MIO 8 MIO 9 to 10 MIO 11 MIO 12 MIO 13 MIO 14 MIO 15 to 39 MIO 40 to 53

NOR/SRAM Flash I/O Interface Signal Name

SMC_SRAM_CE_B[0] SMC_SRAM_CE_B[1] not NOR/SRAM SMC_SRAM_DQ[0:3] SMC_SRAM_OE_B SMC_SRAM_BLS_B SMC_SRAM_DQ[6:7] SMC_SRAM_DQ4 not NOR/SRAM SMC_SRAM_DQ5 not NOR/SRAM SMC_SRAM_A[0:24] not NOR/SRAM

MIO_PIN Register Setting

0x0608 reset value reset value 0x0608 0x0608 0x0608 0x1608 0x1608 0x0608 0x1608 reset value 0x0608 reset value

Pin State I/O

O I I IO O O IO IO I IO I O I

I/O Buffer Output, Pull-up

Enabled 3-state 3-state Enabled Enabled Enabled Enabled, Pull-up Enabled, Pull-up 3-state Enabled, Pull-up 3-state Enabled 3-state

External Connection
~ ~ Pull up/down Pull up/down Pull up/down Pull up/down ~ ~ ~ ~ ~ ~ ~

The shared memory controller is set up to operate with the following timing parameters in the boot ROM (Register SMC.SET_CYCLES): t_rc = 7 t_wc = 7 t_ceoe = 2 r_wp = 5 t_pc = 2 t_tr = 1 we_time = 0

SD Card
SD boot supports these features: Boot from standard SD or SDHC cards FAT 16/32 file system support for storing initial image

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Up to 32 GB densities

Note: The SD card boot mode is not supported in the 7z010 CLG225 device.
The boot ROM performs these steps while booting SD: 1. 2. 3. 4. 5. Initializes the MIO pins listed in Table 6-7 Configures SDIO_CLK_CTRL to a divisor of 32 and SD_CLK_CTL_R with a value of 1 (divide by 2) Sets the SD controller to operate in 4-bit mode Reads BOOT.BIN from the root of the SD file system and copies it into OCM after parsing the required boot ROM header Starts execution from the beginning of OCM Boot ROM SD Card Boot MIO Register Settings MIO Pin Number
MIO 0, 1 MIO 2 to 8 MIO 9 to 39 MIO 40 MIO 41 MIO 42:45

Table 6-7:

SDIO I/O Interface Signal Name

not SD Card boot not SD Card boot not SD Card boot SDIO_0_CLK SDIO_0_CMD SDIO_0_DATA[0:3]

MIO_PIN Register Setting

reset value reset value reset value 0x0680 0x0680 0x1680

Pin State I/O

I I I O O IO

I/O Buffer Output, Pull-up

3-state 3-state 3-state Enabled Enabled Enabled, Pull up

External Connection
~ Pull up/down ~ ~ ~ ~

For the boot ROM to read BOOT.BIN the SD card must be partitioned so that the first partition is a FAT file system. Additional non-FAT partitions are permitted, but the boot ROM does not use the partitions to boot.

JTAG
When the JTAG boot mode is selected, the CPU halts immediately after it disables access to all security-related items and enables the JTAG port. It is the user's responsibility to manage downloading the boot image into OCM RAM or DDR memory via JTAG before waking up the CPU and continuing the boot process.

Miscellaneous MIO Pin Register Settings

Error Lockdown, JTAG, and System Reset MIO Register pin settings are listed in Table 6-8.

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Table 6-8:

Boot ROM Error Lockdown, JTAG and System Reset MIO Register Settings MIO_PIN Register Setting Pin State PL JTAG Boot Mode
reset value reset value reset value reset value

MIO Pin

System Reset Value

0x1601 0x0601 0x0601 0x1601

Error Lockdown
reset value reset value reset value reset value

I/O
I I O I

I/O Buffer (GPIOB)

3-state, Pull up 3-state 3-state 3-state, Pull up

External Connection
~ Pull up/down Pull up/down ~

MIO pin {0:1} MIO pin {2:6} MIO pin {7:8} MIO pin {9:53}

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6.3.5 Boot ROM MultiBoot and Boot Partition Search

The boot ROM supports partition search in the event of a failure in the primary boot ROM partition. As part of the same mechanism for partition search, the boot ROM supports multiboot where different images can be loaded on device reset. The multiboot and boot partition search follows the flow diagram in Figure 6-3.
X-Ref Target - Figure 6-3

POR REBOOT_OFFSET = 0x0

FSBL

MULTIBOOT

REBOOT_ADDR = REBOOT_OFFSET * 32 KB

Set REBOOT_OFFSET

Yes

MULTIBOOT?

No Warm Reset Read Header at REBOOT_ADDR REBOOT_ADDR += 32 KB HEADER CHECK PASSED? Yes Continue Execution

No

Boot Partition Search

REBOOT_OFFSET = REBOOT_ADDR / 32 KB

Move Image to OCM

Jump to FSBL

BootROM

Stage 1

REBOOT_OFFSET is stored in MULTIBOOT_ADDR[12:0]

UG585_c6_02_071012

Figure 6-3:

MultiBoot and Boot Partition Search

Figure 6-3 demonstrates the multiboot flow from the stage 1 Image. The mechanism used in stage 1 could be used in later device stages as well.

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To use multiboot, multiple images must be placed in flash. Each image requires a boot ROM header. These images can be placed in any order, but after POR the boot ROM uses the first image in flash as the initial image. The steps to use multiboot are as follows: 1. Calculate the REBOOT_OFFSET address: a. This offset is relative to the beginning of flash b. REBOOT_OFFSET can be calculated as: Image Byte Address in Flash / 0x8000 2. 3. Write REBOOT_OFFSET to MULTIBOOT_ADDR[12:0]. Perform a warm/soft reset.

For partition search to work, the golden images should be placed after the image intended for load in the absence of a failure. Figure 6-4 and Figure 6-5 demonstrate the flash layout required for boot partition search. Normally the device boots from the standard image but in the event of a failure the boot ROM searches, finds, and boots from the golden image.
X-Ref Target - Figure 6-4

0x00000000 Standard Image

Flash

Golden Image 0xFFFFFFFF

UG585_c6_03_031712

Figure 6-4:

Standard Flash Layout

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X-Ref Target - Figure 6-5

0x00000000 Standard Image Corrupt

Flash

Golden Image 0xFFFFFFFF

UG585_c6_04_031712

Figure 6-5:

Corrupt Flash

The boot ROM partition search mechanism protects against these failures: An update was started on the standard image but the system was interrupted after erasing the section requiring an update. The write operation began but the write process only partially finished.

The boot ROM partition search mechanism does not protect against these failures: The section of memory where the standard image resides became corrupt by some unspecified means. A complete image was written but it is non-functional.

To provide a mechanism for fallback configuration, the boot ROM provides the following functionality: The boot ROM looks for a keyword in the header to identify a boot ROM image ("XLNX" at offset 0x24 in header). The boot ROM calculates a checksum to verify that the header is not corrupt. (Comparison value is located at 0x48 in header.)

If there is a failure in any of the checks, the boot ROM begins searching on 32 KB boundaries for another image that passes the keyword test and the CRC check. The boot ROM is only capable of handling one fallback image. Additionally, the boot ROM only searches a limited address space on the configuration device: SD card: single image in boot page, no searching NAND: first 128 MB NOR: first 32 MB Quad-SPI, signal/dual SS with 4-bit I/O: first 16 MB Quad-SPI, dual SS with 8-bit Parallel I/O: first 32 MB

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6.3.6 Debug Status

The boot ROM has two methods for communicating that an error occurred in the event of a startup failure: 1. Through the INIT_B pin:

In non-secure mode INIT_B drives Low indicating a failure. In secure mode INIT_B pulses the 16-bit error code.

2.

In non-secure boot JTAG is enabled and the REBOOT_STATUS[15:0] register contains the error code.

In secure mode the INIT_B pulses are meant to be read with an LED on the pin. A long Low pulse on the pin indicates a 1 and a short pulse indicates a 0 . Non-secure boot failures result in the boot ROM disabling access to the AES engine, clearing the PL, and enabling JTAG. After JTAG is enabled, the REBOOT_STATUS register can be read to find the source of the boot failure. Table 6-9 defines some parameters that are used for error checking and the defined error output codes for the boot ROM are identified in Table 6-10. Table 6-9: Error Checking parameters Name
IMAGE_MIN_ADDRESS IMAGE_MAX_ADDRESS IMAGE_MAX_LENGTH

Value
0x00000000 0x00030000 0x00030000

Table 6-10:

Boot ROM Error Output Codes Name Value

0x0002 0x2000

Description
This value is written to the REBOOT_STATUS register when the boot ROM performs a successful handoff in JTAG boot mode. This error occurs for the following reasons: The boot ROM detected a Parallel configuration when reading the first device in x1 mode, but when it went on to read both devices in x4 mode it failed to read the expected sync word. The boot ROM was unable to find a sync word within the image search range. This error occurs if there was a problem detecting the ECC mode required for the NAND device. This error occurs in NOR boot mode if the boot ROM is unable to find a valid header within the image search range. This error occurs in QSPI boot mode if the boot ROM is unable to find a valid header within the image search range. This error occurs in NAND boot mode if the boot ROM is unable to find a valid header within the image search range. This error occurs if there is an error in the boot ROM Header register initialization section. This error is triggered by a destination address being out of range.

SUCCESSFUL_JTAG_SLAVE LQSPI_PERIPHERAL_INIT_ERROR

NAND_PERIPHERAL_INIT_ERROR NOR_MAX_OFFSET_GIS_HUNT_ERROR LQSPI_MAX_OFFSET_GIS_HUNT_ERROR NAND_MAX_OFFSET_GIS_HUNT_ERROR REGISTER_INIT_ERROR

0x2001 0x200B 0x200C 0x200D 0x200E

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Table 6-10:

Boot ROM Error Output Codes (Contd) Name Value

0x200F 0x2010 0x2011 0x2012 0x2100 0x2101 0x2102

Description
This error occurs if the start address does not equal 0 and the header indicates a secure image. This error occurs if the start address is equal to 0xFFFFFFFF in non-secure mode. This error occurs if the image header indicates an eXecute In Place image and the boot mode is NAND. XIP is unsupported on NAND. This error occurs if the image header indicates an eXecute In Place image and the boot mode is SD. XIP is unsupported on SD. This error occurs if the boot ROM Header does not contain XLNX. This error occurs if the image header does not have the right checksum. This error occurs if the image source address is less than the last address of the register initialization area of the boot ROM header unless the image is an XIP image. This error occurs if the image source address is not aligned to a 64 byte boundary. This error occurs if the image destination address is greater than IMAGE_MAX_ADDRESS. This error occurs if the image destination address is less than IMAGE_MIN_ADDRESS if the image length is not equal to 0. This error occurs if the image length is greater than IMAGE_MAX_LENGTH This error occurs if the image destination address plus the image length is greater than IMAGE_MAX_LENGTH This error occurs if the image length is not equal to 0 and the execution address is greater than IMAGE_MAX_LENGTH. This error occurs if the image destination address does not equal 0. This error occurs if the image header indicates an eXecute In Place image (length == 0) and the image is flagged as a secure image. XIP is unsupported in secure mode. This error occurs if the image length is not equal to 0 and the length is greater than IMAGE_MAX_LENGTH. This error occurs if the boot ROM detects an XIP image but the mode is setup to NAND or SD. This error occurs if the header checksum fails before performing a register initialization. This error occurs if the header does not contain XLNX. This error occurs if the register initialization contains addresses that are not within the allowed range. This error occurs if the image length is greater than IMAGE_MAX_LENGTH

SECURE_BAD_IMAGE_START_ADDR_ERROR NON_SECURE_BAD_IMAGE_START_ADDR_ERROR NAND_XIP_ERROR SD_XIP_ERROR IMAGE_ID_INVALID_ERROR_1 IMAGE_HEADER_CHKSUM_INVALID_ERROR_1 IMAGE_SOURCE_ADDR_INVALID_ERROR

IMAGE_SOURCE_ADDR_UNALIGNED_ERROR IMAGE_DEST_ADDR_GT_ERROR IMAGE_DEST_ADDR_LT_ERROR IMAGE_LENGTH_GT_ERROR_1 IMAGE_LENGTH_GT_ERROR_2 IMAGE_EXEC_ADDR_GT_ERROR IMAGE_DEST_ADDR_INVALID_ERROR XIP_IN_SECURE_MODE_ERROR

0x2103 0x2104 0x2105 0x2106 0x2107 0x2108 0x2109 0x210A

IMAGE_LENGTH_GT_ERROR_3 XIP_FROM_NAND_SD_MODE_ERROR IMAGE_ID_INVALID_ERROR_2 IMAGE_HEADER_CHKSUM_INVALID_ERROR_2 IMAGE_REGISTER_INIT_ERROR PCAP_SECURE_IMAGE_LENGTH_GT_ERROR

0x210D 0x210E 0x210F 0x2110 0x2111 0x2200

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6.3.7 Accessible Addresses for Boot Image Address-Data Writes

The register address space for the boot image address-data writes is restricted. Accesses attempted outside of these addresses generates a lockdown. The allowed register accesses depend on the boot mode and are listed in Table 6-11. Table 6-11: Boot Image Address-Data Write Address Ranges Non-Secure Boot Mode
E000_1000 to E000_1FFF E000_D000 to E000_EFFF E010_0004 to E010_0FFF (except E010_0058) E000_E000 to E000_EFFF F800_6000 to F800_6FFF F800_0100 F800_01B4 F800_0204 F800_024C F800_0304 F800_0A00 F800_0AB0 to F800_01B0 to F800_01FF to F800_0234 F800_0100 to F800_01AF to F800_0834 to F800_0A8C to F800_0B74 None None None None None

Address Destination
UART 1 Controller registers Quad-SPI Controller registers SDIO 0 Controller registers SMC Controller DDR Controller

Secure Boot Mode

SLCR registers

6.3.8 Post Boot ROM State

The state of the PS after the boot ROM executes depends on these conditions: Whether secure mode is enabled What the mode pins were set to Whether there was a failure

The mode pins impact which MIO are enabled and what I/O standard they are set to after exiting the boot ROM. Additionally, the mode setting impacts the boot peripheral settings. For example, if Quad-SPI is the selected boot source the needed MIO is enabled and the Quad-SPI controller is set with the necessary settings to read from flash. The modified values for each boot source are documented in the associated boot devices section. The general processor state upon boot ROM exit is as follows: MMU, Icache, Dcache, L2 cache are all disabled Both processors are in the supervisor state ROM code is masked and inaccessible 192 KB of OCM is accessible starting at address 0x0 while 64 KB is accessible starting at address 0xFFFF0000 CPU0 branches into the stage 1 image if no failure takes place CPU1 is in a WFE state while executing code located at address 0xFFFFFE00 to 0xFFFFFFF0

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The full list of registers modified by the boot ROM for JTAG boot mode is listed in Table 6-12. Boot modes that use other configuration interfaces have MIO registers and peripheral registers modified for the associated configuration interface. Table 6-12: Boot ROM Modified Registers Post Boot ROM Value
0x4e00e07f 0x0000001a 0x00000508 0xf8020006 0x40000f30 0xffffffff 0x757bdf0d 0x10800000 0x02060000 0x00000004 0x00100000 0xffe00000 0x00000002 0x9dfec6f5 0x00000002 0x00000001 0x00400002 0x03731093 0x00000018 0x00010101 0x01010101 0x00000020 0x00000114 0x00000020 0x00000208 0x00000056 0x000000fb 0x0000000a 0x00000004 0x0C301166 0x0C301100 0x0C301166 0x0C750077 devcfg.CTRL devcfg.LOCK devcfg.CFG devcfg.INT_STS devcfg.STATUS devcfg.ROM_SHADOW devcfg.UNLOCK devcfg.MCTRL l2cache.reg1_aux_control l2cache.reg15_debug_ctrl mpcore.Filtering_Start_Address_Register mpcore.Filtering_End_Address_Register mpcore.ICCBPR mpcore.Global_Timer_Counter_Register0 mpcore.Global_Timer_Counter_Register1 mpcore.Global_Timer_Control_Register slcr.REBOOT_STATUS slcr.PSS_IDCODE slcr.OCM_CFG slcr.L2C_RAM slcr.OCM_RAM slcr.DDRIOB_DCI_CTRL uart1.Control_reg0 uart1.mode_reg0 uart1.Chnl_int_sts_reg0 uart1.Baud_rate_gen_reg0 uart1.Modem_sts_reg0 uart1.Channel_sts_reg0 uart1.Baud_rate_divider_reg0 slcr.GIOB_CFG_CMOS18 slcr.GIOB_CFG_CMOS25 slcr.GIOB_CFG_CMOS33 slcr.GIOB_CFG_HSTL

Address
0xf8007000 0xf8007004 0xf8007008 0xf800700c 0xf8007014 0xf8007028 0xf8007034 0xf8007080 0xf8f02104 0xf8f02f40 0xf8f00040 0xf8f00044 0xf8f00108 0xf8f00200 0xf8f00204 0xf8f00208 0xf8000258 0xf8000530 0xf8000910 0xf8000a1c 0xf8000a90 0xf8000b70 0xe0001000 0xe0001004 0xe0001014 0xe0001018 0xe0001028 0xe000102c 0xe0001034 0xF8000B04 0xF8000B08 0xF8000B0C 0xF8000B14

Register Name

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Table 6-12:

Boot ROM Modified Registers (Contd) Post Boot ROM Value

0xFFFFFFFF 0x003FFFFF 0xFFFFFFFF 0xFFFFFFFF gpio.INT_DIS_0 gpio.INT_DIS_1 gpio.INT_DIS_2 gpio.INT_DIS_3

Address
0xE000A214 0xE000A254 0xE000A294 0xE000A2D4

Register Name

Post Boot ROM Security

If secure mode is enabled the AES engine is accessible post boot ROM. Conversely if the Zynq-7000 device boots non-secure the AES engine is disabled. By default, upon completion of a secure PS first stage boot, the encryption logic remains enabled. It is the user's responsibility to safeguard the PCAP/ICAP interfaces while AES is enabled. The boot ROM locks a number of bits in the DevC module prior to exiting to ensure security. The bits the boot ROM locks are listed in Table 6-13. Table 6-13:
4 3 2 1 0 Notes:
1. The AES_EN_LOCK bit is only locked in NON_SECURE boot.

DEV_CFG Lock Register Bit Name

AES_FUSE_LOCK AES_EN_LOCK SEU_LOCK SEC_LOCK DBG_LOCK

Bit Position

Lock Status
1 1(1) 0 1 0

Post Boot ROM Debug

In the event of a failure while booting non-secure the boot ROM enables JTAG access so that the REBOOT_STATUS register can be read. A debugging tool like XMD will have full access to the processor when JTAG is enabled. If a failure occurs while booting in secure mode the boot ROM disables the AES engine, clears the OCM, clears the PL, and halts the processor. JTAG is not enabled, consequently, the REBOOT_STATUS value is not available to be read. Instead the 16 bit error code is shown by toggling the INIT_B pin.

Starting Code on the CPU1

CPU0 is in charge of starting any additional code on CPU1. The boot ROM keeps CPU1 essentially in the reset state from power-on-reset. Nothing has been enabled and only a few general purpose registers have been modified to place it in a state where it is waiting at the WFE instruction. There is a small amount of protocol required for CPU0 to start an application on CPU1. When CPU1 receives a system event, it immediately reads the contents of address 0xFFFFFFF0 and jumps to that address. If the SEV is issued prior to updating the destination address location (0xFFFFFFF0 ),

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CPU1 continues in the WFE state because 0xFFFFFFF0 has the address of the WFE instruction as a safety net. If the data that is written to address 0xFFFFFFF0 is invalid or points to uninitialized memory, results are unpredictable. Only ARM-32 ISA code is supported for the initial jump on CPU1. Thumb and Thumb-II code is not supported at the destination of the jump. This means that the destination address must be 32-bit aligned and must be a valid ARM-32 instruction. If these conditions are not met, results are unpredictable. The steps for CPU0 to start an application on CPU1 are as follows: 1. 2. Write the address of the application for CPU1 to 0xFFFFFFF0 Execute the SEV instruction to cause CPU1 to wake up and jump to the application.

The address range 0xFFFFFE00 to 0xFFFFFFF0 is reserved and not available for use until the stage 1 or above application is fully functional. Any access to these regions prior to the successful startup of the second CPU causes unpredictable results.

6.4 Device Configuration Interface

The device configuration interface (DevC), shown in Figure 6-6, consists of three main blocks that operate independently: An AXI-PCAP bridge for interfacing to the PL configuration logic Device security management An XADC interface

The device configuration interface also contains an APB interface used by the host to configure the three blocks, to access the overall status, and to communicate with the PL XADC.

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6.4.1 Block Diagram

X-Ref Target - Figure 6-6

Top-level Switch (AXI Slave Interface)

SOC ROM Security Top-level Switch cpu_1x clk pcap_2x clk Debug Control Reset (APB Master Port) (166.75 Mhz) (200 Mhz)

Device Configuration Interface

APB 3.0 Interface

AXI Master

DMA Engine

AXI-PCAP Bridge

Security Policy

XADC Interface

PL PCAP (100 MHz)

PL Configuration

PL XADC (50 MHz)

UG585_c6_05_071012

Figure 6-6:

DevC Block Diagram

6.4.2 Features
The device configuration interface manages basic device security and provides a simple DMA interface, PS setup, and PL configuration. The DevC: Enables PL configuration through the processor configuration access port (PCAP) in both secure and non-secure master boot, including support for compressed PL bitstreams Supports PL configuration readback Supports concurrent bitstream download/upload Enforces Zynq-7000 device system-level security including debug security Supports XADC serial interface Supports XADC alarm and over-temperature interrupt Secure boot ROM code protection

6.4.3 Functional Description

AXI-PCAP Bridge
The AXI-PCAP bridge converts 32-bit AXI formatted data to the 32-bit PCAP protocol and vice versa. The bridge supports both concurrent and non-concurrent download and upload of configuration data. A transmit and receive FIFO buffer data between the AXI and PCAP interfaces. A DMA engine

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moves data between the FIFOs and a memory device, typically the on-chip RAM, the DDR memory, or one of the peripheral memories. Non-secure data to the PCAP interface can be sent every clock cycle, encrypted data can be sent every four clock cycles. To transfer data across the PCAP interface, the PL must be powered on. The PCAP interface is enabled using the devcfg.CTRL [PCAP_MODE] and [PCAP_PR] bits. If encrypted data is being sent, then the devcfg.CTRL [QUARTER_PCAP_RATE_EN] bit should also be set. Data is transferred through the PCAP interface using the DevC's built in DMA engine. To start a transfer, the four DMA registers must be written in this order: 1. 2. 3. 4. DMA Source Address register DMA Destination Address register DMA Source Length register DMA Destination Length register

To transfer data to the PL via the PCAP interface, the destination address should be 0xFFFF_FFFF. Similarly, to read data from the PL via the PCAP interface, the source address should be 0xFFFF_FFFF. Encrypted PS images must also be sent across the PCAP interface because the AES and HMAC engines reside within the PL. In this case, the DMA source address should be an external memory interface and the destination address should be on-chip RAM. All DevC DMA transactions

must be 64-byte aligned to prevent accidently crossing a 4K byte boundary. The DMA status is tracked using the devcfg.INT_STS[DMA_DONE_INT], devcfg.INT_STS[D_P_DONE_INT] and can be monitored using either interrupts or a polling method.

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X-Ref Target - Figure 6-7

Top-level Switch pcap_2xclk CPU_1x clock

AXI Master Interface

DMA Engine

download

Control

upload

TxFIFO

RxFIFO

APB

PCAP Interface

AXI-PCAP Bridge

pcap_mode

PL PCAP Interface
UG585_c6_06_072412

Figure 6-7:

AXI-PCAP Bridge

The DevC's DMA engine can also be used to load non-secure PS images. Before doing this, the INT_PCAP_LPBK bit should be set in the Miscellaneous Control register. This bit enables an internal loopback that bypasses the PCAP interface. This bit needs to be disabled again before using the PCAP interface. The DMA source address should be an external memory and the destination address should be on-chip RAM or a valid external interface like DDR. All DMA transactions must be 64-byte aligned to prevent a 4K byte boundary from being crossed. The PCAP interface can also be used to perform a PL configuration readback. To perform a readback, the PS must be running software capable of generating the correct PL readback commands. Two DMA accesses are required to complete a PL configuration readback. The first access is used to issue the readback command to the PL. The second access is needed to read the PL readback data from the PCAP. The smallest amount of data that can be read back from the PL is one configuration frame which contains 101 32-bit words. Caution should be taken when using the DevC's DMA in loopback mode. Talking to a slave port that prioritizes writes over reads could lead to a DevC DMA hang. Sample first DMA access for PL readback: 1. DMA Source Address location of PL readback command sequence

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2. 3. 4.

DMA Destination Address desired location to store readback data, note that the on-chip RAM is not large enough to hold a complete PL readback DMA Source Length number of commands in the PL readback command sequence DMA Destination Length number of readback words expected from the PL

There are three limitations when accessing the PL configuration systems: 1. 2. Readback of configuration registers or data cannot be performed until the PCFG_DONE is received (bit-2 of the INT_STS register). A single PCAP readback access cannot be split across multiple DMA accesses. If the readback command sent to the PL requests 505 words, the DevC's DMA must also be setup to process 505 words. Splitting the transaction into two DMA accesses results in data loss and unexpected DMA behavior. The DevC DMA must have sufficient bandwidth to process the PL readback data due to a lack of data flow control on the PL side of the PCAP. Overflow of the PCAP RxFIFO results in data loss and unrecoverable DMA behavior. If adequate bandwidth cannot be allocated to the DevC DMA, then the PCAP clock could be slowed down or the readback could be broken up into multiple smaller transactions. All DMA transactions must be 64-byte aligned to prevent accidently crossing a 4K byte boundary.

3.

4.

For more information regarding PL configuration readback, see UG470, 7 Series FPGAs Configuration User Guide.

Device Security Management

The DevC contains a security policy block that provides these functions: Monitors the system security and can assert a security reset when conflicting status is detected that could indicate inconsistent system configuration or tampering Controls and monitors the PL configuration logic via the APB interface Controls the ARM CoreSight's debug access port (DAP) and debug levels Provides on-chip ROM shadow control

See Chapter 32, Device Secure Boot for more information.

XADC Interface
See Chapter 30, XADC Interface for information.

6.4.4 Device Configuration Flow

PS Master Non-Secure Boot
In this boot mode the PS acts as the device master and the boot ROM loads a plain text PS image from the selected external memory (see Figure 6-8). The PL is not required to be powered on and a PL bitstream can be loaded with the PS image right away or at some later time.

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X-Ref Target - Figure 6-8

bootstrap

ROM On-Chip RAM NAND NOR QSPI IOP

CPU

PS Master
DAP MDDR Flash DDR Memory

AXI Top Switch

Common Boot Path PS Boot Path PL Boot Path

Secure Vault FIFO eFuse/BBRAM Security

AXI

FIFO

Device Configuration Block

PCAP-Stream

Device Key AES HMAC TAP

PL

UG585_c6_07_022513

Figure 6-8: The configuration flow is: 1. 2. Device power-on reset Boot ROM execution a. 3. 4. 5.

PS Master Non-Secure Boot Diagram

Reads bootstrap to determine external memory interface

b. Reads boot header to determine encryption status and image destination Boot ROM uses the DevC's DMA to load the first stage boot loader (FSBL) into on-chip RAM Boot ROM shuts down, releases CPU control to the FSBL (Optional) FSBL loads PL bitstream via PCAP

PS Master Secure Boot

In this boot mode the PS acts as the device master and the boot ROM loads an encrypted PS image from the selected external memory (see Figure 6-9). Because the AES and HMAC engines reside in the PL, the PL is required to be powered on for the initial boot sequence. The Boot ROM verifies that

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the PL has power before attempting to decrypt the FSBL. After the PS has booted, the PL can be configured using an encrypted bitstream or it can be powered down to be configured later.
X-Ref Target - Figure 6-9

bootstrap

ROM On-Chip RAM NAND NOR QSPI IOP

CPU

PS Master
DAP

AXI Top Switch

MDDR Flash DDR Memory

Common Boot Path PS Boot Path PL Boot Path

Secure Vault FIFO eFuse/BBRAM Security

AXI

FIFO

Device Configuration Block

PCAP-Stream

Device Key AES HMAC TAP

PL

UG585_c6_08_022513

Figure 6-9: The configuration flow is: 1. 2.

PS Master Secure Boot Diagram

Device power-on reset, including power-on of PL Boot ROM execution a. c. Reads bootstrap to determine external memory interface Ensures PL is powered on to begin FSBL decryption b. Reads boot header to determine encryption status (secure)

3. 4. 5.

Boot ROM uses the DevCs DMA to send the encrypted FSBL to the AES and HMAC in the PL via PCAP The PL uses the PCAP to return the decrypted FSBL to the PS where it is loaded to the on-chip RAM Boot ROM shuts down, releases CPU control to the FSBL

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6.

(Optional) FSBL configures the PL with an encrypted bitstream

PS Cascade JTAG Non-Secure Boot

In this boot mode the PS is a slave to the JTAG port (see Figure 6-10) and the JTAG mode is set to cascade. The PL's external JTAG pins (PL JTAG) are used requiring that the PL be powered up (see Figure 27-1, page 647 in Chapter 27, JTAG and DAP Subsystem). The AES engine is disabled, secure images are not allowed. The PS can be booted independently or the PS and PL can be configured at the same time. If the PS is booted independently, the PL TAP controller instruction and data registers must be accounted for when data is shifted between TDI and TDO. In the cascaded configuration, the PS DAP registers are the last to be shifted in. After the PS has booted, the PL can be configured or powered down to be configured later.
X-Ref Target - Figure 6-10

bootstrap

ROM

CPU

PS Master
DAP

On-Chip RAM NAND NOR QSPI IOP

AXI Top Switch

MDDR Flash DDR Memory

Common Boot Path PS Boot Path PL Boot Path

Secure Vault FIFO eFuse/BBRAM Security

AXI

FIFO

Device Configuration Block

PCAP-Stream

PL JTAG Device Key AES HMAC TAP

PL

UG585_c6_09_022513

Figure 6-10:

PS Cascade JTAG Non-Secure Boot Diagram

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The configuration flow is: 1. 2. Device power-on reset, including power-on of PL Boot ROM execution a. 3. 4. 5. 6. Reads bootstrap to determine boot mode, JTAG mode is set to cascade b. Performs CRC self-check Disables all security features, enables DAP controller and JTAG chain Boot ROM shuts down, releases CPU control to JTAG PL JTAG port is used to load PS image (Optional) PL JTAG or PS image is used to configure PL

PS Independent JTAG Non-Secure Boot

In this boot mode the PS is a slave to the JTAG port (see Figure 6-10) and the JTAG mode is set to independent. The user must route the PS DAP through EMIO to PL SelectIO pins (EMIO PJTAG). The PL's external dedicated JTAG pins (PL JTAG) and the PLs external SelectIO pins (EMIO PJTAG) are used requiring that the PL be powered up (see Figure 27-1, page 647 in Chapter 27, JTAG and DAP Subsystem). The AES engine is disabled, secure images are not allowed. The PL must be configured to access the PS DAP. When the PS is booted, the Boot ROM execution stalls until the PL is programmed. Once the PL is configured, the PS DAP is accessible via EMIO PJTAG. If the PL gets powered down, the PS DAP is no longer accessible.

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X-Ref Target - Figure 6-11

bootstrap

ROM

CPU

PS Master
DAP

On-Chip RAM NAND NOR QSPI IOP

AXI Top Switch

MDDR Flash DDR Memory

Secure Vault PS Boot Path PL Boot Path eFuse/BBRAM Security FIFO

AXI

FIFO

Device Configuration Block

PCAP-Stream

EMIO PJTAG Device Key AES HMAC TAP PL JTAG

PL

UG585_c6_11_022613

Figure 6-11: The configuration flow is: 1. 2.

PS Independent JTAG Non-Secure Boot Diagram

Device power-on reset, including power-on of PL Boot ROM execution a. Reads bootstrap to determine boot mode, JTAG mode is set to independent b. Performs CRC self-check

3. 4. 5. 6. 7.

Disables all security features, enables DAP controller and JTAG chain Stall until the PL is configured PL JTAG port is used to configure the PL a. The PL bitstream routes the PS DAP to the EMIO PJTAG port (see Figure 27-1, page 647) When PL is configured, Boot ROM shuts down and releases CPU control to JTAG EMIO PJTAG port is used to load PS image

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6.4.5 PL Configuration
With the exception of JTAG, the PL must always be configured using the PCAP. Users are free to configure the PL at any time, whether it is directly after PS boot using the FSBL, or at some later time using an image loaded into the PS. This section describes the requirements for configuring the PL.

Determining the PL Power Status

The PL must first be powered on before it can be configured. When power is applied to the PL it begins its independent power-on reset sequence followed by its housecleaning function which clears all of the PL's configuration SRAM cells. The power-on reset status of the PL can be monitored by the PS. The power status of the PL is tracked in the DevC's Miscellaneous Control register, bit 8. If this bit is set, then the PL has power. The PL power status can also be tracked as an interrupt. Bit 29 of the DevC's Control register, PCFG_POR_CNT_4K, can be used to speed up the PL's power on reset stage. Additional information about the PL power-up status can be obtained by reading bit 5 of the DEVCI Status register. If the bit is Low, then the PL is in a reset state. A transition from Low to High indicates the start of the housecleaning function. At any time, the PCFG_PROG_B bit in the Control register can be used to issue a global reset to the PL. If this bit is set Low, the PL begins its housecleaning sequence, PCFG_INIT is held Low until the PCFG_PROG_B bit is set High.

Configuring the PL via PCAP

To send a configuration bitstream, the PL must be finished with its housecleaning function. This status is indicated by the PCFG_INIT bit in the DevCs Status register. The internal loopback function must also be disabled and the PCAP_MODE must be set. The bitstream is transferred to the PL using the DevC DMA. A successful PL configuration is indicated by the PCFG_DONE flag on the Interrupt Status register. This flag also generates a system interrupt. The configuration flow is: 1. 2. 3. 4. Wait for PCFG_INIT to be set High by the PL (STATUS-bit[4]) Set internal loopback to 0 (MCTRLbit[4]) Set PCAP_PR and PCAP_MODE to 1 (CTRL-bit[27 and 26]) Initiate a DevC DMA transfer a. c. 5. Source address: Location of PL bitstream Source length: Total number of 32-bit words in the PL bitstream b. Destination address: 0xFFFF_FFFF d. Destination length: Total number of 32-bit words in the PL bitstream Wait for PCFG_DONE to be set High by the PL (INT_STS-bit[2])

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PL Reconfiguration
After the PL has been configured, it can be reconfigured using either the PCAP or ICAP. To use the ICAP, the PCAP_PR, bit 27 of the Control register, must be set Low. The initial configuration of the PL must also have connected the ICAP to an external interface or to some logic internal to the PL. To reconfigure the PL using PCAP, the PCAP_MODE and PCAP_PR bits must be set to 1 in the Control register. The internal loopback function must also be disabled. The reconfiguration bitstream is sent to the PL using the DevC DMA, the source and destination is the same as for the initial configuration. PL reconfiguration flow using PCAP: 1. 2. Set PCAP_MODE and PCAP_PR High. Clear the previous configuration from the PL (optional): a. c. 3. 4. 5. 6. Set PCFG_PROG_B High. Check for PCFG_INIT = 0 (STATUS-bit[4]). b. Set PCFG_PROG_B Low. d. Clear PCFG_DONE_INT by writing a 1 to INT_STS[2]. Check for PCFG_INIT = 1 (STATUS-bit[4]). Set INT_PCAP_LPBK Low (MCTRL-bit[4]). Clear D_P_DONE_INT by writing a 1 to INT_STS[12]. Initiate a DevC DMA transfer: a. c. 7. 8. Source Address: Location of new PL bitstream. Source Length: Total number of 32-bit words in the new PL bitstream. b. Destination Address: 0xFFFF_FFFF. d. Destination Length: Total number of 32-bit words in the new PL bitstream. Poll or wait for devcfg.INT_STS[D_P_DONE_INT] to trigger an interrupt. (Optional) Check for PCFG_DONE_INT on INT_STS if the previous configuration was cleared.

The PCFG_DONE flag will not be set if the previous PL configuration was not cleared using PCFG_PROG_B. In this case D_P_DONE_INT should be used to indicate that the new bitstream has been fully transmitted to the PL. It is important to note that the PCAP and ICAP interfaces are mutually exclusive. Only one interface can talk to the PL configuration controller at a time. Which interface is in use is controlled by the PCAP_PR bit in the DevC's Control register. It is possible to use both interfaces in the device, care should be taken to ensure that all outstanding transactions have completed before changing interfaces.

Configuring the PL via JTAG

The PL can be configured using JTAG in either cascade or split mode. To use either JTAG mode, the JTAG chain disable bit on the Control register must be set to 0 . In split mode, the PL behaves like a Xilinx 7 Series FPGA. In cascade mode, the PS DAP controller must also be enabled using the DAP enable bits in the Control register. The PS DAP instruction and data registers must also be accounted

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for. Addition information regarding PL configuration via JTAG can be found in UG470, 7 Series FPGAs Configuration User Guide.

PL Secure Configuration
To perform a secure configuration of the PL, the PS must have booted securely. The AES and HMAC engines can only be enabled by the boot ROM. The procedure for loading a secure bitstream is the same as any other bitstream but the quarter PCAP rate enable bit must be set in the Control register. Because the AES engine only de-crypts one byte at a time, the PCAP can only send one 32-bit word to the PL every four clock cycles.

DMA Done Status

The DevC DMA triggers a DMA_DONE interrupt upon completion of a data transfer. The DMA DONE interrupt can be controlled to trigger when the AXI side of the DMA transaction is complete or when both the AXI and PCAP transfers are complete. This allows the host controlling the DevC DMA to perform scatter-gather type operations by issuing multiple DMA commands but holding off the last transfer DONE interrupt until the AXI and PCAP transactions are done. Setting the two LSBs of the source and destination address to 2'b01 indicates the last DMA command of an overall transfer. The DMA controller uses this information to appropriately set the DMA DONE interrupt. For the last DMA command, the DMA DONE interrupt is triggered when both the AXI and PCAP interfaces are done. For all other DMA commands, the DMA DONE interrupt is set when the AXI transfers are done, however there might still be on-going PCAP transfers. This distinction is made to allow overlapping AXI and PCAP transfers for all, except the last DMA transfer.

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6.4.6 Register Overview

Table 6-14 provides an overview of the device configuration registers. Table 6-14: Device Configuration and Boot Register Overview Description
Control Device Config Sticky Locks require POR to reset Configuration Interrupt Status Interrupt Mask Status Device Config DMA DMA Source Address DMA Destination Address DMA Source Length DMA Destination Length Multi-Boot Offset Boot Software ID Register Miscellaneous Control

Function

Hardware Register
CTRL LOCK CFG INT_STS INT_MASK STATUS DMA_SRC_ADDR DMA_DEST_ADDR DMA_SRC_LEN DMA_DEST_LEN MULTIBOOT_ADDR SW_ID MCTRL

Offset
0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x02C 0x030 0x080 R/W

Type
R/Sticky Write R/W R + Clr or Wr R/W R + Clr or Wr R/W R/W R/W R/W R/W R/W R/W

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Interrupts
7.1 Environment
This chapter describes the system-level interrupt environment and the functions of the interrupt controller (see Figure 7-1). The PS is based on ARM architecture, utilizing two Cortex-A9 processors (CPUs) and the GIC pl390 interrupt controller. The interrupt structure is closely associated with the CPUs and accepts interrupts from the I/O peripherals (IOP) and the programmable logic (PL). This chapter includes these key topics: Private, shared and software interrupts GIC functionality Interrupt prioritization and handling

X-Ref Target - Figure 7-1

Generic Interrupt Controller

Software Interrupts Software Generated Interrupts (SGI)
16 each

Enable, Classify, Distribute and Prioritize

CPU 0 CPU 1 IRQ/FIQ

CPU 0
Interrupt Interface

Private Interrupt Registers Execution Unit

CPU 0 Private CPU 1 Private

Private Peripheral Interrupts (PPI)

CPU 0
5

CPU 1
Private Peripheral Interrupts (PPI)
5

CPU 1 IRQ/FIQ Interrupt Interface

Private Interrupt Registers Execution Unit

Shared Peripherals
Shared Peripheral Interrupts (SPI)
60 44 16 60

CPU 0 CPU 1

CPU Private Bus Interrupt Control and Status Registers

UG585_c7_01_030912

PS I/O Peripherals (IOP)

Programmable Logic

WFI, WFE and Event Indicators

Figure 7-1:

System-Level Block Diagram

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7.1.1 Private, Shared and Software Interrupts

Each CPU has a set of private peripheral interrupts (PPIs) with private access using banked registers. The PPIs include the global timer, private watchdog timer, private timer, and FIQ/IRQ from the PL. Software generated interrupts (SGIs) are routed to one or both CPUs. The SGIs are generated by writing to the registers in the generic interrupt controller (GIC). (Refer to Appendix B, Register Details for more information.) The shared peripheral interrupts (SPIs) are generated by the various I/O and memory controllers in the PS and PL. They are routed to either or both CPUs. The SPI interrupts from the PS peripherals are also routed to the PL.

7.1.2 Generic Interrupt Controller (GIC)

The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to the CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface accepts the next interrupt. In addition, the controller supports security extension for implementing a security-aware system. The controller is based on the ARM Generic Interrupt Controller Architecture version 1.0 (GIC v1), non-vectored. The registers are accessed via the CPU private bus for fast read/write response by avoiding temporary blockage or other bottlenecks in the interconnect. The interrupt distributor centralizes all interrupt sources before dispatching the one with the highest priority to the individual CPUs. The GIC ensures that an interrupt targeted to several CPUs can only be taken by one CPU at a time. All interrupt sources are identified by a unique interrupt ID number. All interrupt sources have their own configurable priority and list of targeted CPUs.

7.1.3 Resets and Clocks

The interrupt controller is reset by the reset subsystem by writing to the PERI_RST bit of the A9_CPU_RST_CTRL register in the SLCR. The same reset signal also resets the CPU private timers and private watchdog timers (AWDT). Upon reset, all interrupts that are pending or being serviced are ignored. The interrupt controller operates with the CPU_3x2x clock (half the CPU frequency).

7.1.4 Block Diagram

The shared peripheral interrupts are generated from various subsystems that include the I/O peripherals in the PS and logic in the PL. The interrupt sources are illustrated in Figure 7-2.

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X-Ref Target - Figure 7-2

Private Peripheral Interrupts (PPI)

CPU 0 Timer and AWDT PL FIQ 0, IRQ 0

CPU 0 Distributor

nIRQ nFIQ nIRQ nFIQ nIRQ nFIQ

CPU 0

CPU 0 Interface

Shared Peripheral Interrupts (SPI)

Software Generated Interrupts (SGI) CPU 0 CPU 1

IOP

PL

Interrupt Controller Distributor (ICD)

nIRQ nFIQ

System Watchdog Timer

SGI Distributor

CPU 1 Distributor

Private Peripheral Interrupts (PPI)

CPU 1 Timer and AWDT PL FIQ 1, IRQ 1

nIRQ nFIQ nIRQ nFIQ

CPU 1 Interface

CPU 1
UG585_c7_02_012813

Figure 7-2:

Interrupt Controller Block Diagram

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7.2 Functional Description

7.2.1 Software Generated Interrupts (SGI)
Each CPU can interrupt itself, the other CPU, or both CPUs using a software generated interrupt (SGI). There are 16 software generated interrupts (see Table 7-1). An SGI is generated by writing the SGI interrupt number to the ICDSGIR register and specifying the target CPU(s). This write occurs via the CPU's own private bus. Each CPU has its own set of SGI registers to generate one or more of the 16 software generated interrupts. The interrupts are cleared by reading the ICCIAR (Interrupt Acknowledge) register or writing a 1 to the corresponding bits of the ICDICPR (Interrupt Clear-Pending) register. All SGIs are edge triggered. The sensitivity types for SGIs are fixed and cannot be changed; the ICDICFR0 register is read-only, since it specifies the sensitivity types of all the 16 SGIs. Table 7-1: IRQ ID#
0 1 ~ 15

Software Generated Interrupts (SGI) Name

Software 0 Software 1 ... Software 15

SGI#
0 1 ~ 15

Type
Rising edge Rising edge ... Rising edge

Description
A set of 16 interrupt sources that are private to each CPU that can be routed to up to 16 common interrupt destinations where each destination can be one or more CPUs.

7.2.2 CPU Private Peripheral Interrupts (PPI)

Each CPU connects to a private set of five peripheral interrupts. The PPIs are listed in Table 7-2. All interrupt sensitivity types are fixed by the requesting sources and cannot be changed. The GIC must be programmed to accommodate this. The boot ROM does not program these registers; therefore the SDK device drivers must program the GIC to accommodate these sensitivity types. Note that the fast interrupt (FIQ) signal and the interrupt (IRQ) signal from the PL are inverted and then sent to the interrupt controller. Therefore, they are active High at the PS-PL interface, although the ICDICFR1 register reflects them as active Low level. Table 7-2: IRQ ID#
26:16 27 28 29

Private Peripheral Interrupts (PPI) Name

Reserved Global Timer nFIQ CPU Private Timer

PPI#
~ 0 1 2 Rising edge

Type
~ Active Low level (active High at PS-PL interface) Rising edge Reserved Global timer

Description

Fast interrupt signal from the PL: CPU0: IRQF2P[18] CPU1: IRQF2P[19] Interrupt from private CPU timer

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Table 7-2: IRQ ID#

30 31

Private Peripheral Interrupts (PPI) (Contd) Name

AWDT{0, 1} nIRQ

PPI#
3 4 Rising edge

Type
Active Low level (active High at PS-PL interface)

Description
Private watchdog timer for each CPU Interrupt signal from the PL: CPU0: IRQF2P[16] CPU1: IRQF2P[17]

7.2.3 Shared Peripheral Interrupts (SPI)

A group of approximately 60 interrupts from various modules can be routed to one or both of the CPUs or the PL. The interrupt controller manages the prioritization and reception of these interrupts for the CPUs. All interrupt sensitivity types are fixed by the requesting sources and cannot be changed. The GIC must be programmed to accommodate this. The boot ROM does not program these registers; therefore the SDK device drivers must program the GIC to accommodate these sensitivity types. The SPI interrupts are listed in Table 7-3. Table 7-3: Source PS and PL Shared Peripheral Interrupts (SPI) Interrupt Name
CPU 1, 0 (L2, TLB, BTAC) APU Reserved PMU XADC DVI SWDT Timer Reserved DMAC Memory Debug L2 Cache OCM ~ PMU [1,0] XADC DVI SWDT TTC 0 ~ DMAC Abort DMAC [3:0] SMC Quad SPI CTI

IRQ ID#
33:32 34 35 36 38, 37 39 40 41 43:42 44 45 49:46 50 51 ~

Status Bits (mpcore Registers) Required Type PS-PL Signal Name

spi_status_0[1:0] spi_status_0[2] spi_status_0[3] spi_status_0[3] spi_status_0[6:5] spi_status_0[7] spi_status_0[8] spi_status_0[9] spi_status_0[11:10] spi_status_0[12] spi_status_0[13] spi_status_0[17:14] spi_status_0[18] spi_status_0[19] ~ Rising edge High level High level ~ High level High level High level Rising edge High level ~ High level High level High level High level High level ~ IRQP2F[28] IRQP2F[23:20] IRQP2F[19] IRQP2F[18] IRQP2F[17] ~ ~ ~ ~ ~ ~ ~ ~ ~

I/O
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Output Output Output Output Output

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Table 7-3: Source

PS and PL Shared Peripheral Interrupts (SPI) (Contd) Interrupt Name

GPIO USB 0 Ethernet 0 Ethernet 0 Wakeup

IRQ ID#
52 53 54 55 56 57 58 59 60 63:61 68:64 71:69 75:72 76 77 78 79 80 81 82 83 91:84 92 95:93

Status Bits Required Type PS-PL Signal Name (mpcore Registers)

spi_status_0[20] spi_status_0[21] spi_status_0[22] spi_status_0[23] spi_status_0[24] spi_status_0[25] spi_status_0[26] spi_status_0[27] spi_status_0[28] spi_status_0[31:29] spi_status_1[4:0] spi_status_1[7:5] spi_status_1[11:8] spi_status_1[12] spi_status_1[13] spi_status_1[14] spi_status_1[15] spi_status_1[16] spi_status_1[17] spi_status_1[18] spi_status_1[19] spi_status_1[27:20] spi_status_1[28] spi_status_1[31:29] High level High level Rising edge Rising edge High level High level High level High level High level High level High level High level High level High level Rising edge Rising edge High level High level High level High level High level High level Rising edge ~ IRQP2F[16] IRQP2F[15] IRQP2F[14] IRQP2F[13] IRQP2F[12] IRQP2F[11] IRQP2F[10] IRQP2F[9] IRQP2F[8] IRQF2P[2:0] IRQF2P[7:3] ~ IRQP2F[27:24] IRQP2F[7] IRQP2F[6] IRQP2F[5] IRQP2F[4] IRQP2F[3] IRQP2F[2] IRQP2F[1] IRQP2F[0] IRQF2P[15:8] ~ ~

I/O
Output Output Output Output Output Output Output Output Output Input Input ~ Output Output Output Output Output Output Output Output Output Input ~ ~

IOP

SDIO 0 I2C 0 SPI 0 UART 0 CAN 0 FPGA [2:0] FPGA [7:3] TTC 1 DMAC[7:4] USB 1 Ethernet 1 Ethernet 1 Wakeup SDIO 1 I2C 1 SPI 1 UART 1 CAN 1

PL Timer DMAC

IOP

PL SCU Reserved

FPGA [15:8] Parity ~

7.2.4 Wait for Interrupt Event Signal (WFI)

The CPU can go into a wait state where it waits for an interrupt (or event) signal to be generated. The wait for interrupt signal that is sent to the PL is described in Chapter 3, Application Processing Unit.

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7.3 Register Overview

The ICC and ICD registers are part of the pl390 GIC register set. There are 60 SPI interrupts. This is far fewer than what the pl390 can support, so there are far fewer interrupt enable, status, prioritization and processor target registers in the ICD than is possible for the pl390. A summary of the ICC and ICD registers are listed in Table 7-4 Table 7-4:
Name Interrupt Controller CPU (ICC)
ICCICR ICCPMR ICCBPR ICCIAR ICCEOIR ICCRPR ICCHPIR ICCABPR CPU interface control Interrupt priority mask Binary point for interrupt priority Interrupt acknowledge End of interrupt Running priority Highest pending interrupt Aliased non-secure binary point Yes, except EnableNS ~ ~ ~ ~ ~ ~ ~

Interrupt Controller Register Overview Register Description Write Protection Lockdown

Interrupt Controller Distributor (ICD)

ICDDCR ICDICTR, ICDIIDR ICDISR [2:0] ICDISER [2:0], ICDICER [2:0] ICDISPR [2:0], ICDICPR [2:0] ICDABR [2:0] ICDIPR [23:0] ICDIPTR [23:0] ICDICFR [5:0] Secure/non-secure mode select Controller implementation Interrupt security Interrupt set-enable and clear-enable Interrupt set-pending and clear-pending Interrupt active Interrupt priority, 8-bit fields Interrupt processor targets, 8-bit fields Interrupt sensitivity type, 2-bit field (level/edge, pos/neg) Yes ~ Yes Yes Yes ~ Yes Yes Yes

PPI and SPI Status

PPI_STATUS PPI status: Corresponds to ICDISR[0], ICDISER[0], ICDICER[0], ICDISPR[0], ICDICPR[0], and ICDABR[0] registers (security, enable, pending and active). SPI status: Corresponds to ICDISR[2:1], ICDISER[2:1], ICDICER[2:1], ICDISPR[2:1], ICDICPR[2:1], and ICDABR[2:1] registers (security, enable, pending and active). ~

SPI_STATUS [2:1]

Software Generated Interrupts (SGI)

ICDSGIR Software-generated interrupts ~

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Table 7-4:
Name

Interrupt Controller Register Overview (Contd) Register Description

CFGSDISABLE bit disables some write accesses

Write Protection Lockdown

~

Disable Write Accesses (SLCR register)

APU_CTRL

7.3.1 Write Protection Lock Down

The interrupt controller provides the facility to prevent write accesses to critical configuration registers. This is done by writing a one to the APU_CTRL[CFGSDISABLE] bit. The APU_CTRL register is part of the AP SoCs System Level Control register set, SLCR. This controls the write behavior for the secure interrupt control registers. If the user wants to set the CFGSDISABLE bit, it is recommended that this be done during the user software boot process which occurs after the software has configured the Interrupt Controller registers. The CFGSDISABLE bit can only be cleared by a power-on reset (POR.) After the CFGSDISABLE bit is set, it changes the protected register bits to read-only and therefore the behavior of these secure interrupts cannot be changed, even in the presence of rogue code executing in the secure domain.

7.4 Programming Model

7.4.1 Interrupt Prioritization
All of the interrupt requests (PPI, SGI and SPI) are assigned a unique ID number. The controller uses the ID number to arbitrate. The interrupt distributor holds the list of pending interrupts for each CPU, and then selects the highest priority interrupt before issuing it to the CPU interface. Interrupts of equal priority are resolved by selecting the lowest ID. The prioritization logic is physically duplicated to enable the simultaneous selection of the highest priority interrupt for each CPU. The interrupt distributor holds the central list of interrupts, processors and activation information, and is responsible for triggering software interrupts to the CPUs. SGI and PPI distributor registers are banked to provide a separate copy for each connected processor. Hardware ensures that an interrupt targeting several CPUs can only be taken by one CPU at a time. The interrupt distributor transmits to the CPU interfaces the highest pending interrupt. It receives back the information that the interrupt has been acknowledged, and can then change the status of the corresponding interrupt. Only the CPU that acknowledges the interrupt can end that interrupt.

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7.4.2 Interrupt Handling

The response of the GIC to a pending interrupt when an IRQ line de-asserts is described in the ARM document: IHI0048B_gic_architecture_specification.pdf (see Appendix A, Additional Resources). See the Note in Section 1.4.2 with additional information in Section 3.2.4. If the interrupt is pending in the GIC and IRQ is de-asserted, the interrupt in the GIC becomes inactive (and the CPU never sees it). If the interrupt is active in the GIC (because the CPU interface has acknowledged the interrupt), then the software ISR determines the cause by checking the GIC registers first and then polling the I/O Peripheral interrupt status registers.

7.4.3 ARM Programming Topics

The ARM GIC architecture specification includes these programming topics: GIC register access Distributor and CPU Interfaces Affects of the GIC security extensions PU Interface registers Preserving and restoring controller state

7.4.4 Legacy Interrupts and Security Extensions

When the legacy interrupts (IRQ, FIQ) are used, and an interrupt handler accesses both IRQs and FIQs in secure mode (via ICCICR[AckCtl]= 1), race conditions occasionally occur when reading the interrupt IDs. There is also a risk of seeing FIQ IDs in the IRQ handler, as the GIC only knows what security state the handler is reading from, not which type of handler. There are two workable solutions: Only signal IRQs to a re-entrant IRQ handler and use the preemption feature in the GIC. Use FIQ and IRQ with ICCICR[AckCtl]= 0 and use the TLB tables to handle IRQ in non-secure mode, and handle FIQ in secure mode.

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Timers
8.1 Introduction
Each Cortex-A9 processor has its own private 32-bit timer and 32-bit watchdog timer. Both processors share a global 64-bit timer. These timers are always clocked at 1/2 of the CPU frequency (CPU_3x2x). On the system-level, there is a 24-bit watchdog timer and two 16-bit triple timer/counters. The system watchdog timer is clocked at 1/4 or 1/6 of the CPU frequency (CPU_1x), or can be clocked by an external signal from an MIO pin or from the PL. The two triple timers/counters are always clocked at 1/4 or 1/6 of the CPU frequency (CPU_1x), and are used to count the widths of signal pulses from an MIO pin or from the PL.

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8.1.1 System Diagram

The relationships of the system timers are shown in Figure 8-1.
X-Ref Target - Figure 8-1

System Reset (POR)

The System Watchdog Timer can optionally reset the whole chip. The CPU Private WatchDogs can optionally reset the whole chip. CPU 0

Clock in Reset Out

MIO Pins

System Watchdog Timer

CPU WatchDog
CPU_3x2x

CPU Private Timer MIO / EMIO Interrupt Controller

Clock in Waveform Out TTC 0

CPU
CPU 1

Triple Timer Counter

Global Timer Counter

CPU_3x2x

EMIO
SWDT TTC 0, 1
TTC 1
UG585_c8_01_072512

Figure 8-1:

System View

8.1.2 Notices
7z010 CLG225 Device
The 7z010 CLG225 device supports 32 MIO pins (not 54). This is shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. The 7z010 CLG225 device restricts the available MIO pins so connections through the EMIO might need to be considered. All of the 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

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8.2 CPU Private Timers and Watchdog Timers

The CPU private timers and watchdog timers are fully documented in the Cortex-A9 MPCore Technical Requirements Document , sections 4.1 and 4.2 (see Appendix A, Additional Resources). Both the timer and watchdog blocks have the following features: 32-bit counter that generates an interrupt when it reaches zero 8-bit prescaler to enable better control of the interrupt period Configurable single-shot or auto-reload modes Configurable starting values for the counter

8.2.1 Clocking
All private timers and watchdog timers are always clocked at 1/2 of the CPU frequency (CPU_3x2x).

8.2.2 Interrupt to PS Interrupt Controller

The interrupts sent to the interrupt controller are described in section 7.2.2 CPU Private Peripheral Interrupts (PPI).

8.2.3 Resets
The time and watchdog resets are sent to the PS reset subsystem, see section 26.3 Reset Effects.

8.2.4 Register Overview

A register overview of the CPU private and watchdog timers is provided in Table 8-1. Table 8-1: CPU Private Timers Register Overview Function
CPU Private Timers
Reload and current values Control and Interrupt Timer Load Timer Counter Timer Control Timer Interrupt Values to be reloaded into the decrementer Current value of the decrementer. Enable, Auto reload, IRQ, prescaler, interrupt status.

Name

Overview

CPU Private Watchdogs (AWDT 0 and 1)

Reload and current values Control and Interrupt Watchdog Load Watchdog Counter Watchdog Control Watchdog Interrupt Values to be reloaded into the decrementer. Current value of the decrementer. Enable, Auto reload, IRQ, prescaler, interrupt status. (Note: This register cannot disable watchdog.)

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Table 8-1:

CPU Private Timers Register Overview (Contd) Function Name

Watchdog Reset Status

Overview
Reset status as a result of watchdog reaching 0. Cleared with POR only, so SW can tell if the reset was caused by watchdog. Disable watchdog via a sequence of writes of two specific words.

Reset status

Disable

Watchdog Disable

8.3 Global Timer (GT)

The Global Timer is fully documented in the Cortex-A9 MPCore Technical Requirements Document, sections 4.3 and 4.4 (see Appendix A, Additional Resources). The global timer is a 64-bit incrementing counter with an auto-incrementing feature. The global timer is memory-mapped in the same address space as the private timers. The global timer is accessed at reset in secure state only. The global timer is accessible to all Cortex-A9 processors. Each Cortex-A9 processor has a 64-bit comparator that is used to assert a private interrupt when the global timer has reached the comparator value.

8.3.1 Clocking
The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x).

8.3.2 Register Overview

A register overview of the GTC is provided in Table 8-2. Table 8-2: Global Timer Register Overview Function
Global Timer (GTC)
Current values Control and Interrupt Comparator Global Timer Counter Global Timer Control Global Interrupt Comparator Value Comparator Increment Global Timer Disable Current value of the incrementer Enable timer, enable comparator, IRQ, auto-increment, interrupt status Current value of the comparator Increment value for the comparator Disable watchdog via a sequence of writes of two specific words

Name

Overview

8.4 System Watchdog Timer (SWDT)

In addition to the two CPU private watchdog timers, there is a system watchdog timer (SWDT) for signaling additional catastrophic system failure, such as a PS PLL failure. Unlike the AWDT, the SWDT

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can run off the clock from an external device or the PL, and provides a reset output to an external device or the PL.

8.4.1 Features
Key features of the available timers/counters are as follows: An internal 24-bit counter Selectable clock input from:

Internal PS bus clock (CPU_1x) Internal clock (from PL) External clock (from MIO) System interrupt (PS) System reset (PS, PL, MIO) Time out range 32,760 to 68,719,476,736 clock cycles (330 s to 687.2s at 100 MHz) System interrupt pulse 4 to 32 clock cycles (40 ns to 320 ns at 100 MHz) System reset pulse 2 to 256 clock cycles (20 ns to 2.6 s at 100 MHz)

On time out, outputs one or a combination of:

Programmable time out period:

Programmable output signal duration on time out:

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8.4.2 Block Diagram

A block diagram of the SWDT is shown in Figure 8-2.
X-Ref Target - Figure 8-2

SLCR
WDT_CLK_SEL[0]

INTERCONNECT
APB Interrupt Controller ID41 SWDT Reset (to PS reset system) MIO Pin, EMIOWDTRSTO

Control Logic

Zero CLKSEL CRV Restart CPU_1x MIO Pins, EMIOWDTCLKI Halt (during CPU debug)

Prescaler

24-bit Counter

UG585_c8_02_012813

Figure 8-2: Notes relevant to Figure 8-2:

System Watchdog Timer Block Diagram

SLCR programmable registers (WDT_CLK_SEL, MIO control) select the clock input. SWDT programmable registers set the values for CLKSEL and CRV. Signal restart causes the 24-bit counter to reload the CRV values, and restart counting. Signal halt causes the counter to halt during CPU debug (same behavior as AWDT).

8.4.3 Functional Description

The control logic block has an APB interface connected to the system interconnect. Each write data received from APB has a key field which must match the key of the register to be written in order to be able to write to the register. The Zero Mode register controls the behavior of the SWDT when its internal 24-bit counter reaches zero. Upon receiving a zero signal, the control logic block asserts the interrupt output signal for IRQLN clock cycles if both WDEN and IRQEN are set, and also asserts the reset output signals for RSTLN clock cycles if both WDEN and RSTLN are set. The 24-bit counter then stays at zero until it is restarted. The Counter Control register sets the time out period, via setting reload values in swdt.CONTROL[CLKSET] and swdt.CONTROL[CRV] to control the prescaler and the 24-bit counter. The Restart register is used to restart the counting process. Writing to this register with a matched key causes the prescaler and the 24-bit counter to reload the values from CRV signals.

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The Status register shows whether the 24-bit counter reaches zero. Regardless of the WDEN bit in the Zero Mode register, the 24-bit counter always keeps counting down to zero if it is not zero and the selected clock source is present. Once it reaches zero, the WDZ bit of the Status register is set and remains set until the 24-bit counter is restarted. The prescaler block divides down the selected clock input. The CLKSEL signal is sampled at every rising clock edge. The internal 24-bit counter counts down to zero and stays at zero until it is restarted. While the counter is at zero, the zero output signal is High.

Interrupt to PS Interrupt Controller

The pulse length from the SWDT (four CPU_1x clock cycles) is sufficient for the interrupt controller to capture the interrupt using rising-edge sensitivity.

Reset
The watchdog reset is sent to the PS reset subsystem, see section 26.3 Reset Effects.

8.4.4 Register Overview

A register overview of the SWDT is provided in in Table 8-3. Table 8-3: System Watchdog Timer Register Overview Name
swdt.MODE swdt.CONTROL swdt.RESTART swdt.STATUS

Function
Zero mode Reload values Restart Status

Overview
Enable SWDT, enable interrupt and reset outputs on time out, set output pulse lengths. Set the reload values for prescaler and 24-bit counter on time out. Cause the prescaler and the 24-bit counter to reload and restart. Indicates watchdog reaching zero.

8.4.5 Programming Model

System Watchdog Timer Enable Sequence
1. Select clock input source using the slcr.WDT_CLK_SEL[SEL] bit: Ensure that the SWDT is disabled (swdt.MODE[WDEN] = 0 ) and the clock input source to be selected is running before proceeding with this step. Changing the clock input source when the SWDT is enabled results in unpredictable behavior. Changing the clock input source to a non-running clock results in APB access hang. 2. Set the time out period (Counter Control register): The swdt.CONTROL[CKEY] field must be 0x248 in order to be able to write this register.

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3.

Enable the counter; enable output pulses; set up output pulse lengths (Zero Mode register): The swdt.MODE[ZKEY] field must be 0xABC in order to be able to write this register. Ensure that IRQLN and RSTLN meet the specified minimum values.

4.

To run the SWDT with a different setting, disable the timer first (swdt.MODE[ZKEY] bit). Then repeat the above steps.

8.5 Triple Timer Counters (TTC)

The TTC contains three independent timers/counters. Because a single APB interface is used to access them, the three timers/counters must have the same security status. There are two TTC modules in the PS, for a total of six timers/counters.

8.5.1 Features
Each of the triple timer counters has: Three independent 16-bit prescalers and 16-bit up/down counters Selectable clock input from:

Internal PS bus clock (CPU_1x) Internal clock (from PL) External clock (from MIO)

Three interrupts, one for each counter Interrupt on overflow, at regular interval, or counter matching programmable values Generates waveform output (e.g., PWM) through the MIO and to the PL

8.5.2 Block Diagram

A block diagram of the TTC is shown in Figure 8-3. The clock-in and wave-out multiplexing for Timer/Clock 0 is controlled by the slcr.PIN_MUX registers. If no selection is made in these registers, then the default becomes the EMIO interface.

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X-Ref Target - Figure 8-3

slcr.PIN_MUX_xx

Timer/Clock 0

CPU_1x MIO EMIO

Clock-In

Pre-scaler

16-bit Counter Interrupt

Wave-Out

MIO EMIO

Event Timer

Interrupt (GIC) TTC_0: IRQ ID # 42 TTC_1: IRQ ID # 69 Wave-Out (EMIO)

Interrupt

Timer/Clock 1
slcr.PIN_MUX_xx Pre-scaler 16-bit Counter

Clock-In (EMIO)

Event Timer

Interrupt (GIC) TTC_0: IRQ ID # 43 TTC_1: IRQ ID # 70 Wave-Out (EMIO)

Timer/Clock 2
Pre-scaler 16-bit Counter Interrupt

Clock-In (EMIO)

EMIO Interface Event Timer

Interrupt (GIC) TTC_0: IRQ ID # 44 TTC_1: IRQ ID # 71

APB

Status and Control Registers

TTC 0 TTC 1
UG585_c8_08_032212

Figure 8-3:

Triple Counter Timer Block Diagram

8.5.3 Functional Description

Each prescaler module can be independently programmed to use the PS internal bus clock (CPU_1x), or an external clock from the MIO or the PL. For an external clock, SLCR registers determine the exact pinout via the MIO or from the PL. The selected clock is then divided down from /2 to /65536, before being applied to the counter. The counter module can count up or count down, and can be configured to count for a given interval. It also compares three match registers to the counter value, and generate an interrupt if one matches. The interrupt module combines interrupts of various types: counter interval, counter matches, counter overflow, event timer overflow. Each type can be individually enabled.

Modes of Operation
Each counter module can be independently programmed to operate in either of the following two modes: Interval mode: The counter increments or decrements continuously between 0 and the value of the Interval register, with the direction of counting determined by the DEC bit of the Counter Control register. An Interval interrupt is generated when the counter passes through zero. The corresponding Match interrupt is generated when the counter value equals one of the Match registers.

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Overflow mode: The counter increments or decrements continuously between 0 and 0xFFFF, with the direction of counting determined by the DEC bit of the Counter Control register. An Overflow interrupt is generated when the counter passes through zero. The corresponding Match interrupt is generated when the counter value equals one of the Match registers.

Event Timer Operation

The event timer operates by having an internal (invisible to users) 16-bit counter clocked at CPU_1x which: Resets to 0 during the non-counting phase of the external pulse Increments during the counting phase of the external pulse

The Event Control Timer register controls the behavior of the internal counter: E_En bit: When 0 , immediately resets the internal counter to 0, and stops incrementing E_Lo bit: Specifies the counting phase of the external pulse E_Ov bit: Specifies how to handle overflow at the internal counter (during the counting phase of the external pulse)

When 0 : Overflow causes E_En to be 0 (see E_En bit description) When 1 : Overflow causes the internal counter to wrap around and continues incrementing An interrupt is always generated (subject to further enabling through another register) when an overflow occurs

The Event register is updated with the non-zero value of the internal counter at the end of the counting-phase of the external pulse; therefore, it shows the widths of the external pulse, measured in number of cycles of CPU_1x. If the internal counter is reset to 0, due to overflow, during the counting phase of the external pulse, the Event register will not be updated and maintains the old value from the last non-overflowing counting operation.

8.5.4 Register Overview

A register overview of the TTC is provided in in Table 8-4. Table 8-4: Triple Timer Counter Register Overview Name
Clock Control Register Counter Control Register Counter Value Register

Function
Clock Control

Overview
Controls prescaler, selects clock input, edge Enables counter, sets mode of operation, sets up/down counting, enables matching, enables waveform output Returns current counter value

Status

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Table 8-4:

Triple Timer Counter Register Overview (Contd) Name

Interval Register Sets interval value Sets match values, total 3 Shows current interrupt status Enable interrupts Enable event timer, stop timer, sets phrase Shows width of external pulse Match Register 1 Match Register 2 Match Register 3 Interrupt Register Interrupt Enable Register Event Control Timer Register Event Register

Function
Counter Control

Overview

Interrupt

Event

8.5.5 Programming Model

Counter Enable Sequence
1. Select clock input source, set prescaler value (slcr.MIO_MUX_SEL registers, TTC Clock Control register): Ensure TTC is disabled (ttc.Counter_Control_x [DIS] = 1 ) before proceeding with this step. Set interval value (Interval register): This step is optional, for interval mode only. Set match value (Match registers): This step is optional, if matching is to be enabled. Enable interrupt (Interrupt Enable register): This step is optional, if interrupt is to be enabled. Enable/disable waveform output, enable/disable matching, set counting direction, set mode, enable counter (TTC Counter Control register): This step starts the counter.

2. 3. 4. 5.

Counter Stop Sequence

1. 2. 3. Read back the value of Counter Control register. Set DIS bit to 1 , while keeping other bits. Write back to Counter Control register.

Counter Restart Sequence

1. 2. 3. Read back the value of Counter Control register. Set RST bit to 1 , while keeping other bits. Write back to Counter Control register.

Event Timer Enable Sequence

1. Select external pulse source (slcr.MIO_MUX_SEL registers): The width of the selected external pulse is measured in CPU_1x period.

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2.

Set overflow handling, select external pulse level, enable the event timer (Event Control Timer register): This step starts measuring the width of the selected level (High or Low) of the external pulse. Enable interrupt (Interrupt Enable register): This step is optional, if interrupt is to be enabled. Read the measured width (Event register): Note that the returned value is not correct when overflow happened. See the description for the E_Ov bit of the Event Control Timer register in section 8.5.3 Functional Description.

3. 4.

Interrupt Clear and Acknowledge Sequence

1. Read Interrupt register: All bits in the Interrupt register are cleared on read.

8.5.6 I/O Signals

Timer I/O signals are identified in Table 8-5. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. There are two triple timer counters (TTC0 and TTC1) in the system. Each TTC has three sets of interface signals: clock in and wave out for counter/timers 0, 1, and 2. For each triple timer counter, the signals for counter/timer 0 can be routed to the MIO using the MIO_PIN registers. If the clock in or wave out signal is not selected by the MIO_PIN register, then the signal is routed to EMIO by default. The signals for counter/timers 1 and 2 are only available through the EMIO. Table 8-5: TTC TTC I/O Signals Timer Signal
Counter/Timer 0 Clock In Counter/Timer 0 Wave Out TTC0 Counter/Timer 1 Clock In Counter/Timer 1 Wave Out Counter/Timer 2 Clock In Counter/Timer 2 Wave Out Counter/Timer 0 Clock In Counter/Timer 0 Wave Out TTC1 Counter/Timer 1 Clock In Counter/Timer 1 Wave Out Counter/Timer 2 Clock In Counter/Timer 2 Wave Out

I/O
I O I O I O I O I O I O

MIO Pins
19, 31, 43 18, 30, 42 N/A N/A N/A N/A 17, 29, 41 16, 28, 40 N/A N/A N/A N/A

EMIO Signals
EMIOTTC0CLKI0 EMIOTTC0WAVEO0 EMIOTTC0CLKI1 EMIOTTC0WAVEO1 EMIOTTC0CLKI2 EMIOTTC0WAVEO2 EMIOTTC1CLKI0 EMIOTTC1WAVEO0 EMIOTTC1CLKI1 EMIOTTC1WAVEO1 EMIOTTC1CLKI2 EMIOTTC1WAVEO2

Controller Default Input Value

0 ~ 0 ~ 0 ~ 0 ~ 0 ~ 0 ~

System watchdog timer I/O signals are identified in Table 8-6.

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Table 8-6:

Watchdog Timer I/O Signals I/O

I O

SWDT Signal
Clock In Reset Out

MIO Pins
14, 26, 38, 50, 52 15, 27, 39, 51, 53

EMIO Signals
EMIOWDTCLKI EMIOWDTRSTO

Controller Default Input Value

0 ~

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DMA Controller
9.1 Introduction
The DMA controller (DMAC) uses a 64-bit AXI master interface operating at the CPU_2x clock rate to perform DMA data transfers to/from system memories and PL peripherals. The transfers are controlled by the DMA instruction execution engine. The DMA engine runs on a small instruction set that provides a flexible method of specifying DMA transfers. This method provides greater flexibility than the capabilities of DMA controller methods. The program code for the DMA engine is written by software in to a region of system memory that is accessed by the controller using its AXI master interface. The DMA engine instruction set includes instructions for DMA transfers and management instructions to control the system. The controller can be configured with up to eight DMA channels. Each channel corresponds to a thread running on the DMA engines processor. When a DMA thread executes a load or store instruction, the DMA Engine pushes the memory request to the relevant read or write queue. The DMA controller uses these queues to buffer AXI read/write transactions. The controller contains a multi-channel FIFO (MFIFO) to store data during the DMA transfers. The program code running on the DMA engine processor views the MFIFO as containing a set of variable-depth parallel FIFOs for DMA read and write transactions. The program code must manage the MFIFO so that the total depth of all of the DMA FIFOs does not exceed the 1,024-byte MFIFO. The DMAC is able to move large amounts of data without processor intervention. The source and destination memory can be anywhere in the system (PS or PL). The memory map for the DMAC includes DDR, OCM, linear addressed Quad-SPI read memory, SMC memory and PL peripherals or memory attached to an M_GP_AXI interface. The flow control method for transfers with PS memories use the AXI interconnect. Accesses with PL peripherals can use the AXI flow control or the DMACs PL Peripheral Request Interface. There are no peripheral request interfaces directed to the PS I/O Peripherals (IOPs). For the PL peripheral AXI transactions, software running on a CPU is used in a programmed IO method using interrupts or status polling. The controller has two sets of control and status registers. One set is accessible in secure mode and the other in non-secure mode. Software accesses these registers via the controllers 32-bit APB slave interface. The entire controller is either operated in secure or non-secure mode; there is no mixing of modes on a channel basis. Security configuration changes are controlled by slcr registers and require a controller reset to take effect.

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9.1.1 Features
The DMA Controller provides: DMA Engine processor with a flexible instruction set for DMA transfers:

Flexible scatter-gather memory transfers Full control over addressing for source and destination Define AXI transaction attributes Manage byte streams

Eight cache lines and each cache line is four words wide Eight concurrent DMA channels threads

Allows multiple threads to execute in parallel Issue commands for up to eight read and up to eight write AXI transactions

Eight interrupts to the PS interrupt controller and the PL Eight events within DMA Engine program code 128 (64-bit) word MFIFO to buffer the data that the controller writes or reads during a transfer Security

Dedicated APB slave interface for secure register accessing Entire controller is configured as either secure or non-secure

Memory-to-memory DMA transfers Four PL peripheral request interfaces to manage flow control to and from the PL logic

Each interface accepts up to four active requests

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9.1.2 System Viewpoint

The system viewpoint of the DMA controller is shown in Figure 9-1.
X-Ref Target - Figure 9-1

IRQ ID# {45, 46~49, 72~75}

To Interrupt Controller

DMA Controller
Execution Engine
QoS

IRQ ID# {25, 20~27}

To PL

Channels 0~7

Central Interconnect
Data and Controller Instructions AXI 64-bit Master

R/W 8

CPU_2X clock DMAC_CPU2X_RST signal

TZ_DMA_NS [0] TZ_DMA_IRQ_NS [15:0] TZ_DMA_PERIPH_NS [3:0]

Peripheral Request Interfaces 0 ~ 3 DMA{0:3}_DAVALID DMA{0:3}_DATYPE{0,1} DMA{0:3}_DAREADY DMA{0:3}_DRVALID DMA{0:3}_DRTYPE{0,1} DMA{0:3}_DRLAST DMA{0:3}_DRREADY

PL

Security Control

FPGA_DMA{0:3}_RST signal Slave Interconnect

Register Access APB 32-bit Secure and Non-Secure Slave Ports

CPU_1X clock

Control and Status Registers

UG585_c9_01_021113

Figure 9-1:

DMA Controller System Viewpoint

System Functions
The following system functions are described in section 9.6 System Functions: Clocks Resets and Reset Configuration

DMA Controller Functions and Programming

A block diagram for the DMA controller is shown in Figure 9-2. A brief description of each block follows the diagram. Each functional unit is described in detail in these three main sections: Overall description in section 9.2 Functional Description. SDK Software programming methods are in section 9.3 Programming Guide for DMA Controller. DMA Engine programming methods are in section 9.4 Programming Guide for DMA Engine. Programming restrictions for these methods are in section 9.5 Programming Restrictions:

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9.1.3 Block Diagram

The block diagram of the DMA controller is shown in Figure 9-2.
X-Ref Target - Figure 9-2

DMA Controller
DMA Instruction Execution Engine Instruction Cache Register Access For the Non-secure State Non-secure APB Slave Interface 0xF800_4000 Secure APB Slave Interface 0xF800_3000 Read Instruction Instruction Queue Write Instruction Instruction Queue MFIFO Data Buffer
Data

AXI Master Interface

Central Interconnect

Control and Status Registers

Register Access For the Secure State

Channel Data

Tie-offs

Reset Initialization Interface Peripheral Request Interface

2 3

IRQs

Interrupt Interface

PL Fabric

UG_585_c9_02_030712

Figure 9-2:

DMA Controller Block Diagram

Note: Refer to ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: AXI
characteristics for a DMA transfer and AXI master for more information.

DMA Instruction Execution Engine

The DMAC contains an instruction processing block that enables it to process program code that controls a DMA transfer. The DMAC maintains a separate state machine for each thread. Channel arbitration

Round-robin scheme to service the active DMA channels Services the DMA manager prior of servicing the next DMA channel Changes to the arbitration process are not supported Responds to all active DMA channels with equal priority Changes to the priority of a DMA channel over any other DMA channels are not supported

Channel prioritization

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Instruction Cache
The controller stores instructions temporarily in a cache. When a thread requests an instruction from an address, the cache performs a look-up. If a cache hit occurs then the cache immediately provides the data, otherwise the thread is stalled while the controller uses the AXI interface to perform a cache line fill from system memory. If an instruction is greater than four bytes, or spans the end of a cache line, then it performs multiple cache accesses to fetch the instruction.

Note: When a cache line fill is in progress, the controller enables other threads to access the cache,
but if another cache miss occurs the pipeline is stalled until the first line fill is complete.

Note: Instruction cache latency for fill operations is dependent on the read latency of the system
memory where the DMA engine instructions are written. The performance of the DMAC is highly dependent on the bandwidth of the 64-bit AXI master interface (CPU_2x clock).

Read/Write Instruction Queues

When a channel thread executes a load or store instruction the controller adds the instruction to the relevant read queue or write queue. The controller uses these queues as an instruction storage buffer prior to issuing transactions on the AXI interconnect.

Multi-channel Data FIFO

The DMAC uses a multi-channel first-in-first-out (MFIFO) data buffer to store data that it reads, or writes, during a DMA transfer. Refer to 9.2.4 Multi-channel Data FIFO (MFIFO) for more information.

AXI Master Interface for Instruction Fetch and DMA Transfers

The program code is stored in a region of system memory that the controller accesses using the 64-bit AXI master interface. The AXI master interface also enables the DMA to transfer data from a source AXI slave to a destination AXI slave.

APB Slave Interface for Register Accesses

The controller responds to two address ranges used by software to read and write the control and status registers via the 32-bit APB slave interface. Non-secure register accesses Secure register accesses

Interrupt Interface
The interrupt interface enables efficient communications of events to the interrupt controller.

PL Peripheral DMA Request Interface

The PL peripheral request interface supports the connection of DMA-capable peripherals resident in the PL. Each PL peripheral request interface is asynchronous to one another and asynchronous to the DMA itself. The request/acknowledge signals to and from the PL are described in section 9.2.6 PL

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Peripheral AXI Transactions.

Reset Initialization Interface

This interface enables the software to initialize the operating state of the DMAC as it exits from reset. Refer to section 9.6.3 Reset Configuration of Controller for more information.

9.1.4 Notices
ARM IP Core
The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) PrimeCell peripheral that is developed, tested, and licensed by ARM. A list of the ARM Reference Documents for the DMA controller are summarized in Appendix A, Additional Resources. Technical Reference Manual: ARM PrimeCell DMA Controller (PL330) Technical Reference Manual. Example Application Notes: ARM Application Note 239: Example programs for the CoreLink DMA Controller DMA-330 and refer to 9.4 Programming Guide for DMA Engine.

Secure/Non-Secure Modes
The DMAC includes features to enable it to co-exist with ARMs TrustZone hardware to accelerate the performance of secure systems. The hardware is not required to ensure a secure environment. This chapter includes many references to secure and non-secure modes. It may not be complete. Please contact your Xilinx Sales Representative for more complete details.

Other DMA Controllers

There are other DMA controllers in the system that are local to the IOPs in the PS. These include: GigE controller, refer to Chapter 16, Gigabit Ethernet Controller. SDIO controller, refer to Chapter 13, SD/SDIO Controller. USB controller, refer toChapter 15, USB Host, Device, and OTG Controllers. DevC Interface, refer to section 6.4 Device Configuration Interface .

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9.2 Functional Description

Common to all DMAC operating conditions
9.2.1 DMA Transfers on the AXI Interconnect 9.2.2 AXI Transaction Considerations 9.2.3 DMA Manager 9.2.4 Multi-channel Data FIFO (MFIFO)

Memory-to-memory transfers are managed by the DMAC

9.2.5 Memory-to-Memory Transfers

When the PL Peripheral Request Interface is used

9.2.6 PL Peripheral AXI Transactions Length management option: 9.2.8 PL Peripheral - Length Managed by PL Peripheral Length management option: 9.2.9 PL Peripheral - Length Managed by DMAC

Advanced DMAC operating features

9.2.10 Events and Interrupts 9.2.11 Aborts 9.2.12 Security

IP core Configuration
Based on the ARM PrimeCell DMA Controller (PL330) refer to 9.2.13 IP Configuration Options

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9.2.1 DMA Transfers on the AXI Interconnect

All of the DMA transactions use AXI interfaces to move data between the on-chip memory, DDR memory and slave peripherals in the PL. The slave peripherals in the PL normally connect to the DMAC peripheral request interface to control data flow. The DMAC can conceivable access IOPs in the PS, but this is normally not useful because these paths offer no flow control signals. The data paths that are normally used by the DMAC are shown in figure 9-3. The peripheral request interface (used for flow control) is not shown in the figure. Each AXI path can be a read or write. There are many combinations. Two typical DMA transaction examples include: Memory to memory (On-chip memory to DDR memory) Memory to/from PL peripheral (DDR memory to PL peripheral)

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X-Ref Target - Figure 9-3

DMA Controller PL Memory (Read and Write)

64-bit IOP Masters M AXI_GP, DevC and DAP

DDR Memory (Read and Write)

On-Chip RAM (Read and Write)

S0

S2

S1

Central Interconnect
M0 M1 64-bit M2

AXI_HP Memory Interconnect L2 Cache S0

OCM Interconnect
64-bit M

S1

S0

S1

32-bit M0 M1

Slave Interconnect
M2 M3

SCU

S0

64-bit -bit

S1 AXI_GP0 AXI_GP1 AHB slaves APB slaves

256 KB

On-chip RAM

PL

AXI_HP Memory Interconnect

L2 Cache

64-bit
S0 S1

S3

S2

DDR Memory Controller

UG585_c9_07_021113

Figure 9-3:

DMAC Reads/Writes DDR, On-chip RAM, and PL Peripheral

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9.2.2 AXI Transaction Considerations

AXI data transfer size

Performs data accesses up to the 64-bit width of the AXI data bus Signals a precise abort if the user programs the src_burst_size or dst_burst_size fields to be larger than 64 bits Maximum burst length is 16 data beats The AXI specification does not permit AXI bursts to cross 4 KB address boundaries If the controller is programmed with a combination of burst start address, size, and length that would cause a single burst to cross a 4 KB address boundary, then the controller instead generates a pair of bursts with a combined length equal to that specified. This operation is transparent to the DMAC channel thread program so that, for example, the DMAC responds to a single DMALD instruction by generating the appropriate pair of AXI read bursts. Can be programmed to generate only fixed-address or incrementing-address burst types for data accesses. Wrapping-address bursts are not generated for data accesses or for instruction fetches. Can issue multiple outstanding write addresses up to eight (write issuing capability) The DMAC does not issue a write address until it has read in all of the data bytes required to fulfill that write transaction. Does not generate interleaved write data. All write data beats for one write transaction are output before any write data beat for the next write transaction. Does not support locked or exclusive accesses

AXI bursts crossing 4 KB boundaries

AXI burst types

AXI write addresses

AXI write data interleaving

AXI characteristics

9.2.3 DMA Manager

This section describes how to issue instructions to the DMA manager using one of the two APB interfaces available. When the DMAC is operating in real time, the user can only issue the following limited subset of instructions: DMAGO DMASEV DMAKILL Starts a DMA transfer using a DMA channel that the user specifies. Signals the occurrence of an event, or interrupt, using an event number that the user specifies. Terminates a thread.

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The appropriate APB interface must be used depending on the security state in which the SLCR register TZ_DMA_NS initializes the DMA manager to operate. For example, if the DMA manager is in the secure state, the instruction using the secure APB interface must be used or the DMAC ignores the instruction. The non-secure APB interface is the suggested port to use to start or restart a DMA channel when the DMA manager is in the non-secure state, however, the secure APB interface can be used in non-secure mode. (Refer to section 9.2.12 Security for more details.) Before issuing instructions using the Debug Instruction registers or the DBGCMD register, the DBGSTATUS register must be read to ensure that debug is idle, otherwise, the DMA manager ignores the instructions. Refer to the Debug Command register and Debug Status register in Appendix B, Register Details. When the DMA manager receives an instruction from an APB slave interface, it can take several clock cycles before it can process the instruction for example, if the pipeline is busy processing another instruction. Prior to issuing DMAGO, the system memory must contain a suitable program for the DMA channel thread to execute, starting at the address that the DMAGO specifies.

Example: Start DMA Channel Thread

The following example shows the steps required to start a DMA channel thread using the debug instruction registers. 1. 2. Create a program for the DMA channel. Store the program in a region of system memory.

Use one of the APB interfaces on the DMAC to program a DMAGO instruction as follows: 3. 4. Poll the dmac.DBGSTATUS register to ensure that debug is idle, that is, the dbgstatus bit is 0 . Refer to the Debug Status register in Appendix B, Register Details. Write to the dmac.DBGINST0 register and enter the: a. c. 5. Instruction byte 0 encoding for DMAGO. Debug thread bit to 0 . This selects the DMA manager. Refer to the Debug Instruction-0 register in Appendix B, Register Details. b. Instruction byte 1 encoding for DMAGO.

Write to the dmac.DBGINST1 register with the DMAGO instruction byte [5:2] data, refer to the Debug Instruction-1 register in Appendix B, Register Details. These four bytes must be set to the address of the first instruction in the program that was written to system memory in Step 2.

Instruct the DMAC to execute the instruction that the debug instruction registers contain: 6. Write a 0 to the dmac.DBGCMD register. The DMAC starts the DMA channel thread and sets the dbgstatus bit to 1 . Refer to the Debug Command register in Appendix B, Register Details. After the DMAC completes execution of the instruction, it clears the dbgstatus bit to 0 .

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9.2.4 Multi-channel Data FIFO (MFIFO)

The MFIFO is a shared resource utilized on a first-come, first-served basis by all currently active channels. To a program, it appears as a set of variable-depth parallel FIFOs, one per channel, with the restriction that the total depth of all the FIFOs cannot exceed the size of the MFIFO. The DMAC maximum MFIFO depth is 128 (64-bit) words. The controller is capable of realigning data from the source to the destination. For example, the DMAC shifts the data by two byte lanes when it reads a word from address 0x103 and writes to address 0x205 . The storage and packing of the data in the MFIFO is determined by the destination address and transfer characteristics. When a program specifies that incrementing memory transfers are to be performed to the destination, the DMAC packs data into the MFIFO to minimize the usage of the MFIFO entries. For example, the DMAC packs two 32-bit words into a single entry in the MFIFO when the DMAC has a 64-bit AXI data bus and the program uses a source address of 0x100 , and destination address of 0x200 . In certain situations, the number of entries required to store the data loaded from a source is not a simple calculation of the amount of source data divided by MFIFO width. The calculation of the number of entries required is not simple when any of the following occur: Source address is not aligned to the AXI bus width Destination address is not aligned to the AXI bus width Memory transfers are to a fixed destination, that is, a non-incrementing address

The DMALD and DMAST instructions each specify that an AXI bus transaction is to be performed. The amount of data transferred by an AXI bus transaction depends on the values programmed in to the CCRn register and the address of the transaction. Refer to the AMBA AXI Protocol Specification for information about unaligned transfers. Refer to section 9.3 Programming Guide for DMA Controller for considerations about MFIFO utilization.

9.2.5 Memory-to-Memory Transfers

The controller includes an AXI master interface to access memories in the PS system, such as: OCM DDR

Through the same AXI central interconnect, the controller can potentially access the majority of the peripheral subsystems. If a target peripheral can be seen as a memory-mapped region (or memory port location) without a FIFO or need for flow control, then the DMAC can be used to read and write to it. Typical examples include: QSPI in Linear addressing mode NOR flash NAND flash

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The memory map for the DMA controller is shown in Chapter 4, System Addresses. For more information on the AXI Interfaces, refer to . Examples of memory-to-memory transfer are provided in section 9.4.2 Memory-to-Memory Transfers.

9.2.6 PL Peripheral AXI Transactions

The majority of PL peripherals allow transferring data through FIFOs. These FIFOs must be managed to avoid overflow and underflow situations. For this reason, four specific peripheral request interfaces are available to connect the DMAC to DMA-capable peripherals in the PL. Each one of these interfaces can be assigned to any DMA channel. The DMAC is configured to accept up to four active requests for each PL peripheral interface. An active request is where the DMAC has not started the requested AXI data transaction. The DMAC has a request FIFO for each PL peripheral interface, which it uses to capture the requests from a PL peripheral. When a request FIFO is full, the DMAC sets the corresponding DMA{3:0}_DRREADY Low to signal that the DMAC cannot accept any requests sent from the PL peripheral.

Note: There are no peripheral request interfaces directed to the I/O peripherals (IOP) in the PS.
Processor intervention is needed to avoid underflow or overflow of the FIFOs in the targeted PS peripheral. This section discusses the AXI transactions to/from PL peripherals.

There are two different way to handle the quantity of data flowing between the DMAC and the PL peripheral: PL Peripheral length management: DMAC length management: The PL peripheral controls the quantity of data that is contained in a DMA cycle. The DMAC is controlling the quantity of data in a DMA cycle.

Programming Examples
Refer to section 9.4.3 PL Peripheral DMA Transfer Length Management.

9.2.7 PL Peripheral Request Interface

Figure 9-4 shows that the PL peripheral request interface consists of a PL peripheral request bus and a DMAC acknowledge bus that use the prefixes: DR DA PL Peripheral request bus DMAC acknowledge bus

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X-Ref Target - Figure 9-4

DMA{3:0}_DRVALID

DMA{3:0}_DRTYPE[1:0]
DMA{3:0}_DRLAST DMA{3:0}_DRREADY

Peripheral {3:0}

DMA{3:0}_DAVALID DMA{3:0}_DATYPE[1:0] DMA{3:0}_DAREADY

Peripheral Request Interface {3:0}

DMAC

DMA{3:0}_ACLK
UG585_c9_05_030312

Figure 9-4:

DMAC PL Peripheral Request Interface Request/Acknowledge Signals

Both buses use the valid-ready handshake that the AXI protocol describes. For more information on the handshake process, refer to the AMBA AXI Protocol v1.0 Specification . The PL peripheral uses the DMA{3:0}_DRTYPE[1:0] registers to: Request a single AXI transaction Request a AXI burst transaction Acknowledge a flush request

The DMAC uses the DMA{3:0}_DATYPE[1:0] registers to: Signal when it completes the requested single AXI transaction Signal when it completes the requested AXI burst transaction Issue a flush request

The PL peripheral uses DMA{3:0}_DRLAST to: Signal to the DMAC when the last data cycle of the AXI transaction commences

Handshake Rules
The DMAC uses the DMA handshake rules that Table 9-1 shows, when a DMA channel thread is active, that is, not in the stopped state. Refer to the Figure 9-5, page 220 for more information. Table 9-1: Rule
1

DMAC PL Peripheral Request Interface Handshake Rules Description(1)

DMA{3:0}_DRVALID can change from Low to High on any DMA{3:0}_ACLK cycle, but must only change from High to Low when DMA{3:0}_DRREADY is High. DMA{3:0}_DRTYPE can only change when either: DMA{3:0}_DRREADY is High DMA{3:0}_DRVALID is Low

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Table 9-1: Rule

3

DMAC PL Peripheral Request Interface Handshake Rules (Contd) Description(1)

DMA{3:0}_DRLAST can only change when either: DMA{3:0}_DRREADY is High DMA{3:0}_DRVALID is Low DMA{3:0}_DAVALID can change from Low to High on any DMA{3:0}_ACLK cycle, but must only change from High to Low when DMA{3:0}_DAREADY is High DMA{3:0}_DATYPE can only change when either: DMA{3:0}_DAREADY is High DMA{3:0}_DAVALID is Low

5 Notes:

1. All signals are synchronous to the DMA{3:0}_ACLK clock.

Map PL Peripheral Interface to a DMA Channel

The DMAC enables software to assign a PL peripheral request interface to any of the DMA channels. When a DMA channel thread executes DMAWFP, the value programmed in the PL peripheral [4:0] field specifies the PL peripheral associated with that DMA channel. Refer to the DMAWFP instruction in Table 9-8, page 228.

PL Peripheral Request Interface Timing Diagram

Figure 9-5 shows an example of the functional operation of the PL peripheral request interface using the rules that handshake rules described, when a PL peripheral requests an AXI burst transaction.
X-Ref Target - Figure 9-5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

DMA{3:0}_ACLK DMA{3:0}_DRVALID DMA{3:0}_DRTYPE[1:0] DMA{3:0}_DRREADY DMA{3:0}_DAVALID DMA{3:0}_DATYPE[1:0] DMA{3:0}_DAREADY DMA Activity on the AXI Data Bus AXI Data Burst
UG585_c9_06_030712

Burst

Ack

Figure 9-5:

DMAC PL Peripheral Request Interface Burst Request Signaling

State transitions in Figure 9-5: T1 Between T2 and T7 The DMAC detects a request for an AXI burst transaction. The DMAC performs the AXI burst transaction.

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T7

The DMAC sets DMA{3:0}_DAVALID High and sets DMA{3:0}_DATYPE[1:0] to indicate that the transaction is complete.

For more timing diagrams refer to ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: Peripheral Request Interface Timing Diagrams, keeping in mind that each PL peripheral request interface is asynchronous to one another and asynchronous to the DMA itself.

9.2.8 PL Peripheral - Length Managed by PL Peripheral

The PL peripheral request interface enables a PL peripheral to control the quantity of data that an AXI transfer contains, without the DMAC being aware of how many data cycles the transfer contains. The PL peripheral controls the AXI transaction by using: DMA{3:0}_DRTYPE[1:0] DMA{3:0}_DRLAST Selects a single or burst AXI Transaction Notifies the DMAC when it commences the final request in the current series

When the DMAC executes a DMAWFP instruction, it halts execution of the thread and waits for the PL peripheral to send a request. When the PL peripheral sends the request, the DMAC sets the state of the request flags depending on the state of the following signals: DMA{3:0}_DRTYPE[1:0] 00: 01: DMA{3:0}_DRLAST 0: 1: The DMAC sets the state of the request_type flag: request_type = Single request_type = Burst The DMAC sets the state of the request_last flag: request_last = 0 request_last = 1

If the DMAC executes a DMAWFP single or DMAWFP burst instruction then the DMAC sets: The request_type{3:0} flag to Single or Burst, respectively The request_last{3:0} flag to 0

DMALPFE is an assembler directive which forces the associated DMALPEND instruction to have its nf bit set to 0 . This creates a program loop that does not use a loop counter to terminate the loop. The DMAC exits the loop when the request_last flag is set to 1 . The DMAC conditionally executes the following instructions, depending on the state of the request_type and request_last flags: DMALD, DMAST, DMALPEND When these instructions use the optional B|S suffix then the DMAC executes a DMANOP if the request_type flag does not match.

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DMALDP<B|S>, DMASTP<B|S> The DMAC executes a DMANOP if the request_type flag does not match the B|S suffix. DMALPEND When the nf bit is 0 , the DMAC executes a DMANOP if the request_last flag is set. The DMALDB, DMALDPB, DMASTB and DMASTPB instructions should be used if the DMAC is required to issue an AXI burst transaction when the DMAC receives a burst request, that is, when DMA{3:0}_DRTYPE[1:0] = b01 . The values in the CCRn register control the amount of data in the DMA transfer. Refer to the Channel Control registers in Appendix B, Register Details. The DMALDS, DMALDPS, DMASTS, and DMASTPS instructions should be used if the DMAC is required to issue a single AXI transaction when the DMAC receives a single request, that is, when DMA{3:0}_DRTYPE[1:0] = b00 . The DMAC ignores the value of the src_burst_len and dst_burst_len fields in the CCRn register and sets the arlen[3:0] or awlen[3:0] buses to 0x0 . Refer to the Programming Guide for DMA Controller for an example of microcode for PL peripheral length management.

9.2.9 PL Peripheral - Length Managed by DMAC

DMAC length management is the process by which the DMAC controls the total amount of data to transfer. Using the PL peripheral request interface, the PL peripheral notifies the DMAC when a transfer of data in either direction is required. The DMA channel thread controls how the DMAC responds to the PL peripheral requests. The following constraints apply to DMAC length management: The total quantity of data for all of the single requests from a PL peripheral must be less than the quantity of data for a burst request for that PL peripheral. The CCRn register controls how much data is transferred for a burst request and a single request. ARM recommends that a CCRn register not be updated while a transfer is in progress for that channel. Refer to the Channel Control registers in Appendix B, Register Details. After the PL peripheral sends a burst request, the PL peripheral must not send a single request until the DMAC acknowledges that the burst request is complete.

The DMAWFP single instruction should be used when the program thread is required to halt execution until the PL peripheral request interface receives any request type. If the head entry request type in the request FIFO is: Single: Burst: The DMAC pops the entry from the FIFO and continues program execution. The DMAC leaves the entry in the FIFO and continues program execution.

Note: The burst request entry remains in the request FIFO until the DMAC executes a DMAWFP
burst instruction or a DMAFLUSHP instruction.

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The DMAWFP burst instruction should be used when the program thread is required to halt execution until the PL peripheral request interface receives a burst request. If the head entry request type in the request FIFO is: Single: Burst: The DMAC removes the entry from the FIFO and program execution remains halted. The DMAC pops the entry from the FIFO and continues program execution.

The DMALDP instruction should be used when the DMAC is required to send an acknowledgement to the PL peripheral when it completes the AXI read transaction. Similarly, the DMASTP instruction should be used when the DMAC is required to send an acknowledgement to the PL peripheral when it completes the AXI write transaction. The DMAC uses the DMA{3:0}_DATYPE[1:0] bus to acknowledge the transaction to the PL peripheral {3:0}. The DMAC sends an acknowledgement for a read transaction when rvalid and rlast are High and for a write transaction when bvalid is High. If the system is able to buffer AXI write transactions, it might be possible for the DMAC to send an acknowledgement to the PL peripheral, but the transaction of write data to the end destination is still in progress. The DMAFLUSHP instruction should be used to reset the request FIFO for the PL peripheral request interface. After the DMAC executes DMAFLUSHP, it ignores PL peripheral requests until the PL peripheral acknowledges the flush request. This enables the DMAC and PL peripheral to synchronize with each other. Refer to section 9.3 Programming Guide for DMA Controller for an example of microcode for DMA length management.

9.2.10 Events and Interrupts

The DMAC supports 16 events. The first 8 of these events can be interrupt signals, IRQs [7:0]. Each of the eight interrupts are outputs going to both the PS interrupt controller and the PL at the same time. The events are used internal to the DMA engine to cross-trigger channel-to-channel or manager-to-channel. Table 9-2 shows the mapping between events and interrupts. Refer to the Interrupt Enable register in Appendix B, Register Details for programming details. Table 9-2: DMAC Events and Interrupts System IRQ# (to the PS)
46 ~ 49 72 ~ 75 na

DMAC Event/IRQ #
0~3 4~7 8 ~ 15

IRQP2F (to the PL)

20 ~ 23 24 ~ 27 na

DMA Engine Event#

0~3 4~7 8 ~ 15

When the DMA engine executes a DMASEV instruction it modifies the event/interrupt that the user specifies. If the INTEN register sets the event/interrupt resource to function as an event, the DMAC generates an event for the specified event/interrupt resource. When the DMAC executes a DMAWFE instruction for the same event-interrupt resource then it clears the event.

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If the INTEN register sets the event/interrupt resource to function as an interrupt, the DMAC sets irq<event_num> High, where event_num is the number of the specified event-resource. To clear the interrupt, the user must write to the INTCLR register. Refer to the Interrupt Clear register in Appendix B, Register Details.

Refer to section 9.3 Programming Guide for DMA Controller for more information and Chapter 7, Interrupts for more details about the System IRQs.

9.2.11 Aborts
An abort is sent to the CPUs via IRQ ID #45 and the PL peripheral via the IRQP2F[28] signal. Table 9-3 summarizes all of the possible causes for an abort. Table 9-3 explains the actions that the DMAC takes after an abort condition. After an abort occurs the action the DMAC takes depends on the thread type. Table 9-5 describes the actions that the processors or the PL peripheral must take after the Abort signal is received. Refer to the ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: Aborts for details. Table 9-3: DMAC Abort Types and Conditions Abort Types Condition
A DMA channel thread in a non-secure state attempts to program the Channel Control registers and generates a secure AXI bus transaction. A DMA channel thread in a non-secure state executes DMAWFE or DMASEV for an event that is set as secure. The SLCR register TZ_DMA_IRQ_NS controls the security state for an event.

Security Violation on Channel Control Registers

Security Violation on Events

The DMAC updates the PC Security Violation on PL Peripheral Request Interfaces register with the address of the A DMA channel thread in a non-secure state executes DMAWFP, DMALDP, DMASTP, or instruction that created the DMAFLUSHP for a PL peripheral request interface that is set as secure. The SLCR abort. register TZ_DMA_PERIPH_NS controls the security state for a PL peripheral request interface. Note: When the DMAC signals a precise abort, the instruction Security Violation on DMAGO that triggers the abort is not The DMA manager in a non-secure state executes DMAGO to attempt to start a secure executed; the DMAC executes a DMA channel thread. DMANOP instead. The DMAC receives an ERROR response on the AXI master interface when it performs an instruction fetch. For example; trying to access reserved memory. A thread executes an undefined instruction or executes an instruction with an operand that is invalid for the configuration of the DMAC.

Precise

Error on AXI Master Interface

Error on Execution Engine

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Table 9-3:

DMAC Abort Types and Conditions (Contd) Abort Types Condition

The DMAC receives an ERROR response on the AXI master interface when it performs a data load. The DMAC receives an ERROR response on the AXI master interface when it performs a data store. A DMA channel thread executes DMALD and the MFIFO is too small to store the data or executes DMAST and the MFIFO contains insufficient data to complete the AXI transaction.

Error on Data Load

Error on Data Store

Error on MFIFO

The PC register might contain The DMAC can lock up if one or more DMA channel programs are running and the the address of an instruction that MFIFO is too small to satisfy the storage requirements of the DMA programs. did not cause the abort occur. The DMAC contains logic to prevent it from remaining in a state where it is unable to complete a DMA transfer. The DMAC detects a lock up when all of the following conditions occur: Load queue is empty Store queue is empty All of the running channels are prevented from executing a DMALD instruction either because the MFIFO does not have sufficient free space or another channel owns the load-lock When the DMAC detects a lock up it signals an interrupt and can also abort the contributing channels. The DMAC behavior depends on the state of the wd_irq_only bit in the WD register. For more information, refer to the subsection Resource Sharing Between DMA Channels, page 242.

Imprecise

Watchdog Abort

Table 9-4:

DMAC Abort Handling DMAC Actions

Sets IRQ#45 interrupt and IRQP2F[28] signal High Stops executing instructions for the DMA channel Invalidates all cache entries for the DMA channel Updates the Channel Program Counter registers to contain the address of the aborted instruction provided that the abort was precise Does not generate AXI accesses for any instructions remaining in the read queue and write queue Permits currently active AXI bus transactions to complete Sets IRQ#45 interrupt and IRQP2F[28] signal High

Thread Type

Channel thread

DMA manager

Table 9-5:

DMAC Thread Termination Processor or PL Peripheral Actions

Reads the status of Fault Status DMA Manager register to determine if the DMA manager is faulting and to determine the cause of the abort Reads the status of Fault Status DMA Channel register to determine if a DMA channel is faulting and to determine the cause of the abort

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Table 9-5:

DMAC Thread Termination (Contd) Processor or PL Peripheral Actions

Programs the Debug Instruction-0 register with the encoding for the DMAKILL instruction Writes to the Debug Command register.

9.2.12 Security
When the DMAC exits from reset, the status of the reset initialization interface signals configures the security for the: DMA manager (SLCR register TZ_DMA_NS) Event/Interrupt resources (SLCR register TZ_DMA_IRQ_NS) PL peripheral request interfaces (SLCR register TZ_DMA_PERIPH_NS)

Refer to the section 9.6.3 Reset Configuration of Controller for more details. When the DMA manager executes a DMAGO instruction for a DMA, it sets the security state of the channel setting the ns bit. The status of the channel is provided by the dynamic non-secure bit, CNS in the Channel Status register.

Note: For more information refer to ARM PrimeCell DMA Controller (PL330) Technical Reference
Manual: Security Usage .

Nomenclature
Table 9-6 describes how the nomenclature used in this chapter corresponds to ARM nomenclature. Table 9-6: DMAC Security Nomenclature XILINX Name
DMAC_NS in TZ_DMA_NS

ARM Name

Description
When the DMAC exits from reset, this signal controls the security state of the DMA manager: 0 : DMA manager operates in the secure state 1 : DMA manager operates in the non-secure state When the DMAC exits from reset, this signal controls the security state of an event/interrupt: 0 : DMAC interrupt/event bit is in the secure state 1 : DMAC interrupt/event bit is in the non-secure state When the DMAC exits from reset, this signal controls the security state of a PL peripheral request interface: 0 : DMAC PL peripheral request interface is in the secure state 1 : DMAC PL peripheral request interface is in the non-secure state

DMA Non-secure

DNS

Interrupt Non-secure

INS

DMAC_IRQ_NS<x> in TZ_DMA_IRQ_NS

PL Peripheral Non-secure

PNS

DMAC_PERIPH_NS<x> in TZ_DMA_PERIPH_NS

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Table 9-6:

DMAC Security Nomenclature (Contd) XILINX Name

ns in DMAGO instruction

ARM Name
ns

Description
Bit 1 of the DMAGO instruction: 0 : DMA channel thread starts in the secure state 1 : DMA channel thread starts in the secure state The security state of each DMA channel is provided by bit CNS in the Channel Status register: 0 : DMA channel thread operates in the secure state 1 : DMA channel thread operates in the secure state

DMAGO Non-secure

CHANNEL Non-secure

CNS

CNS in CSR<x>

Security by DMA Manager

A quick summary of the security usage for the DMA Manager is given in Table 9-7. Table 9-7: DMAC Security by DMA Manager DNS Instruction ns
0 DMAGO 0 1 -

INS
-

Description
The instruction must be issued using the secure APB interface. The DMA channel thread starts in secure state (CNS= 0). The instruction must be issued using the secure APB interface. The DMA channel thread starts in non-secure state (CNS=1). The instruction must be issued using the secure APB interface. It signals the appropriate event irrespective of the INS bit. The instruction must be issued using the non-secure APB interface. Abort (see section 9.2.11 Aborts). The instruction must be issued using the non-secure APB interface. The DMA channel thread starts in non-secure state (CNS=1). The instruction must be issued using the non-secure APB interface. Abort (see section 9.2.11 Aborts). The instruction must be issued using the non-secure APB interface. It signals the appropriate event.

DMASEV DMA Manager DMAGO

X -

1 1 DMASEV -

0 1

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Security by DMA Channel Thread

A quick summary of the security usage for the DMA Channel Threads is given in Table 9-8. Table 9-8: DMAC Security by DMA Channel Thread CNS bit Instruction
DMAWFE DMASEV DMAWFP 0 DMALP, DMASTP DMAFLUSH DMAWFE DMASEV DMAWFP 1 DMALP, DMASTP X X 0 1 0 1 0 DMAFLUSHP 1 0 1 0 1 -

PNS bit INS bit

X X X -

Description
On event, execution continues, irrespective of the INS bit Signals the appropriate event, irrespective of the INS bit On peripheral request, execution continues, irrespective of the PNS bit Sends a message to the PL peripheral to communicate that the last AXI transaction of the DMA transfer is complete, irrespective of the PNS bit Clears the state of the peripheral and sends a message to the peripheral to resend its level status, irrespective of the PNS bit Abort On event, execution continues Abort It signals the appropriate event Abort On peripheral request, execution continues Abort Sends a message to the peripheral to communicate that the last AXI transaction of the DMA transfer is complete Abort It only clears the state of the peripheral and sends a message to the peripheral to resend its level status

DMA Channel Thread

9.2.13 IP Configuration Options

The Xilinx implementation of the DMAC uses the IP configuration options shown in Table 9-9. Table 9-9: DMAC IP Configuration Options Value
64 8 16 (8 interrupts, 8 events) 4 (to PL) 8 4 1 16

IP Configuration Option
Data width (bits) Number of channels Number of interrupts Number of peripherals Number of cache lines Cache line width (words) Buffer depth (MIFIFO depth) Read queue depth

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Table 9-9:

DMAC IP Configuration Options (Contd) Value

16 8 8 All capabilities 0xF800_3000 0xF800_4000

IP Configuration Option
Write queue depth Read issuing capability Write issuing capability Peripheral request capabilities Secure APB base address Non-secure APB base address

9.3 Programming Guide for DMA Controller

9.3.1 Startup
Example: Start-up Controller
1. 2. 3. Configure Clocks. Refer to section 9.6.1 Clocks Configure Security State. Refer to section 9.6.3 Reset Configuration of Controller Reset the Controller. Refer to section 9.6.2 Resets

4. Create Interrupt Service Routine. Refer to section 9.3.3 Interrupt Service Routine 5. Execute DMA Transfers. Refer to section 9.3.2 Execute a DMA Transfer

9.3.2 Execute a DMA Transfer

1. Write Microcode into Memory for DMA Transfer. Refer to section 9.4 Programming Guide for DMA Engine a. 2. Create a program for the DMA channel. b. Store the program in a region of system memory. Start the DMA Channel Thread. Refer to section 9.2.3 DMA Manager

9.3.3 Interrupt Service Routine

There are two types of interrupt signals from the DMA controller to the PS interrupt controller:

Eight DMAC IRQs [75:72] and [49:46] One DMAC ABOART IRQ [45]

An interrupt service routine (ISR) can be use for each type of interrupt. The two ISRs are described below. For more information on interrupts, refer to section 9.2.10 Events and Interrupts.

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Example: IRQ Interrupt Service Routine

The following steps need to be performed in this routine. This routine can support all 8 DMAC IRQs. 1. 2. 3. Check which event has caused the interrupt. Read dmac.INT_EVENT_RIS. Clear the corresponding event. Write to the dmac.INTCLR register. Inform the application that the DMA transfer has finished. Call the user callback function if registered during DMA transfer setup.

Example: IRQ_ABORT Interrupt Service Routine

The following steps need to be performed in this routine. 1. 2. 3. Determine if a Manager fault occurred. Read dmac.FSRD. If the value of fs_mgr field is set, read dmac.FTRD to know about the fault type. Determine if a Channel fault occurred. Read dmac.FSRC. If the value of fault_status field for a channel is set, read dmac.FTRx of the corresponding channel to know about the fault type. Execute DMAKILL instruction. Do this for the DMA Manager or the DMA Channel Thread: a. For the DMA Manager write the dmac.DBGINST0 register (refer to Appendix B, Register Details) and enter the: c. Instruction byte 0 encoding for DMAKILL. debug_thread bit to 0. This selects the DMA manager. Instruction byte 0 encoding for DMAKILL. channel_num bit set to the channel number to kill. debug_thread bit to 1. This selects the DMA channel thread.

b. For the DMA Channel Thread write the dmac.DBGINST0 register and enter the:

Wait until the dbgstatus field in dmac.DBGSTATUS is busy.

d. Write 0x0 to the dmac.DBGCMD register to execute the instruction that the DBGINSTx registers contain.

9.3.4 Register Overview

Table 9-10 provides an overview of the DMA Controller registers. Table 9-10: DMAC Register Overview Register Name
dmac.XDMAPS_DS dmac.XDMAPS_DPC dmac.INT_EVENT_RIS dmac.INTCLR dmac.INTEN dmac.INTMIS

Function
DMAC Control Interrupts and Events

Overview
Provides the security state and the program counter. Enables/disables the interrupt detection, mask interrupt sent to the interrupt controller, and reads raw interrupt status.

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Table 9-10:

DMAC Register Overview (Contd) Register Name

dmac.FSRD dmac.FSRC dmac.FTRD dmac.FTR{7:0} dmac.CPC{7:0} dmac.CSR{7:0} dmac.SAR{7:0} dmac.DAR{7:0} dmac.CCR{7:0} dmac.LC0_{7:0} dmac.LC1_{7:0} dmac.DBGSTATUS dmac.DBGCMD dmac.DBGINST{1,0} dmac.XDMAPS_CR{4:0} dmac.XDMAPS_CRDN dmac.WD slcr.DMAC_RST_CTRL slcr.TZ_DMAC_NS slcr.TZ_DMA_IRQ_NS slcr.TZ_DMAC_PERIPH_NS slcr.DMAC_RAM slcr.APER_CLK_CTRL

Function
Fault Status and Type

Overview
Provides the fault status and type for the manager and the channels.

Channel Thread Status

These registers provide the status of the DMA channel threads.

Debug

These registers enable the user to send instructions to a channel thread. These registers enable system firmware to discover the hardwired configuration of the DMAC Controls how the DMAC responds when it detects a lock-up condition. Control reset, clock, and security state.

IP Configuration Watchdog System-level

9.4 Programming Guide for DMA Engine

The programming guide for the DMA Engine includes these section: 9.4.1 Write Microcode to Program CCRx for AXI Transactions 9.4.2 Memory-to-Memory Transfers 9.4.3 PL Peripheral DMA Transfer Length Management 9.4.4 Restart Channel using an Event 9.4.5 Interrupting a Processor 9.4.6 Instruction Set Reference

Note: Table 9-14 and Table 9-15, page 240 summarize the DMAC instructions and commands. Note: For more programming information, refer to the ARM Application Note 239: Example
programs for the CoreLink DMA Controller DMA-330 for more programming examples.

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9.4.1 Write Microcode to Program CCRx for AXI Transactions

The channel microcode is used to set the dmac.CCRx registers to define the attributes of the AXI transactions. This is done using the DMAMOV CCR instruction. The user should program the microcode to write to the dmac.CCR{7:0} register before it initiates a DMA transfer. Here are the AXI attributes that the microcode writes: 1. 2. 3. 4. 5. Program the src_inc and dst_inc bit fields based on the type of burst (incrementing or fixed address). This affects the ARBURST[0] and AWBURST[0] AXI signals. Program the src_burst_size and dst_burst_size bit fields (number bytes per data beat on AXI). This affects the ARSIZE[2:0] and AWSIZE[2:0] AXI signals. Program the src_burst_len and dst_burst_len bit fields (number of data beats per AXI burst transaction). This affects the ARLEN[3:0] and AWLEN[3:0] AXI signals. Program the src_cache_ctrl and dst_cache_ctrl bit fields (caching strategy). This affects the ARCACHE [2:0] and AWCACHE[2:0] AXI signals. Program the src_prot_ctrl and dst_prot_ctrl bit fields (security state of the manager thread.) If the manager thread is secure, ARPROT[1] should be set = 0 and if non-secure then it should be set = 1. ARPROT[0] and ARPROT[2] values should be set = 0 . For example: 6. Set src_prot_ctrl = 0b000 if DMA Manager is secure, Set scr_prot_ctrl = 0b010 if DMA Manager is non-secure

Program endian_swap_size = 0 (no swapping).

9.4.2 Memory-to-Memory Transfers

This section shows examples of microcode that the DMAC executes to perform aligned, unaligned, and fixed data transfers. Refer to Table 9-11 for aligned transfer, Table 9-12 for unaligned transfer, and Table 9-13 for Fixed transfer. MFIFO utilization is also described.

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Table 9-11:

DMAC Aligned Memory-to-Memory Transfers Description Code

DMAMOV CCR, SB4 SS64 DB4 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 DMALP 16 DMALD DMAST DMALPEND DMAEND

MFIFO Usage
Each DMALD requires four entries and each DMAST removes four entries. This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.

Simple Aligned Program In this program the source address and destination address are aligned with the AXI data bus width.

Aligned asymmetric program with multiple loads The following program performs four loads for each store and the source address and destination address are aligned with the AXI data bus width.

DMAMOV CCR, SB1 SS64 DB4 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 DMALP 16 DMALD DMALD DMALD DMALD DMAST DMALPEND DMAMOV CCR, SB4 SS64 DB1 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 DMALP 16 DMALD DMAST DMAST DMAST DMAST DMALPEND DMAEND

Each DMALD requires one entry and each DMAST removes four entries. This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.

Aligned asymmetric program with multiple stores The following program performs four stores for each load and the source address and destination address are aligned with the AXI data bus width.

Each DMALD requires four entries and each DMAST removes one entry. This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.

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Table 9-12:

DMAC Unaligned Transfers Description Code

DMAMOV CCR, SB4 SS64 DB4 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4004 DMALP 16 DMALD DMAST DMALPEND DMAMOV CCR, SB4 SS64 DB1 DS32 DMAST DMAEND

MFIFO Usage
The first DMALD instruction loads four double words but because the destination address is unaligned, the DMAC shifts them by four bytes and therefore it uses five entries in the MFIFO. Each DMAST requires only four entries of data and therefore the extra entry remains in use for the duration of the program until it is emptied by the last DMAST. This example has a static requirement of one MFIFO entry and a dynamic requirement of four MFIFO entries.

Aligned source address to unaligned destination address In this program, the source address is aligned with the AXI data bus width but the destination address is unaligned. The destination address is not aligned to the destination burst size so the first DMAST instruction removes less data than the first DMALD instruction reads. Therefore, a final DMAST of a single word is required to clear the data from the MFIFO.

Unaligned source address to aligned destination address In this program the source address is unaligned with the AXI data bus width but the destination address is aligned. The source address is not aligned to the source burst size so the first DMALD instruction reads in less data than the DMAST requires. Therefore, an extra DMALD is required to satisfy the first DMAST.

DMAMOV CCR, SB4 SS64 DB4 DS64 DMAMOV SAR, 0x1004 DMAMOV DAR, 0x4000 DMALD DMALP 15 DMALD DMAST DMALPEND DMAMOV CCR, SB1 SS32 DB4 DS64 DMALD DMAST DMAEND

The first DMALD instruction does not load sufficient data to enable the DMAC to execute a DMAST and therefore the program includes an additional DMALD, prior to the start of the loop. After the first DMALD, the subsequent DMALDs align with the source burst size. This optimizes the performance but it requires a larger number of MFIFO entries. This example has a static requirement of four MFIFO entries and a dynamic requirement of four MFIFO entries.

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Table 9-12:

DMAC Unaligned Transfers (Contd) Description Code

DMAMOV CCR, SB5 SS64 DB4 DS64 DMAMOV SAR, 0x1004 DMAMOV DAR, 0x4000 DMALD DMAST DMAMOV CCR, SB4 SS64 DB4 DS64 DMALP 14 DMALD DMAST DMALPEND DMAMOV CCR, SB3 SS64 DB4 DS64 DMALD DMAMOV CCR, SB1 SS32 DB4 DS64 DMALD DMAST DMAEND

MFIFO Usage
The first DMALD instruction loads five beats of data to enable the DMAC to execute the first DMAST. After the first DMALD, the subsequent DMALDs are not aligned to the source burst size, for example the second DMALD reads from address 0x1028. After the loop, the final two DMALDs read the data required to satisfy the final DMAST. This example has a static requirement of one MFIFO entry and a dynamic requirement of four MFIFO entries.

Unaligned source address to aligned destination address, with excess initial load This program is an alternative to that described in unaligned source address to aligned destination address. The program uses a different sequence of source bursts which might be less efficient but requires fewer MFIFO entries.

Aligned burst size, unaligned MFIFO In this program the destination address, which is narrower than the MFIFO width, aligns with the burst size but does not align with the MFIFO width.

DMAMOV CCR, SB4 SS32 DB4 DS32 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4004 DMALP 16 DMALD DMAST DMALPEND DMAEND

If the DMAC configuration has a 32-bit AXI data bus width then this program requires four MFIFO entries. However, in this example the DMAC has a 64-bit AXI data bus width and, because the destination address is not 64-bit aligned, it requires three rather than the expected two MFIFO entries. This example has a static requirement of zero MFIFO entries and a dynamic requirement of three MFIFO entries.

Table 9-13:

DMAC Fixed Transfers Description Code

DMAMOV CCR, SB2 SS64 DB4 DS32 DAF DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 DMALP 16 DMALD DMAST DMALPEND DMAEND

MFIFO Usage
Each DMALD in the program loads two 64-bit data transfers into the MFIFO. Because the destination address is a 32-bit fixed address then the DMAC splits each 64-bit data item across two entries in the MFIFO. This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.

Fixed destination with aligned address In this program the source address and destination address are aligned with the AXI data bus width, and the destination address is fixed.

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9.4.3 PL Peripheral DMA Transfer Length Management

Example: Length Managed by Peripheral
The following example shows a DMAC program that transfers 64 words from memory to peripheral 0 when the peripheral sends a burst request (DMA{3:0}_DRTYPE[1:0] = 01) . When the peripheral sends a single request (DMA{3:0}_DRTYPE[1:0] = 00 ) then the DMAC program transfers one word from memory to peripheral 0. To transfer the 64 words, the program instructs the DMAC to perform 16 AXI bus transactions. Each transaction consists of a 4-beat burst (SB=4, DB=4), each beat of which moves a word of data (SS=32, DS=32). In this example, the program shows use of the following instructions: DMAWFP instruction. The DMAC waits for either a burst or single request from the peripheral. DMASTPB and DMASTPS instructions. The DMAC informs the peripheral when a transfer is complete.
# Set up for burst transfers (4-beat burst, so SB4 and DB4), # (word data width, so SS32 and DS32) DMAMOV CCR SB4 SS32 DB4 DS32 DMAMOV SAR ... DMAMOV DAR ... # Initialize peripheral '0' DMAFLUSHP P0 # Perform peripheral transfers # Outer loop - DMAC responds to peripheral requests until peripheral # sets drlast_0 = 1 DMALPFE # Wait for request, DMAC sets request_type0 flag depending on the # request type it receives DMAWFP 0, periph # Set up loop for burst request: first 15 of 16 sets of transactions # Note: B suffix - conditionally executed only if request_type0 # flag = Burst DMALP 15 DMALDB DMASTB # Only loopback if servicing a burst, otherwise treat as a NOP DMALPENDB # Perform final transaction (16 of 16). Send the peripheral # acknowledgement of burst request completion DMALDB DMASTPB P0 # Perform transaction if the peripheral signals a single request # Note: S suffix - conditionally executed only if request_type0 # flag = Single

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DMALDS DMASTPS P0 # Exit loop if DMAC receives the last request, that is, drlast_0 = 1 DMALPEND DMAEND

Example: Length Managed by DMAC

This example shows a DMAC program that can transfer 1,027 words when a peripheral signals 16 consecutive burst requests and 3 consecutive single requests.
# Set up for AXI burst transfer # (4-beat burst, so SB4 and DB4), (word data width, so SS32 and DS32) DMAMOV CCR SB4 SS32 DB4 DS32 DMAMOV SAR ... DMAMOV DAR ... # Initialize peripheral '0' DMAFLUSHP P0 # Perform peripheral transfers # Burst request loop to transfer 1024 words DMALP 16 # Wait for the peripheral to signal a burst request. # DMAC transfers 64 words for each burst request DMAWFP 0, burst # Set up loop for burst request: first 15 of 16 sets of transactions DMALP 15 DMALD DMAST DMALPEND # Perform final transaction (16 of 16). # Send the peripheral acknowledgement of burst request completion DMALD DMASTPB 0 # Finish burst loop DMALPEND # Set up for AXI single transfer (word data width, so SS32 and DS32) DMAMOV CCR SB1 SS32 DB1 DS32 # Single request loop to transfer 3 words DMALP 3 # Wait for the peripheral to signal a single request. DMAC to transfer # one word DMAWFP 0, single # Perform transaction for single request and send completion # acknowledgement to the peripheral DMALDS

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DMASTPS P0 # Finish single loop DMALPEND # Flush the peripheral, in case the single transfers were in response # to a burst request DMAFLUSHP 0 DMAEND

9.4.4 Restart Channel using an Event

When the INTEN register is programmed to generate an event, the DMASEV and DMAWFE instructions can be used to restart one or more DMA channels. Refer to the Interrupt Enable register in Appendix B, Register Details. The following sections describe the DMAC behavior when: DMAC executes DMAWFE before DMASEV DMAC executes DMASEV before DMAWFE

DMAC Executes DMAWFE before DMASEV

To restart a single DMA channel: 1. 2. The first DMA channel executes DMAWFE and then stalls while it waits for the event to occur. The other DMA channel executes DMASEV using the same event number. This generates an event, and the first DMA channel restarts. The DMAC clears the event, one DMA{3:0}_ACLK cycle after it executes DMASEV.

Multiple channels can be programmed to wait for the same event. For example, if four DMA channels have all executed DMAWFE for event 12, then when another DMA channel executes DMASEV for event 12, the four DMA channels all restart at the same time. The DMAC clears the event one clock cycle after it executes DMASEV.

DMAC Executes DMASEV before DMAWFE

If the DMAC executes DMASEV before another channel executes DMAWFE, then the event remains pending until the DMAC executes DMAWFE. When the DMAC executes DMAWFE, it halts execution for one DMA{3:0}_ACLK cycle, clears the event, and then continues execution of the channel thread. For example, if the DMAC executes DMASEV 6 and none of the other threads have executed DMAWFE 6, then the event remains pending. If the DMAC executes DMAWFE 6 instruction for channel 4 and then executes DMAWFE 6 instruction for channel 3, then: 1. 2. 3. The DMAC halts execution of the channel 4 thread for one DMA{3:0}_ACLK cycle. The DMAC clears event 6. The DMAC resumes execution of the channel 4 thread.

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4.

The DMAC halts execution of the channel 3 thread and the thread stalls while it waits for the next occurrence of event 6.

9.4.5 Interrupting a Processor

The controller provides the seven active-High sensitive interrupts (IRQ ID #75:72 and 49:46) to the CPUs via the interrupt controller (GIC). When the INTEN register is programmed to generate an interrupt, after the DMAC executes DMASEV, the controller sets the corresponding interrupt to an active High state. The controller can also generate an Abort interrupt (IRQ ID #45) as described in section 9.2.11 Aborts. The DMAC interrupt enable and mask control registers are shown in Appendix B, Register Details. An external microprocessor can clear the interrupt by writing to the Interrupt Clear register. Executing DMAWFE does not clear an interrupt. If the DMASEV instruction is used to notify a microprocessor when the DMAC completes a DMALD or DMAST instruction, ARM recommends that a memory barrier instruction be inserted before the DMASEV. Otherwise the DMAC might signal an interrupt before the AXI transaction complete. This is demonstrated in the following example:
DMALD DMAST # Issue a write memory barrier # Wait for the AXI write transfer to complete before the DMAC can # send an interrupt DMAWMB # The DMAC sends the interrupt DMASEV

9.4.6 Instruction Set Reference

Table 9-14 and Table 9-15 summarize the DMAC instructions and commands. Refer to ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: AXI characteristics for a DMA transfer and AXI master for more information about the DMA Engine instructions. Table 9-14: DMA Engine Instruction Summary Mnemonic
DMAADDH DMAADNH DMAEND DMAFLUSHP DMAGO

Instruction
Add Halfword Add Negative Halfword End Flush and Notify Peripheral Go

Thread Usage: M = DMA Manager C = DMA Channel

M C C C C -

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Table 9-14:

DMA Engine Instruction Summary (Contd) Mnemonic

DMAKILL DMALD DMALDP DMALP DMALPEND DMALPFE DMAMOV DMANOP DMARMB DMASEV DMAST DMASTP

Instruction
Kill Load Load and Notify Peripheral Loop Loop End Loop Forever Move No operation Read memory Barrier Send Event Store Store and Notify Peripheral Store Zero Wait For Event Wait For Peripheral Write memory Barrier

Thread Usage: M = DMA Manager C = DMA Channel

M M M C C C C C C C C C C C C C C C C

DMASTZ
DMAWFE DMAWFP DMAWMB

Table 9-15:

DMA Engine Additional Commands Provided by the Assembler Directives Mnemonic

DCD DCB DMALP DMALPFE DMALPEND

Place a 32-bit immediate Place a 8-bit immediate Loop Loop Forever Loop End Move CCR

DMAMOV CCR

9.5 Programming Restrictions

Note: Refer to the ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: Programming
Restrictions for details about restrictions that apply when programming the DMAC. There are four considerations: Fixed unaligned bursts Endian swap size restrictions

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Updating channel control registers during a DMA cycle (section, below) Full MFIFO causes DMAC watchdog to abort a DMA channel (section, below, titled Resource sharing between DMA channels)

The following sections describe these last two restrictions in detail.

9.5.1 Updating Channel Control Registers During a DMA Cycle

Prior to the DMAC executing a sequence of DMALD and DMAST instructions, the values software programs in to the CCRn register, SARn register, and DARn register control the data byte lane manipulation that the DMAC performs when it transfers the data from the source address to the destination address. Refer to the Channel Control registers, Source Address registers, and Destination Address registers in Appendix B, Register Details. These registers can be updated during a DMA cycle, but if certain register fields are changed, the DMAC might discard data. The following sections describe the register fields that might have a detrimental impact on a data transfer: Updates that affect the destination address Updates that affect the source address

Updates That Affect the Destination Address

If a DMAMOV instruction is used to update the DARn register or CCRn register part way through a DMA cycle, a discontinuity in the destination datastream might occur. A discontinuity occurs if any of the following is changed: dst_inc bit dst_burst_size field when dst_inc = 0, (fixed-address burst) DARn register so that it modifies the destination byte lane alignment. For example, when the bus width is 64 bits and bits [2:0] in the DARn register are changed.

When a discontinuity in the destination datastream occurs, the DMAC: 1. 2. 3. 4. Halts execution of the DMA channel thread. Completes all outstanding read and write operations for the channel (just as if the DMAC was executing DMARMB and DMAWMB instructions). Discards any residual MFIFO data for the channel. Resumes execution of the DMA channel thread.

Updates That Affect the Source Address

If a DMAMOV instruction is used to update the SARn register or CCRn register part way through a DMA cycle, a discontinuity in the source datastream might occur. A discontinuity occurs if any of the following is changed: src_inc bit src_burst_size field

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SARn register so that it modifies the source byte lane alignment. For example, when the bus width is 32 bits and bits [1:0] in the SARn register are changed.

When a discontinuity in the source datastream occurs, the DMAC: 1. 2. 3. Halts execution of the DMA channel thread. Completes all outstanding read operations for the channel (just as if the DMAC was executing DMARMB instruction). Resumes execution of the DMA channel thread. No data is discarded from the MFIFO.

Resource Sharing Between DMA Channels

DMA channel programs share the MFIFO data storage resource. A set of concurrently running DMA channel programs must not be started with a resource requirement that exceeds the configured size of the MFIFO. If this limit is exceeded, the DMAC might lock up and generate a watchdog abort. The DMAC includes a mechanism called the load-lock to ensure that the shared MFIFO resource is used correctly. The load-lock is either owned by one channel, or it is free. The channel that owns the load-lock can execute DMALD instructions successfully. A channel that does not own the load-lock pauses at a DMALD instruction until it takes ownership of the load-lock. A channel claims ownership of the load-lock when: It executes a DMALD or DMALDP instruction. No other channel currently owns the load-lock.

A channel releases ownership of the load-lock when any of the following controller actions occur: Executes a DMAST, DMASTP, or DMASTZ. Reaches a barrier, that is, it executes DMARMB or DMAWMB. Waits, that is, it executes DMAWFP or DMAWFE. Terminates normally, that is, it executes DMAEND. Aborts for any reason, including DMAKILL.

The MFIFO resource usage of a DMA channel program is measured in MFIFO entries, and rises and falls as the program proceeds. The MFIFO resource requirement of a DMA channel program is described using a static requirement and a dynamic requirement which are affected by the load-lock mechanism. ARM defines the static requirement to be the maximum number of MFIFO entries that a channel is currently using before that channel does one of the following: Executes a WFP or WFE instruction. Claims ownership of the load-lock.

ARM defines the dynamic requirement to be the difference between the static requirement and the maximum number of MFIFO entries that a channel program uses at any time during its execution. To calculate the total MFIFO requirement, add the largest dynamic requirement to the sum of all the static requirements.

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To avoid DMAC lock-up, the total MFIFO requirement of the set of channel programs must be equal to or less than the maximum MFIFO depth. The DMAC maximum MFIFO depth is 1 words, 64 bits each.

9.6 System Functions

9.6.1 Clocks
The controller is clocked by the CPU_1x clock for the APB interface and by the CPU_2x clock on the AXI interface. Programming information for the CPU_1x and CPU_2x clocks is in Chapter 25, Clocks.

Example: Enable Clocks

1. 2. Enable CPU_1x clock for APB. This clock is likely already enabled for the interconnect. Enable CPU_2x clock for AXI. This clock is likely already enabled for the interconnect by writing a 1 to slcr.AER_CLK_CTRL[DMA_CPU_2XCLKACT].

Peripheral Request Interface Clock

The peripheral request interface is clocked by the DMA{3:0}_ACLK signals. All of the interface signals are listed in section 9.7.2 Peripheral Request Interface.

9.6.2 Resets
Controller Reset
The controller is reset using the slcr.DMAC_RST_CLTR[DMAC_RST] register bit. This bit is used in the controller startup example shown in section Example: Start-up Controller.

PL Peripheral Reset
Use a general purpose I/O or other signal to the PL to reset PL peripherals.

9.6.3 Reset Configuration of Controller

Table 9-16 shows the tie-off signals used to program security state of the DMAC. Depending on the state of the SLCR registers after reset, the DMA is configured in secure or non-secure mode. Refer to the ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: Security Usage for more details.

Note: When set, each security state remains constant until the DMAC resets. Note: After reset, the controller waits for software to begin executing, refer to section 9.2.3 DMA
Manager.

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Table 9-16:

DMAC Initialization Signals Type

Input

Name
boot_manager_ns

Source
SLCR register TZ_DMA_NS

Description
Controls the security state of the DMA manager, when the DMAC exits from reset: 0: Assigns DMA manager to the secure state 1: Assigns DMA manager to the non-secure state Controls the security state of an event-interrupt resource, when the DMAC exits from reset: boot_irq_ns[x] is Low: Assigns event<x> or irq[x] to the secure state boot_irq_ns[x] is High: Assigns event<x> or irq[x] to the non-secure state Controls the security state of a peripheral request interface, when the DMAC exits from reset: boot_periph_ns[x] is Low: Assigns peripheral request interface x to the secure state boot_periph_ns[x] is High: Assigns peripheral request interface x to the non-secure state Configures the address location that contains the first instruction that the DMAC executes, when the DMAC exits from reset. Note: The DMAC only uses this address when boot_from_pc is High. Controls the location of where the DMAC executes its initial instruction, after the DMAC exits from reset: 0: DMAC waits for an instruction from either APB interface 1: DMA manager executes the instruction that is located at the address provided by boot_addr[31:0]

boot_irq_ns[15:0]

Input

SLCR register TZ_DMA_IRQ_NS

boot_periph_ns[3:0]

Input

SLCR register TZ_DMA_PERIPH_NS

boot_addr[31:0]

Input

Hard-wired 32'h0

boot_from_pc

Input

Hard-wired 1'b0

9.7 I/O Interface

9.7.1 AXI Master Interface
The AXI bus transaction attributes for caching, burst type and size, protection, etc are programmed by microcode as described in section 9.4.1 Write Microcode to Program CCRx for AXI Transactions.

9.7.2 Peripheral Request Interface

The peripheral request interfaces support the connection of DMA-capable peripherals to enable memory-to-peripheral and peripheral-to-memory DMA transfers to occur, without intervention from a microprocessor. These peripherals must be in the PL and attached to the M_AXI_GP interface. All peripheral request interface signals are synchronous to the respective clocks.

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Table 9-17: Type

Clock

DMAC PL Peripheral Request Interface Signals I/O

I I

Name
DMA{3:0}_ACLK DMA{3:0}_DRVALID

Description
Clock for DMA request transfers Indicates when the peripheral provides valid control information: 0 : No control information is available 1 : DMA{3:0}_DRTYPE[1:0] and DMA{3:0}_DRLAST contain valid information for the DMAC Indicates that the peripheral is sending the last AXI data transaction for the current DMA transfer: 0 : Last data request is not in progress 1 : Last data request is in progress Note: The DMAC only uses this signal when DMA{3:0}_DRTYPE[1:0] is b00 or b01 . Indicates the type of acknowledgement, or request, that the peripheral signals: 00: Single level request 01: Burst level request 10: Acknowledging a flush request that the DMAC requested 11: Reserved Indicates if the DMAC can accept the information that the peripheral provides on DMA{3:0}_DRTYPE[1:0]: 0 : DMAC not ready 1 : DMAC ready Indicates when the DMAC provides valid control information: 0 : No control information is available 1 : DMA{3:0}_DATYPE[1:0] contains valid information for the peripheral Indicates if the peripheral can accept the information that the DMAC provides on DMA{3:0}_DATYPE[1:0]: 0 : Peripheral not ready 1 : Peripheral ready Indicates the type of acknowledgement, or request, that the DMAC signals: 00: DMAC has completed the single AXI transaction 01: DMAC has completed the AXI burst transaction 10: DMAC requesting the peripheral to perform a flush request 11: Reserved

DMA{3:0}_DRLAST

DMA Request

DMA{3:0}_DRTYPE[1:0]

DMA{3:0}_DRREADY

DMA{3:0}_DAVALID

I DMA Acknowledge I

DMA{3:0}_DAREADY

DMA{3:0}_DATYPE[1:0]

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DDR Memory Controller

10.1 Introduction
The DDR memory controller supports DDR2, DDR3, DDR3L, and LPDDR2 devices and consists of three major blocks: an AXI memory port interface (DDRI), a core controller with transaction scheduler (DDRC) and a controller with digital PHY (DDRP). The DDRI block interfaces with four 64-bit synchronous AXI interfaces to serve multiple AXI masters simultaneously. Each AXI interface has its own dedicated transaction FIFO. The DDRC contains two 32-entry content addressable memories (CAMs) to perform DDR data service scheduling to maximize DDR memory efficiency. It also contains fly-by channel for low latency channel to allow access to DDR memory without going through the CAM. The PHY processes read/write requests from the controller and translates them into specific signals within the timing constraints of the target DDR memory. Signals from the controller are used by the PHY to produce internal signals that connect to the pins via the digital PHYs. The DDR pins connect directly to the DDR device(s) via the PCB signal traces. The system accesses the DDR via DDRI via its four 64-bit AXI memory ports. One AXI port is dedicated to the L2-cache for the CPUs and ACP, two ports are dedicated to the AXI_HP interfaces, and the fourth port is shared by all the other masters on the AXI interconnect. The DDR interface (DDRI) arbitrates the requests from the eight ports (four reads and four writes). The arbiter selects a request and passes it to the DDR controller and transaction scheduler (DDRC). The arbitration is based on a combination of how long the request has been waiting, the urgency of the request, and if the request is within the same page as the previous request. The DDRC receives requests from the DDRI through a single interface. Both reads and writes flow through this interface. Read requests include a tag field that is returned with the data from the DDR. The DDR controller PHY (DDRP) drives the DDR transactions.

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10.1.1 Features
DDR Controller System Interface (DDRI)
The DDR controller system interface has these features: Four identical 64-bit AXI ports support INCR and WRAP burst types Four 64-bit AXI interfaces with separate read/write ports and 32-bit addressing Write data byte enable support for each data beat Sophisticated arbitration schemes to prevent data starvation Low latency path using urgent bit to bypass arbitration logic Deep read and write command acceptance capability TrustZone extension with 64 MB resolution Out-of-order read data returned for requests with different master ID Nine-bit AXI ID signals on all ports Burst length support from 1 to 16 data beats Burst sizes of 1, 2, 4, 8 (bytes per beat) Does not support locked accesses from any AXI port Low latency read mechanism using HPR queue Special urgent signaling to each port TrustZone regions programmable on 64 MB boundaries Exclusive accesses for two different IDs per port (locked transactions are not supported, cannot do exclusive access across different ports)

DDR Controller PHY

The DDR controller PHY has these features: Compatible DDR I/Os

1.2V LPDDR2 1.8V DDR2 1.5V DDR3 and 1.35V DDR3L

Selectable 16-bit and 32-bit data bus widths Optional ECC in 16-bit data width configuration Self-refresh entry on software command and automatic exit on command arrival Autonomous DDR power down entry and exit based on programmable idle periods Data read strobe auto-calibration

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DDR Controller Core and Transaction Scheduler

The DDR controller core and transaction scheduler has these features: Efficient transaction scheduling to optimize data bandwidth and latency Advanced re-ordering engine to maximize memory access efficiency for continuous reads and writes as well as random reads and writes Write - read address collision detection to avoid data corruption Obeys AXI ordering rules

10.1.2 Block Diagram

The block diagram for the DDR memory controller is shown in Figure 10-1. The DDR memory controller consists of an arbiter, a core with transaction scheduler, and the physical sequencing of the DDR memory signals.
X-Ref Target - Figure 10-1

CPUs and ACP

64-bit

Other Bus Masters

64-bit

AXI_ HP{2,3}
64-bit

AXI_ HP{1,0}
64-bit

APB
32-bit

S0

S1

S2

S3

DDR Interface

AXI 3 Port Arbiter Seperate Read/Write Requests

Configuration Registers

DDR Core

Transaction Scheduler and Queues Programmable Algorithms

DDR PHY

DDR2, LPDDR2, DDR3

Device Boundary
16 or 32-bit

DDR DRAM Memory Device(s)

UG585_c10_01_032012

Figure 10-1:

DDR Memory Controller Block Diagram

The controller core and transaction scheduler contains two 32-entry CAMs to perform DDR data service re-ordering to maximize DDR memory access efficiency. It also contains a fly-by channel for low latency access to DDR memory without going through the CAM. The PHY processes read/write requests from the controller and translates them into specific signals within the timing constraints of the target DDR memory. Signals from the controller are used by the

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PHY to produce internal signals that connect to the pads of the PS using the PHY. The pads connect directly, via the PCB signal traces, to the external memory devices. The arbiter arbitrates across the four AXI ports for access to the DDR core. The arbitration is priority based and also allows promotion of priorities via an urgent mechanism.

10.1.3 Notices
7z010 CLG225 Device Note
All devices support the 32- and 16-bit data bus width options except the 7z010 CLG225 device. The 7z010 CLG225 supports only the 16-bit data bus width, not the 32-bit bus.

10.1.4 Interconnect
The four AXI_HP interfaces are multiplexed down, in pairs, and are connected to ports 2 and 3 as shown in Figure 10-2. These ports are commonly configured for high bandwidth traffic. The path from these four interfaces to the DDR include two ports on the DDR memory port arbiter. The interconnect switch arbitrates back-and-forth between each of the two ports. Read and write channels operate separately. The arbitration in the bridge can be affected by the QoS signals from each PL interface. A requestor with a higher QoS value is given preferential treatment by the interconnect bridge. Arbitration is priority based using QoS as priority. In the event of a tie, an LRG scheme is used to break the tie. The L2-cache is connected to port 0 and is used to serve the CPUs and the ACP interface to the PL. This port is commonly configured for low-latency. The other masters on the AXI interconnect are connected to port 1.

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X-Ref Target - Figure 10-2

PL

High Performance AXI Controllers (AXI_HP)

M1 M2 M3

M0

FIFO

FIFO

FIFO

FIFO

AXI_HP Path to DDR

S0

S1

S2

S3

AXI_HP to DDR Interconnect

64-bit
M0 M1 M2

From Central Interconnect

From L2 Cache

to OCM
S3 S2 S1 S0

DDR Memory Controller

UG585_c10_02_032012

Figure 10-2:

DDRC System Viewpoint

10.1.5 DDR Memory Types, Densities, and Data Widths

The DDR memory controller is able to connect to devices under the conditions identified in Table 10-1. Table 10-1: Connectivity Limitations Parameter
Maximum Total Memory Density Total Data Width (bits) Component Data Width (bits) Maximum Ranks Maximum Row Address (bits) Maximum Bank Address (bits)

Value
1 GB 16, 32 8, 16, 32 1 15 3

Notes
1 GB of address map is allocated to DRAM ECC can only use a 32-bit configuration: 16 data bits, 10 check bits 4-bit devices are not supported

Table 10-2 provides a collection of example memory configurations.

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Table 10-2:

Example Memory Configurations Component Configuration

x16 x8 x32 x16 x16

Technology
DDR3/DDR3L DDR2 LPDDR2 LPDDR2 LPDDR2

Number of Components
2 4 1 2 1

Component Density
4 Gb 2 Gb 2 Gb 2 Gb 2 Gb

Total Width
32 32 32 32 16

Total Density
1 GB 1 GB 256 MB 512 MB 256 MB

10.1.6 I/O Signals

The DDR signal pins are listed in Table 10-3. The DDR I/O buffers are powered by the VCC_DDR power pins. The I/O state (including initial state) of the DDR signals is controlled via registers: slcr.DDRIOB_ADDR0 slcr.DDRIOB_ADDR1 slcr.DDRIOB_DATA0 slcr.DDRIOB_DATA1 slcr.DDRIOB_DIFF0 slcr.DDRIOB_DIFF1 slcr.DDRIOB_CLOCK

The output characteristics are controlled by the following registers and are reserved to specific values produced by Xilinx tools: slcr.DDRIOB_DRIVE_SLEW_ADDR slcr.DDRIOB_DRIVE_SLEW_DATA slcr.DDRIOB_DRIVE_SLEW_DIFF slcr.DDRIOB_DRIVE_SLEW_CLOCK

The input Vref settings are controlled by slcr.DDRIOB_DDR_CTRL. The DDR DCI settings are controlled by slcr.DDRIOB_DCI_CTRL.

Note: The 7z010 CLG225 device supports only a 16-bit data bus width, not a 32-bit bus width.
Table 10-3: DDR I/O Signal Pin List Connections Device Pin Name
DDR_CK_{P,N} DDR_CKE DDR_CS_B DDR_RAS_B DDR_CAS_B

I/O
O O O O O

DDR3/ DDR2 LPDDR2 DDR3L

X X X X X X X X X X X X X Clock enable Chip select

Description
Differential clock outputs

RAS row address strobe RAS column address strobe

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Table 10-3:

DDR I/O Signal Pin List (Contd) Connections I/O

O O O O O IO O IO ~ ~ X X X X X X X X X X

Device Pin Name

DDR_WE_B DDR_BA[2:0] DDR_A[14:0] DDR_ODT DDR_DRST_B DDR_DQ[31:0] DDR_DM[3:0] DDR_DQS_{P,N}[3:0] DDR_VR{P,N} DDR_VREF{0,1}

DDR2 LPDDR2
X X X X X

DDR3/ DDR3L
X X X X X X X X X X Write enable Bank address

Description

DDR2/DDR3: Row/Column Address LPDDR2: CA[9:0] = DDR_A[9:0] Output dynamic termination signal Reset 32-bit Data bus: [31:0] 16-bit Data bus: [15:0] 16-bit Data with ECC Data byte masks Differential data strobes DCI voltage reference. Used to calibrate input termination. and DDR I/O drive strength. Connect DDR_VRP to a resistor to GND. Connect DDR_VRN to a resister to VCC_DDR. Voltage reference

10.2 AXI Memory Port Interface (DDRI)

10.2.1 Introduction
Each AXI master port has an associated slave port in the arbiter. The command FIFO located inside the port stores the address, length and ID contained in the command. The RAM in the write port stores the write data and byte enable. The RAM in the read port stores the read data coming back from the core. Because the read data coming back from the core can come out of order, the RAM is used for data re-ordering. Each AXI command can make a request (write or read) for up to 16 data transfers (up to the AXI limit). A single command coming from the AXI can be split into multiple requests going to the arbiter logic and the controller. The incoming command is first stored in the command FIFO. After a valid command is detected in the write or read port, the value of the length field is checked and the number of requests associated with this command is calculated. The logic then sends arbiter requests to the arbitration logic. The arbitration logic looks at the requests from all the ports and gives the grant to one port at a time. When a write port receives the grant from the arbiter, it generates write address, and write data pointer and asserts the command valid. A read port on receiving grant generates read address, read command length and the read token and asserts the command valid. Requests from various ports are multiplexed using the grant signal.

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When a write command is accepted by the DDR controller, it sends the write data pointer back to the arbiter. The write data from all ports is multiplexed using the port ID contained in the write data pointer. When the read data comes back from the core, an associated ID is used to direct the data to the appropriate read port. According to AXI specifications, the read data with the same ID is required to be given back to the AXI read master in the same order in which read commands were received by the port.

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10.2.2 Block Diagram

The block diagram of the DDRI is shown in Figure 10-3.
X-Ref Target - Figure 10-3

URGENT PL Signals
PL Fabric

AXI_HP 0, 1
PL Fabric

AXI_HP 2, 3
PL Fabric

Other Masters
(Via Central Interconnect)

CPUs/ACP
(Via L2 Cache)

AXI_HP to DDR Interconnect

Read Request Write Request Read Request Write Request Read Request

Interconnect
Write Request Read Request Write Request

Urgent Read/Write 0 Urgent Read/Write 1 Urgent Read/Write 2 Urgent Read/Write 3 Page Match Read 3 Aging Read 3

Read 3
Urgent R

Write 3
Urgent W

Read 2

Write 2

Read 1

Write 1

Read 0

Write 0

Priority Level

Priority Level

Priority Level

Priority Level

Priority Level

Priority Level

Priority Level

Priority Level

Page Match Write 3 Aging Write 3

DDR Interface

DDR Core

DDR PHY
UG585_c10_03_012113

Figure 10-3:

DDRI Block Diagram

10.2.3 AXI Feature Support and Limitations

This list shows supported and unsupported features for the AXI ports into the DDRI: Fixed burst type is not supported. Note that the behavior is unknown if this transfer type is received at one of the AXI ports. Byte, half-word and word sub-width commands are supported. EXCL accesses are only supported on a single DDR port, ie., there is no support for EXCL accesses across DDR ports. AWPROT/ARPROT[1] bit is used for trust zone support, AWPROT/ARPROT[0], and AWPROT/ARPROT[2] bits are ignored and do not have any effect. ARCACHE[3:0]/AWCACHE[3:0] (cache support) are ignored, and do not have any effect. Sparse AXI write transfers (random strobes asserted/de-asserted for any data beat) are supported. Unaligned transfers are supported.

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10.2.4 TrustZone
The DDR memory can be configured in 64 MB sections. Each section can be configured to be either secure or non-secure. This configuration is provided via a system level control register. A 0 on a particular bit indicates a secure memory region for that particular memory segment. A 1 on a particular bit indicates a non-secure memory region for that particular memory segment.

In the case of a non-secure access to a secure region, a DECERR response is returned back to the master. For writes, the write data is masked out before being sent to the controller which results in no actual writes occurring in the DRAM. On reads, the read data is all zeros on a TZ violation.

10.3 DDR Core and Transaction Scheduler (DDRC)

The DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues and sends the next transaction to the DDR PHY. Between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next.
X-Ref Target - Figure 10-4

DDR PHY DDR Core

Optimization Algorithms DRAM R/W State Open Bank State

DDR Interface
AXI Port Arbiter
Read Arbiter

Pending DDR Transactions

Reads

Transaction Scheduler

Sequencer

Read Request Stage 1

Stage 3

Stage 2

Write Arbiter

Write Request

Writes Self-Coherent and with DDR

DDR DRAM Device(s)

UG585_c10_04_032012

Figure 10-4:

DDRC Block Diagram

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10.3.1 Row/Bank/Column Address Mapping

The DDRC is responsible for mapping byte-addressable physical addresses used by the PS and PL AXI masters to DDR row, bank and column addresses. This address mapping has a limited configurability to allow user optimization. Optimizing the mapping to specific data access patterns can allow increased DDR utilization by reducing page and row change overhead.

Note: Many combinations of address remapping are not available, notably a complete
bank-row-column mapping. The address mapper associates linear request addresses to DRAM addresses by selecting the AXI bit that maps to each and every applicable DRAM address bit. The full available address space is only accessible to the user when no two DRAM address bits are determined by the same AXI address bit. Each DRAM row, bank, and column address bit has an associated register vector to determine its associated AXI source in the DDRC DRAM_addr_map_bank, DRAM_addr_map_row, and DRAM_addr_map_col registers. The associated AXI address bit is determined by adding the internal base of a given register to the programmed value for that register, as described in the following equation: [internal base] + [register value] = [AXI address bit number] For example, from the description for reg_ddrc_addrmap_col_b3, it can be seen that this register determines the mapping for DRAM column bit 4 and its internal base is 3. When the full data bus is in use, DRAM column bit 4 is determined by the following: [internal base] + [register value]. If reg_ddrc_addrmap_col_b3 register is programmed to 2, then the AXI address bit is: 3 + 2 = 5. In other words, the column address bit 4 sent to DRAM is mapped to AXI address bit *_ADDR[5]. All the column bits left-shift one bit in half bus width mode (including ECC). In this case, reg_ddrc_addrmap_col_b2 determines the mapping of DRAM column address bit 4. In the full bus width case, reg_ddrc_addrmap_col_b3 determines DRAM column address 4.

10.4 DDRC Arbitration

The DDRC arbitration consists of three stages (see Figure 10-5): Stage 1 is AXI read/write port arbitration Stage 2 is winner of read and write compete Stage 3 is transaction scheduler

Each of these stages has their own arbitration steps that will be discussed in more detail.

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X-Ref Target - Figure 10-5

Stage 1 Read

Stage 1 Write

Stage 2 Queue to DDR PHY

Stage 3 Transaction Scheduler

UG585_c10_05_032012

Figure 10-5:

DDRC Arbitration

10.4.1 Priority, Aging Counter and Urgent Signals

DDR controller arbitration is based on round robin with aging. The round robin mechanism circularly scans all requesting devices and services all outstanding requests before servicing the same device again. The aging mechanism measures the time each request has been pending and assigns higher priority to requests with longer wait times. Each of the DDRC read and write ports is assigned a 10-bit priority value (see registers axi_priority_wr_port0-3 and axi_priority_rd_port0-3). This value is used as an initial value for an aging counter that counts down. Thus at any instant, a lower aging counter value takes priority over a higher one. In addition, each of the DDRC read and write ports has an urgent input signal. This signal acts as a reset to the aging counter. When urgent is asserted, the aging counter for that port is reset, instantly making this port's priority the highest. The source of the urgent bit is selectable via an SLCR host-programmable register (DDR_URGENT_SEL) to be one of the following: The most-significant bit of the 4-bit QoS signal in the AXI interface for a port (except for memory port 0 used by the CPUs and APU) A programmable SLCR register value (DDR_URGENT) One of the PL signal DDRARB[3:0] bits

While the priority value is static in nature, the urgent bit and QoS signal can be manipulated dynamically.

10.4.2 Page-Match
To improve DDR utilization, the address of each new request is compared with the address of the previous request. The DDRC has a preference for taking new requests that are to the same page as the previous request. The memory port compares the addresses to determine if there is a page match. A port that has been selected by the arbiter continues to get preference (priority 0) as long as there continues to be page hits. They will compete against other ports with a priority of 0.

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The page size is defined by PAGE_MASK (32 bit register that all bits are the mask) and is always address aligned. For proper operation, the software must program the page size in the PAGE_MASK to match the size of the DDR memory. Setting this register to 0 disables the page-match step of the arbitration.

10.4.3 Aging Counter

When a request is pending and not serviced, a decrementing aging counter is enabled. The starting value of this counter is loaded from the 10-bit value in the priority register (axi_priority_<rd/wr>_port<n>, there are 8 registers, one for each ports). The counter reloads when the request is serviced. The value of this counter is used to help indicate the priority of an AXI memory port. The lower the value of this counter, the higher the priority. When the priority reaches 0, the request has the highest priority. For arbitration purposes, only the upper-most 5 bits are used to differentiate priority among ports. This keeps the arbitration mechanism to a manageable size and latency, while still comprehending an approximation of the age-based priority of each port.

10.4.4 Stage 1 AXI Port Arbitration

The eight ports (four read and four write) compete to get the DDRC to accept their request. The arbiter grants a request based on many factors. Read and write requests are treated the same, meaning they go through the same arbitration. Each port maintains a priority level that steadily moves from a preset state to the highest state or 0. This mechanism is important to maintain a minimum bandwidth on a port. Each port also has different ways to signal an urgent situation, either on a per-transaction basis (QoS) or for multiple transactions. The per-transaction urgency can be good for low-latency masters. The priority as shown in Figure 10-6 has the following logic. If there is a port with Priority 0 or 0 in its aging counter (the highest priority), then it wins. If there is no port with 0 priority, the arbitration checks if the port being serviced has a page match. If there is no page match, the lowest value in the aging counter wins. If there is a tie for the lowest value in the aging counter, round robin is used to resolve any ties.

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X-Ref Target - Figure 10-6

Aging Counter 0

Aging Counter 1

Aging Counter 2

Aging Counter 3

Is 0?
F

Winner

Page Match?
F

Winner

Lowest Priority
Tie

Winner

0 3 2 1

Round Robin

Winner

UG585_c10_06_050212

Figure 10-6:

Stage 1 AXI Port Arbitration

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10.4.5 Stage 2 Read Versus Write

The reads and the writes each have a queue in the DDR Core. The entries in these queues then vie for the next level of arbitration, shown in Figure 10-7.
X-Ref Target - Figure 10-7

Read Winner Aging Counter

Write Winner Aging Counter

Same Type Priority 0?

Winner

Other Type Priority 0?

Winner

Stay with Same Type

Winner
UG585_c10_07_032012

Figure 10-7:

Stage 2 Read Versus Write

This stage of arbitration starts with the aging counter as shown in Figure 10-7. If there is a same type of transaction with a priority 0, it wins. For example if a read won the last round of arbitration and there is a read with priority 0, it wins. If there is not a same type of transaction with priority 0, and another type of transaction with a priority 0 is present, it wins. If there is no Priority 0 in the queue then it stays with the same type of transaction. An appropriate credit availability check is done before selecting any request in all the above cases.

10.4.6 High Priority Read Ports

Before going into Stage 3 of the arbitration, a feature of the DDRC, the high priority read, needs to be described. The HPR, or high priority read feature, allows splitting the read data queue (32 words) within the DDRC into two separate queues for low and high priority. Each of the four read ports can be assigned a low or high priority. By default this feature is disabled. When used, a high priority read device is not slowed down by the (potentially slower) read data rate of a low-priority device. In a typical use case, HPR is enabled on port 0 (CPU), thus reducing the CPU average read latency. The split of the read data queue does not have to be two equal parts. Thus giving the CPU a small queue to bypass the larger queue to service reads that need a lower latencies. Figure 10-8 shows where the read queue is split.

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X-Ref Target - Figure 10-8

DDR PHY DDR Core

Optimization Algorithms DRAM R/W State Open Bank State

Transaction Scheduler

Sequencer

DDR Interface
AXI Port Arbiter

Pending DDR Transactions

Reads

Stage 3

Port Priority Select

Read Arbiter

HPR

Read Request Stage 1

LPR

Stage 2

Write Arbiter

Write Request

Writes Self-Coherent and with DDR

DDR DRAM Device(s)

UG585_c10_08_032012

Figure 10-8:

Read Queue

This can be changed by setting the reg_arb_set_hpr_rd_port<n> bit to 1'b1 for AXI ports (this is in the axi_priority_<rd/wr>_port<n> register). The DDRC is configured by default to serve only LPR. The read CAM can service only LPR by default. The total CAM depth is 32 for Read. (However, one slot is always allocated for ECC purposes.) The reg_ddrc_lpr_num_entries register field in the DDRC ctrl_reg1 register specifies the number of entries reserved for LPR. Taking 31 and subtracting the reg_ddrc_lpr_num_entries gives the number of entries reserved for HPR. It is necessary to change the REG_DDRC_LPR_NUM_ENTRIES field if a port is configured as an HPR port to avoid deadlock in the credit mechanism

10.4.7 Stage 3 Transaction State

The transaction state is the last stage of arbitration before the transaction goes to the DDR PHY and the DDR device. The transaction state can be read or write. To change the transaction state there must be no more transactions of that type or there can be a critical transaction of the other type. Figure 10-9 shows the simple state machine for this.

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X-Ref Target - Figure 10-9

Read, No Critical Write

Read Mode

Critical Read OR Read and No Write

Critical Write OR Write and No Read

Write Mode

Write, No Critical Read

UG585_c10_09_032012

Figure 10-9:

Stage 3 Transaction State

The transaction state stays the same until the other type of transaction is critical or there is no more of that type of transaction. The state machine defaults to the read state. Table 10-4 shows how a transaction in the queue can go from a normal state to critical. Table 10-4:
Normal

Transaction Store State Transitions

Critical A transaction has been pending for this transaction store and has not been serviced for a count of *_max_starve_x32 pulses of the 32-cycle timer. *_xact_run_length number of transactions has been serviced from this transaction store. *_min_non_critical number of cycles has passed in this state.

Critical Hard Non-Critical Notes:

Hard Non-Critical Normal

* Can be WR, LPR or HPR. Example is wr_max_starve_x32 which is a field of the WR_Reg.

Taking the low priority read transaction store as an example, it is expected that the transaction store generally functions independently based on the following signals: lpr_max_starve_x32 lpr_xact_run_length lpr_min_non_critical

The reg_arb_go2critical_en field in the DDRC ctrl_reg2 register enables the arbiter to drive co_gs_go2critical_* signals to the DDRC. There are sideband signals on AXI (awurgent and arurgent) that drive the co_gs_go2critical_* signals. If any port asserts their urgent sideband signal, and if this feature is enabled, the arbiter asserts the corresponding co_gs_go2critical_* signal to the controller.

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Inside the controller, assertion of this signal causes the state machine to switch from one state to another. For example, if the DDRC is currently servicing reads and co_gs_go2critical_wr goes High, the controller ignores the normal state switching methods (starvation counter etc), and jumps to servicing writes. There is a register in the controller to control how long to keep servicing the current command type before switching to the other (reg_ddrc_go2critical_hysteresis field in the DDRC ctrl_reg2). In summary, this go2critical feature is used in the controller and ensures fast switching between reads and writes for transactions with super high priority.

Note:
1. The normal programming condition is expected to be reg_ddrc_prefer_Write=0. (this is a bit field in the DRAM_param_reg4 register) This means that the read requests are always serviced immediately when received by an idle controller. Also, it is often desirable to set the reg_ddrc_rdwr_idle_gap (this field is in the ddrc_ctrl register) to a very low number (such as 0, 1, or 2) to ensure that writes do not go un-serviced in an otherwise-idle controller for any length of time, wasting bandwidth. (The trade-off here is that by servicing writes more quickly, the likelihood increases that reads issued to the controller immediately following writes incurs additional latency to allow writes to be serviced and turn the bus around.) Because the ordering is guaranteed on all requests issued to the controller, write latency must not be a concern to system design. (In the event that write data is required by a subsequent read, the controller automatically forces the write data out to DRAM before servicing the read.)

2.

10.4.8 Read Priority Management

Normally in a read mode, high priority read requests are preferred for service over low priority read requests. However, if the low priority read transaction store is critical and the high priority read transaction store is not, then low priority read requests are preferred over high priority read requests. This prevents starvation of low priority reads.

10.4.9 Write Combine

The write combine feature allow multiple writes to the same address to be combined into a single write to DRAM. When a new write collides with a queued write in the CAM: If write combine is enabled, the DDRC overwrites the data for the old write with that from the new write and only performs one write transaction (write combine). If write combine is disabled, the DDRC follows the following sequence of operations:

Holds the new write transaction in a temporary buffer Applies flow control back to the core to prevent more transactions from arriving Flushes the internal queue holding the colliding transaction until that transaction has been serviced Accepts the new transaction and removes flow control

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10.4.10 Credit Mechanism

The DRAM controller employs a credit mechanism to ensure that buffers do not overflow (pending DDR transactions). The interface making the request to the controller can only request commands for which it has been granted credits or open slots in the queues to issue. Credits are tracked separately for the following three command types: High priority reads Low priority reads Writes

Credits are counted for each command type independently according to the following rules: Initially the interface has zero credits. Following the de-assertion of reset to the DRAM controller, credits are issued to the interface for each command type. A given credit count increments every time a credit is issued by the DRAM controller, indicated by the assertion of the appropriate *_credit signal on the rising edge of the clock. When the credit count is greater than zero, the interface can issue requests of that type to the controller. Each time a request is issued to the controller, the associated credit count is decremented.

10.5 Controller PHY (DDRP)

The DDRP processes read and write requests from the DDRC and translates them into specific signals within the timing constraints of the target DDR memory. The DDRP is composed of functional units including PHY control, master DLL, and read/write leveling logic. The PHY data slice block handles the DQ, DM, DQS, DQ_OE and DQS_OE signals. The PHY control block synchronizes all of the control signals with the DDR_x3 clock. There are two kinds of DLLs, the master DLL, and the slave DLL. The DLLs are responsible for creating the precise timing windows required by the DDR memories to read and write data. The master DLL measures the cycle period in terms of a number of taps and passes this number through the ratio logic to the slave DLLs. The slave DLLs can be separated on the target die to minimize skew and delay and to account for process, temperature and voltage variations. Write leveling and read leveling are new functions required for DDR3 operation. These functions help automatically determine delay timings required to align data to the optimal window for reliable data capture: Read leveling and write leveling for DDR3 Support for 16- and 32-bit data bus width with one rank Optional ECC with a 16-bit data width Individual bytes with read data mask bits

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10.6 Initialization and Calibration

To start operation of the PS DRAM interface, the following sequence of operations must take place: 1. 2. 3. 4. 5. 6. 7. DDR clock initialization DDR I/O buffers (DDR IOB) initialization and calibration DDR controller (DDRC) register programming DRAM reset and initialization DRAM input impedance (ODT) calibration DRAM output impedance (Ron) calibration DRAM Training a. c. Write leveling Read data eye training b. Read DQS gate training

This section is intended for reference and debug purposes only. Generally, programming for steps 17 are provided via the appropriate Xilinx design suite, such as EDK XPS. Unless otherwise specified, all DDR3 settings and procedures also apply to DDR3L.

10.6.1 DDR Clock Initialization

Prior to DDR initialization, a DDR clock must be active. Both the ddr_2xclk and ddr_3xclkclocks must be configured properly. The ddr_3x clk is the clock used by the DRAM and should be set to the desired operating frequency (note that the data rate per bit is twice the operating frequency). The ddr_2xclk is used by the interconnect and is typically set to 2/3 of the operating frequency. The DDR PLL frequency should be set to an even multiple of the operating frequency. Table 10-5 provides frequency configuration examples assuming a 50 MHz reference clock. Table 10-5: Operating Frequency
525.00 400.00

Frequency Configuration Examples DDR PLL Frequency

1050.00 1600.00

ddr_3xclk Frequency
525.00 400.00

ddr_2xclk PLL Feedback ddr_3xclk Frequency Divider Divider

350.00 266.67 21 32 2 4

ddr_2xclk Divider
3 6

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Programming the DDR clock involves the DDR_PLL_CTRL and DDR_CLK_CTRL registers in the SLCR. The programming sequence is as follows. 1. 2. 3. 4. 5. 6. 7. Put the PLL in bypass mode Assert the PLL reset Set the PLL feedback divider value Set the ddr_2xclk and ddr_3xclk divisor values Deassert the PLL reset Wait for PLL lock Remove PLL bypass mode

In addition to the main DDR clock, a 10 MHz clock is used by the digitally controlled impedance (DCI) function built into the DDR IOB. This clock is configured via the SLCR DCI_CLK_CTRL register.

10.6.2 DDR IOB Impedance Calibration

The DDR IOBs support calibrated drive strength and termination strength using the DCI digitally controlled impedance mode of the IOB. In DDR2/DDR3 modes this is used to calibrate termination strength. In LPDDDR2 mode this is used to calibrate drive strength. The DCI state machine requires two external pins, VRN and VRP, which are connected to external resistors to VCCO_DDR and ground, respectively. DCI settings are shown in Table 10-6. Table 10-6: DCI Settings Termination Impedance
40 50 None 40

DDR standard
DDR3 DDR2 LPDDR2

Drive Impedance

VRN resistor (to VCCO_DDR)

80 100 40

VRP resistor (to ground)

80 100 40

When enabled, the DCI state machine will automatically match drive and termination impedance to the external resistors. This background calibration takes 1-2 ms to lock and then runs continuously.

Calibration
1. 2. Configure the clock module to configure a 10 MHz clock on dci_clk Enable the DDR DCI calibration system using the SLCR registers DDRIOB_DCI_CTRL and DDRIOB_DCI_STATUS a. c. e. Toggle DDRIOB_DCI_CTRL.RESET_B to 0 and set to 1 Set DDRIOB_DCI_CTRL. UPDATE_CONTROL to 0 Poll on the DDRIOB_DCI_STATUS.DONE bit until it is 1 b. Set DDRIOB_DCI_CTRL.PREF_OPT, and NREF_OPT fields according to Table 10-7 d. Set DDRIOB_DCI_CTRL.ENABLE to 1

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Table 10-7:

Calibration Reset
0 000 00 000 000 00

Field Name
UPDATE_CONTROL PREF_OPT2[2:0] PREF_OPT1[1:0] NREF_OPT4[2:0] NREF_OPT2[2:0] NREF_OPT1[1:0]

Power Down
0 000 00 000 000 00

DCI Enable DCI Enable DDR3 DDR2

0 000 00 001 000 00 0 000 00 001 000 00

DCI Enable LPDDR2

0 000 10 001 000 10

DCI Disabled
1 000 00 000 000 00

10.6.3 DDR IOB Configuration

The DDR IOBs must be configured to function as I/O. Each type of DDR IOB is controlled by two different SLCR configuration registers. The configuration registers configure the IOB's input mode, output mode, DCI mode, and other functions.

Configuration
The DDR system supports DDR3/DDR2/LPDDR2 in 16 and 32 bit modes and power down modes. The registers identified in Table 10-8 control groups of I/Os and must be configured depending on the particular mode. Table 10-8: DDR IOB Configuration Registers Affected I/O Blocks
VREF, VRN, VRP, DRST DCI controller DCI controller DDR_A[14:0], DDR_CKE, DDR_BA[2:0], DDR_ODT, DDR_WE_B, DDR_CAS_B, DDR_RAS_B DDR_CS_B DDR_CK_P, DDR_CK_P DDR_DQ[15:0], DDR_DM[1:0], DDR_FIFO_IN[0], DDR_FIFO_OUT[0] DDR_DQ[31:16], DDR_DM[3:2], DDR_FIFO_IN[1], DDR_FIFO_OUT[1] DDR_DQS_P[1:0], DDR_DQS_N[1:0] DDR_DQS_P[3:2], DDR_DQS_N[3:2] DDR_A[14:0], DDR_CKE, DDR_BA[2:0], DDR_ODT, DDR_WE_B, DDR_CAS_B, DDR_RAS_B, DDR_CS_B DDR_CK_P, DDR_CK_P

Register
DDRIOB_DDR_CTRL DDRIOB_DCI_CTRL DDRIOB_DCI_STATUS DDRIOB_ADDR0 DDRIOB_ADDR1 DDRIOB_CLOCK DDRIOB_DATA0 DDRIOB_DATA1 DDRIOB_DIFF0 DDRIOB_DIFF1 DDRIOB_DRIVE_SLEW _ADDR DDRIOB_DRIVE_SLEW _CLOCK

Description
Controls special I/O modes for internal and external VREF and DCI reference pins VRN and VRP Enables the DCI controller Status for the DCI controller Configuration settings for address and control outputs used by LPDDR2, DDR2 and DDR3 Configuration settings for the differential clock outputs. Controls DDR_CK_P, DDR_CK_P Configuration settings for data and mask bits for lower 16-bits Configuration settings for data and mask bits for upper16-bits Configuration settings for dqs bits for lower 16-bits Configuration settings for dqs bits for upper 16-bits Drive strength and slew rate settings for address and control output Drive strength and slew rate settings for the clock outputs

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Table 10-8:

DDR IOB Configuration Registers (Contd) Affected I/O Blocks

DDR_DQ[31:0], DDR_DM[3:0], DDR_FIFO_IN[1:0], DDR_FIFO_OUT[1:0] DDR_DQS_P[3:0], DDR_DQS_N[3:2]

Register
DDRIOB_DRIVE_SLEW _DATA DDRIOB_DRIVE_SLEW _DIFF

Description
Drive strength and slew rate settings for data I/Os Drive strength and slew rate settings for data strobe I/Os

Set the IOB configuration as follows: 1. 2. 3. 4. Set DCI_TYPE to DCI Drive for all LPDDR2 I/Os. Set DCI_TYPE to DCI Termination for DDR2/DDR3 bidirectional I/Os. Set OUTPUT_EN = obuf to enable outputs. Set TERM_DISABLE_MODE and IBUF_DISABLE_MODE to enable power saving input modes. The TERM_DISABLE_MODE and IBUF_DISABLE_MODE fields should not be set before DDR training has completed. Set INP_TYPE to VREF based differential receiver for SSTL, HSTL for single ended inputs. Set INP_TYPE to Differential input receiver for differential inputs. Set TERM_EN to enabled for DDR3 and DDR2 bidirectional I/Os (Outputs and LPRDDR2 IOs are un terminated). Set DDRIOB_DATA1 and DDRIOB_DIFF1 registers to power down if only 16 bits of DQ DDR are used (including ECC bits). For DDR2 and DDR3 DCI only affects termination strength, so address and clock outputs do not use DCI.

5. 6. 7. 8. 9.

10. For LPDDR2 DCI affects drive strength, so all I/Os use DCI.

VREF Configuration
DDR I/Os use a differential input receiver. One input to this receiver is connected to the data input, and the other is connected to a voltage reference called VREF. For DDR2/3 and LPDDR2 DRAM interfaces, the V REF voltage is set to half of the I/O VCCO voltage. The VREF can be supplied either externally over dedicated VREF pads, or from an internal voltage source. External VREF is recommended for all designs to provide additional timing margin, but requires external board components. To configure the V REF reference supply, set the DDRIOB_DDR_CTRL register as follows: To enable internal V REF

Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 00 (disconnect I/Os from external signal) Set DDRIOB_DDR_CTRL.VREF_SEL to the appropriate voltage setting depending on the DDR standard (V REF=VCCO_DDR/2) Set DDRIOB_DDR_CTRL.VREF_INT_EN to 1 to enable the internal VREF generator Set DDRIOB_DDR_CTRL.VREF_INT_EN to 0 to disable the internal V REF generator Set DDRIOB_DDR_CTRL.VREF_SEL to 0000 Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 11 to connect the IOBs VREF input to the external pad for a 32-bit interface

To enable external V REF

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Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 01 to connect the IOBs VREF input to the external pad for a 16-bit interface

10.6.4 DDR Controller Register Programming

Prior to enabling the DDRC, all DDRC registers must be initialized to system-specific values. About 80 registers with over 350 parameters might be set or left at their power-on default values. The DDRC is then enabled, by writing to the ddrc_ctrl register. Once enabled, the DDRC automatically performs the initialization steps 4-7 (Initialization and Calibration). DDRC operation is autonomous, requiring no further programming unless functionality changes are desired (e.g. changing AXI port priority levels).

10.6.5 DRAM Reset and Initialization

The DDRC performs DRAM reset and initialization per the JEDEC specs, including reset, refresh, and mode registers initialization.

10.6.6 DRAM Input Impedance (ODT) Calibration

DRAM device MR/EMR registers are controlled via the ddrc.DRAM_EMR_MR_reg and ddrc.DRAM_EMR_reg registers. MR/EMR encodings can be found in DRAM device data sheets or JEDEC specifications. The on-die-termination (ODT) is available in DDR2 and DDR3 devices with the following features: In DDR3 devices, the ODT value is controlled via Mode register MR1. It can be disabled, or set to one of the following values: 120 , 60 , or 40 . In DDR2 devices, the ODT value is controlled via the mode register EMR. It can be disabled, or set to one of the following values: 75 , 150 , or 50. Both DDR2 and DDR3 devices have a dedicated ODT input pin that is used to enable the ODT during write operations, and disable it otherwise.

Calibration
DDR3 devices provide ODT calibration via the ZQCL and ZQCS commands. The ZQCL (ZQ calibration long) command is issued as part of the DRAM initialization procedure and is used for initial calibration, which takes about 512 DDR_3x clock cycles. The ZQCS (ZQ calibration short) is subsequently issued automatically by the DDRC for minor calibration adjustments. A typical ZQCS interval is 100 ms. DDR2 (and LPDDR2) devices do not provide ODT calibration.

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10.6.7 DRAM Output Impedance (RON) Calibration

DRAM device MR/EMR registers are controlled via the ddrc.DRAM_EMR_MR_reg and ddrc.DRAM_EMR_reg registers. MR/EMR encodings can be found in DRAM device data sheets or JEDEC specifications. The output impedance control feature is available in DDR2, DDR3 and LPDDR2 devices. In DDR2 devices, the value is controlled via the mode register EMR, and can be set to full strength or reduced strength. In DDR3 devices, the value is controlled via the mode register MR1, and can be set to one of the following values: 40 or 35. In LPDDR2 devices, the value is controlled via MR3, and can be set between 34 and 120 (default value is 40 ).

Calibration
In DDR3 and LPDDR2 devices, the output impedance is calibrated by the same ZQCL/ZQCS commands discussed above. In DDR2 devices, the DDR2 external calibration procedure (OCD for off-chip driver calibration) is not supported by the DDRC.

10.6.8 DRAM Training

DRAM training includes three steps, executed in the following order: 1. 2. 3. Write leveling Read DQS gate training Read data eye training

Not all DRAM types support all three steps, as detailed below. Each step can be enabled or disabled independently. If a training step is enabled, the user must provide an initial delay value as a starting point of the automatic training procedure. The value is a rough estimate of the expected delay or skew (see details below) on the system board, minus some margin. If a training step is disabled, the user must provide a delay value to be used to compensate for the board delay or skew. There are several possible reasons why the user might choose to disable a training step. The step is not supported by the particular DRAM type. For example, write leveling is not supported by DDR2 and LPDDR2. Board delays are well-known and operating conditions are such that timing variance is minimal, and training is not required. Delay settings are known from previous training events.

Training time is on the order of 1-2 ms at a 500 MHz DRAM clock.

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Write Leveling
Goal Desired Nominal Final Ratio Initial Ratio Applies To Adjust WR DQS relative to CLK DQS aligned with clock (0 phase offset) Equal to the DQS to CLK board delay at the DRAM Final value minus 0.5 cycle. If < 0 set to 0. If skew is too small, invert clock. DDR3 only

Write leveling is part of the DDR3 specification. Due to the fly-by topology recommended for DDR3 systems, the clock (CLK) tends to lag relative to write DQS at the DRAM input. In order to align CLK and DQS as required by the DRAM specification, the PHY delays the DQS signal to match the board skew. The write leveling procedure is used to find the required delay. When write leveling is enabled (via MR1), the DRAM asynchronously feeds back CLK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. Write leveling is performed independently for each byte lane. The DDRC supports write leveling as part of the initialization procedure. Optionally, write leveling can be disabled and pre-determined delay values can be programmed via registers (required for DDR2 and LPDDR2 where write leveling is not supported). It should be noted that successful training depends on providing an approximate minimum DQS to CLK delay value. This value should be estimated based on system board layout. This value should be estimated based on system board layout as well as package delay information.

Read DQS Gate Training

Goal Desired Nominal Final Ratio Initial Ratio Applies To Adjust valid RD DQS window. Surround the 4 (BL=8) valid DQS pulses 2 * board delay. Add 0.5 cycle if the clock is inverted Final ratio minus 0.125 cycle (0x20 units), but not < 0. DDR3, LPDDR2

The read DQS gate training is used by the PHY to identify the valid interval of read DQS and capture the read data. It is necessary to align the valid read window to the read data burst and exclude the preamble period and any period during which the DQS signal is tri-stated or driven by the PHY itself. The DDRC supports read DQS gate training as part of the initialization procedure. Optionally, training can be disabled and pre-determined delay values can be programmed via registers (required for DDR2, where read training is not supported). Note that when using LPDDR2, with read gate training, automatic training is not recommended. Instead, the following procedure is recommended (Xilinx tools implement this flow): 1. The even byte lanes are trained and the results are recorded by software.

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2. 3.

The odd byte lanes are trained and the results are recorded by software. The results from 1 and 2 are then applied during DRAM controller initialization, with automatic training disabled.

It should be noted that successful training depends on providing an approximate minimum Zynq to DRAM board delay value. This value should be estimated based on system board layout.

Read Data Eye Training

Goal Desired Nominal Final Ratio Initial Ratio Applies To Adjust RD DQS relative to RD data. DQS edge in the middle of data eye Nominal ideal value is 0.25 cycle since at DRAM output DQ and DQS are aligned None required DDR3, LPDDR2

Enabled by the MPR bit-field in MR3, DDR3 Read data eye training is done to compensate for possible imbalanced loading on the read path. In this mode, the DRAM outputs a stream of 01010101 in a burst length of 8 bits with a regular memory read command. Given the known data pattern, the memory controller adjusts the internal DQS delay so that DQS edges occur in the middle of the data eye. The DDRC supports read data eye training as part of the initialization procedure. Optionally, training can be disabled and pre-determined delay values can be programmed via registers (required for DDR2 where read training is not supported).

10.6.9 Write Data Eye Adjustment

There is no DDRC support for write data eye training, i.e., automatic alignment of write data relative to write DQS (recall that write leveling adjusts write DQS relative to CLK). However, manual alignment is possible. Nominally, write DQS edges should be aligned in the middle of the write data eye at the DRAM inputs. The DDRC PHY provides a user-programmable phase shift value of data relative to DQS. The default nominal value is a 90 degrees phase shift. Given a balanced board design in which the DQ and DQS signals exhibit the same delay and loading, the default value is adequate. Otherwise, the user can provide a different phase shift value. The recommended value based on characterization across PVT is slightly less than 90 degrees, and will be automatically provided by the xilinx tools (PCW, FSBL).

10.6.10 Alternatives to Automatic DRAM Training

If for some reason the automatic training is not successful, alternative calibration schemes can also be used. Training failures can be detected by performing a simple memory write-read-compare test. Since training is done independently for each byte lane, the memory test should check each data byte

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independently. In the event of training failure, two possible solutions are proposed here: a semi-automatic and a manual training method. As the method gets more manual, the training time increases. It is therefore recommended to follow this sequence: 1. 2. 3. Try automatic training, verify board measurement-driven initial values If failed, try semi-automatic training If failed, use manual training

Automatic Training
The standard training procedure is described above. The estimated time for initialization and training is 1-2 ms.

Semi-Automatic Training
This method is useful when system/board delays are known, but PVT timing uncertainty causes the automatic training to fail. Note that only two initial timing parameters are needed to enable successful automatic training: Write DQS to CLK skew The one-way board delay from Zynq to DRAM

These values are known in this case, but the PHY PVT variations modify these values in an additive fashion. Therefore, given a nominal delay value T, the actual value might be in the range (T-delta, T+delta), where delta is the maximum PVT variation. The semi-automatic training method is performed as follows: 1. 2. Divide the range (T-delta, T+delta) into n parts, and thus create (n+1) possible values for each of the two delay parameters. Perform (n+1) 2 automatic training procedures and follow each one with a memory test.

For example, for n=2, the three data points for each parameter are T-delta, T, and T+delta. Perform nine automatic training procedures and observe the results. For n=4, perform 25 tests, etc. As final parameters, pick the values that are in the center of the successful tests region. Note that each data byte lane (aka data slice) has its own independent parameters, and should be tested independently in the memory tests. The estimated time for a training iteration is 1-2 ms plus the duration of the memory test. Assuming a simple 1,000 word read-write test and an average access time of 30 cycles, test duration is on the order of 60,000 cycles or about 0.12 ms at 500 MHz. Thus, a 25-iteration semi-automatic training might last 25-50 ms.

Multi-Set Semi-Automatic Training

Before resorting to manual training, a multi-set semi automatic training method is recommended.

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The DDR PHY contains five adjustable delay elements, four of which are per byte lane (so the actual number of unique adjustable delay elements is 17). Of these five elements, only three are adjusted by the automatic training. These three elements are the write DQS delay, read DQS delay, and read data delay. The remaining two elements are the write data delay, and the control path delay, which take their value from a programmable register, and the value is not adjusted by the automatic training. The automatic training process varies the delay of those three elements over a wide range, and the semi-automatic procedure increases that range. If both automatic and semi-automatic procedures fail, it is highly likely that one or both of the remaining two delay elements require adjustment. Therefore, multiple sets of semi-automatic training procedures can be run, each set using different values of the two remaining delay values. Thus we still take advantage of the efficiency of the automatic training, and reduce the total number of experiments compared to all-manual training.

Manual Training
This method is useful when nothing is known, or if the semi-automatic method has failed. In its simplest form, this method consists of: Disabling the automatic training Performing a manual sweep of all delay parameters over their entire range. For each setting:

Initialize the DDRC with training disabled Perform a memory test

Keeping a scoreboard of results Locating the mid-point of all delay parameters (which might be different for each data lane)

The recommended delay increment value per iteration is 1/32 of a clock cycle, thus requiring 32 iterations to cover a one-cycle delay range per parameter. The estimated time for a manual training iteration is 700 us (500 us are required as part of the DRAM reset/initialization procedure for DDR3) plus the duration of the memory test, or about 0.8 ms. Simplifying assumptions can be used to reduce the search range, but even then the number of iterations might be on the order of 1,000, bringing the manual training time to about one second. Table 10-9 provides summary of register values involved in manual training. All values are in units of 1/256 of a clock cycles (256 units = 1 clock cycle, 8 units = 1/32 of a clock cycle). Table 10-9: Manual Training Register Summary Parameter
1 2 3 4 Write DQS delay/write leveling Write data delay/write data eye adjustment Read DQS gate delay/read DQS gate training Read data to DQS delay/read data eye training

Register
reg_phy_wr_dqs_slave_ratio[9:0] reg_phy_wr_data_slave_ratio[9:0] reg_phy_fifo_we_slave_ratio[10:0] reg_phy_rd_dqs_slave_ratio[9:0]

Nominal Value
DQS to DCLK delay DQS to DCLK delay + 64 2 * board delay 53, placing the DQS edges in the middle of the data eye

Minimum Suggested Search Range

0 -256 64-320 0-512 0 - 104(1)

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Table 10-9:

Manual Training Register Summary Parameter Register

reg_phy_ctrl_slave_ratio[9:0]

Nominal Value
128 (64 for LPDDR2)

Minimum Suggested Search Range

64-192 (32-96 for LPDDR2)

Control

Notes:
1. Parameter 4 is an offset value relative to parameter 3.

10.6.11 DRAM Write Latency Restriction

Note that the minimum DRAM write latency supported is 3. This implies that the minimum CAS latency is 4.

10.7 Register Overviews

In general, the DDRC registers are static and can only be changed while the DDRC is in reset. However, there is a set of registers labeled as dynamic in their description that can be modified at anytime.

10.7.1 DDRI
Table 10-10 shows an overview of DDRI registers. There are no dynamic bit fields in the DDRI registers. Table 10-10: Function
Arbitration PAGE_MASK AXI_PRIORITY_{WR,RD}_PORT{0:3} Misc AXI_ID

DDRI Registers Overview Hardware Register Name

10.7.2 DDRC
Table 10-11 shows an overview of DDRC registers.

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Table 10-11: Function

Status

DDRI Registers Overview Hardware Register Name

MODE_STS_REG

Dynamic Bit Fields

~

Transaction Scheduler

HPR_REG HPR_REG LPR_REG WR_REG ~ ~ ~

DDR Protocol DRAM_PARAM_REG0 DRAM_PARAM_REG1 DRAM_PARAM_REG2 DRAM_PARAM_REG3 DRAM_PARAM_REG4 DRAM_ODT_REG ODT_DELAY_HOLD CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 MODE_REG_READ LPDDR_CTRL{0:3} DFI_TIMING DDR Refresh CHE_REFRESH_TIMER01 CHE_T_ZQ CHE_T_ZQ_SHORT_INTERVAL DDR Init DRAM_INIT_PARAM DRAM_EMR_REG DRAM_EMR_MR_REG DRAM_BURST8_RDWR DRAM_DISABLE_DQ Address Mapping [1]: dis_dq ~ [16]: dis_auto_refresh ~ [13:6]: t_rfc_min ~ ~ [20:16]: refresh_to_x32 ~ ~ ~ [12]: selfref_en [8]: refresh_update_level ~ ~ ~ ~

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Table 10-11: Function

Power Reduction

DDRI Registers Overview (Contd) Hardware Register Name

DRAM_ADDR_MAP_{BANK,COL,ROW}

Dynamic Bit Fields

DEEP_PWRDWN_REG ECC CHE_ECC_CONTROL CHE_{CORR,UNCORR}_ECC: _LOG _ADDR _DATA_31_0 _DATA_63_32 _ECC_DATA_71_64 CHE_ECC_STATS ECC_SCRUB CHE_ECC_CORR_BIT_MASK: _31_0 _63_32

[0]: deeppowerdown_en ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

10.7.3 DDRP
Table 10-12 shows an overview of DDRP registers. Table 10-12: Function
DDR Control DDRC_CTRL TWO_RANK_CFG PHY_CONFIG{0:3} PHY_CMD_TIMEOUT_RDDATA_CPT Training PHY_{WR,RD,GATE}_LVL_FSM PHY_INIT_RATIO{0:3} REG_{64,65} REG_{2C,2D} REG69_6C{0:3} REG6E_71{0:3} ~ ~ ~ ~ ~ ~ [ ]: soft_rstb [ ]: powerdown_en [ ]: t_rfc_nom_x32 ~ ~

DDRP Registers Overview Hardware Register Name Dynamic Bit Fields

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Table 10-12: Function

DLL

DDRP Registers Overview (Contd) Hardware Register Name

DLL_CALIB PHY_CTRL_STS PHY_CTRL_STS_REG2 PHY_DLL_STS{0:3} DLL_LOCK_STS WR_DATA_SLV{0:3} PHY_{RD,WR}_DQS_CFG{0:3} PHY_WE_CFG{0:3}

Dynamic Bit Fields

~ ~ ~ ~ ~ ~ ~ ~ ~ ~

Others PHY_RCVR_ENABLE PHY_DBG_REG

10.8 Error Correction Code (ECC)

There is optional ECC support in half-bus width (16-bit) data width configuration only. Externally 26 bits of a DRAM DDR device are required, 16-bits for data and 10 bits for ECC. Each data byte uses an independent 5-bit ECC field. This mode provides single error correction and dual error detection. The ECC bits are interlaced with the data bits and unused bits as shown in Table 10-13. Table 10-13: DRAM DQ pin
DQ[7:0] DQ[15:8] DQ[20:16] DQ[23:21] DQ[28:24] DQ[31:29]

ECC Data Bit Assignments Number of Pins

8 8 5 3 5 3 First Data Byte Second Data Byte ECC bits associated with first Data Byte 3'b000 ECC bits associated with second Data Byte 3'b000

Function

10.8.1 ECC Initialization

ECC is supported in 16-bit bus mode only. When enabled, a write operation computes and stores an ECC code along with the data, and a read operation reads and checks the data against the stored ECC code. It is therefore possible to receive ECC errors when reading uninitialized memory locations. To avoid this problem, all memory locations must be written before being read. Note that, since ECC is computed and checked over a byte resolution, a read of 1 byte is done to a 16-bit location that has

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only that byte initialized (second byte of 16-bit location is uninitialized) does not result in an ECC error. The controller only checks ECC on the byte that has been read. Note that while only two data byte lanes are used for actual data, all four lanes are used in ECC mode, and therefore DDR training must be performed on all lanes.

10.8.2 ECC Error Behavior

For correctable ECC errors, there is no error actively signaled via an interrupt or AXI response. For uncorrectable ECC errors, the controller returns a SLVERR response back to the re-questing AXI bus master. In both cases, information regarding the error (such as column, row and bank error address, error byte lane, etc.) is logged in the controller register space. When the controller detects a correctable ECC error, it does the following: Sends the corrected data to the core as part of the read data. Sends the ECC error information to the register interface for logging. Performs a RMW operation to correct the data present in the DRAM (only if ECC scrubbing is enabled (reg_ddrc_dis_scrub = 0 ). This RMW operation is invisible to the core. Only one scrub RMW command can be outstanding in the controller at any time. No scrub is performed on single-bit ECC errors that occur while the controller is processing another scrub RMW.

When the controller detects an uncorrectable error, it does the following: Sends the uncorrectable data with an error response to the core. This results in an AXI SLVERR response on the AXI interface along with the corrupted data. Sends the ECC error information to the register module for logging.

10.8.3 Data Mask During ECC Mode

ECC is calculated over a byte of data and hence any data byte can be masked if necessary with ECC enabled. This alleviates the need for the controller to perform a RMW operation when byte masking occurs.

10.8.4 ECC Programming Model

The following details the ECC programming requirements. Note that these configurations are in addition to the regular DDR initialization programming. Also note that initialization of the whole DDR space before reading any data from it is recommended, to prevent ECC error generation as a result of accessing uninitialized areas of memory. Refer to section 10.8.1 ECC Initialization section for further details.

Enabling ECC operation (Switching from Non-ECC Mode to ECC Mode)

1. 2. Program reg_ddrc_soft_rstb to 0 (resets the controller) Program the ECC mode by programming reg_ddrc_ecc_mode to 3'b100

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3. 4. 5.

Program reg_ddrc_dis_scrub to 1'b0 Program reg_ddrc_data_bus_width to 2'b0 Program reg_ddrc_soft_rstb to 1 (takes the controller out of reset)

Note that re-initialization of the whole DDR space before reading any data from it is recommended to prevent ECC error generation as a result of accessing uninitialized areas of memory.

Disabling the ECC Operation (Switching from ECC Mode to Non-ECC Mode)
1. 2. 3. 4. 5. Program the reg_ddrc_soft_rstb to 0 (resets the controller) Program the ECC mode by programming the reg_ddrc_ecc_mode to 3'b000 Program the reg_ddrc_dis_scrub to 1'b1 Program the reg_ddrc_data_bus_width to 2'b00 Program the reg_ddrc_soft_rstb to 1 (takes the controller out of reset)

Monitoring ECC Status

1. 2. 3. 4. 5. CHE_CORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC error correction CHE_UNCORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC unrecoverable error B[0] of CHE_CORR_ECC_LOG_REG_OFFSET indicates correctable ECC status B[0] of CHE_UNCORR_ECC_LOG_REG_OFFSET indicates uncorrectable ECC status CHE_ECC_STATS_REG_OFFSET

B[7:0] -> gives the number of uncorrectable errors B[15:8] -> gives the number of correctable errors

10.9 Programming Model

10.9.1 Operating Modes
The operating mode register bits, mode_sts_reg.ddrc_reg_operating_mode, can be polled to determine the current mode of operation of the controller. The different modes are: 000 uninitialized. The controller might be in soft reset, or it might be out of soft reset, but DRAM initialization sequence has not yet completed. 001 normal operating mode. The controller is ready to accept read and write requests and the controller can issue reads and writes to DRAM. 010 DRAM is in power down mode. 011 DRAM is in self refresh mode. 100 : 111 For LPDDR2 designs only, indicates DRAM is in deep power down.

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10.9.2 Changing Clock Frequencies

The process of changing clock frequencies is as follows: 1. 2. 3. 4. Request the controller to place the DRAM into self refresh mode, by asserting ctrl_reg1.reg_ddrc_selfref_en. Wait until mode_sts_reg.ddrc_reg_operating_mode[1:0]== 11 indicating that the controller is in self refresh mode. Change the clock frequency to the controller (see 10.6.1 DDR Clock Initialization). Update any registers which might be required to change for the new frequency. This includes static and dynamic registers. If the updated registers involve any of reg_ddrc_mr, reg_ddrc_emr, reg_ddrc_emr2 or reg_ddrc_emr3, then go to step 5. Otherwise go to step 6. Assert reg_ddrc_soft_rstb to reset the controller. When the controller is taken out of reset, it re-initializes the DRAM. During initialization, the mode register values updated in step 4 are written to DRAM. Anytime after de-asserting reset, go to step 6. Take the controller out of self refresh by de-asserting reg_ddrc_selfref_en.

5.

6.

Note: This sequence can be followed in general for changing DDRC settings, in addition to just clock
frequencies.

Note: DRAM content preservation is not guaranteed when the controller is reset.

10.9.3 Power Down

Enable power down mode in the Master Control register, ddrc_ctrl. Once enabled, the DDRC automatically puts the DRAM into pre-charge all power down after the programmed number of idle cycles (DDRC_param_reg1.reg_ddrc_powerdown_to_x32). A refresh request brings the DRAM out of power down. It goes back into power down after the idle period. Any transaction brings the DRAM out of power down automatically. Clearing the power down enable bit also brings the DRAM out of power down.

10.9.4 Deep Power Down

Note: Deep power down only applies to LPDDR2 mode.
Set deep_pwrdwn_reg.deeppowerdown_en= 1 . The DDRC puts the DRAM into deep power down as soon as the transaction buffers are empty. If transactions keep arriving the DDRC never puts the DRAM into deep power down. deep_pwrdwn_reg.deeppowerdown_en must be reset to 0 to take DRAM out of deep power down mode. During deep power down exit, the controller performs automatic DRAM initialization. In LPDDR2, once deep_pwrdwn_reg.deeppowerdown_en is reset to 0 , there is a wait period (determined by register reg_ddrc_deeppowerdown_to_x1024) before the DRAM comes out of deep power down. The value from the spec for this register is 500 us.

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Note that any command that comes in while the DRAM is in deep power down mode is stored in the CAM and is processed after deep power down exit and DRAM re-initialization.

10.9.5 Self Refresh

Set the Self Refresh Request bit in the Master Control register, ddrc_ctrl. The DDRC puts the DRAM into self refresh as soon as the transaction buffers are empty. Software must ensure that no transactions arrive. If transactions keep arriving the DDRC never puts the DRAM into self refresh. The first valid transaction brings the DRAM out of self refresh.

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Static Memory Controller

11.1 Introduction
The static memory controller (SMC) can be used either as a NAND flash controller or a parallel port memory controller supporting the following memory types: NAND flash Asynchronous SRAM NOR flash

System bus masters can access the SMC controller as shown in Figure 11-1. The operational registers of the SMC are configured through an APB interface. The memory mapping for the SMC is described in Chapter 4, System Addresses. The SMC handles all commands, addresses, data, and the memory device protocols. It allows the users to access the controller by reading or writing into the operational registers. The SMC is based on ARM's PL353 static memory controller.
X-Ref Target - Figure 11-1

IRQ ID# 50 Interconnect

AXI Slave port

MIO SMC Controller

MIO Pins NAND Flash Or SRAM Or NOR

SMC_Ref clock SMC_Ref reset

CPU_1x clock SMC CPU_1x reset

Device Boundary

Interconnect

APB

Slave port

Control and Status Registers

UG585_c11_01_031812

Figure 11-1:

SMC System Level Diagram

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11.1.1 Features
Features of the SMC are listed for each type of memory. The controller is configured to operate in one of two interface modes.

NAND Flash Interface

ONFI Specification 1.0 Up to a 1 GB device 8/16-bit IO width with a single chip select 16-word read and 16-word write data FIFOs 8-word command FIFO Programmable IO cycle timing 1-bit ECC hardware with software assist Asynchronous memory operating mode

Parallel (SRAM/NOR) Interface

8-bit data bus width One chip select with up to 26 address signals (64 MB) Two chip selects with up to 25 address (32 + 32 MB) 16-word read and 16-word write data FIFOs 8-word command FIFO Programmable I/O cycle timing on a per chip select basis Asynchronous memory operating mode

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11.1.2 Block Diagram

The block diagram for the SMC is shown in Figure 11-2.
X-Ref Target - Figure 11-2

SMC
NAND Flash Controller IRQ ID# 50
Read Data Slave port Write Data Read Data FIFO Write Data FIFO Command FIFO ECC Memory Interface Controller

Interconnect AXI

Format

SRAM/NOR Controller
Slave port

IO Buffer Control

MIO to the Memory Device

Interconnect APB

Memory Manager

Command FIFO Write Data FIFO

Memory Interface Controller

Control and Status Registers

Read Data FIFO

UG585_c11_02_031812

Figure 11-2:

SMC Block Diagram

Interconnect Interfaces
For the NOR/SRAM controller mode, the AXI interface is memory mapped so software can read and write to/from memory. For the NAND flash controller mode, software writes commands to the NAND controller via the AXI interface. Details can be found in the ARM specification. The APB bus interface provides a memory mapped area for the software to read and write the control and status registers.

Memory Manager
The memory manager tracks and controls the current state of the CPU_1x clock domain state machine. This block is responsible for updating register values that are used in the memory clock domain and controlling direct commands issued to memory and controlling entry-to and exit-from low-power mode through the APB interface.

Format
The format block arbitrates between memory accesses from the AXI slave interface and the memory manager. Requests from the manager have the highest priority. Requests from AR and AW channels are arbitrated on a round-robin basis. The format block also maps AXI transfers onto appropriate memory transfers and passes these to the memory interface through the command FIFO.

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11.1.3 Notices
7z010 CLG225 Device
The 7z010 CLG225 device does not support the NOR/SRAM interface. The NAND interface is supported in the 8-bit interface, but not the 16-bit interface.

11.2 Functional Operation

The functional operation of the SMC is described in the ARM Static Memory Controller (PL350 series) Technical Reference Manual. Additional information is provided in the following sections.

11.2.1 Boot Device

The NOR and NAND Flash controllers can be configured as a boot device. Its memory interface can only be routed through the MIO.

11.2.2 Clocks
The SMC has two clock domains that are driven by the CPU_1x and SMC_Ref clocks, see Table 11-1. These clocks are controlled by the clock generator, refer to Chapter 25, Clocks. The two clock domains are asynchronous to each other. The main benefit of asynchronous clocking is to maximize the memory performance while running the interconnect interface at a fixed system frequency. Table 11-1: Clock
CPU_1x SMC_Ref

SMC Clocks and Resets Resets

CPU_1x SMC_Ref

Clock Domain
Interconnect domain SMC domain

Description
This clock runs at 1/6th or 1/4th the CPU clock rate depending on the CPU clock mode. To stop this clock, first put the SMC is in low-power mode. This clock is used to control the I/O memory interfaces.

11.2.3 Resets
The controller has two reset inputs that are controlled by the reset subsystem; refer to Chapter 26, Reset System. This SMC CPU_1x reset is used for the AXI and APB interfaces. The SMC_Ref reset is for the FIFOs and the rest of the controller including the control and status registers.

11.2.4 Interrupts
A single interrupt is generated by the controller, IRQ ID # 50. The interrupt is triggered on the rising edge of the busy input for the NAND memory interface. The SRAM/NOR interface does not generate an interrupt. The cause of the SMC reset is determined by reading the relevant status registers.

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11.2.5 PL353 Functionality

The SMC is based on ARM's PL353 Primecell core and is hard-coded such that controller 0 can operate in SRAM/NOR mode and controller 1 can operate in NAND flash mode. The SRAM/NOR or NAND interface can be used in a system, but not both. The SRAM/NOR interface does not support PSRAM. The NAND flash controller does not support wear leveling. When referencing ARM documentation, for programming and other purposes, refer to the implementation notes in Table 11-2. Table 11-2: SMC PL353 Implementation Notes Value
2 1 16 8 32 ~ 8 16 16 Yes Yes

Parameter
Chip Selects (Interface 0) Chip Select (Interface 1) NAND flash mode data width SRAM mode data width System interface bus width System interface clock rate Command FIFO depth Read data word FIFO depth Write data word FIFO depth ECC support ECC Extra Block

Design Notes
SRAM/NOR interface chip selects operate independently. NAND flash interface chip select Data width can be 8 or 16 bits Data width is 8 bits. AXI CPU_1x (1/6th or 1/4th the CPU clock frequency) Maximum supported depth on both interfaces Maximum supported depth on both interfaces Maximum supported depth on both interfaces 1-bit ECC hardware with assistance from software Supported

11.2.6 Address Map

The registers and memory base address are listed in Table 11-3. Table 11-3: SMC Address Map Summary Mnemonic
SMC SMC_NAND SMC_SRAM0 SMC_SRAM1

Base Address
0xE000_E000 0xE100_0000 0xE200_0000 0xE400_0000

Description
Configuration registers base address SMC NAND memory base address SMC SRAM Chip Select 0 base address SMC SRAM Chip Select 1 base address

Type
Registers Memory Memory Memory

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11.3 I/O Signals

The MIO pin assignments for SRAM/NOR and NAND flash connections are shown in Table 11-4. The SMC interface signals are routed only to the MIO pins, they are not available on the EMIO interface. The MIO pins and restrictions (no NOR/SRAM and only 8-bit NAND) are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 11-4: MIO Pin SMC MIO Pins SRAM/NOR Interface Mode Signal Name I/O Default Value
0 0 0 0 0 0 0 0 -

Description

MIO Pin

NAND Flash Interface Mode Signal Name I/O Default Value

0 0 0 0 0 0 0 0 0 -

Description

MIO Voltage Bank 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SRAM_CE_B[0] SRAM_CE_B[1] or SRAM_A [25] SRAM_DQ[0] SRAM_DQ[1] SRAM_DQ[2] SRAM_DQ[3] SRAM_OE_B SRAM_BLS_B SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[4] SRAM_DQ[5] SRAM_A[0] O O IO IO IO IO O O IO IO IO IO O SRAM/NOR chip sel 0 SRAM/NOR chip sel 1 or Address bit 25 SRAM/NOR data SRAM/NOR data SRAM/NOR data SRAM/NOR data SRAM/NOR output en SRAM/NOR write en SRAM/NOR data SRAM/NOR data SRAM/NOR data SRAM/NOR data SRAM/NOR address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAND_CE_B NAND_ALE NAND_WE_B NAND_IO[2] NAND_IO[0] NAND_IO[1] NAND_CLE NAND_RE_B NAND_IO[4] NAND_IO[5] NAND_IO[6] NAND_IO[7] NAND_IO[3] NAND_BUSY O O O IO IO IO O O IO IO IO IO IO I NAND chip select NAND address latch NAND write enable NAND data/address/cmd NAND data/address/cmd NAND data/address/cmd NAND chip select NAND read enable NAND data/address/cmd NAND data/address/cmd NAND data/address/cmd NAND data/address/cmd NAND data/address/cmd NAND busy -

MIO Voltage Bank 1

23:16 SRAM_A [8:1] 39:24 SRAM_A [24:9] O O SRAM/NOR address SRAM/NOR address 23:16 NAND_IO [15:8] 39:24 IO 0 NAND data/address/cmd -

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Optional Pins
For either SRAM or NOR, the upper address bits are optional. When not used, they can be assigned to other functions.

11.4 Wiring Diagrams

The SMC supports the configurations shown in Figure 11-3, Figure 11-4, and Figure 11-5. The NOR/SRAM mode of the SMC can support two devices (NOR and/or SRAM) using chip selects 0 and 1.
X-Ref Target - Figure 11-3

NOR Device
SRAM_CE_B0 SRAM_CE_B1 SRAM_OE_B MIO Multiplexer SMC Controller SRAM_BLS_B NOR or SRAM Device CEn

OEn WEn

SRAM_A[25:0] SRAM_DQ[7:0]

A[25:0] (upper bits are optional and A[25] is available only if CE1 is not used) DQ[7:0]

Zynq Device Boundary

System Reset#

RESETn

UG585_c11_03_020513

Figure 11-3:
X-Ref Target - Figure 11-4

NOR Device Wiring Diagram

SRAM Device

SRAM_CE_B0 SRAM_CE_B1 SRAM_OE_B MIO Multiplexer SMC Controller SRAM_BLS_B NOR or SRAM Device

CEn

OEn WEn

SRAM_A[25:0] SRAM_DQ[7:0]

A[25:0] (upper bits are optional and A[25] is available only if CE1 is not used) DQ[7:0]

Zynq Device Boundary

System Reset#

RESETn

UG585_c11_04_020513

Figure 11-4:

SRAM Device Wiring Diagram

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X-Ref Target - Figure 11-5

NAND Flash
NAND_CE_B0 NAND_CLE NAND_ALE MIO Multiplexer NAND_RE_B NAND_WE_B NAND_BUSY NAND_IO[7:0] NAND_IO[15:0] (for 16-bit data) GPIO Zynq Device Boundary System Reset# CEn CLE ALE RE# WE# R/B# IO[7:0] IO[15:8] WPn RESETn

SMC Controller

UG585_c11_05_020613

Figure 11-5:

NAND Flash Device Wiring Diagram

11.5 Register Overview

The SMC registers are summarized in Table 11-5. Table 11-5:
Controller

SMC Register Overview

Register Name
MEMC STATUS MEMIF_CFG MEMC_CFG_{SET, CLR}

Description
Operating and interrupt status, read-only SMC configuration information, read-only Enable/disable/clear interrupts and control low power state Issue a set command, write-only Stage a cycles or opmode operation to the SRAM/NOR and NAND flash registers Insert idle cycles between SRAM/NOR burst cycles Timing cycles Operating mode Timing cycles Operating mode ECC status and configuration Commands used for ECC reads and writes Address generated by controller Value generated by controller

Both

DIRECT_CMD SET_{CYCLES, OPMODE} USER_{STATUS, CONFIG}

SRAM/NOR CS 0, 1

REFRESH_PERIOD_{0,1} SRAM_CYCLES0_{0,1} OPMODE0_{0,1} NAND_CYCLES1_0 OPMODE1_0 ECC_{STATUS, MEMCFG}_1 ECC_MEMCOMMAND{2:1}_1 ECC_ADDR{1:0}_1 ECC_VALUE{3:0}_1

NAND Flash

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11.6 Programming Model

The programming model is described in the ARM Static Memory Controller (PL350 series) Technical Reference Manual (see Appendix A, Additional Resources). The configuration of the SMC is summarized in Table 11-2.

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Quad-SPI Flash Controller

12.1 Introduction
The Quad-SPI flash controller is part of the input/output peripherals (IOP) located within the PS. It is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. In I/O mode, software interacts closely with the flash device protocol. The software writes the flash commands and data to the controller using the four TXD registers. Software reads the RXD register that contains the data received from the flash device. Linear addressing mode uses a subset of device operations to eliminate the software overhead that the I/O mode requires to read the flash memory. Linear Mode engages hardware to issue commands to the flash memory and control the flow of data from the flash memory bus to the AXI interface. The controller responds to memory requests on the AXI interface as if the flash memory were a ROM memory. In legacy mode, QSPI controller acts as a normal SPI controller. The controller can interface to one or two flash devices. Two devices can be connected in parallel for 8-bit performance, or in a stacked, 4-bit arrangement to minimize pin count. The two device combinations are shown in Figure 12-1.

12.1.1 Features
32-bit AXI interface for Linear Addressing mode transfers 32-bit APB interface for I/O mode transfers Programmable bus protocol for flash memories from Micron and Spansion Legacy SPI and scalable performance: 1x, 2x, 4x, 8x I/O widths Flexible I/O

Single SS 4-bit I/O flash interface mode Dual SS 8-bit parallel I/O flash interface mode Dual SS 4-bit stacked I/O flash interface mode Single SS, legacy SPI interface

16 MB addressing per device (32 MB for two devices) Device densities up to 128 Mb

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I/O mode (flash commands and data)

Software issues instructions and manages flash operations Interrupts for FIFO control 63-word RxFIFO, 63-word TxFIFO Memory reads and writes are interpreted by the controller AXI port buffers up to four read requests AXI incrementing and wrapping address functions

Linear addressing mode (executable read accesses)

12.1.2 System Viewpoint

The Quad-SPI flash controller is part of the IOP and connects to external SPI flash memory through the MIO as shown in Figure 12-1. The controller supports one or two memories.
X-Ref Target - Figure 12-1

Single SS 4-bit I/O

QSPI 0 SS

Quad-SPI Device
OR

4-bit I/O

IRQ ID# 51

Dual SS 8-bit Parallel I/O

Interconnect
Quad-SPI Ref Clock Quad-SPI Ref Reset

AXI

Slave Port

Quad-SPI Controller

MIO

QSPI 0 SS

MIO Pins
QSPI 1 SS

Quad-SPI Device Quad-SPI Device

OR

8-bit I/O

Interconnect
CPU 1x Clock

APB

Slave Port

Dual SS 4-bit Stacked I/O

Quad-SPI CPU 1x Reset

Control and Status Registers Device Boundary

QSPI 0 SS

Quad-SPI Device Quad-SPI Device

4-bit I/O

QSPI 1 SS

UG585_c12_01_101912

Figure 12-1:

Quad-SPI Controller System Viewpoint

Address Map and Device Matching for Linear Address Mode

When a single device is used, the address map for direct memory reads starts at FC00_0000 and goes to a maximum of FCFF_FFFF (16 MB). The address map for a two-device system depends on the memory devices and the I/O configuration. In two-device systems, the Quad-SPI devices need to be from the same vendor so they have the same protocol. The 8-bit parallel I/O configuration also requires that the devices have the same capacity. The address map for the parallel I/O configuration starts at FC00_0000 and goes to the address of the combined memory capacities, up to a maximum of FDFF_FFFF (32 MB).

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For the 4-bit Stacked I/O configuration, the devices can have difference capacities, but must have the same protocol. If using two different size devices, Xilinx recommends using a 128 Mb device at the lower address. In this mode, the QSPI 0 device starts at FC00_0000 and goes to a maximum of FCFF_FFFF (16 MB). The QSPI 1 device starts at FD00_0000 and goes to a maximum of FDFF_FFFF (another 16 MB). If the first device is less than 16 MB in size, then there will be a memory space hole between the two devices.

12.1.3 Block Diagram

The block diagram of the is shown in Figure 12-2.
X-Ref Target - Figure 12-2

Linear Addressing Mode Command FIFO AXI Interface SPI-to-AXI Data Formatter
AXI-to-SPI

Command Converter

I/O Mode

Mux

Tx FIFO

Serializer

APB Interface

Control MIO Rx FIFO Config, Control, and Status Registers De serializer

Loopback Clock Control

UG585_c12_02_101912

Figure 12-2:

Quad-SPI Controller Block Diagram

12.1.4 Notices
Operating Restrictions
When a single device is used, it must be connected to QSPI 0. When two devices are used, both devices must be identical (same vendor and same protocol sequencing). The MIO pins for the Quad-SPI controller conflict with both the NOR and NAND interfaces of the SMC controller. The NOR/SRAM and NAND interfaces cannot be used when Quad-SPI is used. More information about the MIO pins is provided in section 2.5 PS-PL MIO-EMIO Signals and Interfaces.

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12.2 Functional Description

The Quad-SPI flash controller can operate in either I/O mode or linear addressing mode. For reads, the controller supports single, dual and quad read modes in both I/O and linear addressing modes. For writes, single and quad modes are supported in I/O mode. Writes are not supported in linear addressing mode.

12.2.1 Operational Modes

Quad-SPI operating mode transitions are shown in Figure 12-3.
X-Ref Target - Figure 12-3

Software Reset:
slcr.QSPI_RST_CTRL[QSPIx_REF_RST, LQSPIx_CPU1x_RST]

Quad-SPI

Boot Mode

Reset

Software Reset

Linear Addressing Mode

I/O Mode

UG585_c12_10_072612

Figure 12-3:

Quad-SPI Operating Mode Transitions

In I/O mode, software can choose varying degrees of control over different aspects of read data management by setting appropriate register bits. In linear mode, the controller carries out all necessary read data management and the memory reads like a ROM to software.

12.2.2 I/O Mode

In I/O mode, the software is responsible for preparing and formatting commands and data into instructions according to the Quad-SPI protocol. The formatted instruction sequence, consisting of CMD and data, is then pushed into a transmit FIFO by repeated writing into a TXD register. The transmit logic serializes the content of the TxFIFO in accordance with the Quad-SPI interface specification and send the data out to the flash memory. While the transmit logic is sending out the content of the TxFIFO, it concurrently samples the raw serial data, performs serial-to-parallel conversion, and stores data into RxFIFO. In the case of a read command, when data is to be driven by the flash memory after the command and address bytes, the MIO switches from output to input at the appropriate time under the control

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of the transmit logic. Data shifted into the RxFIFO reflects the switch resulting in valid data in the RxFIFO at the corresponding FIFO entry Software needs to filter the raw data from the RxFIFO to obtain the relevant data content. The controller does not modify either the instruction written by software or the captured data put into the RxFIFO. The controller supports little endian mode and the most significant bit of the least significant byte of a 4-byte word of an instruction is sent first.

Flow Control
I/O mode has different modes of flow control during data transfer. The user can select between automatic and manual mode, controlled by config_reg.MANSTARTEN (Man_start_com). In Manual mode, the user can further select manual or automatic chip select with Config_reg.SSFORCE (Manaual_CS). Asserting chip select signals the beginning of a command sequence on MIO. Immediately following the CS assertion, serial data on D0 is interpreted as command by the flash memory. In automatic mode, the entire transmission sequence, including control of chip select is done in hardware. No software intervention is required. The transmission starts as soon as data is pushed into the TxFIFO via writing to TXD, chip select automatically becomes active. Data transmission ends when the TxFIFO is empty and chip select automatically becomes inactive. In this mode, to carry out continuous data transfer, software must be able to keep up with supplying data to the TxFIFO at a rate equal or higher than the rate of data movement on the MIO. This can be difficult since reading from RXD and writing to TXD occurs at the APB clock rate. In Manual mode, the user controls the start of data transmission. In this case, software either writes the entire transmission sequence to the TxFIFO or until the TxFIFO is full. Upon writing of the Man_start_en bit, the controller takes over, asserts CS, shifts data out of the TxFIFO and into the RxFIFO, controls the input/ouput state of the MIO as appropriate, and terminates the sequence when the TxFIFO is empty by de-asserting CS. The maximum number of bytes per command sequence in this mode is limited by the depth of the TxFIFO of 252 bytes. In manual mode, the user can further choose to control the chip select in addition to controlling the start of transmission. Software again writes the transmission sequence to the TxFIFO starting with the command until the TxFIFO is full. Software then asserts CS, followed by manual start. The hardware takes over. However, CS is not de-asserted when the TxFIFO becomes empty. Software can fill the TxFIFO again with the appropriate data to continue the previous command. This method removes the limit on the number of bytes per command sequence and can be used effectively for large data transfers. On completion of the command sequence, the software de-asserts CS by writing to the Manual_CS bit.

12.2.3 I/O Mode Transmit Registers (TXD)

Software writes byte sequences that are needed for the specific flash device. Refer to the Quad-SPI device vendor's specification. The controller has four write-only 32-bit TXD registers for software to issue a stream of commands to get status and read/write data from the flash memory. Quad-SPI TXD register write formats are described in Table 12-1. Each access to the TXD0, TXD1, TXD2, or TXD3 register results into a corresponding write to the TxFIFO. The TxFIFO only remembers first CMD entry

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and assumes that the rest of the FIFO have the same type (TXDx) of CMD. Because of this the user must empty the TxFIFO between consecutive accesses to TXD0, TXD1, TXD2, and TXD3 Table 12-1: Register
TXD 1 TXD 2 TXD 3 TXD 0

Quad-SPI TXD Register Write Formats Write Data Format 31:24

Reserved Reserved Reserved Data 3

23:16
Reserved Reserved Data 1 Data 2

15:8
Reserved Data 0 Data 0 Data 1

7:0
Command only Command only Command only Data or Command

Example Usage
Set write enable Write status with data Read status with two dummy bytes Write data to transmit or dummy data for reads

FIFO Reads and Writes

The TxFIFO and RxFIFO share the same gated clock. Therefore for every byte, including command and address bytes shifted out of the TxFIFO, a corresponding byte is shifted into the RxFIFO To read data from Quad-SPI flash memory, the software writes the appropriate command, address, mode (when in Quad or Dual I/O mode) and dummy cycles as required by the Quad-SPI flash memory into the TxFIFO. In addition, software must pad the TxFIFO with additional dummy data. This additional dummy data provides the CLK needed to shift data into the RxFIFO. See section 12.3.5 Rx/Tx FIFO Response to I/O Command Sequences for additional programming details.

12.2.4 I/O Mode Issues

There are a couple of legacy issues that users need to be aware of when using the I/O mode. Neither of these issues apply to the linear addressing mode. The RxFIFO interrupt status bit indicates when data is available before data is actually available for read. The latency is associated with clock domain crossing and is almost always made-up by the time that software takes to service the interrupt. During read command, software must write to the TxFIFO with dummy data to receive data from the device. In automatic mode, if TxFIFO goes empty, the Quad-SPI controller deasserts chip select. To further receive data, software must send the read command and address to the device.

12.2.5 Linear Addressing Mode

The controller has a 32-bit AXI slave interface to support linear address mapping for read operations. When a master issues an AXI read command through this port, the Quad-SPI controller generates QSPI commands to load the corresponding memory data and send it back through the AXI interface. In linear mode, the flash memory subsystem behaves like a typical read-only memory with an AXI interface that supports a command pipeline depth of four. The linear mode improves both the user friendliness and the overall read memory throughput over that of the I/O mode by reducing the amount of software overhead. From a software perspective, there is no perceived difference between

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accessing the linear Quad-SPI memory subsystem and that of other ROMs, except for a potentially longer latency. A simplified block diagram of the controller showing the linear and I/O portions is shown in Figure 12-2.

AXI Interface Operation

Only AXI read commands are supported by the linear addressing mode. All valid write addresses and write data are acknowledged immediately but are ignored, that is, no corresponding programming (write) of the flash memory is carried out. All AXI writes generate an SLVERR error on the write response channel. Both incrementing- or wrapping-address burst reads are supported. Fixed-address bursts are not supported and cause an SLVERR error. Therefore, the only recognized arburst[1:0] value is either 2'b01 or 2'b10 . All read accesses must be word-aligned and the data width must be 32-bits (no narrow burst transfers are allowed). Table 12-2 lists the read address channel signals from a master that are ignored by the interface. Table 12-2: Signal
araddr[1:0] arsize[2:0] arlock[1:0] arcache[3:0] arprot[2:0]

Ignored AXI Read Address Channel Signals Value

Ignored, assumed to be 0, i.e., always assumed to be word aligned Ignored, always a 32-bit interface Ignored Ignored Ignored

The AXI slave interface provides a read acceptance capability of 4 so that it can accept up to four outstanding AXI read commands.

Interface Configuration and Read Modes

AXI read burst transfers are translated into SPI flash read instructions that are sent to the controller's TxFIFO. The transmit logic retrieves the read instructions from the TxFIFO and passes them to the SPI flash memory device according to the SPI protocol. Software defines the SPI read command that is used in linear addressing mode by writing to qspi.LQSPI_CFG[INST_CODE]. The supported read command codes and the recommended configuration register settings (qspi.LQSPI_CFG) are listed in Table 12-3. Table 12-3: Quad-SPI Device Configuration Register Values Instruction Code
0x03 0x0B

Operating Mode
Read (serial bit) Fast Read (serial bit)

Winbond & Spansion 1 Device

0x80000003 0x8000010B

Micron 1 Device
0x80000003 0x8000010B

2 Devices
0xE0000003 0xE000010B

2 Devices
0xE0000003 0xE000010B

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Table 12-3:

Quad-SPI Device Configuration Register Values (Contd) Instruction Code

0x3B 0x6B 0xBB 0xEB

Operating Mode
Dual Output Fast Read Quad Output Fast Read Dual I/O Fast Read Quad I/O Fast Read

Winbond & Spansion 1 Device

0x8000013B 0x8000016B 0x82FF00BB 0x82FF02EB

Micron 1 Device
0x8000013B 0x8000016B 0x82FF01BB 0x82FF04EB

2 Devices
0xE000013B 0xE000016B 0xE2FF00BB 0xE2FF02EB

2 Devices
0xE000013B 0xE000016B 0xE2FF01BB 0xE2FF06EB

Performance Modes
To get the highest performance, the user should use the Quad-SPI controller in the Quad I/O mode. The user can improve read performance by using the Quad-SPI device in continuous read mode. This eliminates read instruction overhead for successive commands. Please refer to the LQSPI_CFG register for more details (see Appendix B, Register Details). Refer to the applicable Zynq-7000 AP SoC data sheet for operating frequencies.

Read Data Management

A 63-deep RxFIFO provides read data buffering to hold a minimum of three AXI burst transfer lengths of 16 bytes each. Since the RxFIFO starts receiving data as soon as the chip-select signal is active, the linear address adapter removes incoming data that corresponds to the instruction code, if any, the address, and the dummy cycles. The read data must be aligned with the corresponding word boundary specified by the address. For data alignment purposes, the controller can modify the address as illustrated in Figure 12-4 before it is sent to the flash memory device. The address modification involves reducing the address by up to 3 byte locations such that the intended return data is word aligned automatically. The amount of address change is transparent to the AXI interface, and is instruction dependent. For example, if Cmd + address + mode + dummy (QSPI_intruction) does not end on a 32 bit boundary, the linear controller subtracts 1,2,3 from the address to align data on the 32 bit boundary.
X-Ref Target - Figure 12-4

Address Offset
AXI read addr Flash mem addr = AXI read addr - x Where x depends on the instr type and is either 0, 1, 2 or 3 Flash mem addr

UG585_c12_05_022712

Figure 12-4:

Automatic Address Offset For Word Alignment

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Read Latency
In linear mode, the default read mode is fast Quad I/O. The following is an example to calculate latency at the memory in the Quad I/O mode at 100 MHz with 2 dummy bytes. For a single device, the number of clock cycles from the time an 8-bit instruction code and a 24-bit address is available to the time when the first 32-bit data becomes available is: Total latency = instruction latency + address latency + overhead (mode + dummy bites + offset) + latency = 8 cycles + 6 cycles + 8 (2+4+2) cycles + 8 cycles =30 cycles With the SPI clock of 100 MHz, the latency at the memory interface is 320 ns. Other read modes have higher latency and can be calculated in a similar manner.

12.2.6 Unsupported Devices

A number of devices implement custom 4-bit wide SPI-like interfaces for flash memory access, such as the SQI devices from SST, and the Fast4 devices from Atmel. Some other Quad-SPI devices, like some Micron/Numonyx devices, offer an option to switch operation to such a custom 4-bit interface, through a non-volatile configuration bit. These interfaces operate differently from the devices supported by the Quad-SPI controller. These flash memory devices operate in 4-bit mode during the instruction phase, as well as the address and data phases. This requires the Quad-SPI flash controller to power up in 4-bit mode and remain in that mode permanently (or until configured otherwise, if that option is available). There are no plans to enable the support for these custom interfaces.

12.3 Programming Guide

Example: Start-up Sequence
1. 2. 3. 4. Configure Clocks . Refer to section 12.4.1 Clocks. Configure Tx/Rx Signals . Refer to section 12.5.2 MIO Programming. Reset the Controller. Refer to section 12.4.2 Resets. Configure the Controller. Refer to section 12.3.1 Configuration.

Now, either configure the controller for linear addressing mode (section 12.2.5 Linear Addressing Mode) or configure the controller for I/O mode (section 12.3.3 Configure I/O Mode and section 12.3.4 I/O Mode Interrupts).

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12.3.1 Configuration
Example: Configure Controller
This example applies to both linear addressing and I/O modes. It prepares the controller baud rate, FIFO, flash mode, clock phase/polarity, and programs the loopback delay. The values to program into the qspi.Config_reg register are shown in Table 12-3, page 298. 1. Configure the controller. Write to the qspi.Config_reg register. a. c. e. f. 2. Set baud rate, [BAUD_RATE_DIV]. Select flash mode (not Legacy SPI), [LEG_FLSH] = 1. Set FIFO width to 32 bits, [FIFO_WIDTH]. Set clock phase, [CLK_PH] and Polarity, [CLK_POL]. b. Select master mode, [MODE_SEL] = 1. d. Select Little Endian, [endian] = 0 .

If baud rate divider is 2, then change default setting . If the qspi.Config_reg[BAUD_RATE_DIV] is set to 0b00 , configure the qspi.LPBK_DLY_ADJ (loopback delay adjustment) register with the following settings: a. c. Set to select internal clock . qspi.LPBK_DLY_ADJ[USE_LPBK] = 1 . Set the clock delay 1. qspi.LPBK_DLY_ADJ[DLY1] = 0b00 . b. Set the clock delay 0. qspi.LPBK_DLY_ADJ[DLY0] = 0b00 .

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12.3.2 Linear Addressing Mode

Example: Linear Addressing Mode (Memory Reads)
The sequence of operations for data reads in linear addressing mode is as follows: 1. 2. 3. 4. 5. 6. 7. Set manual start enable to auto mode . Set qspi.Config_reg[Man_start_en] = 0 . Assert the chip select . Set qspi.Config_reg[PCS] = 0 . Program the configuration register for linear addressing mode . Example values are shown in Table 12-3, page 298. Enable the controller. Set qspi.En_REG[SPI_EN] = 1 . Read data from the linear address memory region . The memory range depends on the size and number of devices. The range is from 0xFC00_0000 up to 0xFDFF_FFFF. Disable the controller. Set qspi.En_REG[SPI_EN] = 0 . De-assert chip select . Set qspi.Config_reg[PCS] = 1 .

12.3.3 Configure I/O Mode

Example: I/O Mode (Memory Reads and Writes)
The sequence of operations uses I/O mode for reads and writes. 1. 2. Enable manual mode . Write 1 to qspi.Config_reg[Man_start_en, Manual_CS] = 1 . Configure the flash device . Refer to Figure 12-6, page 309. Use reset values of the qspi.LQSPI_CFG register for a single flash device. In case of a parallel dual flash device, write 1 to the TWO_MEM, SEP_BUS bit fields. Assert chip select. Set qspi.Config_reg[PCS] = 0 . Enable the controller. Set qspi.En_REG[SPI_EN] = 1 . Write byte sequences to the flash memory. Write from 1 to 4 bytes to the TxFIFO using the TXD registers. Refer to section 12.2.3 I/O Mode Transmit Registers (TXD). Avoid TxFIFO overflow. When the TxFIFO is empty, 252 bytes can be written. After that, software can avoid overflowing the TxFIFO by reading qspi.Intr_status_REG[TX_FIFO_full] and waiting until it equals 0 before writing to a TXD register. Enable the interrupts . Write to qspi.Intrpt_en_REG. Interrupt handlers that handle the interrupt conditions are discussed in interrupt handlers section. Start data transfer. Set qspi.Config_reg[Man_start_com] = 1 . Interrupt handler: Transfer all the required data to QSPI flash during program/read operations to Quad-SPI flash. (See Example: I/O Mode Interrupt Service Routine, page 303.)

3. 4. 5. 6.

7. 8. 9.

10. If read operations are carried out : re-arrange the READ data to eliminate the data read due to dummy cycles. 11. Disable controller. Set qspi.En_REG[SPI_EN] = 0 . 12. De-assert chip select . Set QSPI.Config_reg[PCS] = 1 .

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Note that the TxFIFO width must be programmed to 32 bits: qspi.Config_reg[FIFO_WIDTH] = 0b11 . Software needs to take care of consecutive non word aligned transfers.

Example: I/O Mode Interrupt Service Routine

1. Configure the ISR to handle the interrupt conditions based on the Quad-SPI device type . To read from the Quad-SPI device, the simplest ISR reads data from the RxFIFO and writes content to the TxFIFO. The system interrupt controller (GIC) is described in Chapter 7, Interrupts. The controller generates a system peripheral interrupt (SPI), IRQ ID #51. The interrupt mechanism for the Quad-SPI controller is described in section 12.3.4 I/O Mode Interrupts. a. Read transfer interrupt. RxFIFO Not Empty Interrupt b. Write transfer interrupt. TxFIFO Not Full Interrupt

12.3.4 I/O Mode Interrupts

Interrupts are only used in I/O mode. The controller interrupt is asserted whenever any of the interrupt conditions are met. The Quad-SPI interrupt handler checks the cause of the interrupt. A single interrupt service routine can manage all of the interrupt conditions.

Example: Interrupt Handler for Rx and Tx

The interrupt handler is trigger by IRQ ID #51. The example reads the RxFIFO until it is empty and then fills-up the TxFIFO. The RxFIFO Not Empty Interrupt status is used to determine if content can be read from the RxFIFO. The TxFIFO Not Full interrupt indicates if there is room in the TxFIFO for more content. 1. 2. 3. Disable all of the interrupts in the controller. Set qspi.Intrpt_dis_REG[TX_FIFO_not_full , RX_FIFO_full] both = 1 . Clear the interrupts. Read the interrupt status register qspi.Intr_status_REG. Empty the RxFIFO. Check if RxFIFO Not Empty interrupt is asserted. If qspi.Intr_status_REG[RX_FIFO_not_empty] = 1 , then there is data in the RxFIFO. a. If the status is asserted, then read data from the RxFIFO. Read the data using the qspi.RX_data_REG register.

b. Read data from the RxFIFO and poll the interrupt status until the RxFIFO is empty. The RxFIFO is empty when qspi.Intr_status_REG[RX_FIFO_not_empty] = 0 . 4. Fill the TxFIFO. Check if the TxFIFO Not Full status is asserted. If qspi.Intr_status_REG[TX_FIFO_not_Full] = 1, then there is data to be sent to the flash device (program and/or read operations): a. c. 5. 6. Write data to the qspi.TXD0 register. Follow steps a and b until all the data is written to the TxFIFO or until qspi.Intr_status_REG[TX_FIFO_full] = 1 . b. Poll for qspi.Intr_status_REG[TX_FIFO_full] = 1 , which indicates TX FIFO is full.

Enable the interrupts . Set qspi.Intrpt_en_REG[TX_FIFO_not_full, RX_FIFO_full] both = 1 . Start the data transfer. Set qspi.Config_reg[MANSTRTEN] = 1 .

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12.3.5 Rx/Tx FIFO Response to I/O Command Sequences

Example command and sequences: Write Enable Command Read Status Command Read Data Sequence

In these examples, YY can have any value. Each YY pair could have a different value. To receive data in serial legacy mode, the value is sampled from MISO/DQ1 line into RxFIFO synchronous to clock, while the command and address transactions occur on MOSI/DQ0.

Example: Write Enable Command (code 0x06)

1. Send the Write Enable Command (WREN) . Write 0xYYYY_YY06 to the qspi.TXD1 register. a. c. 2. WREN command = 0x06 . The controller shifts one bytes out of the TxFIFO to the device and receives two bytes in the RxFIFO. Value is 0x0000_0000 when YY = 0x0 (the status) and PP_PPPP = 0x0 (previous state of the bits). b. YY = 0 .

Read Status. Reads the qspi.RXD register and receive 0xYYPP_PPPP. a.

b. Software remembers that one byte resulted from the Write Enable command and returns 0xYY to the calling function. The content in the RxFIFO after sending the WREN command follows. (Previous means that the value has not changed from the register's previous value.) RxFIFO Entry 1 0 MSB
Invalid 00 Invalid Previous Invalid Previous

LSB
Invalid Previous

Example: Read Status Command (code 0x05)

1. Send the Read Status Command (RDSR) . Write 0xYYYY_DD05 to the qspi.TXD2 register. a. Command is 0x05 , DD = dummy data, YY = 0 b. The controller shifts two bytes out of the TxFIFO to the flash memory and receives two bytes in the RxFIFO. 2. Read Status Value . Read 0xZZYY_PPPP from the qspi.RXD register. a. Value is 0x0300_0000 when ZZ = 0x03 , YY == 0x0 and PPPP = 0x0 . b. Software remembers that two bytes are valid and returns 0x00 , 0x03 to the calling function. The content in the RxFIFO after sending the RDSR command is shown in the table (previous means the value has not changed from the register's previous value):

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TxFIFO Entry 1 0

MSB
Invalid 0x3 Invalid 0x00 Invalid Previous

LSB
Invalid Previous

Example: Read Data Sequence

This example returns the four bytes of data at address 0 to the calling function. 1. 2. Send the data read instruction . Write 0xA2A1_A003 to the qspi.TXD0 register. a. Instruction includes command (0x03) plus address (A0, A1 and A2). Send dummy data . Write 0xD0D1_D2D3 (dummy data) to the qspi.TXD0 register (second TxFIFO entry). a. The controller shifts 8 bytes out of the TxFIFO to the flash memory and receives 8 bytes in the RxFIFO.

The content of the TxFIFO for this example follows. The byte sequence from controller to the device is: 0x03 , Y0, Y1, Y2, D0, D1, D2 and D3. TxFIFO Entry 1 0 3. 4. MSB
D3 A2 D2 A1 D1 A0

LSB
D0 0x03

Read past the instruction word . Read the qspi.RXD register and receive 0xYYYY_YYYY : a. a. c. YY = 0 . For the second read, software remembers that four bytes are valid. Overall, software reads these bytes: 0x00, 0x00, 0x00, 0x00, 0x24, 0x68, 0xAC, 0xEF and returns the four bytes of data to the calling function. Read flash memory data . Read the RXD register again and receives 0xD3D2_D1D0 . b. Example data: 0x2468ACEF.

The content of the RxFIFO for this example follows. The byte sequence from the device to controller is: YY, YY, YY, YY, 0xEF, 0xAC, 0x68 and 0x24 . RxFIFO Entry 1 0 MSB
0x24 YY 0x68 YY 0xAC YY

LSB
0xEF YY

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12.3.6 Register Overview

The register overview is provided in Table 12-4. Table 12-4: Address Offset
0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C

Quad-SPI Register Overview Mnemonic Software Name

Config_reg Intr_status_REG Intrpt_en_REG Intrpt_dis_REG Intrpt_mask_REG En_REG Delay_REG TXD0 Rx_data_REG Slave_Idle_count_REG TX_thres_REG RX_thres_REG GPIO LPBK_DLY_ADJ TXD1 TXD2 TXD3 LQSPI_CFG LQSPI_STS MOD_ID Configuration Interrupt status Interrupt enable Interrupt disable Interrupt mask Controller enable Delay Transmit 1-byte command and 3-byte data OR 4-byte data Receive data (RxFIFO) Slave idle count TxFIFO threshold level (in 4-byte words) RxFIFO Threshold level (in 4-byte words) General purpose inputs and outputs Loopback master clock delay adjustment Transmit 1-byte command Transmit 1-byte command and 1-byte data Transmit 3-byte 1-byte command and 2-byte data Linear mode configuration Linear mode status Module ID

Description

0x20 0x24 0x28 0x2C 0x30 0x38 0x80 0x84 0x88 0xA0 0xA4 0xFC

12.4 System Functions

12.4.1 Clocks
The controller and I/O interface are driven by the reference clock (QSPI_REF_CLK). The controller's interconnect also requires an APB interface CPU_1x clock. These clocks are generated by the PS clock subsystem.

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CPU_1x Clock
Refer to section 25.2 CPU Clock, for general clock programming information. The CPU_1x clock runs asynchronous to the Quad-SPI reference clock.

Reference Clock
The QSPI_REF_CLK is the main controller clock and is divided down to generate the SCLK clock for the flash memory interface. The QSPI_REF_CLK is sourced from the PS Clock Subsystem. The clock enable, PLL select, and divisor setting are programmed using the slcr.LQSPI_CLK_CTRL register. Refer to section 25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks for Quad-SPI clock programming information. For power management, the clock enable in the slcr register can be used to turn off the clock. The operating frequency for the reference clock is defined in the data sheet.

Clock Ratio Restriction in Manual Mode

In manual mode, the QSPI_REF_CLK frequency must be of greater than or equal value to that of CPU_1x clock frequency for reliable operation of the controller. There is no such restriction in automatic mode.The reference clock is divided down by qspi.Config_reg[baud_rate_divisor] to generate the SCLK clock for the flash memory.

Example: Setup Reference Clock

This example assumes the selected PLL (ARM, DDR or IO) is operating at 1000 MHz and the desired Quad-SPI reference clock frequency is 200 MHz. 1. Select PLL source, divisors and enable . Write 0x0000_0501 to the slcr.QSPI_CLK_CTRL register. a. c. Enable the reference clock. Select the I/O PLL as the clock source. b. Divide the I/O PLL clock by 5: DIVISOR = 0x05 .

Quad-SPI Feedback Clock

The Quad-SPI interface supports an optional feedback clock pin named qspi_sclk_fb_out. This pin is used with the high speed Quad-SPI timing mode, where the memory interface clock needs to be greater than 40 MHz. The feedback signal is received from the internal input from the I/O so MIO pin 8 needs to be programmed and allowed to freely toggle. Refer to optional programming example in section 12.5.2 MIO Programming for instructions on how to program the MIO_PIN_08 register. When Quad-SPI feedback mode is used, the qspi_sclk_fb_out pin should only be connected to a pull-up or pull-down resistor which is needed to set the MIO voltage mode (vmode). When operating at a Quad-SPI clock frequency greater than FQSPICLK2, the MIO 8 pin must be programmed as the feedback output clock and the MIO 8 pin must only be connected to a pull-up/pull-down resistor on the PCB for boot strapping.

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12.4.2 Resets
The controller has two reset domains: the APB interface and the controller itself. They can be controlled together or independently. The effects for each reset type are summarized in Table 12-5. Table 12-5: Quad-SPI Reset Effects Name
ABP Interface Reset slcr.LQSPI_RST_CTRL[LQSPI_CPU1X_RST] PS Reset Subsystem slcr.LQSPI_RST_CTRL[QSPI_REF_RST]

APB Interface
Yes No

TxFIFO and RxFIFO

Yes Yes

Protocol Engine
No Yes

Registers
Yes No

Example: Reset the APB Interface and Quad-SPI Controller

1. 2. Set controller resets . Write a 1 to the slcr.LQSPI_RST_CTRL[QSPI__REF_RST and LQSPI_CPU1X_RST] bit fields. Clear controller resets . Write a 0 to the slcr.LQSPI_RST_CTRL[QSPI__REF_RST and LQSPI_CPU1X_RST] bit fields.

12.5 I/O Interface

12.5.1 Wiring Connections
The I/O signals are available via the MIO pins. The Quad-SPI controller supports up to two SPI flash memories in either a shared or separate bus configuration. The controller supports operation in several configurations: Quad-SPI single SS, 4-bit I/O Quad-SPI dual SS, 8-bit parallel I/O Quad-SPI dual SS, 4-bit stacked I/O Quad-SPI single SS, legacy I/O

QSPI 0 should always be present if the QSPI memory subsystem is to be used. QSPI 1 is optional and is only required for the two-memory arrangement. Therefore, QSPI_1 cannot be used alone.

Single SS, 4-bit I/O

A block diagram of the 4-bit flash memory interface connected to the controller configuration is shown in Figure 12-5.

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X-Ref Target - Figure 12-5

Zynq Device
QSPI0_SCLK
CLK

Linear Quad-SPI Controller

QSPI0_IO[3:0]

IO[3:0]

Quad-SPI Flash Memory

QSPI0_SS_B

UG585_c12_06_022712

Figure 12-5:

Quad-SPI Single SS 4-bit I/O

Dual SS, 8-bit Parallel

The controller supports up to two SPI flash memories operating in parallel, as shown in Figure 12-6. This configuration increases the maximum addressable SPI flash memory from 16 MB (24-bit addressing) to 32 MB (25-bit addressing).
X-Ref Target - Figure 12-6

Zynq Device
QSPI1_SCLK QSPI1_IO[3:0]
CLK

IO[3:0]

QSPI1_SS_B

Quad-SPI Flash Memory (Upper)

Linear Quad-SPI Controller

QSPI0_SCLK QSPI0_IO[3:0]

CLK

IO[3:0]

Quad-SPI Flash Memory

QSPI0_SS_B

UG585_c12_07_022712

Figure 12-6:

Quad-SPI Dual SS, 8-bit Parallel I/O

For 8 bit parallel configuration, even bits of the data words are located in lower memory and odd bits of data are located in upper memory. The controller takes care of data management in both I/O and linear mode. The Quad-SPI controller does a read from the two Quad-SPI devices and ORs (or operation) both devices status information before writing the status data in the RXFIFO. Table 12-6 shows the data bit arrangement of a 32-bit data word for 8 bit parallel configuration .

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Table 12-6:
7 6 5 4

Quad-SPI Dual SS, 8-bit Parallel I/O Data Management

Single Device
3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24

byte 0

byte 1

byte 2

byte 3

Dual Devices Lower Memory

6 4 2 0 14 12 10 8 22 20 18 16 30 28 26 24

Dual Devices Upper Memory

7 5 3 1 15 13 11 9 23 21 19 17 31 29 27 25

byte 0

byte 1

byte 2

byte 3

In 8 bit parallel configuration, total addressable memory size is 32 MB. This requires a 25-bit address. All accesses to memory must be word aligned and have double-byte resolution. In linear mode, the Quad-SPI controller divides the AXI address by 2 and sends the divided address to the Quad-SPI device. In IO mode, software is responsible for doing the address translation to comply with SPI 24-bit address support.

Dual SS, 4-bit Stacked I/O

To reduce the I/O pin count, the controller also supports up to two SPI flash memories in a shared bus configuration, as shown in Figure 12-7. This configuration increases the maximum addressable SPI flash memory from 16 MB (24-bit addressing) to 32 MB (25-bit addressing), but the throughput remains the same as for single memory mode. Note that in this configuration, the device level XIP mode (read instruction codes of 0xbb and 0xeb ), is not supported. The lower SPI flash memory should always be connected if the linear Quad-SPI memory subsystem is used, and the upper flash memory is optional. Total address space is 32 MB with a 25-bit address. In IO mode, the MSB of the address is defined by U_PAGE which is located at bit 28 of register 0xA0 . In Linear address mode, AXI address bit 24 determines the upper or lower memory page. All of the commands will be executed by the device selected by U_PAGE in I/O mode and address bit 24 in linear mode.

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X-Ref Target - Figure 12-7

Zynq Device
CLK

IO[3:0]

QSPI1_SS_B

Quad-SPI Flash Memory (Upper)

Linear Quad-SPI Controller

QSPI0_SCLK QSPI0_IO[3:0]

CLK

IO[3:0]

Quad-SPI Flash Memory

QSPI0_SS_B

UG585_c12_08_022712

Figure 12-7:

Quad-SPI Dual SS 4-bit Stacked I/O

Single SS, Legacy I/O

The Quad-SPI controller can be operated in legacy single-bit serial interface mode for 1x, 2x and 4x I/O modes as shown in Figure 12-8.
X-Ref Target - Figure 12-8

Zynq Device (SPI Master)

QSPI0_SCLK
CLK

QSPI0_IO[0]

MOSI

QSPI0_IO[1]

Linear Quad-SPI Controller

MISO

QSPI0_SS_N

SPI Slave

SS

QSPI0_IO[2]

WP

QSPI0_IO[3]

HOLD

UG585_c12_09_022912

Figure 12-8:

Quad-SPI Single SS, Legacy I/O

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12.5.2 MIO Programming

The Quad-SPI signals can be routed to specific MIO pins, refer to Table 12-7, Quad-SPI Interface Signals. Wiring diagrams are shown in Figure 12-5 to Figure 12-8. The general routing concepts and MIO I/O buffer configurations are explained in section 2.4 PSPL Voltage Level Shifter Enables. If a four-bit I/O bus is used, then use Quad-SPI 0. If a bus frequency of greater than 40 MHz is needed, then the Quad-SPI feedback clock must be routed on MIO pin 8.

Example: Program I/O for a Single Device

These steps are required for all of the Quad-SPI I/O interface connections listed above. 1. Configure MIO pin 1 for chip select 0 output. Write 0x0000_1302 to the slcr.MIO_PIN_01 register: a. c. e. f. 2. Route Quad-SPI 0 chip select to pin 1. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

Configure MIO pins 2 through 5 for I/O. Write 0x0000_0302 to each of the slcr.MIO_PIN_{02:05} registers: a. c. e. f. Route Quad-SPI 0 I/O pins to pin 2 through 5. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS drive edge.

3.

Configure MIO pin 6 for serial clock 0 output. Write 0x0000_0302 to the slcr.MIO_PIN_06 register: a. c. e. f. Route Quad-SPI 0 serial clock to pin 6. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

Option: Add Second Device Chip Select

This step is required for the following I/O connections: Dual selects, shared 4-bit data memory interface.

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4.

Dual selects, separate 4-bit data memory interface. Configure MIO pin 0 for chip select 1 output. Write 0x0000_1302 to the slcr.MIO_PIN_00 register: a. c. e. f. Route Quad-SPI 1 chip select to pin 0. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

Option: Add Second Serial Clock

This step is required for the Dual Selects, Separate 4-bit Data Memory Interface: 5. Configure MIO pin 9 for serial clock 1 output. Write 0x0000_0302 to the slcr.MIO_PIN_09 register: a. c. e. f. Route Quad-SPI 1 serial clock to pin 9. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

Option: Add 4-bit Data

These steps are required for the dual selects, separate 4-bit data memory interface: 6. Configure MIO pins 10 through 13 for I/O. Write 0x0000_0302 to each of the slcr.MIO_PIN_{10:13} registers: a. c. e. f. Route Quad-SPI 1 I/O pins to pin 9 through 13. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS drive edge.

Option: Add Feedback Output Clock

The optional feedback clock is used when the I/O interface is operated above 40 MHz. It should only be connected to a pull-up or pull-down resistor for pin strapping resistor for MIO voltage mode, vmode. The feedback clock must also be enabled. 7. Configure MIO pin 8 for feedback clock . Write 0x0000_0302 to the slcr.MIO_PIN_08 register:

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a. c. e. f.

Route Quad-SPI feedback clock output to pin 8. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Diable HSTL receiver.

b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

12.5.3 MIO Signals

The Quad-SPI flash memory signals are routed through the MIO multiplexer to the MIO device pins. Each side of the dual controller port can be individually enabled or operate together as an 8-bit I/O interface. The Quad-SPI flash memory signals are routed to the MIO pins as shown in Table 12-7. Table 12-7: Quad SPI Interface Signals MIO Pin I/O
O O O 10 11 12 13 IO IO IO IO

Quad-SPI Flash Memory Interface I/O Mode for Data Signal

Flash Chip Select Serial Clock Output Feedback Clk I/O 0 I/O 1 I/O 2 I/O 3 Master Output Master Input Write Protect Hold

1-Bit Data

2-Bit Data
~ ~ ~ I/O 0 I/O 1 Write Protect Hold

4-Bit Quad SPI 0 Quad SPI 1 Data

1 6 8 I/O 0 I/O 1 I/O 2 I/O 3 2 3 4 5 0 9

Name
QSPI{1,0}_SS_B QSPI{1,0}_SCLK QSPI_SCLK_FB_OUT QSPI{1,0}_IO_0 QSPI{1,0}_IO_1 QSPI{1,0}_IO_2 QSPI{1,0}_IO_3

Controller Default Input Value

~ ~ ~ 0 0 0 0

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SD/SDIO Controller
13.1 Introduction
The SD/SDIO controller communicates with SDIO devices and SD memory cards. The SDIO interface can be routed through the MIO multiplexer to the MIO pins or through the EMIO to SelectIO pin in the PL. The controller can support SD and SDIO applications in a wide range of portable low-power applications such as 802.11 devices, GPS, WiMAX, UWB, and others. The SD/SDIO controller block diagram is shown in Figure 13-1. The SD/SDIO controller is compatible with the standard SD Host Controller Specification Version 2.0 Part A2 with SDMA (single operation DMA), ADMA1 (4 KB boundary limited DMA), and ADMA2 (ADMA2 allows data of any location and any size to be transferred in a 32-bit system memory scatter-gather DMA) support. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards. The user should be familiar with the SD2.0/SDIO 2.0 specifications. These are listed in Appendix A, Additional Resources. The SD/SDIO controller is accessed by the ARM processor via the AHB bus. The controller also includes a DMA unit with an internal FIFO to meet throughput requirements.

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X-Ref Target - Figure 13-1

SDMA ADMA1 ADMA2

Command Decoder

Response Generator AHB SD/SDIO Host Controller Transmitter/ Receiver AHB Interface Interrupts SD/SDIO Bus

CPRM

Interrupt

FIFO

UG585_c13_01_020613

Figure 13-1:

SD/SDIO Controller Block Diagram

13.1.1 Key Features

The two SDIO controllers are controlled and operate independently with the same feature set: Host mode controller

Four I/O signals (MIO or EMIO) Command, Clock, CD, WP, Pwr Ctrl (MIO or EMIO) LED control, bus voltage (EMIO) Interrupt or polling driven

AHB master-slave interface operating at the CPU_1x clock rate

Master mode for DMA transfers (with 1 KB FIFO)

Slave mode for register accesses Low-speed, 1 KHz to 400 KHz Full-speed, 1 MHz to 50 MHz (25 MB/sec) High-speed and high-capacity memory cards

SDIO Specification 2.0

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13.1.2 System Viewpoint

Figure 13-2 shows the SD/SDIO controller system viewpoint.
X-Ref Target - Figure 13-2

IRQ ID# {56, 79} Interconnect AHB Master port

MIO EMIO Routing SDIO Interface Controller

Device Boundary

MIO Pins

CPU_1x clock SDIO{0, 1} CPU_1x reset AHB Slave port Control Registers EMIO Signals

Interconnect

PL

SDIO{0, 1} Ref Clock

UG585_c13_02_031812

Figure 13-2:

SD/SDIO Controller System Viewpoint Diagram

13.2 Functional Description

13.2.1 AHB Interface and Interrupt Controller
When using programmed I/O for data transfers, software reads and writes the sdio.Buffer_Data_Port register. When using the local DMA unit for data transfers, the DMA unit initiates read or write memory transactions. The SDIO controller cannot be used with the PS DMAC. The controller can generate IRQ interrupt #56 and 79 for SDIO 0 and SDIO 1, respectively. The status and masking of the interrupts are controlled by registers.

13.2.2 SD/SDIO Host Controller

The SD/SDIO host controller comprises: Host-AHB controller All control registers Bus monitor Clock generator CRC generator and checker (CRC7 and CRC16)

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The host-AHB controller acts as bridge between the AHB bus and the host controller. The SD/SDIO controller registers are programmed by the processor through the AHB interface. Interrupts are generated based on the values set in the Interrupt Status and Interrupt Enable registers. The bus monitor checks for violations occurring on the SD bus and timeout conditions. The clock generation block generates the SD clock depending on the value programmed in the Clock Control register. The CRC7 and CRC16 generators calculate the CRC for command and data transfers to the SD/SDIO card. The CRC7 and CRC16 checker checks for any CRC errors in the response and data received from the SD/SDIO card. To detect data defects on the card, the host can include error correction codes in the payload data. ECC code is used to store data on the card. This ECC code is used by the application to decode the user data.

13.2.3 Data FIFO

The controller uses two 512 byte dual port FIFOs for performing write and read transactions. During a write transaction (data is transferred from the processor to an attached card) data is written by the processor alternatively into the first and second FIFO. When data is transferred to an attached card, alternatively the second and first FIFO is used, providing maximum data throughput. During a read transaction (data is transferred from an attached card to the processor) the data from the card is alternatively written in the two FIFOs. When data from one FIFO is transferred to the processor the second FIFO is filled with data from the card and vice versa, optimizing data throughput. If the controller cannot accept any data from a connected card, it issues a read wait, stopping the data transfer from the card by stopping the clock.

13.2.4 Command and Control Logic

The control logic block transmits data on the data lines during a write transaction and receives data during read transaction The command control logic block transmits commands on the command lines and receives the response from the SD2.0 or SDIO2.0.

13.2.5 Bus Monitor

The bus monitor checks for violations occurring in the SD bus, and timeout conditions.

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13.2.6 Stream Write and Read

This functionality applies to both DMA and non-DMA modes. WRITE_DAT_UNTIL_STOP(CMD20) writes a data stream from the host, starting at the given address, until a STOP_TRANSMISSION follows. READ_DAT_UNTIL_STOP(CMD11) reads a data stream from the card, starting at the given address, until a STOP_TRANSMISSION follows. The host controller switches to the second FIFO after writing/reading a block of data to/from the first FIFO, but the stream transaction block size is not be programmed by the driver. So for both stream write and stream read transactions, it is recommended that the host driver writes the maximum FIFO size value to the Block Size register. Because the SDIO FIFO slice is set to 512 bytes, the host driver must write 512 bytes to the Block Size register. Therefore FIFO switching occurs after writing/reading the 512 bytes of data.

13.2.7 Clocks
The SDIO clock is derived from SDIO reference clock based on the Clock Control register value programmed by the driver and is available only when the SD clock enable is set by the driver. The maximum frequency is 50 MHz for SD. The host controller supports both full speed and high speed cards. For the high speed card, the host controller should clock out the data at the rising edge of the SDIO clock. For the full speed card, the host controller should clock out the data at the falling edge of the SDIO clock.

13.2.8 Soft Resets

The host controller supports all soft resets mentioned in the SD2.0/SDIO2.0 Host Controller Specification .

13.2.9 FIFO Overrun and Underrun Conditions

This functionality applies to both DMA and non-DMA modes.

Write
During the write transaction, the host controller transmits data to the card only when a block of data is ready to transmit and the card is not busy. Therefore an under-run condition cannot occur in the SD side. In DMA mode, the host controller initiates a DMA READ from the ARM processor only if space is available to accept a block of data. In non-DMA mode, the host controller asserts a buffer write ready interrupt only if space is available to accept a block of data.

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Read
During the read transaction when the FIFO is full (the FIFO does not have enough space to accept a block of data from the card) the host controller stops the clk_sd to the card. Therefore an over-run condition cannot occur in SD side. In DMA mode the host controller initiates a DMA WRITE to the ARM processor only on reception of a block of data from card. In non-DMA mode, the host controller asserts a buffer read ready interrupt only on reception of a block of data from card.

13.3 Programming Model

13.3.1 Data Transfer Protocol Overview
SD transfers are basically classified into following three types according to how the number of blocks is specified:

Single Block Transfer

The number of blocks is specified to the host controller before the transfer. The number of blocks specified is always one.

Multiple Block Transfer

The number of blocks is specified to the host controller before the transfer. The number of blocks specified is one or more.

Infinite Block Transfer

The number of blocks is not specified to the host controller before the transfer. This transfer is continued until an abort transaction is executed. This abort transaction is performed by CMD12 in the case of an SD memory card and by CMD52 in the case of an SDIO card.

13.3.2 Data Transfers Without DMA

Figure 13-3 shows data transfers without using DMA.

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X-Ref Target - Figure 13-3

Start
(1) (5)

Set Block Size Reg

(2) (6)

Set Command Reg

Set Block Count Reg

(3) (7)

Wait for Command Complete Int

Command Complete Int Occur

Set Argument Reg

(4) (8)

Clr Command Complete Sts

Set Transfer Mode Reg

Get Response Data

Write

(9)

Write or Read

Read

(10-W)

(10-R)

Wait for Buffer Write Ready Int

(11-W) Buffer Write Ready Int Occur (11-R)

Wait for Buffer Write Ready Int

Buffer Read Ready Int Occur

Clr Buffer Wr Rdy Sts

(12-W) (12-R)

Clr Buffer Rd Rdy Sts

Set Block Data

Get Block Data

(13-W)

(13-R)

More Blocks?
Yes No Yes

More Blocks?
No

Single or Multi Block Transfer (15)

(14)

Single / Multi / Infinite Block Transfer?

(17)

Infinite Block Transfer

Wait for Transfer Complete Int

(16) Transfer Complete Int Occur

Abort Transaction

Clr Transfer Complete Sts

End
UG585_c13_03_031812

Figure 13-3:

Data Transfer Using DAT Line Sequence (Without Using DMA)

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The sequence for data transfers without using DMA is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set the value corresponding to the executed data byte length of one block to the Block Size register. Set the value corresponding to the executed data block count to the Block Count register. Set the value corresponding to the issued command to the Argument register. Set the value to Multi/Single Block Select and Block Count Enable. Set the value corresponding to the issued command to Data Transfer Direction, Auto CMD12 Enable, and DMA Enable. Set the value corresponding to the issued command to the Command register.

Note: When writing the upper byte of the command register, the SD command is issued.
Wait for the command complete interrupt. Write a 1 to the Command Complete bit in the Normal Interrupt Status register to clear this bit. Read the Response register and get the necessary information in accordance with the issued command. In the case where this sequence is for writing to a card, go to Step (10-W). In case of read from a card, go to Step (10-R).

(10-W). Wait for a buffer write ready interrupt.

Non-DMA Write Transfer On receiving the buffer write ready interrupt the ARM processor acts as a master and starts transferring the data via the Buffer Data Port register (FIFO_1). The transmitter starts sending the data on the SD bus when a block of data is ready in FIFO_1. While transmitting the data on the SD bus the buffer write ready interrupt is sent to the ARM processor for the second block of data. The ARM processor acts as a master and starts sending the second block of data via the buffer data port register to FIFO_2. The buffer write ready interrupt is asserted only when a FIFO is empty and available to receive a block of data.

(11-W). Write a 1 to the Buffer Write Ready bit in the Normal Interrupt Status register to clear this bit. (12-W). Write a block of data (according to the number of bytes specified in Step (1)) to the Buffer Data Port register. (13-W). Repeat until all blocks are sent and then go to Step (14).

Non-DMA Read Transfer A buffer read ready interrupt is asserted whenever a block of data is ready in one of the FIFOs. On receiving the buffer read ready interrupt, the ARM processor acts as a master and starts reading the data via the Buffer Data Port register (FIFO_1). The receiver starts reading the data from the SD bus only when a FIFO is empty and available to receive a block of data. When both of the FIFOs are full the host controller stops the data coming from the card by means of a read wait mechanism (if the card supports read wait) or through clock stopping.

(10-R). Wait for a buffer read ready interrupt (11-R). Write a 1 to the Buffer Read Ready bit in the Normal Interrupt Status register to clear this bit.

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(12-R). Read a block of data (according to the number of bytes specified in Step (1)) from the Buffer Data Port register. (13-R). Repeat until all blocks are received and then go to Step (14). 14. 10. 11. 12. If this sequence is for a single or multiple block transfer, go to Step (15). In case of an infinite block transfer, go to Step (17). Wait for a transfer complete interrupt. Write a 1 to the Transfer Complete bit in the Normal Interrupt Status register to clear this bit. Perform the sequence for abort transaction.

Note: Step (1) and Step (2) can be executed at same time. Step (4) and Step (5) can be executed at
same time.

13.3.3 Using DMA

Figure 13-4 shows data transfers using DMA.
X-Ref Target - Figure 13-4

Start
(1)

Set System Address Reg

(2)

Set Block Size Reg

(3)

(10)

Wait For Transfer Complete Int and DMA Int

Set Block Count Reg

(4) (11)

Set Argument Reg

(5) (12)

Check Interrupt Status

Transfer Complete Int Occur

Set Transfer Mode Reg

(6) (13)

Clr DMA Interrupt Status

Set Command Reg Get System Address Reg

(7)

Wait For Command Command Int

(8)

(14)

Command Complete Int Occur Clr Command Complete Status Clr Transfer Complete Status Clr DMA Interrupt Status

(9)

Get Response Data

End
UG585_c13_04_031812

Figure 13-4:

SDIO Controller Data Transfer Using DMA

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Burst types such as an 8-beat incrementing burst or a 4-beat incrementing burst, or a single transfer is used to transfer or receive the data from the system memory mainly to avoid the hold of the AHB bus by the master for a longer time. The sequence for using DMA is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set the system address for DMA in the System Address register. Set the value corresponding to the executed data byte length of one block in the Block Size register. Set the value corresponding to the executed data block count in the Block Count register. Set the value corresponding to the issued command to the Argument register. Set the value to Multi/Single Block Select and Block Count Enable. Set the value corresponding to the issued command to Data Transfer Direction, Auto CMD12 Enable, and DMA Enable. Set the value corresponding to the issued command to the Command register.

Note: When writing to the upper byte of the Command register, the SD command is issued.
Wait for the command complete interrupt. Write a 1 to the Command Complete in the Normal Interrupt Status register for clearing this bit. Read the Response register and get the necessary information in accordance with the issued command.

DMA Read Transfer On receiving the Response End Bit from the card for the write command (data is flowing from the host to the card) the SD host controller acts as the master and requests the AHB bus. After receiving the grant the host controller starts reading a block of data from system memory and fills the first half of the FIFO. Whenever a block of data is ready the transmitter starts sending the data on the SD bus. While transmitting the data on the SD bus the host controller requests the bus to fill the second block in the second half of the FIFO. Ping Pong FIFOs are used to increase the throughput. Similarly, the host controller reads a block of data from system memory whenever a FIFO is empty. This continues until all of the blocks are read from system memory. A transfer complete interrupt is set only after transferring all of the blocks of data to the card.

DMA Write Transfer The block of data received from the card (data is flowing from the card to the host) is stored in the first half of the FIFO. Whenever a block of data is ready the SD host controller acts as the master and request the AHB bus. After receiving the grant the host controller starts writing a block of data into system memory from the first half of the FIFO. While transmitting data into system memory the host controller receives the second block of data and stores it in the second half of the FIFO. Similarly the host controller writes a block of data into system memory whenever data is ready. This continues until all of the blocks are transferred to system memory. A transfer complete interrupt is set only after transferring all of the blocks of data into system memory.

Note: The host controller receives a block of data from the card only when it has room to

store a block of data in the FIFO. When both FIFOs are full the host controller stops the data coming from the card through a read wait mechanism (if the card supports read wait) or through clock stopping.

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10. Wait for the transfer complete interrupt and DMA interrupt. 11. If Transfer Complete is set to 1 , go to Step (14). If DMA Interrupt is set to 1 go to Step (12). Transfer Complete has a higher priority than DMA Interrupt. 12. Write a 1 to the DMA Interrupt bit in the Normal Interrupt Status register to clear this bit. 13. Set the next system address of the next data position to the System Address register and go to Step (10). 14. Write a 1 to the Transfer Complete and DMA Interrupt in the Normal Interrupt Status register to clear this bit.

Note: Step (2) and Step (3) can be executed at same time. Step (5) and Step (6) can also be executed
at same time. For example, if the host wants to transfer 4 KB of data to the card and assuming the maximum block size is 256 bytes, the host driver programs the Block Size register as 256 and Block Count register with the value 16. The AHB master and transmitter residing inside the SD2.0/SDIO2.0 host controller get the information (how much data to transfer) from these registers. Using the above information, the AHB master acts as a master and initiates a data read transaction (to read a block of data 256 bytes from the system memory). The following types of burst are used mainly to avoid hold of the AHB bus by the master for a longer time. Single transfer 4-beat incrementing burst 8-beat incrementing burst

The first block of data is received in the first half of the FIFO and the second block in the second half of the FIFO. Similarly, the remaining blocks are received in alternate FIFOs. Whenever a block of data is ready in FIFO, the transmitter starts transmitting the block of data (256 bytes) onto the SD bus. After transmitting the entire block of data to the card, the transmitter waits for a status response from the card. Transmitter sends the next block of data only when it receives a good status response from the card for the previous block of data, otherwise the transaction is aborted and the host goes for a fresh transaction.

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13.3.4 Using ADMA

Figure 13-5 shows data transfers using ADMA.
X-Ref Target - Figure 13-5

Start
(1)

Create Descriptor Table

(2) (11)

Set ADMA System Address Reg

(3)

Wait For Transfer Complete Int and ADMA Error Int

Set Block Size Reg

(4) (12)

Set Block Count Reg

(5)

Check Interrupt Status

ADMA Error Int. Occurs

Set Argument Reg

(6)

(13)

Transfer Complete Int. Occurs (14) Clr Transfer Complete Interrupt Status
(15)

Set Transfer Mode Reg

(7)

Clr ADMA Error Interrupt Status

Set Command Reg

(8)

Abort ADMA Operation

Wait For Command Complet Int End

(9)

Command Complete Int Occurs Clr Command Complete Status

(10)

Get Response Data

UG585_c13_05_031812

Figure 13-5:

SDIO Controller Data Transfer Using ADMA

The sequence for using ADMA is as follows 1. 2. 3. 4. Create a descriptor table for ADMA in system memory. Set the descriptor address for ADMA in the ADMA System Address register. Set the value corresponding to the executed data byte length of one block in the Block Size register. Set the value corresponding to the executed data block count in the Block Count register in accordance with SDIO register map.

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If the Block Count Enable bit in the Transfer Mode register is set to 1 , the total data length can be designated by the Block Count register and the descriptor table. These two parameters shall indicate same data length. However, transfer length is limited by the 16-bit Block Count register. If the Block Count Enable bit in the Transfer Mode register is set to 0 , the total data length is designated not by Block Count register, but the descriptor table. In this case, if the ADMA reads more data than the length programmed in the descriptor from the SD card, the operation is aborted asynchronously and the extra read data is discarded when the ADMA is completed. 5. 6. Set the argument value to the Argument register. Set the value to the Transfer Mode register. The host driver determines Multi/Single Block Select, Block Count Enable, Data Transfer Direction, Auto CMD12 Enable and DMA Enable. Multi/Single Block Select and Block Count Enable are determined according to SDIO register map. Set the value to the Command register.

7.

Note: When writing to the upper byte [3] of the Command register, the SD command is issued
and DMA is started. 8. 9. Wait for the command complete interrupt. Write a 1 to the Command Complete bit in the Normal Interrupt Status register to clear this bit.

10. Read the Response register and get the necessary information from the issued command. 11. Wait for the transfer complete interrupt and ADMA error interrupt. 12. If the Transfer Complete is set to 1 , go to Step (13). If the ADMA Error Interrupt is set to 1 , go to Step (14). 13. Write a 1 to the Transfer Complete Status bit in the Normal Interrupt Status register to clear this bit. 14. Write a 1 to the ADMA Error Interrupt Status bit in the Error Interrupt Status register to clear this bit. 15. Abort ADMA operation. SD card operation should be stopped by issuing an abort command. If necessary, the host driver checks the ADMA Error Status register to detect why the ADMA error is generated.

Note: Step (3) and Step (4) can be executed simultaneously. Step (6) and Step (7) can also be executed simultaneously. Note: During ADMA2 operation, the controller will not generate a DMA interrupt if the INT attribute
is set along with NOP, RSVD, or LINK attribute.

13.3.5 Abort Transaction

An abort transaction is performed using CMD12 for a SD memory card and by using CMD52 for a SDIO card. There are two cases where the HD needs to do an abort transaction: When the HD stops infinite block transfers. When the HD stops transfers while a multiple block transfer is executing.

There are two ways to issue an abort command. The first is an asynchronous abort. The second is a synchronous abort. In an asynchronous abort sequence, the HD can issue an abort command at anytime unless the Command Inhibit (CMD) bit in the Present State register is set to 1 . In a synchronous abort, the HD issues an abort command after the data transfer stopped via the Stop At Block Gap Request bit in the Block Gap Control register.

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Synchronous Abort
The following sequence performs a synchronous abort. 1. 2.
X-Ref Target - Figure 13-6

Set the Stop At Block Gap Request bit in the Block Gap Control register to 1 to stop SD transactions. Wait for a transfer complete interrupt.

Start
(1)

Set Stop at Block Gap Request

(2)

(5)

Wait For Transfer Complete Int Transfer Complete Int Occur Clr Transfer Complete Status

Set Software Reset For DAT Line (DR) and CMD Line (CR)

(6)

DR=1 or CR=1 Check DR and CR DR=0 and CR=0

(3)

(4)

Issue Abort Command

End

UG585_c13_06_031812

Figure 13-6: 3. 4. 5. 6.

SDIO Controller Synchronous Abort Sequence

Set the Transfer Complete bit to 1 in the Normal Interrupt Status register to clear this bit. Issue an abort command. Set both the Software Reset for DAT Line and Software Reset for CMD Line bits to 1 in the Software Reset register to do a software reset. Check the Software Reset for DAT Line and Software Reset for CMD Line in the Software Reset register. If both Software Reset for DAT Line and Software Reset for CMD Line are 0 , go to END. If either the Software Reset for DAT Line or the Software Reset for CMD Line is 1 , repeat Step (6).

13.3.6 External Interface Usage Example

Zynq-7000 devices provide two secure digital (SD) ports that support SD and SDIO devices (see Figure 13-7).

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X-Ref Target - Figure 13-7

SDx_CLK

CLK CMD DAT[3:0]

SD/SDIO Controller

SDx_CMD SDx_DAT[3:0]

SDIO Device Zynq Device

UG595_c13_07_031812

Figure 13-7:

SDIO Controller Device Wiring Diagram

13.3.7 Supported Configurations

The SD/SDIO controller supports operation in several configurations: Secure digital (SD) memory Secure digital input/output (SDIO)

Some SD card slots provide two additional pins: card detect (CDn) to signal the insertion or presence of a card and write protect (WPn) to report the position of the write protect switch on memory cards. These pins are usually pulled to GND when a card is detected or the card is write-protected. They need to be pulled up to the MIO I/O voltage with a 50 K resistor (see Figure 13-8).
X-Ref Target - Figure 13-8

VIO

SDx_CLK SDx_CMD SDx_DAT[3:0]

CLK CMD DAT[3:0]

SD Memory Card

SD/SDIO Controller
SDx_CDn SDx_WPn

Zynq Device

SD Card Slot
UG595_c13_08_020613

Figure 13-8:

SDIO Controller SD Card Detect and Write Protect Diagram

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13.3.8 Bus Voltage Translation

The SDIO power pin SDx_POW can be used to control power to the SDIO slots. Depending on the I/O voltage for the selected MIO bank and the SD/SDIO devices connected to the bus, it might be necessary to use a level translator.

13.4 SDIO Controller Media Interface Signals

The SDIO media interface signals are independently routed to the MIO pins or to a set of EMIO interface signals, see Table 13-1. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 13-1: SDIO Interface Signals Default Controller Input Value
0 ~ 0 SDIO 0 Command ~ ~ 0 SDIO 0 Data 0 ~ ~ 0 SDIO 0 Data 1 ~ ~ 0 SDIO 0 Data 2 ~ ~ 0 SDIO 0 Data 3 SDIO 0 Card Detect SDIO 0 Write Protect SDIO 0 Power Control SDIO 0 LED Control SDIO 0 Bus Voltage ~ ~ ~ ~ ~ Any pin except 7 and 8 Any pin except 7 and 8 Any even pin ~ ~ I I O ~ ~ 21, 33, 45 IO 20, 32, 44 IO 19, 31, 43 IO 18, 30, 42 IO 17, 29, 41 IO

MIO Pin Number

16, 28, 40

EMIO Signal I/O

IO

SDIO Interface

Name
EMIOSDIO0CLKFB EMIOSDIO0CLK EMIOSDIO0CMDI EMIOSDIO0CMDO EMIOSDIO0CMDTN EMIOSDIO0DATAI0 EMIOSDIO0DATAO0 EMIOSDIO0DATATN0 EMIOSDIO0DATAI1 EMIOSDIO0DATAO1 EMIOSDIO0DATATN1 EMIOSDIO0DATAI2 EMIOSDIO0DATAO2 EMIOSDIO0DATATN2 EMIOSDIO0DATAI3 EMIOSDIO0DATAO3 EMIOSDIO0DATATN3 EMIOSDIO0CDN EMIOSDIO0WP EMIOSDIO0BUSPOW EMIOSDIO0LED EMIOSDIO0BUSVOLT[2:0]

I/O
I O I O O I O O I O O I O O I O O I I O O O

SDIO 0 Clock

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Table 13-1:

SDIO Interface Signals (Contd) Default Controller Input Value

0 ~ 0 ~ ~ 0

MIO Pin Number

12, 24, 36, 48

EMIO Signal I/O

IO

SDIO Interface

Name
EMIOSDIO1CLKFB EMIOSDIO1CLK EMIOSDIO1CMDI EMIOSDIO1CMDO EMIOSDIO1CMDTN EMIOSDIO1DATAI0

I/O
I O I O O I O O I O O I O O I O O I I O O O

SDIO 1 Clock

SDIO 1 Command

11, 23, 35, 47

IO

SDIO 1 Data 0

~ ~ 0

10, 22, 34, 46

IO

EMIOSDIO1DATAO0 EMIOSDIO1DATATN0 EMIOSDIO1DATAI1

SDIO 1 Data 1

~ ~ 0

13, 25, 37, 49

IO

EMIOSDIO1DATAO1 EMIOSDIO1DATATN1 EMIOSDIO1DATAI2

SDIO 1 Data 2

~ ~ 0

14. 26, 38, 50

IO

EMIOSDIO1DATAO2 EMIOSDIO1DATATN2 EMIOSDIO1DATAI3

SDIO 1 Data 3 SDIO 1 Card Detect SDIO 1 Write Protect SDIO 1 Power Control SDIO 1 LED Control SDIO 1 Bus Voltage

~ ~

15, 27, 39, 51 Any pin except 7 and 8 Any pin except 7 and 8

IO I I O ~ ~

EMIOSDIO1DATAO3 EMIOSDIO1DATATN3 EMIOSDIO1CDN EMIOSDIO1WP EMIOSDIO1BUSPOW EMIOSDIO1LED EMIOSDIO1BUSVOLT[2:0]

~ ~ ~

Any odd pin ~ ~

13.4.1 SDIO EMIO Considerations

The SDIO interfaces are enabled through the MIO as well as the EMIO interface. They are mutually exclusive in that once you route the interface through the MIO it no longer is available via the EMIO. If the designer chooses to use the EMIO interface for SDIO due to other MIO priorities, the designer should know that the maximum operating frequency for SDIO via EMIO is limited. The PL connectivity should connect the EMIO signals directly to the SelectIO pins. Additionally, it might be necessary to restrict the SDIO to operate in full or low speed modes, refer to the data sheet for frequency and timing values.

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General Purpose I/O (GPIO)

14.1 Introduction
The general purpose I/O (GPIO) peripheral provides software with observation and control of up to 54 device pins via the MIO module. It also provides access to 64 inputs from the Programmable Logic (PL) and 128 outputs to the PL through the EMIO interface. The GPIO is organized into four banks of registers that group related interface signals. Each GPIO is independently and dynamically programmed as input, output, or interrupt sensing. Software can read all GPIO values within a bank using a single load instruction, or write data to one or more GPIOs (within a range of GPIOs) using a single store instruction. The GPIO control and status registers are memory mapped at base address 0xE000_A000 .

14.1.1 Features
Key features of the GPIO peripheral are summarized as follows: 54 GPIO signals for device pins (routed through the MIO multiplexer)

Outputs are 3-state capable 64 Inputs, 128 outputs (64 true outputs and 64 output enables)

192 GPIO signals between the PS and PL via the EMIO interface

The function of each GPIO can be dynamically programmed on an individual or group basis Enable, bit or bank data write, output enable and direction controls Programmable interrupts on individual GPIO basis

Status read of raw and masked interrupt Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both)

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14.1.2 Block Diagram

X-Ref Target - Figure 14-1

GPIO Bank 0

32b

x 54

MIO GPIO Bank 1

22b

GPIO Bank 2

32b

EMIOGPIOI[31:0], EMIOGPIOO[31:0], EMIOGPIOTN[31:0]

EMIO Interface to PL

GPIO Bank 3

32b

EMIOGPIOI[63:32], EMIOGPIOO[63:32], EMIOGPIOTN[63:32]

UG585_c14_01_022212

Figure 14-1:

GPIO Block Diagram

As shown in Figure 14-1, the GPIO module is divided into four banks: Bank0: 32-bit bank controlling MIO pins[31:0] Bank1: 22-bit bank controlling MIO pins[53:32]

Note: Bank1 is limited to 22 bits because the MIO has a total of 54 pins.
Bank2: 32-bit bank controlling EMIO signals[31:0] Bank3: 32-bit bank controlling EMIO signals[63:32]

The GPIO is controlled by software through a series of memory-mapped registers. The control for each bank is the same, although there are minor differences between the MIO and EMIO banks due to their differing functionality.

14.1.3 Notices
7z010 CLG225 Device
The 7z 01 0 CLG225 device reduces the available MIO pins to 32 as shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Thus, in this device, the only GPIO pins that are available for MIO are 15:0, 39:28, 48, 49, 52, and 53. The other MIO pins are unconnected and should not be used. All EMIO signals are available.

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MIO Considerations
Banks 0 and 1 of the GPIO peripheral module are routed to device pins through the MIO module. Refer to section 2.5 PS-PL MIO-EMIO Signals and Interfaces for a complete description of MIO operation. Primary control of the MIO is achieved through the slcr.MIO_PIN_xx registers. Please note the following: The user must choose the proper Type of I/O using the IO_Type, PULLUP, DisableRcvr, and Speed fields according to the users system. The user must select the GPIO module through the multiplexor control fields L0_SEL, L1_SEL, L2_SEL, and L3_SEL. Note that each I/O pin can be individually selected. TRI_ENABLE should be set to 0 . This enables the GPIO to control the 3-state mode of the I/O. If TRI_ENABLE is set to 1 in the MIO, then the output driver will be 3-stated regardless of GPIO settings.

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14.2 Functional Description

14.2.1 GPIO Control of Device Pins
This section describes the operation of Bank0 and Bank1 (see Figure 14-2).
X-Ref Target - Figure 14-2

INT_MASK INT_DIS INT_EN

Read

INT_STAT

Write-1-to-clear

INT_TYPE INT_POLARITY INT_ANY Interrupt Detection Logic

Clr D Q

IRQ #52 to GIC

INT State

DATA_RO

Input

MIO DATA MASK_DATA_LSW MASK_DATA_MSW EMIO DIRM OEN

Output Enable Output

(Banks 0 & 1)

GPIO Device Pad

or

(Banks 2 & 3)

MIO Device I/O Buffers and Pins (Banks 0 & 1)

UG585_c14_02_022712

Figure 14-2:

GPIO Channel

Software configures the GPIO as either an output or input. The DATA_RO register always returns the state of the GPIO pin regardless of whether the GPIO is set to input (OE signal false) or output (OE signal true). To generate an output waveform, software repeatedly writes to one or more GPIOs (usually using the MASK_DATA register). Applications might need to switch more than one GPIO at the same time (less a small amount of inherent skew time between two I/O buffers). In this case, all of the GPIOs that need to be switched simultaneously must be from the same 16-bit half-bank (i.e., either the most-significant 16 bits or the least-significant 16 bits) of GPIOs to enable the MASK_DATA register to write to them in one store instruction.

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GPIO bank control (for Bank0 and Bank1) is summarized as follows: DATA_RO: This register enables software to observe the value on the device pin. If the GPIO signal is configured as an output, then this would normally reflect the value being driven on the output. Writes to this register are ignored.

Note: If the MIO is not configured to enable this pin as a GPIO pin, then DATA_RO is

unpredictable because software cannot observe values on non-GPIO pins through the GPIO registers. DATA: This register controls the value to be output when the GPIO signal is configured as an output. All 32 bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. MASK_DATA_LSW: This register enables more selective changes to the desired output value. Any combination of up to 16 bits can be written. Those bits that are not written are unchanged and hold their previous value. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. This register avoids the need for a read-modify-write sequence for unchanged bits. MASK_DATA_MSW: This register is the same as MASK_DATA_LSW, except it controls the upper16 bits of the bank.

DIRM: Direction Mode. This controls whether the I/O pin is acting as an input or an output. Since the input logic is always enabled, this effectively enables/disables the output driver. When DIRM[x]== 0 , the output driver is disabled. OEN: Output Enable. When the I/O is configured as an output, this controls whether the output is enabled or not. When the output is disabled, the pin is 3-stated. When OEN[x]==0 , the output driver is disabled.

Note: If MIO TRI_ENABLE is set to 1, enabling 3-state and disabling the driver, then OEN is ignored and the output is 3-stated.

14.2.2 EMIO Signals

This section describes the operation of Bank2 and Bank3 (see Figure 14-2). The register interface for the EMIO banks is the same as for the MIO banks described in the previous section. However, the EMIO interface is simply wires between the PS and the PL, so there are a few differences: The inputs are wires from the PL and are unrelated to the output values or the OEN register. They can be read from the DATA_RO register when DIRM is set to 0, making it an input. The output wires are not 3-state capable, so they are unaffected by OEN. The value to be output is programmed using the DATA, MASK_DATA_LSW, and MASK_DATA_MSW registers. DIRM must be set to 1, making it an output. The output enable wires are simply outputs from the PS. These are controlled by the DIRM/OEN registers as follows: EMIOGPIOTN[x] = DIRM[x] & OEN[x]

The EMIO I/Os are not connected to the MIO I/Os in any way. The EMIO inputs cannot be connected to the MIO outputs and the MIO inputs cannot be connected to the EMIO outputs. Each bank is independent and can only be used as software observable/controllable signals.

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14.2.3 Bank0, Bits[8:7] are Outputs

GPIO bits[8:7] of Bank0 correspond to package pins that are used to control the voltage mode of the I/O buffers themselves during reset. Therefore, they must be driven by the external system according to the proper voltage mode. To prevent them from being driven by other system logic, they cannot be used as general purpose inputs. These bits can be used as general purpose outputs since the output is disabled at reset. The system can start using these as outputs after the voltage mode has been read during system boot.

14.2.4 Interrupt Function

The interrupt detection logic monitors the GPIO input signal. The interrupt trigger can be a positive edge, negative edge, either edge, Low-level or High-level. The trigger sensitivity is programmed using the INT_TYPE, INT_POLARITY and INT_ANY registers. If an interrupt is detected, the GPIO's INT_STAT state is set true by the interrupt detection logic. If the INT_STAT state is enabled (unmasked), then the interrupt propagates through to a large OR function. This function combines all interrupts for all GPIOs in all four banks to one output (IRQ ID#52) to the interrupt controller. If the interrupt is disabled (masked), then the INT_STAT state is maintained until cleared, but it does not propagate to the interrupt controller unless the INT_EN is later written to disable the mask. As all GPIOs share the same interrupt, software must consider both INT_MASK and INT_STAT to determine which GPIO is causing an interrupt. The interrupt mask state is controlled by writing a 1 to the INT_EN and INT_DIS registers. Writing a 1 to the INT_EN register disables the mask allowing an active interrupt to propagate to the interrupt controller. Writing a 1 to the INT_DIS register enables the mask. The state of the interrupt mask can be read using the INT_MASK register. If the GPIO interrupt is edge sensitive, then the INT state is latched by the detection logic. The INT latch is cleared by writing a 1 to the INT_STAT register. For level-sensitive interrupts, the source of the interrupt input to the GPIO must be cleared in order to clear the interrupt signal. Alternatively, software can mask that input using the INT_DIS register. The state of the interrupt signal going to the interrupt controller can be inferred by reading the INT_STAT and INT_MASK registers. This interrupt signal is asserted if INT_STAT=1 and INT_MASK= 0 . GPIO bank control is summarized as follows: INT_MASK: This register is read-only and shows which bits are currently masked and which are un-masked/enabled. INT_EN: Writing a 1 to any bit of this register enables/unmasks that signal for interrupts. Reading from this register returns an unpredictable value. INT_DIS: Writing a 1 to any bit of this register masks that signal for interrupts. Reading from this register returns an unpredictable value. INT_STAT: This registers shows if an interrupt event has occurred or not. Writing a 1 to a bit in this register clears the interrupt status for that bit. Writing a 0 to a bit in this register is ignored. INT_TYPE: This register controls whether the interrupt is edge sensitive or level sensitive.

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INT_POLARITY: This register controls whether the interrupt is active-Low or active High (or falling-edge sensitive or rising-edge sensitive). INT_ON_ANY: If INT_TYPE is set to edge sensitive, then this register enables an interrupt event on both rising and falling edges. This register is ignored if INT_TYPE is set to level sensitive. Interrupt Trigger Settings Type
Rising edge-sensitive Falling edge-sensitive Both rising- and falling edge-sensitive Level sensitive, asserted High Level sensitive, asserted Low

Table 14-1:

gpio.INT_TYPE_0
1 1 1 0 0

gpio.INT_POLARITY_0
1 0 X 1 0

gpio.INT_ANY_0
0 0 1 X X

14.3 Programming Guide

The GPIO Controller has four banks, two each for MIO and EMIO. Each GPIO pin can be programmed individually. Multiple pins can be programmed with a single write as described in section 14.2.1 GPIO Control of Device Pins.

14.3.1 Start-up Sequence

Main Example: Start-up Sequence
1. 2. 3. 4. 5. Resets: The reset options are described in section 14.4.2 Resets. Clocks: The clocks are described in section 14.4.1 Clocks. GPIO Pin Configurations: Configure pin as input/output is described in section 14.3.2 GPIO Pin Configurations. Write Data to GPIO Output pin: Refer to example in section 14.3.3 Writing Data to GPIO Output Pins. Read Data from GPIO Input pin: Refer to example in section 14.3.4 Reading Data from GPIO Input Pins .

14.3.2 GPIO Pin Configurations

Each individual GPIO pin can be configured as input/output. However, bank0 [8:7] pins must be configured as outputs. Refer to section 14.2.3 Bank0, Bits[8:7] are Outputs for further details.

Example: Configure MIO pin 10 as an output

1. 2. Set the direction as output: Write 0x0000_0400 to the gpio.DIRM_0 register. Set the output enable : Write 0x0000_0400 to the gpio.OEN_0 register.

Note: The output enable has significance only when the GPIO pin is configured as an output.

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Example: Configure MIO pin 10 as an input

1. Set the direction as input : Write 0x0 to the gpio.DIRM_0 register. This sets gpio.DIRM_0[10] = 0.

14.3.3 Writing Data to GPIO Output Pins

For GPIO pins configured as outputs, there are two options to program the desired value. Option 1: Read, modify, and update the GPIO pin using the gpio.DATA_0 register. Example: Set GPIO output pin 10 using the DATA_0 register. 1. 2. 3. Read the gpio.DATA_0 register: Read gpio.DATA_0 register to the reg_val variable. Modify the value: Set reg_val [10] =1 . Write updated value to output pin: Write reg_val to the gpio.DATA_0 register.

Option 2: Use the MASK_DATA_x_MSW/LSW registers to update one or more GPIO pins. Example: Set output pins 20, 25, and 30 to 1 using the MASK_DATA_0_MSW register. 1. 2. 3. Generate the mask value for pins 20, 25, and 30: To drive pins 20, 25 and 30, 0xBDEF is the mask value for gpio.MASK_DATA_0_MSW [MASK_0_MSW]. Generate the data value for pins 20, 25, 30: To drive 1 on pins 20, 25, and 30, 0x4210 is the data value for gpio.MASK_DATA_0_MSW [DATA_0_MSW]. Write the mask and data to the MASK_DATA_x_MSW register: Write 0xBDEF_4210 to the gpio.MASK_DATA_0_MSW register.

14.3.4 Reading Data from GPIO Input Pins

For GPIO pins configured as inputs, there are two options to monitor the input. Option 1: Use the gpio.DATA_RO_x register of each bank. Example: Read the state of all GPIO input pins in bank 0 using the DATA_RO_0 register. 1. Read Input Bank 0: Read the gpio.DATA_0 register.

Option 2: Use interrupt logic on input pins (refer to section 14.2.4 Interrupt Function). Example: Configure MIO pin 12 to be triggered as rising edge. 1. 2. 3. 4. Set the trigger as a rising edge: Write 1 to gpio.INT_TYPE_0 [12]. Write 1 to gpio.INT_POLARITY_0 [12]. Write 0 to gpio.INT_ANY_0 [12]. Enable interrupt: Write 1 to gpio.INT_EN_0 [12]. Status of Input pin: gpio.INT_STAT_0 [12] =1 implies that an interrupt event occurred. Disable interrupt: Write 1 to gpio.INT_DIS_0 [12].

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14.3.5 Register Overview

An overview of the GPIO registers is shown in Table 14-2 (also refer to section 14.2.1 GPIO Control of Device Pins). Details of registers are provided in Appendix B, Register Details. Table 14-2: GPIO Register Overview Function
Data Reads and Data Writes

Register Name
gpio.MASK_DATA_{3:0}_{MSW,LSW} gpio.DATA_{3:0} gpio.DATA_{3:0}_RO gpio.DIRM_{3:0} gpio.OEN_{3:0} gpio.INT_MASK_{3:0} gpio.INT_EN_{3:0} gpio.INT_DIS_{3:0}

Overview
Bit masked data output writes. 32-bit data output write 32-bit data read of inputs Direction Output Enable Interrupt Mask Interrupt Enable Interrupt Disable Interrupt Status Interrupt Type Interrupt Polarity Interrupt Any

Type
Mixed R/W RO R/W R/W RO WO WO WTC RW RW RW

I/O Buffer Control

Interrupt Controls

gpio.INT_STAT_{3:0} gpio.INT_TYPE_{3:0} gpio.INT_POLARITY_{3:0} gpio.INT_ANY_{3:0}

14.4 System Functions

The controller clocks and resets are described in this section. All of the interrupts generated in the GPIO controller are routed to IRQ 52. The GPIO I/O signals are routed to either the MIO or EMIO.

14.4.1 Clocks
The controller is clocked by the CPU_1x clock from the APB interface. All outputs and input sampling is done using the CPU_1x clock.

14.4.2 Resets
The controller is reset by the slcr.GPIO_RST_CTRL [GPIO_CPU1X_RST] bit. Refer to chapter 26, Reset System, for more information. This reset only affects the bus interface, not the controller logic itself.

14.4.3 Interrupts
The controller interrupts are explained in section 14.2.4 Interrupt Function. The controller asserts IRQ # 52 to the GIC. A programming example is described in section 14.3.4 Reading Data from GPIO Input Pins .

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14.5 I/O Interface

14.5.1 MIO Programming
Bank 0 and Bank 1 pins are routed through the MIO. These pins can be configured as GPIO using the slcr.MIO_PIN_XX register.

Example: Configure MIO pin 6 as a GPIO signal

1. 2. 3. 4. 5. 6. Select MIO pin as GPIO: Set L0_SEL, L1_SEL, L2_SEL, L3_SEL = 0 . Set TRI_ENABLE = 0 . LVCMOS18 (refer to the register definition for other voltage options). Slow CMOS edge. Enable internal pull-up resistor. Disable HSTL receiver.

Note: If TRI_ENABLE=1, then the output is 3-stated regardless of any GPIO settings. If TRI_ENABLE= 0 , then 3-state is controlled by the gpio.OEN_x register.

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USB Host, Device, and OTG Controllers

15.1 Introduction
The USB controller is capable of fulfilling a wide range of applications for USB 2.0 implementations as a host, a device, or On-the-Go. Two identical controllers are in the Zynq-7000 device. Each controller is configured and controlled independently. The USB controller I/O uses the ULPI protocol to connect external ULPI PHY via the MIO pins. The ULPI interface provides an 8-bit parallel SDR data path from the controllers internal UTMI-like bus to the PHY. The ULPI interface minimizes device pin count and is controlled by a 60 MHz clock output from the PHY. USB is a cable bus that supports data exchange between a host device and a wide range of computer peripherals. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals remain operational. The USB controller in USB 2.0 Host compatible with the EHCI specification with some enhancements and minor deviations. The OTG operating mode software switches the controller between Idle and either Device or Host mode as needed by the application using the Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller is designed to make efficient use of the system resources in an SoC design. The DMA engine is responsible for moving USB transaction data between the Rx/Tx FIFOs and system memory. The FIFOs are used to buffer the high-speed USB data rates with periodic delays associated with the PS Interconnect data transfers. The EHCI-compatible host controller is a schedule driven environment for data transfers of periodic (interrupt and isochronous) and asynchronous (control and bulk) types. Device mode includes a simple pair of descriptors to respond to USB data transfers in a timely manner between the software and USB. The transfer descriptors of the host schedules and device endpoints control the DMA engine to move data between the 32-bit AHB master system bus interface and the Rx and Tx data FIFOs that respond in real-time to the USB. The controller makes strategic use of software for tasks that do not require time-critical responses. This approach reduces the amount of hardware logic. At the same time, the controller includes hardware assistance logic to enable the controller to respond quickly to USB events and simplify the software.

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15.1.1 Features
The USB controller has the following key features: USB 2.0 High Speed Host controller (480 Mb/s).

Intel EHCI software programming model. Up to 12 Endpoint: Control Endpoint plus 11 configurable Endpoints Embedded Transaction Translator to support FS/LS in Host mode. Host Negotiation Protocol (HNP). Session Request Protocol (SRP). Control, Bulk, Interrupt, Isochronous AHB Bus Master. Transfers data between system memory and controller FIFOs. Processes transfer descriptors for Device Endpoints and Host Schedules. Interprets USB packets Responds in real-time based on controller status 8-bit parallel data pass-thru bus Translates Rx and Tx transfers between ULPI I/O interface and a UTMI-like interface. Bridge between the protocol engine and the ULPI interface. Rx and Tx commands 8-bit SDR data plus clock, direction, next, stop signals. 12 ULPI PHY signals via MIO pins. Clocked by PHY in Clock-out mode. Viewport access to ULPI PHY registers 4 signals per controller via EMIO.

USB 2.0 HS and FS Device controller.

USB 1.1 legacy FS/LS.

On-the-Go, OTG 1.3 supplement.

All USB Transaction types

Local DMA Engine.

Protocol Engine

Port/Transceiver Controller

ULPI Link Wrapper

ULPI I/O interface

Host port indicator, power select and power fail indicator signals.

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15.1.2 Operating Modes

The USB controller can operate in the modes shown in Figure 15-1.
X-Ref Target - Figure 15-1

Host Mode
Zynq PHY
Device or Downstream Hub

OTG
Zynq HNP SRP PHY

HS: EHCI FS/LS: TT in EHCI

Device Mode
Zynq
HS, FS

PHY

Host or Upstream Hub

Another OTG Device

UG585_c15_30_030712

Figure 15-1:

USB Controller Operating Modes

Host mode. In host mode, the software includes driver-layer programming to discover and enumerate the bus, manage PHY operations, and setup the periodic and asynchronous schedules of transfer descriptors.

EHCI software model except as described in section 15.11 EHCI Implementation.

Device mode. In device mode, the controller responds to host commands. Software can include driver-layer programming to respond, as a single- or multi-function device, to the upstream commands. On-the-Go. The OTG software switches between Host and Device modes based on the Host Negotiated Protocol (HNP) and the Session Request Protocol (SRP). Once the controller is in device or host mode, it has all the functionality of the selected mode.

15.1.3 Hardware System Viewpoint

The USB controllers are integrated into the PS IOP to bridge between the PS interconnect and an external ULPI PHY. The controllers registers are memory mapped and the local DMA engine initiates reads and writes to system memory. The ULPI signals flow through the MIO. There are sideband signals (port indicators and power controls) that flow through the EMIO interface where they are normally routed to PL SelectIO pins. The system-level viewpoint is shown in Figure 15-2.

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X-Ref Target - Figure 15-2

MIO
IRQ ID# {53, 76}
Master port ULPI Data, flow control

Interconnect

AHB

USB Controllers

USB {0, 1} CPU 1x clock USB {0, 1} CPU 1x reset

Slave port

EMIO
Control Registers
Port Indicator, Power Control

Interconnect

APB

UG585_c15_31_030713

Figure 15-2:

USB Hardware System Block Diagram

The two independent USB controllers have individual control and status registers. Each ULPI interface is independently enabled through the MIO. There are separate port indicator and power signals for each controller that are routed through the EMIO. The system functions are further described in section 15.15 System Functions.

System Interfaces
Each controller is an AHB bus master to the PS interconnect for DMA transfers. The control and status registers are accessed via the controllers APB slave interface. Each controller has its own reset input from the PS reset module and interrupt output to the interrupt controller, GIC. There is a ULPI clock input for each controller and a CPU_1x clock for the AMBA AHB and APB interfaces. Details are in section 15.15 System Functions.

ULPI I/O signals

The I/O signals are described in section 15.16 I/O Interfaces. The MIO pin muxing scheme is described, in general terms, in section 2.5 PS-PL MIO-EMIO Signals and Interfaces.

I/O Wiring
The ULPI interface on the MIO pins is an 8-bit SDR data bus that is augmented with port indicators and power control signals routed through the EMIO interface to the PL. The PS GPIO module, Chapter 14, General Purpose I/O (GPIO), can provide a PHY reset signal to the PHY. An I/O wiring diagram is shown in Figure 15-19 USB I/O Signal and PHY Wiring Diagram, page 427. Here is a summary of the I/O signals: ULPI via MIO. The controller interfaces to the external ULPI PHY via 12 MIO pins: 8 data I/Os, direction input, control input, clock input and a stop output. GPIO. A PS GPIO signal can be used to reset the external PHY.

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ULPI Pins

PL

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Port Indicator and Power Pins via EMIO. The USB port indicator outputs, power select output, and power fault input signals are routed through the EMIO to the SelectIO pins in the PL and external board logic.

15.1.4 Controller Block Diagram

The controller interfaces to the PS system memory on one side and an external ULPI PHY device on the USB side. A block diagram is shown in Figure 15-3. A detailed functional block is shown in section 15.1.9 Notices.
X-Ref Target - Figure 15-3

Zynq-7000 AP SoC USB Controller (Host and Device)

System Memory MIO PHY ULPI

AHB

DMA Engine
Rx & Tx FIFOs Dual-port RAM

Protocol Engine
Context Dual-port RAM

Port Controller Interface

Similar to UTMI+

ULPI Link Wrapper

UG585_c15_32_030713

Figure 15-3:

USB Controller Block Diagram

System Memory
The PS system memory is accessible to the DMA engine that holds transfer descriptors and data buffers. The system memory can be DDR, OCM and memory that is mapped in the PL. The system memory map is shown in section 4.1 Address Map. In this table, the USB controller is one of the Other Bus Masters, refer to the table footnotes.

DMA, Protocol Engines, Context and FIFOs

The DMA engine works with the Protocol engine to process endpoints, periodic elements, queue heads, and other transfer descriptors. Software writes these data structures into the system memory. The DMA engine fetches these data structures and copies them into the controllers local dual-ported RAM (DPRAM). The controller reads and writes the data structures in the DPRAM as the data structures are processed. The descriptors are written back to memory by the DMA engine when a transfer is complete. In addition to the context information of the data structures, the dual-port RAM is also used by the controller to implement Rx and Tx data FIFOs. These FIFOs decouple the system processor memory bus transfers from the real-time requirements of the USB. The use of the FIFOs differs between host and device mode operation. In Host mode, a single data channel is maintained in each direction through the dual-port RAM. In Device mode, multiple FIFO channels are maintained for each of the active device endpoints and their direction(s).

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Port Transceiver Controller

The port transceiver controller provides suspend/resume and, for device mode, chirp control functions. The port transceiver controller is fairly simple because the 8-bit data bus of the protocol engine is passed-through to the 8-bit ULPI and the entire back-end of the USB controller works synchronously to the 60 MHz USB clock from the PHY.

ULPI Link Wrapper

The protocol engine includes an internal bus that is similar to UTMI+. The ULPI wrapper provides an bridge between this bus similar to UTMI+ and the ULPI interface. This is transparent to the user. The ULPI Link wrapper passes-through packet data and interprets Rx commands as well as send Tx commands. The controller includes a PHY Viewport function that enables software to read and write PHY registers using a simple address/data combination in the usb.VIEWPORT register.

ULPI Rx/Tx Commands

The ULPI Rx commands are initiated by the PHY to set status bits to give software visibility to PHY events. The commands set controller status bits. The Tx commands are initiated by register writes by software to control PHY functions. These commands are defined by the ULPI specification.

ULPI PHY Viewport

The ULPI viewport provides a mechanism for software to read and write PHY registers with explicit control of the address and data. An interrupt is generated when a transaction is complete, including when the requested read data is available.

Programmable Timers
There are two independent general-purpose timers that can be used to generate a timeout or to measure time related activities. The programmable timers should not be confused with the controllers interval timers which are used by the controller to generate frame and microframe intervals and to generate strobes for the host controller scheduler. The programmable timers are described in section 15.2.6 General Purpose Timers.

Software Programming Interface

In addition to maintaining data and buffer structures in system memory, the software reads and writes the control and status registers. The CPU environment that executes the software is described in Chapter 15, USB Host, Device, and OTG Controllers. The controller can generate interrupts cause by the DMA and Protocol engine activities, the PHY, and other controller functions. The interrupts are summarized in Table 15-2 USB Interrupt and Status Register Bits. The system will include either a Host Controller Driver (HCD) or a Device Controller Driver (DCD). There may be additional of software to support the OTG functions.

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Control and Status Registers

The control and status registers include constants, configuration and operational/status for EHCI compatibility (Host mode) and non-EHCI functions (Device, OTG and enhanced Host mode). The registers are summarized in section 15.3.4 Register Overview.

Clocks
The ULPI interface and Protocol engine are clocked by the 60 MHz input on the ULPI interface (PHY clock output). The AHB interface is clocked by the CPU_1x clock. The clock domain crossing between the CPU_1x clock and the 60 MHz ULPI PHY clock for the Protocol engine is at the dual-port RAM.

Resets
There are several different types of resets associated with the USB controller, these are further discussed in section 15.15.2 Reset Types. Controller Resets

PS Reset System (full controller reset), usb.USBCMD [RST] bit (partial controller reset useful for OTG).

ULPI PHY reset (output from PS GPIO). USB Bus Resets

Auto-Reset feature in OTG mode. USB reset control transfer.

15.1.5 Configuration, Control and Status

Software manages the controller itself (configuration and control) and a consistent set of data structures and memory buffers for USB transactions. There are two data structure models (host and data) and three controller modes (host, device, and OTG). OTG uses either the host or device mode. The controller registers are outlined in Table 15-1 USB Controller Register Overview.

15.1.6 Data Structures

The controller processes descriptors to facilitate FS/LS and HS USB operations. Device and host modes use descriptors in very different ways. The models are illustrated in Figure 15-4.

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X-Ref Target - Figure 15-4

Endpoint Queue Heads

Host Schedules (EHCI)

Periodic Frame List
Frame n Elements

Queue Head List

dQH Endpoint 11 IN

Programmable number of elements

Aysnchronous Queue Heads

Insert and Remove QHs as needed

Queue Head a Queue Head b Queue Head b

Device Responds to Host Requests

Maintain Queue Head List

Frame 3 Elements EndPoint 1 OUT Frame 2 Elements EndPoint 0 IN Frame 1 Elements EndPoint 0 OUT Frame 0 Elements FRINDEX pointer is advanced for every USB Frame

Round Robin as Bandwidth allows.

UG585_c15_33_030713

Figure 15-4:

USB Endpoint Descriptors (device mode) and Schedules (host mode)

Device Mode
As requested by the host, the Device Controller Driver (DCD) sets up descriptors for endpoints and manages the real-time needs of the endpoints. The high-speed data transfers between memory and ULPI are managed by the controller using queue heads and transfer descriptors. The results of each transfer is reviewed by DCD to take appropriate action. Device Endpoints. The device controller includes a simple descriptor model to enable the controller to quickly respond to host requests. Each of the 12 endpoints has two device Queue Heads (dQH); one for IN and the other for OUT transfer types. There are a total of 24 device dQHs. An endpoint data transfer in defined with one dQH and one or more linked list of device Transfer Descriptors (dTD). An example is shown in Figure 15-13.

Host Mode
Host Schedules. The Host Controller Driver (HCD) maintains two types of transaction schedules to generate USB traffic: periodic (isochronous/interrupt) and asynchronous (bulk/control). The Periodic schedule is a list of high to low priority-order periodic transfers. An element in the periodic frame list is executed at the start of every frame (SOF). The list includes elements that indicate when to execute (periodic interval) and what to execute. An example is shown in Figure 15-15. The asynchronous schedule is a circular loop of Queue Heads that point to transfer descriptors that are processed in a round-robin priority. Within each microframe, the asynchronous schedule is executed after the periodic schedule is finished. An example is shown in Figure 15-16.

Link-list Concept
The host and device controllers use link-list descriptors to manage transfers to and from memory buffers. The concept is shown in Figure 15-5. The first Transfer Descriptors (TD) is pointed to by a

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Queue Head (QH). Each dTD can point to another dTD (using next dTD pointer) or terminate the linked list by setting its (T) bit = 1. The controller maintains a local, working copy of the dQH that it overlays with the one or more dTDs as the transaction request is processed. After each dTD transfer is complete, the dTD overlay is written back to the system memory with transfer results (status). While a transfer is in progress, the overlay area of the dQH in controller memory is used as a staging area for the dTDs.
X-Ref Target - Figure 15-5

QH

First TD

Read TD

Last TD Write Result

T=1

Completed TDs

Current TD

TDs Queued and Ready

UG585_c15_34_030713

Figure 15-5:

USB Controller Link-list Concept

15.1.7 Implementation Summary

There are EHCI enhancements to support the embedded Transaction Translator and hardware assistance features to support OTG. Here is a summary of special features, enhancements, deviations and unsupported features. EHCI Enhancements and Deviations, section 15.11 EHCI Implementation. Hardware Assistance Features for OTG, section 15.14.1 Hardware Assistance Features. Embedded Transaction Translator (no separate companion controller hardware), section 15.11.2 Embedded Transaction Translator. The AHB interface is a master-only and used by the DMA controller (no PCI registers). The ULPI Carkit feature is not supported.

15.1.8 Documentation
Scope of TRM
The Zynq-7000 Technical Reference Manual (TRM) describes hardware functionality and register-level software programming for Host controller mode drivers (HCD) and Device controller mode drivers (DCD). Guidance for the upper software layers, including device classes and applications, are beyond the scope of the TRM.

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Documents and Specifications

The reader should be familiar of USB technology and access to the following documents. These documents are mentioned in the text and are listed in Third-Party IP and Standards Documents in Appendix A.

Zynq-7000 AP SoC Documents

TRM for all Zynq-7000 series; UG585 . Architecture and register-level programming. Data Sheet for 7z010 and 7z020 devices; DS187 . Electrical specifications. Data Sheet for 7z030, 7z045 and 7z100 devices; DS191 . Electrical specifications. Errata Sheets for all devices; ENxxx (multiple). Related AR list, AR47916 .

7-Series FPGA Documents

Refer to the list in Appendix A.3.8.

USB Specifications

USB 2.0 Specification UTMI+ Low Pin Interface (ULPI) Specification Enhanced Host Controller Interface (EHCI) Specification for Universal Serial Bus

Chapter Nomenclature
Refer to the USB 2.0 Specification, Chapter 2 Terms and Abbreviations. Xilinx Corporate glossary includes general terms. Chapter-specific terms:

DCD means device controller driver. This is the device driver software used in device mode. HCD means host controller driver. This is the device driver software used in host mode. The term Frame applies to FS/LS mode. Microframe applies to HS mode. (Micro)frame applies to FS/LS and HS modes. In the USB Controller chapter, DWord means 32 bits. In the rest of the PS, a word is defined to mean 32 bits. There are two dual-purpose registers (for host and device mode) listed in Table 15-1. The usb.ASYNCLISTADDR_ENDPOINTLISTADDR register is referred to as usb.ASYNCLISTADDR_ when discussing Host mode and usb._ENDPOINTLISTADDR when discussing Device mode. The usb.PERIODICLISTBASE_DEVICEADDR register is similar.

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15.1.9 Notices
7z010 CLG225 Device
The 7z010 CLG225 device supports 32 MIO pins as shown in the MIO table in section MIO-at-a-Glance Table in . Only one USB interface is available in the 7z010 CLG225 device. If USB and GigE are required, the GigE I/O signals must interface through the EMIO.

15.1.10 Chapter Overview

Functional Descriptions and Programming Guides
The USB controller chapter includes multiple sections of introductions, functional descriptions and programming guides. The functional descriptions explain controller functionality and includes register programming information that is related to hardware functions. Content for All Modes

15.1 Introduction 15.2 Functional Description 15.3 Programming Overview and Reference 15.15 System Functions 15.16 I/O Interfaces 15.4 Device Mode Control 15.5 Device Endpoint Data Structures 15.6 Device Endpoint Packet Operational Model 15.7 Device Endpoint Descriptor Reference 15.8 Programming Guide for Device Controller 15.10 Host Mode Data Structures 15.11 EHCI Implementation 15.12 Host Data Structures Reference 15.13 Programming Guide for Host Controller 15.14 OTG Description and Reference

Device Operating Mode

Host Operating Mode

OTG Operating Mode

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15.2 Functional Description

This section generally applies to both device and host modes.

15.2.1 Controller Flow Diagram

The controller flow diagram in Figure 15-6 shows the USB data transfer flows, the descriptor flows, and the interface to software.
X-Ref Target - Figure 15-6

System Memory

DMA Engine

AHB Master

* Bus Interface * Data Movement * Host: Periodic and Async Schedules * Device: Endpoint Queue Head

Microprocessor(s)

Dual-port RAM Tx and Rx FIFO

channels

DMA

DMA

IRQ to GIC

Context (QH and TD data structures)

Interrupts

Protocol Engine
* Interval Timers * Error Handling * CRC Handling * Bus Handshake Generation

APB Slave

Control and Status Registers

Port Controller
* Port Status and Control * Transceiver Interface Logic

ULPI Master

ULPI Interface
UG585_c15_35_030713

Figure 15-6:

USB Controller Flow Diagram

15.2.2 DMA Engine

Data Transfers
In host mode, the data structures are defined by the EHCI specification and represent queues of periodic and asynchronous transfers to be performed by the host controller including the split transaction requests that allow the controller to direct packets to FS/LS devices that are downstream of an external HS hub or root hub. Host mode uses the queue head (QH), queue element transfer descriptor (qTD), isochronous transfer descriptor (iTD), split transaction isochronous transfer descriptor (siTD) and the periodic frame span transversal node (FSTN) data structures. In device mode, the data structures are simpler and consist of device queue heads (dQH) and device transfer descriptors (dTD) that are used in a linked-list fashion.

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X-Ref Target - Figure 15-7

The DMA engine is a 32-bit bus master on the AHB interface to access the PS system interconnect.

PS Interconnect

APB
Slave

Control and Status Registers

DMA Traffic DMA Arbitrator

* Packet Movement * Host: HS * Device: HS and FS Traffic Context Registers

DMA Control
Host Mode: * EHCI * Scheduler Device Mode: * Prime/Unprime Control * Endpoint Manager

* Burst Movement * Bus State * FIFO Arbitration PS Interconnect AHB

Master

DMA Context
* Context Storage Dual-port RAM * Byte Count ALU * Update Logic * Address Incrementing Dual-port RAM
Tx FIFO Rx FIFO

Protocol Engine

Port Controller

ULPI Link Wrapper

ULPI

UG585_c15_36_030713

Figure 15-7:

USB DMA Controller Block Diagram

15.2.3 Protocol Engine

The protocol engine parses the USB tokens, generates response packets and performs error checking functions. Data packets are passed through the transfer buffers, the DMA engine and system memory. The controller does not provide a hardware-based Transaction Translator for Low and Full speed operations. Instead, the DMA and Protocol engines are used to support this functionality as described in section 15.11.2 Embedded Transaction Translator.
X-Ref Target - Figure 15-8

APB
Slave

Control and Status Registers

Protocol Engine Data Path

* Muxing / Pipelining * FIFO Control * CRC

Protocol Engine Control

* Handshake Decision Logic * Datapath Control Device: * Prime Endpoint Logic * PID Tracking Host: * SOF Generation * PID Generation

Interval Timers
* Bus Timeout * Inter-Packet Delay

Tx FIFO Rx FIFO

Port Controller

Timebase Interval Timers

AHB
Master

DMA Controller

ULPI Link Wrapper

ULPI
I/O Interface

* Generate Frame/MicroFrame * Generate Scheduler Timing Strobes

UG585_c15_37_030713

Figure 15-8:

USB Protocol Engine Block Diagram

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The protocol engine is responsible for all error checking, check field generation, formatting all the handshake, Ping and data response packets on the bus, and for generating signals that are needed based on a USB based time frame.

Protocol Engine Functions

The protocol engine contains several functions for both host and device mode: The token state machines track all of the tokens on the bus and filters the traffic based on the address and endpoint information in the token. The CRC5 and CRC16 CRC generator/checker circuits check and generate the CRC check fields for the token and data packets. The data and handshake state machines generate any responses required on the USB and move the packet data through the dual port RAM to the DMA controller. The Interval Timers provide timing strobes that identify important bus timing events: the bus timeout interval, the microframe interval, the start of frame interval, and the bus reset, resume, and suspend intervals. Reports all transfer status to the DMA engine.

15.2.4 Port Controller

The port transceiver controller provides a couple of basic functions: Suspend/Resume For device mode, Chirp control.

15.2.5 ULPI Link Wrapper

The ULPI Link wrapper passes-through packet data and interprets Rx commands as well as send Tx commands and provide viewport services to the software. The ULPI link wrapper interfaces between the port controller (a bus similar to UTMI+ that connects to the rest of the controller and its registers) and the ULPI interface.

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X-Ref Target - Figure 15-9

APB
Slave

Control and Status Registers

Port Controller Control

Protocol Engine * Suspend/Resume Similar to UTMI+ Host: * Port State Machine

ULPI Link Wrapper

* Transceiver Logic

Device: * Port State Machine * Chirp Control

ULPI
I/O Interface

UG585_c15_38_030713

Figure 15-9:

USB Port Controller and ULPI Link Wrapper Block Diagram

15.2.6 General Purpose Timers

The two independently programmable timers can be used to generate a timeout or to measure time related activities.The programmable timers should not be confused with the controllers interval timers which are used by the controller to generate frame and microframe intervals and to generate strobes for the host controller scheduler. A timer is controlled by its control and load registers; usb.GPTIMERxCTRL and usb.GPTIMERxLD. The load register contains the value that is loaded into the timer when a timer reset occurs. The control register contains timer configuration and a data field which can be queried to determine the running count value. The timer has granularity of 1 microsecond and can be programmed to count for a little over 16 seconds. There are two modes for this timer; one-shot and looped count. When the timer counter value transitions to 0, an interrupt is controllable using the usb.USBSTS and usb.USBINTR registers. The one-shot mode, usb.GPTIMERxCTRL [GPTMODE] = 0, selects a single timer countdown where the timer will count down to 0, generate an interrupt and stop until the counter is reset by software. In repeat, looped countdown, the timer will count down to 0, generate an interrupt and automatically reload the counter from the usb.GPTIMERxLD register to begin to count down again.

15.3 Programming Overview and Reference

This section includes an overview of the programming model for host and device modes. The programming model details for each mode are separately described in other sections of the Zynq-7000 AP SoC Technical Reference Manual (TRM).

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15.3.1 Hardware/Software System

The physical and virtual data flows for a USB hardware/software system are illustrated in Figure 15-10. These flows form the basis of USB. The TRM is focused on the operations of the bus interface and device layers as a foundation for writing drivers that include the functional layer.
X-Ref Target - Figure 15-10

USB Host
Application Software
Data pipes

USB Device
Function Interface

Function Layer

System Software

Control pipe

USB Logical Device

Device Layer

Host Controller

Bus Interface

Bus Interface Layer

Endpoints
USB Cabling and Hubs

Virtual Data Flow Physical Data Flow

UG585_c15_39_030713

Figure 15-10:

USB System Stack

15.3.2 Operational Mode Control

States
The controller can be configured for device mode or host mode. In OTG mode, the controller must perform tasks independent of the device and host controller modes to determine what mode to put the controller into. Software can use the usb.USBCMD [RST] reset bit to reset the vast majority of the controller, but preserve register values and controller state to support OTG operations. This reset transitions the controller out of host or device mode and into an idle state as shown in figure Figure 15-11. OTG tasks are performed independent of the [RST] bit reset as well as independent of the controller mode. The software sets the usb.USBMODE [CM] mode bit to select either host or device mode.

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X-Ref Target - Figure 15-11

Reset * PS_POR_B reset (all USB registers) * slcr.USB_RST_CTRL [USB_CPU1X_RST] (all USB registers) * usb.USBCMD [RST] (USB registers except those for OTG functionality)

Idle

usb.USBMODE [CM] = 10 usb.USBMODE [CM] = 11 reset

Device Mode

reset

Host Mode
UG585_c15_40_030713

Figure 15-11:

USB Controller Mode Diagram

15.3.3 Power Management

Stop-Clock
The USB controller can be held in reset by the PS reset subsystem and the PHY clock from the PHY can be stopped to reduce power consumption. The clocks and resets are described in section 15.15 System Functions.

Suspend and Resume

The USB controller supports Suspend/Resume functions for both host and device modes.

15.3.4 Register Overview

Each controller includes its own set of independent control and status registers that are memory mapped at 0xE000_2000 for controller 0 and at 0xE000_3000 for controller 1. The register address offsets and brief descriptions are summarized in Table 15-1. The detailed descriptions are in Appendix B. The controller and all registers are reset by the assertion of the USB Ref Reset from the PS. The mechanism is described in Chapter 26, Reset System. The reset value of the controller registers are shown in Appendix B. Software can reset the controller and the non-OTG registers by writing a 1 to the usb.USBCMD [RST] bit. The registers that are reset by usb.USBCMD [RST] are identified in a the last column of Table 15-1.

Register Overview Table

The controller registers include configuration constants, capability constants and operational registers for EHCI compatibility (Host mode) and non-EHCI functions (Device and OTG modes). The non-EHCI registers support device mode and OTG functions. The EHCI register fields are overlaid into the controllers register set. OTG/Mode registers provide control and status for HNP and SRP.

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Dev register is used by the device controller driver software (DCD). Host register is used by the host controller driver software (HCD). EHCI register includes content from the specification. x means partial. ex means exclusive. USB Controller Register Overview

Table 15-1: Offset Address

Register Name
Bit Acronym

OTG/ Mode

Dev

Host

EHCI

Type

Affected by USBCMD Reset

no no no no no no yes yes yes no no no no no yes yes, except RO yes, except RO yes yes yes yes yes yes, except RO yes yes yes yes yes, except RO

Identification: Configuration Constants.

0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0080/88 0x0084/8C 0x0090 0x0100 0x0104 0x0108 0x0120 0x0124 0x0140 0x0144 0x0148 0x014C 0x0154 0x0158 ID HWGENERAL HWHOST HWDEVICE HWTXBUF HWRXBUF GPTIMER{0,1}LD GPTIMER{0,1}CTRL SBUSCFG CAPLENGTH_HCIVERSION HCSPARAMS HCCPARAMS DCIVERSION DCCPARAMS USBCMD USBSTS, refer to Table 15-2. USBINTR FRINDEX PERIODICLISTBASE_ _DEVICEADDR ASYNCLISTADDR_ _ENDPOINTLISTADDR x x ~ ~ ~ ~ x x x x x ~ x x x x x ~ ~ ~ ~ ~ ~ x x x ~ x x x x x x x ~ ~ x x x x x x ~ x ~ x ~ x x x x x x ~ x ~ x x x x ex x ex ~ ex ~ ~ ~ x x x ~ x x x x x x x x ~ ~ ~ x ex ex x RO RO RO RO RO RO rw mixed RW RO RO RO RO RO RW RW, R/W1C, RO RW, R/W1C, RO RW RW RW RW RW RW, RO RW RW, R/W1C RW, R/W1C x x x x x x ~ ~ RW RW, RO

General Purpose (GP) Timers.

AXI Interconnect Capability: Controller and EHCI Capabilities Constants (IP Configuration Constants).

Operational: Interrupts, Schedule Pointers (Host), and Endpoint Pointers (Device).

Operational: Transaction Translator.

0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 TTCTRL BURSTSIZE TXFILLTUNING TXTTFILLTUNING IC_USB ULPI_VIEWPORT

Operational: Misc.

Operational: Endpoint Control (Device mode), refer to Figure 15-4 for details.

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Table 15-1: Offset Address

0x0178 0x017C 0x0180 0x0184

USB Controller Register Overview (Contd)

Register Name
Bit Acronym ENDPTNAK ENDPTNAKEN CONFIGFLAG PORTSC1 [WKDS] [WKCN] [WKOC] [PIC] [PR] others

OTG/ Mode

Dev x x

Host ~ ~ x x

EHCI ~ ~ x x

Type
R/WTC RW RO RW, RO, R/W1C

Affected by USBCMD Reset

Operational: Host mode (EHCI) and Device mode.

x x x x partial no no yes x x ~ ~ ~ ~ ~ ~ ~ ~ x x x x x x x x ~ x ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RW, RO, R/W1C RW R/W1C R/W1S R/W1S RO R/W1C RW, RO RW, R/W1C no yes yes yes yes no yes yes, except RO yes

Operational: Mode Control.

0x01A4 0x01A8 0x01AC 0x01B0 0x01B4 0x01B8 0x01BC 0x01C0 0x01C4 to 0x01EC OTGSC USBMODE ENDPTSETUPSTAT ENDPTPRIME EMDPTFLUSH ENDPTSTAT ENDPTCOMPLETE ENDPTCTRL 0 ENDPTCTRL {1 to 11}

Endpoint Configuration and Control (Device mode), refer to Figure 15-4 for details.

15.3.5 Interrupt and Status Bits Overview

Each controller has a IRQ interrupt signal to the PS interrupt controller that is an accumulation of enable interrupts listed in Table 15-2 except for some Status-only bit that cant generate an interrupt. Controller 0: IRQ ID #53 Controller 1: IRQ ID #76

USBSTS Interrupt, Status and Enable Registers

The interrupt and status bits of the usb.USBSTS registers are listed in Table 15-2 USB Interrupt and Status Register Bits. The interrupt bits are maskable using the usb.USBINTR registers. The status bits do not generate an interrupt and are read-only to provide status information to software.

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Table 15-2: USBSTS (status) Bit Field

[TI1] [TI0] [UPI] [UAI] [NAKI] [AS] [PS] [RCL] [HCH] [ULPII] [SLI] [SRI] [URI] [AAI] [SEI] [FRI] [PCI] [UEI] [UI] 25 24 19 18 16 15 14 13 12 10 8 7 6 5 4 3 2 1 0

USB Interrupt and Status Register Bits Type

Interrupt Interrupt Interrupt Interrupt Interrupt Status-only Status-only Status-only Status-only Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt

USBINTR (enable) Bit Field

25 24 19 18 16 na na na na 10 8 7 6 5 4 3 2 1 0 Timer 1. Timer 0.

Description

Dev Host x x ~ ~ x ~ ~ ~ x x x x ~ x x x

Cross Reference

15.2.6 General Purpose Timers

Periodic qTD complete. Async qTD complete. Device generated NAK. Async Schedule state. Periodic Schedule state. Host Reclamation status. Halt status of Run/Stop. ULPI Viewport transfer complete. Device enters Suspend state. Start of Frame (SOF) received. Reset received. Async schedule advance. System Error response on AHB. Periodic Frame List rollover. Port Change Detect. USB Transaction Error. TD complete

x x x x ~ x ~ x

x ~ ~ ~ x x x x Table 15-17 USB Device High Frequency Interrupt

Table 15-17 USB Device High Frequency Interrupt

15.3.6 OTG Status/Interrupt and Control Register

The programming model for On-the-Go (OTG) USB is supported by the OTG status and control register (OTGSC). The OTG operation works independently of the host and device modes. In OTG mode, once the controller has determined which mode to operate in, the full features of that mode (host or device) are available to the software. Please refer to 15.14.2 OTG Interrupt and Control Bits.

15.4 Device Mode Control

When the controller is in device mode, software enables its control endpoint, prepares descriptors based on the functionality of the device and prepares the necessary endpoints.

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15.4.1 Controller State

The device mode includes the active physical state of the controller, left side of Figure 15-12, and the suspend state maintained in software, right side of the figure. Power interruptions, resets and USB activity all contribute to the sequencing through these states.
X-Ref Target - Figure 15-12

Active State

Suspend State

Powered

Power Interruption Attach

Set the Run bit: usb.USBCMD [RS] = 1.

When the host resets the device returns to the default state.

Reset Bus Inactive Default FS/HS Bus Activity Address Assigned Bus Inactive Address FS/HS Bus Activity Device Device Deconfigured Configured Bus Inactive Configured FS/HS Bus Activity Suspend FS/HS Suspend FS/HS Suspend FS/HS

Software Maintained State

UG585_c15_12_030413

Figure 15-12:

USB Device State Diagram

It is the responsibility of software to maintain a state variable to differentiate between the default FS/HS state and the address/configured states. Change of state from default to address and the configured states is part of the enumeration process described in the device framework section of the USB 2.0 Specification.

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Table 15-3:

USB Device State Information Bits Bit Description Register Bit

usb.USBSTS [SLI] usb.USBSTS [URI] usb.USBSTS [PCI] usb.PORTSC1 [PSPD] Yes Yes Yes No

Interrupt

Suspend Mode USB Reset Received Port Change Detect High-Speed Port

As a result of entering the address state, the device address register (usb._DEVICEADDR) must be programmed by the DCD. Entry into the configured state indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the usb.ENDPTCTRLx registers and initializing the associated queue heads.

15.4.2 USB Bus Reset Response

A USB bus reset is used by the host to initialize downstream devices. The USB reset is one of several types of resets in the system, refer to section 15.15.2 Reset Types for a list. When a bus reset is detected, the device controller hardware renegotiates its attachment speed, reset the device address to 0 and notify the DCD by interrupt (assuming the USB reset interrupt enable is set). After a reset is received, all endpoints (except EP 0) are disabled and any primed transactions are canceled by the device controller. The concept of priming will be clarified below, but the DCD must perform the following tasks when a reset is received.

DCD Actions
1. Clear all setup token semaphores by reading the usb.ENDPTSETUPSTAT register and writing the same value back to the usb.ENDPTSETUPSTAT register. Clear all the endpoint complete status bits by reading the usb.ENDPTCOMPLETE register and writing the same value back to the usb.ENDPTCOMPLETE register. Cancel all primed status by waiting until all bits in the usb.ENDPTPRIME register are 0 and then writing FFFF_FFFFh to usb.ENDPTFLUSH register. Read the reset bit in the PORTSC1 register and make sure that it is still active. A USB reset occurs for a minimum of 3 ms and software must reach this point in the reset cleanup before end of the reset occurs, otherwise a hardware reset of the device controller is recommended (rare).

2. 3.

Device Controller Reset

4. A hardware reset can be performed by writing a 1 to the usb.USBCMD [RST] reset bit. A hardware reset will cause the device to detach from the bus by clearing the run/stop bit. Thus, software must completely re-initialize the device controller after a hardware reset. Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated.

5.

At this time, the DCD might release control back to the OS because no further changes to the device controller are permitted until a port change detect is indicated.

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Port Change Detect

After a port change detect, the device has reached the default state and the DCD can read the PORTSC1 register to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and the DCD can respond to enumeration according to the USB Chapter 9 - Device Framework . The DCD can use the FS/HS mode information to determine the bandwidth mode of the device.

Note: Before resume signaling can be used, the host must be enabled using the Set Feature
command defined in device framework of the USB 2.0 Specification .

15.5 Device Endpoint Data Structures

The device endpoint data structures consist of link-list endpoint descriptors that must be initialized and managed by software. This consists of programming the endpoint control registers, maintaining a set of descriptors in system memory, and managing system memory buffers.

15.5.1 Link-list Endpoint Descriptors

There are two types of descriptors used for the device controller: the device Queue Head (dQH) and the device Transfer Descriptor (dTD). Figure 15-13 shows how these are used in a link-list fashion. The DMA engine uses link-list descriptors to respond to endpoint packet transfer requests from the host. It is necessary for the DCD to maintain head and tail pointers to the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed. The operations described in next section for managing dTD will assume the DCD can reference the head and tail of the dTD linked list.

Note: To conserve memory, the reserved fields at the end of the dQH can be used to store the Head
and Tail pointers but it still remains the responsibility of the DCD to maintain the pointers.

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X-Ref Target - Figure 15-13

0x600

Queue Head List

Endpoint 11 IN
dTD Pointer

dTD

4KB Memory ffer Buffer Bu ter in Po dTD Pointer T=0

dTD

4KB Memory Buffer ffer Bu ter n i Po dTD Pointer T=0

0x5C0 4KB Memory Buffer ffer Bu ter in Po dTD Pointer T=0 4KB Memory Buffer

0x0B0

Endpoint 1 OUT
0x080

dTD Pointer

dTD

dTD

ffer Bu ter in Po
T=1

Endpoint 0 IN
0x040

ffer Bu ter in Po
dTD Pointer

4KB Memory Buffer

dTD

T=1

Endpoint 0 OUT

ffer Bu ter in Po
dTD Pointer

4KB Memory Buffer

dTD

After a dTD is processed, the controller will generate an interrupt if its IOC bit is set = 1.

T=1

Transfer Buffers

Endpoint Queue Heads (dQH)

Transaction Descriptors (dTD)

usb.ENDPOINTLISTADDR
UG585_c15_41_030713

Figure 15-13:

USB Device Link-list Endpoints Example

The device controller API software incorporates and abstracts for the application developer all of the information contained in the device operational model. Each Endpoint can be configured for bi-directional transfers (contain both IN and OUT endpoints). Queue Head and Linked Transfer Descriptors: 15.7.1 Endpoint Queue Head Descriptor (dQH) 15.7.2 Endpoint Transfer Descriptor (dTD) 15.7.3 Endpoint Transfer Overlay Area

Descriptor and Data Flow

The top portion of Figure 15-14 shows the list of queue heads (one for each endpoint) and the list of transfer descriptors that are referenced by the dQH and other dTD descriptors. The low portion of the figure shows data being transferred between memory and the ULPI connection to USB.

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X-Ref Target - Figure 15-14

System Memory
0x600 0x5C0

USB Controller

dQH Endpoint 11 IN

Queue Head List 0x0C0

EndPoint 1 OUT
0x080

dQH Read/Write

dQH

dTD

Transfer Overlay Area (7 DWords) 0

EndPoint 0 IN
0x040

EndPoint 0 OUT
0x000

31 Transaction Descriptor Processor

usb.ENDPOINTLISTADDR [31:11]

Transfer Descriptors
EndPoint dTD Next dTD Pointers

dTD Read/Write

DMA Engine

dTD Rx and Tx FIFOs

(Latency Buffers)

Memory Buffers 4KB each

Buffer Pointers Transfer Buffers

DMA

Protocol Engine

Dual-port RAM

Port Controller and ULPI Link Wrapper

ULPI
UG585_c15_42_030713

Figure 15-14:

USB Device Descriptor and Data Flow

15.5.2 Manage Endpoints

The USB 2.0 Specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a USB device that can source or sink data in a communications channel between the host and the device. The endpoint address is specified by the combination of the endpoint number and the endpoint direction. The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a device is always a control type data channel used for device discovery and enumeration. Other types of endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific behavior related to packet response and error handling. More detail on endpoint operation can be found in the USB 2.0 Specification . The device controller hardware is configured to support up to 12 endpoints. The DCD can enable, disable and configure endpoint type up to the maximum selected during synthesis. Each endpoint direction is essentially independent and can be configured with differing behavior in each direction. For example, the DCD can configure endpoint 1 IN to be a bulk endpoint and endpoint 1 OUT to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device operation. The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint. Endpoint 0, for example, is always a control endpoint and uses the pair of directions. Each endpoint direction requires a queue head allocated in memory. For 12 endpoints, numbers is used, then 24 queue heads are required one for each endpoint direction being used by the device

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controller. The operation of an endpoint and use of queue heads are described later in this document.

15.5.3 Endpoint Registers

The endpoint registers are listed in Table 15-4 USB Device Endpoint Register Summary. These registers were summarized at the end of Table 15-1, page 359. In general, there is one bit for each endpoint. The lower half of the register bits are for Rx endpoints and the upper half is for Tx endpoints. Exceptions include the ENDPTSETUPSTAT and the endpoint control registers, ENDPTCTRL{11:0}.

Endpoint Registers
Table 15-4: USB Device Endpoint Register Summary Description and Register Bit Field Tx Endpoint (11:0)
[EPTN], 27:16 (IN token) [EPTNE], 27:16 ~

Register Name ENDPTNAK ENDPTNAKEN ENDPTSETUPSTAT

Rx Endpoint (11:0)
[EPRN], 11:0 (OUT or Ping token) [EPRNE], 11:0 [ENDPTSETUPSTAT], 11:0

Type
Read and Write-one-to-clear. Read/Write. Read and Write-one-to-clear. Read and Write-one-to-set.

Bit is set when an endpoint sends a NAK to the Host.

Interrupt enable bits for ENDPTNAK bits. Bit is set when an endpoint receives a Setup transaction. Software sets a bit to instruct the controller to prepare for a packet transfer. The QH, dTDs, and endpoint registers are ready. [PETB], 27:16 (IN or Interrupt) [PERB], 11:0 (OUT)

ENDPTPRIME

ENDPTFLUSH

Software sets a bit to instruct the controller to flush an endpoint. [FETB], 27:16 [FERB], 11:0 Indicates that the controller hardware has primed the endpoint as requested by the ENDPTPRIME register. [ETBR], 27:16 [ERBR], 11:0 Indicates that the controller has completed the transfer that was primed. [ETCE], 27:16 [ERCE], 11:0

Read and Write-one-to-set. Read-only.

ENDPTSTAT

ENDPTCOMPLETE

Read and Write-one-to-clear.

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Endpoint Configuration Registers

Table 15-5: USB Device Endpoint Configuration Register Summary Description and Register Bit Field Tx Rx
Software can control the STALL behavior for Rx and Tx transactions to the control endpoint. Software can read the control endpoint configuration. [TXS], 16 Others: always enabled, Tx and Rx capable. Software configuration and control bits for each endpoint. Refer to Table 15-6 USB Device Endpoint Initialization. Force controller to send Stall responses. [TXS], 16 Always set = 0 (datapath includes FIFOs). [TXD], 17 [RXD], 1 [RXT], 3:2 [RXI], 5 [RXR],6 [RXE], 7 Write-one. Read-write. Select endpoint type (Control, ISO, Bulk, Interrupt). [TXT], 19:18 [TXI], 21 [TXR], 22 Endpoint enable. [TXE], 23 Always set = 0 (test mode to ignore data toggling). Data toggle reset (write 1 to synchronize data PIDs). [RXS], 0 Read-write. [RXS], 0

Register Name

Type
(see below) Read-write. Read-only.

ENDPTCTRL0

ENDPTCTRL {11:0}

15.5.4 Endpoint Initialization

After hardware reset, all endpoints except endpoint 0 are uninitialized and disabled. The DCD must configure and enable each endpoint by writing to the configuration register usb.ENDPTCTRLx. Each 32-bit usb.ENDPTCTRLx is split into an upper and lower half. The lower half of usb.ENDPTCTRLx register is used to configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half of the usb.ENDPTCTRLx register otherwise the behavior is undefined. Table 15-6 shows how to construct a configuration word for endpoint initialization. Table 15-6: USB Device Endpoint Initialization Value
1

Field
Data Toggle Reset, usb.ENDPTCTRLx [TXR]

Meaning
Restart transfers with DATA0 PID.

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Table 15-6:

USB Device Endpoint Initialization (Contd)

0 Toggle between DATA0 and DATA1 PIDs. 00: 01: 10: 11: Control Isochronous Bulk Interrupt

Date Toggle Inhibit, usb.ENDPTCTRLx [TXI]

Endpoint Type, usb.ENDPTCTRLx [TXT ]

Depends on the setup request. 0

Endpoint Stall, usb.ENDPTCTRLx [TXS]

Do not force stall response.

Stall
There are two occasions where the device controller might need to return a STALL to the host: Functional Stall: software initiated (non-control endpoints only). Protocol Stall: hardware initiates (control endpoint).

The functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework. A functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the usb.ENDPTCTRLx [TXS] stall bit associated with the given endpoint and the given direction. In a functional stall condition, the device controller will continue to return STALL responses to all transactions occurring on the respective endpoint and direction until the endpoint stall bit is cleared by the DCD. A protocol stall, unlike a function stall, is used on control endpoints and automatically cleared by the device controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD should enable the stall bits (both directions) as a pair. A single write to the usb.ENDPTCTRLx register can ensure that both stall bits are set at the same instant.

Note: Any write to the usb.ENDPTCTRLx register during operational mode must preserve the
Table 15-7: USB Device Packet Mismatch Response Endpoint Type
Control Non-Control All All

endpoint type field (i.e. perform a read-modify-write of this register and preserve the [TXT] field).

USB Packet Type Received

Stall Bit setting [TXS]

x x 0 1

Hardware action on Stall bit

Clears [TXS] None None None

Bus Response
ACK STALL ACK/NAK/NYET STALL

Setup IN/OUT/Ping

Data Toggle
Data toggle is a mechanism to maintain data ordering between the host and device for a given data pipe. For more information on data toggle, refer to the USB 2.0 specification. The DCD can reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a 1 to the data toggle reset bit in the usb.ENDPTCTRLx [TXR] register bit. This

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should only be necessary when configuring/initializing an endpoint or returning from a STALL condition.

Data Toggle Inhibit

This feature is for test purposes only and should never be used during normal device controller operation. Setting the data toggle inhibit bit active (usb.ENTPTCTRLx [RXI] bit = 1 ) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state. In normal operation, the device controller checks the DATA0/DATA1 bit against the data toggle to determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device controller assumes the packet was already received and discards the packet (not reporting it to the DCD). To prevent the host controller from re-sending the same packet, the device controller will respond to the error packet by acknowledging it with either an ACK or NYET response.

15.6 Device Endpoint Packet Operational Model

All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request from the host within the turnaround time stated in the USB 2.0 Specification . At USB 1.1 Full or Low Speed rates, this turnaround time was significant and the USB 1.1 device controllers were designed so that the device controller could access main memory or interrupt a host protocol processor in order to respond to the USB 1.1 transaction. The architecture of the USB 2.0 device controller must be different because the same methods will not meet USB 2.0 High-speed turnaround time requirements. A USB host sends requests to the device controller in an order that cannot be precisely predicted as a single pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the order of packet requests is predictable when the endpoint number and direction is considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN requests to that endpoint.

Prime and Flush Endpoints

This device controller is designed in such a way that it can prepare packets for each endpoint or direction in anticipation of the host request. The process of preparing the device controller to send or receive data in response to host initiated transaction on the bus is referred to as priming the endpoint. The term flushing is used to describe the action of clearing a packet that was queued for execution.

15.6.1 Prime Transmit Endpoints

Priming a transmit endpoint will cause the device controller to fetch the dTD for the transaction pointed to by the dQH. After the dTD is fetched, it will be copied in the dQH until the device controller completes the transfer described by the dTD. Copying the dTD in the dQH overlay area

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allows the device controller to fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint up to the maximum number of endpoints configured at device synthesis time. After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of High Speed USB. Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. More information about FIFO sizing is presented in section Bandwidth and Latency Issues.

15.6.2 Prime Receive Endpoints

Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD. At the device controller the major difference in the operational model is that there is no data movement of the leading packet data simply because the data is to be received from the host. Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of the RxFIFO does not scale with the number of endpoints.

15.6.3 Interrupt and Bulk Endpoint Operational Model

The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed. Once the endpoint has been primed, data delivery will commence. A dTD will be retired by the device controller when the packets described in the transfer descriptor have been completed. Each dTD describes N packets to be transferred according to the USB Variable Length transfer protocol. The formula and table on the following page describe how the device controller computes the number and length of the packets to be sent/received by the USB vary according to the total number of bytes and maximum packet length. With Zero Length Termination dTD.ZLT = 0 , N = INT (Number of Bytes/Max. Packet Length) + 1 With Zero Length Termination dTD.ZLT = 1 , N = MAXINT (Number of Bytes/Max. Packet Length)

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Table 15-8: Bytes dTD

511 512 512

USB Device Variable Length Transfer Protocol Examples Max. Packet Length dQH
256 256 512

dTD.ZLT = 0
N
2 3 2

dTD.ZLT = 1
P3 N
2 0 2 1

P1
256 256 512

P2
256 256 0

P1
256 256 512

P2
256 256

P3

Note: The dQH.Mult field must be set to 00 for Bulk, Interrupt, and Control endpoints.
The dQH.ZLT bit operates as follows on Bulk and Control transfers:

dQH.ZLT = 0, the default value

The zero length termination is active. With the dQH.ZLT option enabled, when the device is transmitting, the hardware automatically appends a zero length packet when the following conditions are true: The packet transmitted equals maximum packet length The dTD has exhausted the field Total Bytes

After this the dTD will be retired. When the device is receiving, if the last packet length received equal maximum packet length and the total bytes is 0, it will wait for a zero length packet from the host to retire the current dTD.

dQH.ZLT = 1
The zero length termination is inactive. With the dQH.ZLT option disabled, when the device is transmitting, the hardware will not append any zero length packet. When receiving, it will not require a zero length packet to retire a dTD whose last packet was equal to the maximum packet length packet. The dTD is retired as soon as total bytes field goes to 0, or a short packet is received. Each transfer is defined by one dTD, so the zero length termination is for each dTD. In some software application cases, the logic transfer does not fit into just one dTD, so it does not make sense to add a zero length termination packet each time a dTD is consumed. On those cases we recommend to turn off this dQH.ZLT feature and use the DCD to generate the zero length termination.

Tx dTD Completes
All packets described in the dTD were successfully transmitted. Total bytes in dTD equals 0 when this occurs.

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Rx dTD Completes
All packets described in dTD were successfully received. Total bytes in dTD equals 0 when this occurs. A short packet (number of bytes < maximum packet length) was received. This is a successful transfer completion; the DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received. A long packet was received (number of bytes > maximum packet size) OR (total bytes received > total bytes specified). This is an error condition. The device controller will discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed and the USBERR interrupt will become active.

On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the device controller will flush the endpoint/direction and cease operations for that endpoint/direction. On the unsuccessful completion of a packet (see long packet above), the dQH is left pointing to the dTD that was in error. In order to recover from this error condition, the DCD must properly reinitialize the dQH by clearing the active bit and update the next dTD pointer before attempting to re-prime the endpoint.

Note: All packet level errors such as a missing handshake or CRC error are retried automatically by
the device controller. There is no required interaction with the DCD for handling such errors.

Interrupt and Bulk Endpoint Bus Response

The shaded column in Table 15-9 is the normal operating mode. Table 15-9: Packet Identifier
Setup IN OUT

USB Device Interrupt and Bulk Endpoint Bus Response Stall Bit [TXS]
Ignore STALL STALL

Endpoint Not Primed

Ignore NAK NAK

Endpoint Primed
Ignore Transmit Receive and then NYET/ACK

Buffer Underflow
N/A BS Error N/A

Buffer Overflow
N/A N/A NAK

Endpoint Not Enabled

BTO BTO BTO

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Table 15-9:
Ping Invalid Notes:

USB Device Interrupt and Bulk Endpoint Bus Response

STALL Ignore NAK Ignore ACK Ignore N/A Ignore N/A Ignore BTO BTO

1. BS Error Force Bit Stuff Error. 2. NYET/ACK NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. 3. SYSERR System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 4. BTO Bus Time Out.

15.6.4 Isochronous Endpoint Operational Model

Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by the device controller is accomplished by the following: Exactly MULT Packets per (micro)frame are transmitted/received. Note: MULT is a two-bit field in the device queue head. The variable length packet protocol is not used on isochronous endpoints. NAK responses are not used. Instead, zero length packets are sent in response to an IN request to an unprimed endpoints. For unprimed Rx endpoints, the response to an OUT transaction is to ignore the packet within the device controller. Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the ISO-dTD is still active after that frame, then the ISO-dTD is held ready until executed or canceled by the DCD.

Note: If the MULT field is set to more packets than present in the dTD to be transmitted, the

controller sends zero length packets to all extra incoming IN tokens and report fulfillment error (transaction error) in current dTD. If more dTDs exist in memory, the controller moves to the next dTD to be transmitted in the next (micro)frame. Because of this behavior it is recommended to always use the correct MULT matching the number of packets to be processed for a given dTD. An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for the device controller does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is in the handling of the dTD. The first difference between bulk and iso endpoints is that priming an iso endpoint is a delayed operation such that an endpoint will become primed only after a SOF is received. After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to the DCD that the device controller completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the device controller can match the dTD to a specific (micro)frame. Another difference with isochronous endpoints is that the transaction must wholly complete in a (micro)frame. Once an isochronous transaction is started in a (micro)frame it will retire the corresponding dTD when MULT transactions occur or the device controller finds a fulfillment condition.

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The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the iso dTD and move to the next iso dTD. It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed iso endpoint, the transaction will stay primed indefinitely. This means it is up to the DCD to discard transmit iso dTDs that pile up from a failure of the host to move the data. Finally, the last difference with iso packets is in the data level error handling. When a CRC error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort out.

Tx Isochronous Packet Retired

The Tx Packet is retired when: MULT counter reaches 0. Fulfillment Error [Transaction Error bit is set] # Packets Occurred > 0 AND # Packets Occurred < MULT

Note: For Tx isochronous endpoint, the MULT Counter can be loaded with a lesser value in the dTD
Multiplier Override field. If the Multiplier Override is 0, the MULT Counter is initialized to the dQH.Mult field.

Rx Isochronous Packet Retired

The Rx Packet is retired when: MULT counter reaches 0. Non-MDATA Data PID is received Overflow Error: Packet received is > maximum packet length. [Buffer Error bit is set] Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set] Fulfillment Error [Transaction Error bit is set] # Packets Occurred > 0 AND # Packets Occurred < MULT CRC Error [Transaction Error bit is set]

Note: For isochronous transfers, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame to (micro)frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro)frames.

Isochronous Pipe Synchronization

When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number (read the FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific

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(micro)frame number [N], the DCD should interrupt on SOF during frame N - 1. When the FRINDEX = N - 1, the DCD must write the prime bit. The device controller primes the isochronous endpoint in (micro)frame N - 1 so that the device controller executes delivery during (micro)frame N. Caution: Priming an endpoint towards the end of (micro)frame N - 1 does not guarantee delivery in (micro)frame N. The delivery might actually occur in (micro)frame N+1 if device controller does not have enough time to complete the prime before the SOF for packet N is received.

Isochronous Endpoint Bus Response

Table 15-10: Token Type
Setup IN OUT Ping Invalid Notes:
1. BS Error Force Bit Stuff Error. 2. NULL Packet Zero length packet. 3. BTO Bus Time Out.

USB Device Isochronous Endpoint Bus Response Stall Bit [TXS]

STALL NULL Packet Ignore Ignore Ignore

Endpoint Not Primed

STALL NULL Packet Ignore Ignore Ignore

Endpoint Primed
STALL Transmit Receive Ignore Ignore

Buffer Underflow
N/A BS Error N/A Ignore Ignore

Buffer Overflow
N/A N/A Drop Packet Ignore Ignore

Endpoint Not Enabled

BTO BTO BTO BTO BTO

15.6.5 Control Endpoint Operational Model

All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The device controller always accepts the setup phase unless the setup lockout is engaged.

Lockout and Tripwire for Setup Packets

The setup lockout can be engage so that future setup packets from the host are ignored by the controller while the DCD retrieves the current setup packet. Lockout of setup packets ensures that while the DCD is reading the setup packet stored in the queue head data is not written as it is being read potentially causing an invalid setup packet. The setup lockout mechanism can be disabled and a tripwire type semaphore will ensure that the setup packet payload is extracted from the queue head without being corrupted by an incoming setup packet. This is the preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue. The tripwire semaphore can ensure the proper addition of a new dTD to an active (primed) endpoints linked list. The add dTD tripwire bit, usb.USBCMD [ATDTW] can be set and cleared by software. This bit can be cleared by hardware when its state machine is in a hazard region for which adding a dTD to a primed endpoint may go unrecognized.

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Setup Packet Handling using the Tripwire

Disable setup lockout by writing 1 to setup lockout mode, usb.USBMODE [SLOM] bit field; once at initialization. Setup lockout is not necessary when using the tripwire as described in the example below.

Example: Setup Packet Handing using the Tripwire

After receiving an interrupt and inspecting usb.ENDPTSETUPSTAT register to determine that a setup packet was received on a particular pipe (i.e., the dQH was written to memory by the hardware): 1. 2. 3. Setup the Tripwire Mechanism: Write 1 to usb.USBCMD [SUTW]. Read the Setup Buffer: Copy the contents of dQH.SetupBuffer into local software byte array. Test to see if another Setup Packet was received. Read the tripwire bit [SUTW] again. a. 4. If [SUTW] = 1 (not received), then continue to step 4 and process the setup buffer. b. If [SUTW] = 0 (another packet received), then go to step 1 and copy that setup buffer, too. Clear the Interrupt: Write 1 to clear corresponding usb.ENDPTSETUPSTAT register bit. A poll loop should be used to wait until usb.ENDPTSETUPSTAT transitions to 0 and before priming for the status/handshake phases. The time from writing a 1 to usb.ENDPTSETUPSTAT register and reading back a 0 is very short (approximately 1 to 2 microsecond) so a poll loop in the DCD should not be harmful in most systems. 5. 6. 7. Clear the Tripwire: Write 0 to clear setup tripwire bit usb.USBCMD [SUTW]. Process setup packet: Use the local software byte array copy and execute status/handshake phases. Check Endpoint status: Before priming for status/handshake phases, ensure that the usb.ENDPTSETUPSTAT bit is = 0 .

Note: After receiving a new setup packet, the status and/or handshake phases might still be

pending from a previous control sequence. These should be flushed and deallocated before linking a new status and/or handshake dTD for the most recent setup packet.

Data Phase
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime the transfer. After priming the packet, the DCD must verify a new setup packet has not been received by reading the usb.ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime completes when the associated bit in the usb.ENDPTPRIME register is 0 and the associated bit in the usb.ENDPTSTATUS register is a 1. If a prime fails, i.e., the usb.ENDPTPRIME bit goes to 0 and the usb.ENDPTSTATUS bit is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the endpoint prime bit is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.

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Should a setup arrive after the data stage is primed, the device controller automatically clears the prime status (usb.ENDPTSTATUS) to enforce data ordering with the setup packet.

Note: The dQH.Mult field must be set to 00 for bulk, interrupt, and control endpoints. Error
handling of data phase packets is the same as bulk packets described previously.

Status Phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal 0) and prime the endpoint for the status phase. The DCD must also perform the same checks of the usb.ENDPTSETUPSTAT as described above in the data phase.

Note: The dQH.Mult bit field must be set to 00 for bulk, interrupt, and control endpoints. Error
handling of data phase packets is the same as bulk packets described previously.

Control Endpoint Bus Response

The device controller response to packets on a control endpoint according to the device controller state is shown in Table 15-11. The normal operating mode is shaded. Table 15-11: Packet Identifier
Setup IN OUT Ping Invalid Notes:
1. BS Error Force Bit Stuff Error. 2. NYET/ACK NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. 3. SYSERR System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 4. BTO Bus Time Out.

USB Device Control Endpoint Bus Response Stall Bit [TXS]

ACK STALL STALL STALL Ignore

Endpoint Not Primed

ACK NAK NAK NAK Ignore

Endpoint Primed
ACK Transmit Receive and then NYET/ACK ACK Ignore

Buffer Underflow
N/A BS Error N/A N/A Ignore

Buffer Overflow
SYSERR N/A NAK N/A Ignore

Endpoint Not Enabled

BTO BTO BTO BTO BTO

Setup Lockout
N/A N/A N/A Ignore

15.7 Device Endpoint Descriptor Reference

This section contains the definitions of the endpoint descriptors for the device controller. There usages are described in other chapter sections, including section 15.5.1 Link-list Endpoint Descriptors. 15.7.1 Endpoint Queue Head Descriptor (dQH) 15.7.2 Endpoint Transfer Descriptor (dTD)

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15.7.3 Endpoint Transfer Overlay Area

15.7.1 Endpoint Queue Head Descriptor (dQH)

The device Endpoint Queue Head (dQH) is where all device controller transfers are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the hardware reads the dQH and the first device transfer descriptor (dTD) from system memory and overlays it onto DWords 2 through 8 of the dQH as shown in Table 15-12. Table 15-12:
Reference Table 15-13

USB Device Queue Head (dQH) Descriptor Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Mult ZLT 0 Maximum Packet Length Next dTD Pointer IOS 8 7 0 0 0000
IOC

DWord 0 1

Current Pointer

Current dTD Pointer 0 Total Bytes Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) reserved C_Page MultO 0 reserved reserved reserved reserved Setup Buffer Bytes 3..0 Setup Buffer Bytes 7..4 Device Controller Read/Write Device Controller Read-only Status Current Offset

2 3 4 5 6 7 8 9 10 11

Table 15-15

Table 15-13

Table 15-13: Bits

Transfer Overlay Area

USB Device dQH DWords 0 to 11: Descriptor Bit Details Description

DWord 0: Endpoint Capabilities/Characteristics

31:30 High-Bandwidth Pipe Multiplier, Mult . This field is used to indicate the number of packets executed per transaction description as given by the following: 00 : Execute N Transactions as demonstrated by the USB variable length packet protocol where N is computed using the Maximum Packet Length (dQH) and the Total Bytes field (dTD). 01 : Execute 1 Transaction. 10 : Execute 2 Transactions. 11 : Execute 3 Transactions. Non-Isochronous endpoints: must set Mult = 00 . Isochronous endpoints: must set Mult = 01, 10, or 11 as needed. Zero Length Termination Select, ZLT. This bit is used to indicate when a zero length packet is used to terminate transfers where to total transfer length is a multiple. This bit is not relevant for Isochronous. 0: Enable zero length packet to terminate transfers equal to a multiple of the Maximum Packet Length. 1: Disable the zero length packet on transfers that are equal in length to a multiple Maximum Packet Length. Reserved. Field reserved and should be set to 0. Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The maximum value this field can contain is 400h (1,024).

29

28:27 26:16

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Table 15-13:
15 14:0

USB Device dQH DWords 0 to 11: Descriptor Bit Details (Contd)

Interrupt On Setup, IOS. This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. Reserved. Field reserved and should be set to 0.

DWord 1: Current dTD Pointer

31:5 Current dTD Pointer. Pointer to the dTD that is represented in the transfer overlay area. This field will be modified by the Device Controller to next dTD pointer during endpoint priming or queue advance. The current dTD pointer is used by the device controller to locate the transfer in progress. This word is for the Device Controller hardwares use only and should not be modified by the DCD. Reserved. Field reserved and should be set to 0.

4:0

DWords 2 to 8: Overlay Area, refer to Table 15-15 USB Device Transfer Overlay. DWord 9: reserved. DWord 10: Setup Buffer Bytes 3:0
31:24 24:16 15:8 7:0 Byte Byte Byte Byte 3 2 1 0

DWord 11: Setup Buffer Bytes 7:4

31:24 24:16 15:8 7:0 Byte Byte Byte Byte 7 6 5 4

15.7.2 Endpoint Transfer Descriptor (dTD)

The dTD describes to the device controller the location and quantity of data to be sent/received for given transfer. The DCD should not attempt to modify any field in an active dTD except the Next dTD Pointer. The dTD descriptors are illustrated in Table 15-14. The fields are detailed in Table 15-8 and described in section 15.7.3 Endpoint Transfer Overlay Area. Table 15-14:
Reference

USB Device Transfer Descriptor (dTD) Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Next dTD Pointer 0 Total Bytes Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) Device Controller Read/Write R C_Page MultO 0 8 7 6 5 4 3 2 1 0 T DWord 0 1 2 3 4 5 6 0000
IOC

Transfer Overlay Area

Status Current Offset Frame Number reserved reserved reserved

Table 15-15

Device Controller Read-only

15.7.3 Endpoint Transfer Overlay Area

The dQH is read from memory by the controller and links to a dTD. The dTD is also read from memory and is written into the overlay area of the dQH as shown in Table 15-15. The seven DWords in the overlay area represent a transaction working space for the device controller. After an endpoint is readied, the dTD will be copied into this dQH overlay area by the device controller. Until a transfer is expired, the DCD must not write the queue head overlay area or

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the associated transfer descriptor. When the transfer is complete, the device controller will write the dTD back to system memory (with transfer status results added) and advance the queue pointer. If the link list continues, then another dTD is fetched from memory and written into the transfer overlay area of the dQH. After the link list is processed, the dQH is written back to system memory and the endpoint servicing is completed. The Overlay Transaction dQH DWords 2 through 8 are nearly identical to the dTD DWords 0 through 6 as shown in Table 15-15.

Transfer Overlay Table

The transfer overlay DWords that are used in both dQH and dTD descriptors are listed in Table 15-15 USB Device Transfer Overlay. The descriptions for Total Bytes and Multiplier Override fields are described in the beginning of this section. Table 15-15: Bits Next dTD Pointer and Terminate.
31:5 4:1 0 Next Transfer Element Pointer, Next dTD Pointer. System memory address [31:5] of the next dTD to be processed. Reserved. Field reserved and should be set to 0. Terminate transfer, T. 0: link to the Next dTD Pointer field; the address is valid. 1: end the transaction, the Next dTD Pointer field is not valid.

USB Device Transfer Overlay Description dTD DWord dQH DWord

Total Bytes, MultO, and Status.

31 30:16 15 14:12 11:10 9:8 7:0 Reserved. Field reserved and should be set to 0. Total Bytes. Total number of bytes to be moved with this transfer descriptor. Refer to section Total Bytes to Transfer Parameter for more info. Interrupt On Complete, IOC. Indicates if USBINT is to be set in response to device controller being finished with this dTD. Current Page, C_Page . Reserved in Device mode. Multiplier Override, MultO. Used for transmit isochronous packets, refer to text. Reserved. Field reserved and should be set to 0. Status. This field is used by the device controller to communicate individual command execution status back to the DCD. This field contains the status of the last transaction performed on this dTD. Bit [7] Active Status. Bit [6] Halted Status. Bit [5] Data Buffer Error Status . Bit [3] Transaction Error Status. Other bits: reserved.

Buffer Pointer Page 0 and Current Offset

31:12 11:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Current Offset.

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Table 15-15: Bits

USB Device Transfer Overlay (Contd) Description dTD DWord dQH DWord

Frame Number and Buffer Pointer Page 1

31:12 11 10:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Reserved, R. Field reserved and should be set to 0. Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically used to correlate relative completion times of packets on an iso endpoint.

Buffer Pointer Pages 2 to 4

31:12 11:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Reserved. Field reserved and should be set to 0.

4 to 6

6 to 8

Multiplier Override (MultO) Bit Field

The total bytes field is used for both dQH and dTD descriptors and is also used for transmit iso IN endpoints to override the multiplier in the dQH. This field must be 0 for all packet types that are not transmit (IN) iso endpoints. For maximal efficiency, the DCD should compute MultO = greatest integer of (Total Bytes / Max. Packet Size) except for the case when Total Bytes = 0; then MultO should be set = 1.

Example 1: Send three packets

If dQH.multiplier = 3; Max packet size = 8; Total Bytes = 15; dQH.Mult = 0 (default), then three packets are sent: Data2 (8) + Data1 (7) + Data0 (0).

Example 2: Send two packets

If dQH.multiplier = 3; Max packet size = 8; Total Bytes = 15; dQH.Mult = 2, then two packets are sent: Data1 (8) +Data0 (7).

Buffer Pointer Pages

The buffer pointers are aligned to 4KB boundaries. The total byes and buffer pointers are discussed in section Total Bytes to Transfer Parameter.

Total Bytes to Transfer Parameter

The Total Bytes bit field specifies the total number of bytes to be moved with the transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and only on the successful completion of the transaction. This bit field applies to: qTD for host mode, refer to section 15.12.5 Queue Element Transfer Descriptor (qTD). dTD for device mode, refer to section 15.7.2 Endpoint Transfer Descriptor (dTD).

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The maximum value that the DCD may store in the field is 5 times 4 KB (5000h). This is the maximum number of bytes that 5 page pointers can reference. Although it is possible to create a transfer up to 20 KB this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16 KB. Therefore, the maximum recommended transfer is 16 KB (4000h).

Device Mode Note

If the value of the Total Bytes bit field is 0 when the device controller fetches this transfer descriptor (and the active bit is set), the reaction of the device controller depends on the setting of the dQH.ZLT bit. Refer to section 15.6.3 Interrupt and Bulk Endpoint Operational Model. It is not a requirement for that Total Bytes To Transfer be an even multiple of Maximum Packet Length. If the DCD builds such a transfer descriptor for a transfer, the last transaction will always be less that Maximum Packet Length.

15.8 Programming Guide for Device Controller

The function of the device controller is to transfer a request in the memory image to and from the USB. The device controller programs and primes the endpoints based on the application protocol. The controller executes a set of linked list transfer descriptors, pointed to by a queue head that the device controller executes to perform the requested data transfers. The following sections explain the use of the device controller from the DCD point-of-view and further describe how specific USB bus events relate to status changes in the device controllers registers.

15.8.1 Software Model

The USB device controller API software provides a framework of routines to control the USB controller in device applications. The software should be designed to significantly simplify the software tasks required to develop a USB device application. The API software presents a high-level data transfer interface to the user's application code. All the register, interrupt and DMA interactions with the controller are managed by the API. The API also includes routines that handle all the USB device framework commands which are required for all USB devices.

15.8.2 USB Reset

After receiving a USB reset from the bus, the port enters the default FS or default HS state in accordance with the reset protocol described in Appendix C.2 of the USB Specification Rev. 2.0. The state diagram shown in Figure 15-12 depicts the state of the controller in device mode.

15.8.3 Register Controlled Reset

To reset the controller, the DCD writes a 1 to the usb.USBCMD [RST] bit. When the reset process is completed, the controller hardware sets this bit to 0. Once the reset is started, the controller cannot stop the process. Writing a 0 has no effect.

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Writing a 1 to the [RST] bit will reset the internal pipelines, timers, counters, and state machines to their initial value. Writing a 1 when the device is in the attached state is not recommended since the effects on an attached host are undefined. In order to ensure that the device is not in an attached state, all primed endpoints should be flushed and the usb.USBCMD [RS] bit should be set to 0.

15.9 Programming Guide for Device Endpoint Data Structures

This section describes how to manage the device endpoint data structures. These are images written in system memory that are accessed by the controller to service USB transaction initiated by the host. These structures are the basis for the device controller functions.

15.9.1 Device Controller Initialization Overview

After hardware reset, the device is disabled until the Run/Stop bit is set to a 1 . In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint 0 before the device attach occurs. Shortly after the device is enabled, a USB reset occurs followed by setup packet arriving at endpoint 0. A Queue head must be prepared so that the device controller can store the incoming setup packet. In order to initialize a device, the DCD should perform the following steps: 1. Set the controller to device mode. Write 10 to the usb.USBMODE [CM] bit.

Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE. Set usb.OTGSC [OT] bit = 1. Minimum: Initialize dQHs for endpoint 0 for Tx and Rx. All control endpoint queue heads must be initialized before the control endpoint is enabled. Non-control queue heads must be initialized before the endpoint is used and not necessarily before the endpoint is enabled. For information on device queue heads, refer to section 15.7.1 Endpoint Queue Head Descriptor (dQH).

2.

Allocate and initialize dQHs.

3. 4.

Configure the Endpoint List Address. Write the memory address for the Queue Head endpoint list into the usb._ENDPOINTLISTADDR [31:11] bit field. Enable the software interrupt.

Enable IRQ interrupt signal in GIC (ID#53 for USB 0 and ID#76 for USB 1). Enable device interrupts in the usb.USBINTR register: USB interrupt [UI] USB Error Interrupt [UEI]

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Port change detect [PCI] USB Reset received [URI] DCSuspend [SLI]

For a list of available interrupts refer to Table 15-2 USB Interrupt and Status Register Bits. After the run bit is set, a device USB reset occurs. The DCD must monitor the reset event and adjust the DCD state as described in the Bus Reset section of the following Port State and Control section below. Endpoint 0 is designed as a control endpoint only and does not need to be configured using ENDPTCTRL0 register. It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework (Chapter 9) command set.

5.

Enable Run mode. Set Run/Stop bit to Run Mode.

15.9.2 Manage Transfer Descriptors

The function of the endpoint is to instruct the DMA engine to move data between system memory and the Tx and Rx FIFOs. Each endpoint has two data structures: one for IN and the other for OUT data transfers. The device mode data structures include a device Queue Head (dQH) and one or more device Transfer Descriptors (dTD). The dQH defines the type of data transfer and points to the first dTD. The dTD includes a system address pointer to the memory buffer(s) where data is either stored or read from. The dQHs are indexed (two for each endpoint) in the 24-element Endpoint Queue Head List. To setup a transfer, software constructs the dQH and dTD(s) for an IN or OUT operation. Software must maintain a consistent set of descriptors, schedules/lists, and data buffers in system memory for the controller. When the endpoint is ready to receive or send the data, software primes the endpoint. When an endpoint is primed, the device controller reads the associated dQH and dTD into the controllers dual-port RAM for easy access by the DMA and protocol engines. When the DMA for a dTD is done, the controller writes the dTD back to system memory with transfer results (status). If the terminate bit, T = 0 (do not terminate) then the controller fetches and processes the next dTD from system memory. If T = 1, then the controller stops processing the endpoint dQH and writes the dQH back to system memory.In a long link-list the controller will repeatedly cause the controller to read and write dTDs between system memory the controllers dual-port RAM.

Example: Initialize dQH

One pair of device queue heads must be initialized before an endpoint is primed to respond to the host. To initialize a device queue head (dQH): 1. 2. Write the wMaxPacketSize field as required by the USB specification Chapter 9 or application specific protocol. Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For IsoUSB endpoints, set the multiplier to 1, 2, or 3 as required bandwidth and in conjunction with the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for IsoUSB endpoints.

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3. 4. 5.

To terminate the Transfer: Set T = 1 in the Terminate bit of the next dTD. Write the Active bit in the status field to 0 . Write the Halt bit in the status field to 0 .

Note: The DCD must only modify dQH if the associated endpoint is not primed and there are no
outstanding dTD's.

Example: Operational Model for Setup Transfers

As discussed in 15.6.5 Control Endpoint Operational Model, setup transfer requires special treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH. 1. 2. Copy setup buffer contents from dQH - Rx to software buffer. Acknowledge setup packet by writing a 1 to the corresponding bit in usb.ENDPTSETUPSTAT. a. The acknowledge must occur before continuing to process the setup packet. b. After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH - Rx. Only the local software copy should be examined. 3. Check for pending data or status dTD's from previous control transfers and flush if any exist as discussed in section Flushing/De-priming an Endpoint. a. It is possible for the device controller to receive setup packets before previous control transfers complete. Existing control packets in progress must be flushed and the new control packet completed.

1.

Decode setup packet and prepare data phase (optional) and status phase transfer as required by the USB Chapter 9 or application specific protocol.

15.9.3 Manage Transfers with Transfer Descriptors

Example: Build a Transfer Descriptor
Before a transfer can be executed, a dTD must be built to describe the transfer. Use the following procedure for building dTDs. To hold the 8-DWord dTD in memory, allocate a 32-Byte block of system memory aligned to a 32-Byte boundary (address [4:0] = 00000 ). Write the following fields: 1. 2. 3. 4. 5. 6. 7. Initialize first 7 DWords. Write 0 all bits in all DWords. Program the Terminate Bit. If only one dTD or its the last dTD, set the terminate bit to 1. Fill in total bytes with transfer size. Set the interrupt on complete if desired. Initialize the status field with the active bit set to 1 and all remaining status bits set to 0 . Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer.

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Example: Execute a Transfer Descriptor

To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. Determine whether the link list is empty: . Check to see if pipe is empty (internal software representation of linked-list should indicate if any packets are outstanding). Case 1: Link list is empty 1. 2. 3. Write dQH next pointer and the dQH terminate bit to 0 as a single DWord operation. Clear active and halt bit in dQH (in case set from a previous error). Prime endpoint by writing 1 to correct bit position in usb.ENDPTPRIME.

Case 2: Link list is not empty 1. 2. 3. 4. 5. Add dTD to end of linked list. Read correct prime bit in usb.ENDPTPRIME - if 1 DONE. Set the usb.USBCMD [ATDTW] bit = 1 . Read correct status bit in usb.ENDPTPRIME. (store in tmp. variable for later) Read usb.USBCMD [ATDTW] bit. If 0 go to step 3. If 1 continue to step 6. 6. 7. 8. Write usb.USBCMD [ATDTW] bit = 0 . If status bit read in (4) is 1 DONE. If status bit read in (4) is 0 then Goto Case 1: step 1.

Transfer Completion
After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if the interrupt on complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, the DCD can check the status bits to determine success or failure. Caution: Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, the DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared). By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed successfully. Success is determined with the following combination of status bits: Active = 0 Halted = 0 Transaction Error = 0 Data Buffer Error = 0

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Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the device error matrix. In addition to checking the status bit, the DCD must read the Transfer Bytes field to determine the actual bytes transferred. When a transfer is complete, the Total Bytes transferred is decremented by the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reach 0, but for receive packets, the host might send fewer bytes in the transfer according the USB variable length packet protocol.

Example: Flushing/De-priming an Endpoint

It is necessary for the DCD to use the flush bit(s) to de-prime one or more endpoints when a USB device reset is received or when a broken control transfer occurs. There can also be application specific requirements to stop transfers in progress. The following procedure can be used by the DCD to stop a transfer in progress and ensure the transfer has stopped: 1. 2. Write a 1 to the corresponding bit(s) in usb.ENDPTFLUSH. Wait until all bits in usb.ENDPTFLUSH are 0 . Software interrupt routine note: This operation can take a large amount of time depending on the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine. 3. Read usb.ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now 0 . If the corresponding bits are 1 after step #2 has finished, then the flush failed: in very rare cases, a packet is in progress to the particular endpoint when commanded flush using usb.ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD might need to repeatedly flush any endpoints that fail to flush be repeating steps 13 until each endpoint is successfully flushed. Note: A time out counter can be programmed to recover from when an endpoint flush fails.

Device Errors
Table 15-16 summarizes packet errors that are not automatically handled by the device controller.

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Table 15-16: Error

USB Device Errors Direction Data Buffer Transaction Packet Error Bit Error Bit Type (dTD.Status (dTD.Status bit 5) bit 3)
Any

Description
Number of bytes received exceeded max. packet size or total buffer length. This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the endpoint, then those will not be executed. CRC Error on received isochronous packet. Contents not guaranteed to be correct. Host failed to complete the number of packets defined in the dQH.Mult field within the given (micro)frame. For scheduled data delivery the DCD might need to readjust the data queue because a fulfillment error will cause Device Controller to cease data transfers on the pipe for one (micro)frame. During the dead (micro)frame, the Device Controller reports error on the pipe and primes for the following frame.

Overflow

Rx

Isochronous Packet

Rx

Iso

Isochronous Fulfillment

Both

Iso

Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data buffer overflow. However, for IsoUSB endpoints, errors packets are not retried and errors are tagged as indicated.

15.9.4 Service Device Mode Interrupts

Note: The interrupt service routine must consider that there are high-frequency, low-frequency
operations, and error interrupts.It is likely that multiple interrupts will stack up on a call to the Interrupt Service Routine (ISR) and then during the execution of the interrupt service routine.

The interrupt handling strategy is up to the user. The ISR can poll the high-frequency and then low-frequency interrupts before exiting. If another interrupt is detected and processed, then the ISR would perform another last scan of the interrupts before exiting.

High-Frequency Interrupts
High frequency interrupts , in particular, should be handed in the order shown in Table 15-17. The most important of these are the first two, 1a and 1b. They have equal priority because the software must acknowledge a setup token in the timeliest manner possible to have the control endpoint and buffer always available for another Setup token. The SOF interrupt is next important.

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Table 15-17: Execution Order

1a

USB Device High Frequency Interrupt Interrupt

USB Interrupt ENDPTSETUPSTATUS USB Interrupt ENDPTCOMPLETE SOF Interrupt

usb.USBSTS

Action
Copy contents of setup buffer and acknowledge setup packet. Process setup packet according to USB 2.0 Chapter 9 or application specific protocol.

[UI]

1b 2

[UI] [SRI]

Handle completion of dTD. Action as deemed necessary by application. This interrupt might not have a use in all applications.

Low-Frequency Interrupts
The low frequency events include the following interrupts. These interrupt can be handled in any order since they do not occur often in comparison to the high-frequency interrupts. Table 15-18: USB Device Low Frequency Interrupt usb.USBSTS
[PCI] [SLI] [URI]

Interrupt
Port Change Suspend Reset Received

Action
Change the software state information. Change the software state information. Change the software state information. Abort pending transfers.

Error Interrupts
Error interrupts will be least frequent and should be placed last in the interrupt service routine. Table 15-19: USB Device Error Interrupt usb.USBSTS
[UEI]

Interrupt
USB Error

Action
This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt (with ENDPTCOMPLETE). Unrecoverable error. Immediate Reset of controller, free transfers buffers in progress and restart the software.

System Error

[SEI]

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15.10 Host Mode Data Structures

The programming model follows the EHCI specification model and includes additional registers and bits to support a virtual transaction translator that is embedded into the DMA and protocol engines of the high speed host controller. The Rx and Tx data FIFOs must respond to the USB in real-time. Packet sizes can be up to 1024 bytes. The transfer descriptors must have memory bandwidth for accessing descriptors and DMA to/from the FIFOs. The embedded transaction translator uses QH and qTD descriptors for interrupt endpoints and siTDs for isochronous endpoints. The host controller is a schedule driven environment of periodic (interrupt / isochronous) and asynchronous (control / bulk) data transfers.

EHCI Enhancements and Deviations

These are listed in section 15.11 EHCI Implementation.

Transfer Schedules
The structures of the Transfer Schedules are defined in the EHCI specification.

Suspend and Resume

The programming model for suspend and resume is defined in the EHCI specification.

15.10.1 Host Controller Transfer Schedule Structures

The host controller uses two types of schedules to communicate control, status, and data between the HCD and the EHCI-compatible host controller in support of USB functions: periodic and asynchronous. The HCD writes the data structures for these schedules in to system memory (32-bit address space) and the controller hardware reads and modifies these structures as it executes the transaction schedules. The periodic schedule includes the periodic frame list which is the root of all periodic (isochronous and interrupt transfer type) transfers, refer to section 15.10.2 Periodic Schedule. The asynchronous schedule includes the bulk and control queue heads list which is a circular set of pointers which are at the root of all the bulk and control transfer types, refer to section 15.10.3 Asynchronous Schedule. The host controller uses different types of descriptors for the periodic and asynchronous schedules in support of the Isochronous, Interrupt, Control and Bulk transfers as described in section 15.12.1 Descriptor Usage. Isochronous data streams are managed using isochronous transaction descriptors (iTD).

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Isochronous split transaction data streams are managed with split-transaction isochronous transfer descriptors (siTD). Interrupt, Control, and Bulk data streams are managed via queue heads (QH) and queue element transfer descriptors (qTD). These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction.

15.10.2 Periodic Schedule

The periodic schedule provides interrupt and isochronous transfers by using the Periodic Frame list of elements and transfer descriptors as shown in Figure 15-15.
X-Ref Target - Figure 15-15

Programmable number of elements: 8, 16, 32, 1024. Programmed by usb.USBCMD [FS2] [FS0]

Periodic Frame List (EHCI)

Isochronous Transfer Descriptors

Example

Frame 8 Elements Frame 7 Elements Frame 6 Elements Frame 5 Elements

Interrupt QH executed every Frame Last QH has terminate

bit set, T = 1. Link Pointer

Periodic Frame List Element Address (32-bit system address)

Frame 4 Elements Frame 3 Elements Frame 2 Elements

Interrupt QH executed every 4 Frames

Link Pointer

000 usb.FRINDEX
advanced for every USB Frame.

Frame 1 Elements Frame 0 Elements

Interrupt QH executed every 8 Frames

usb.PERIODLISTBASE_ [31:12]
UG585_c15_43_030713

Figure 15-15:

USB Host Periodic Schedule with Example

Periodic Frame List

The host controller uses the Periodic Frame List to schedule isochronous and interrupt transfers. The periodic frame list is written into memory by the HCD. The host controller hardware reads the elements using the usb.PERIODICLISTBASE_ base address and the FRINDEX index registers. The current element within the periodic frame list is pointed to by the FRINDEX register. The Periodic Frame List implements a sliding window of work over time.

Note: The periodic frame list is a 4 KB page-aligned array for pointers to Isochronous and interrupt

transfer descriptors. The length of the frame list is programmable: 8, 16, 32, 64, 128, 256, 512, or 1024 elements using the usb.USBCMD [FS2] and [FS0] bit fields. When [FS2] is set = 0, then the EHCI programming model: 256, 512 and 1024 elements can be used in [FS0]. The length of the frame list affects the amount of system memory to allocate and the number of periodic transactions that can be queued. The HCD writes the memory address of the first element in the periodic frame list in the usb.PERIODICLISTBASE_ [PERBASE_] bit field. The controller beings processing the periodic frame list when the (micro)frame time stamp occurs.

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Table 15-20: Bits

USB Host Periodic Frame List Element Bit Fields Bit Field

Description
Frame List Link Pointer (system memory pointer, 32-byte aligned): The referenced object might be: an isochronous transfer descriptor (iTD for HS devices), a split-transaction isochronous transfer descriptor (siTD for FS isochronous endpoints), or a queue head (QH for FS/LS/HS interrupts). Set = 00. Transaction Descriptor Type, TYP. Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field. Terminate Linking, T: 0: Continue linking using Frame List Link Pointer. 1: Terminate transaction (done), host controller ignores the link pointer.

31:5

Pointer

4:3 2:1

reserved TYP

Note: The HCD should write only periodic schedule items (QH, iTD, siTD, FSTN) into the periodic
schedule. When using QH, it is an interrupt endpoint.

15.10.3 Asynchronous Schedule

The asynchronous schedule includes a circular list of queue heads for control and bulk transfers. The host controller executes the data transfers after the periodic schedule is handled. This happens: after the controller processes the periodic list the periodic list is disabled, or the periodic list is empty.

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X-Ref Target - Figure 15-16

Aysnchronous Queue Heads

(Bulk and Control)

Round Robin Priority. QHs are processed as Bandwidth allows.

Asynchronous QH Address Pointer (32-bit system address)

Start of List

Queue Head 0 Queue Head 1 Queue Head 2

00000 Insert and Remove QHs as needed usb.ASYNCLISTADDR_ [31:05]

Queue Head n
End of List

UG585_c15_44_030713

Figure 15-16:

USB Host Controller Asynchronous Schedule Organization

The asynchronous list is a simple circular list of queue heads that are aligned on 32-byte address boundaries. The usb.ASYNCLISTADDR_ [31:5] bit field is a pointer to the next queue head. This bit field is initialized by software. Hardware uses this field to traverse the Asynchronous schedule. Hardware does not modify this field. The Asynchronous schedule implements a pure round-robin service for the queue heads. Each queue head has one or more transfer descriptors (qTDs). The number of queue heads in the circular can be added to and reduced. The number of QHs is not limited by the EHCI specification.

15.11 EHCI Implementation

The host controller utilizes the programming mode of the Intel EHCI 1.0 specification. This includes register models and host functionality.

15.11.1 Overview
The host controller operational mode is nearly compatible with the EHCI 1.0 specification. There are a few differences and enhancements to handle an FS/LS link: Embedded Transaction Translator EHCI Reserved Bits No PCI registers SOF Interrupt

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Embedded Transaction Translator

The host controller uses the DMA and protocol engines to emulate the transaction translator (TT) for FS/LS devices attached to Zynq. The embedded transaction translator (TT) affects multiple functions in the host controller:

Discovery Mechanism, refer to section 15.11.3 EHCI Functional Changes for the TT FS/LS Data Structures, refer to section 15.11.6 FS/LS Data Structures Operational Model of the TT, refer to section 15.11.7 Operational Model of the TT Capability and Operational registers/bits, refer to section 15.11.3 EHCI Functional Changes for the TT PHY Rx Commands, refer to section 15.11.3 EHCI Functional Changes for the TT

The embedded transaction translator is described in section 15.11.2 Embedded Transaction Translator.

EHCI Reserved Bits

EHCI reserved fields should be set to zero, except those that are assigned to other functions. The register set is summarized in section 15.3.4 Register Overview and detailed in Appendix B.

No PCI Bus Registers

This controller does not have a PCI Interface and the PCI configuration registers described in the EHCI specification are not applicable (e.g., the frame adjustment register is not supported; the starts of the microframes are timed by the controllers timers to deliver 125-microsecond intervals based on the 60 MHz clock from the ULPI PHY).

SOF Interrupt
This SOF Interrupt a free running 125-microsecond interrupt for the host controller. EHCI does not specify this interrupt but it has been added for convenience and as a potential an HCD time base. The interrupt is indicated and enabled in the USBSTS and USBINTR registers.

Capability Register Bit Fields Added

The following additions have been added to the capability registers: usb.HCSPARAMS [N_TT] usb.HCSPARAMS [N_PTT}

Operational Register and Bit Field Added

The following additions have been added to the operational registers: TTCTRL is a new register. Addition of two-bit Port Speed: usb.PORTSC1 [PSPD].

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15.11.2 Embedded Transaction Translator

The host controller emulates one transaction translator (TT) with up to 16 periodic (Iso/Int) contexts and 2 asynchronous (bulk/ctrl) contexts. The TT allows FS/LS devices to be attached directly to the controller in host mode without the need for hardware to implement a companion controller. The transaction translator is modeled as an extension to EHCI specification by making use of the standard data structures and operational models that exist in the EHCI specification. The TT is responsible for: All error checking Field generation checking Formatting of all the necessary handshake actions Ping and data response packets on the bus

For any signal that must be generated based on a USB based time in the host controller, the protocol engine also generates all of the token packets required by the USB protocol. There is no separate transaction translator hardware to handle FS/LS protocols. The transaction translator function implemented within the DMA and the protocol engine blocks to support direct connection to LS and FS devices.

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Functional Block Diagram

X-Ref Target - Figure 15-17

Traditional Hardware Based Companion Controller In a Hub-based Design

Embedded Transaction Translator in Host Mode Using EHCI Software Model

EHCI Shared Memory EHCI Software Stack

HS USB 2.0

High-speed Handler

EHCI High Speed Controller

B/C Transfer Iso/Int State & Context

Iso/Int Transfer (2) (16) Iso/Int Transfer

(16) Iso/Int State & Context B/C State & Context B/C State & Context

TT Traffic Management

Small Latency FIFOs

Iso/Int Startsplit FIFO Iso/Int Compl. Split FIFO B/C In/Out FIFO B/C In/Out FIFO

Latency FIFOs

Full/Low Speed Protocol Engine

High Speed Protocol Engine

Full/Low Speed Handler

FS/LS USB

Port Controller
FS/LS USB
UG585_c15_11_030413

Figure 15-17:

USB Host Embedded Transaction Translator Implementation

On the left side of Figure 15-17 is a typical hub implementation with a companion transaction translator controller. It shows two ongoing asynchronous transactions capable of ping-pong access from each end. Periodic traffic is aggregated into a single data stream for each direction while a table of state and context for each pipe is stored within the transaction translator. The right side of Figure 15-17 shows how the same functions have been integrated into the host controller. The advantage of integrating those functions into the host controller is that the changes to the EHCI host controller driver (HCD) are minimal while allowing direct connection of FS and LS devices without the need for a companion controller or external USB 2.0 hub. In addition, the host controller with the transaction translator requires less local data storage than a hub-based transaction translator because the data storage is provided by main memory instead of hardware-based RAM. The host controller supports 16 periodic contexts and 2 asynchronous contexts.

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15.11.3 EHCI Functional Changes for the TT

This section includes: Port Reset Timer to off-load software Port Speed detection

In a standard EHCI controller design, the Host controller driver (HCD) detects a full-speed or low-speed device by noting if the port enable bit is set after the port reset operation. The port enable is set after the port reset operation when the host and device negotiate a High-Speed connection (i.e., chirp completes successfully). Because the controller emulates a transaction translator (TT), the port enable is always set after the port reset operation regardless of the result of the host device chirp result. The resulting port speed is indicated by the usb.PORTSC1 [PSPD] bit field. Therefore, a standard EHCI HCD requires alteration to handle direct connection to Full and Low speed devices or hubs. The changes are fundamental and summarized in Table 15-21. Table 15-21: Function
Hub Speed

USB EHCI Functional Changes for the Embedded Transaction Translator Standard EHCI
After port enable bit is set following a connection and reset sequence, the device/hub is assumed to be HS. FS and LS devices are assumed to be downstream from a HS hub thus, all port-level control is performed through the Hub Class to the nearest Hub.

Embedded Transaction Translator

After port enable bit is set following a connection and reset sequence, the device (hub) speed is noted from PORTSC1. FS/LS device can be either downstream from an HS hub or directly attached. When its downstream, then port-level control is done using the Hub Class through the nearest Hub. When a FS/LS device is directly attached, then port-level control is accomplished using PORTSC1. FS/LS device can be either downstream from a HS hub with HubAddr = X [HubAddr > 0] or directly attached; where HubAddr = [TTHA]. [TTHA] is programmable and defaults to 0. HubAddr is the address of the Root Hub where the bus transitions from HS to FS/LS (i.e. Split target hub is the root hub).

FS/LS devices

Split Target

FS and LS devices are assumed to be downstream from a HS hub with HubAddr=X; where HubAddr > 0 and HubAddr is the address of the Hub where the bus transitions from HS to FS/LS (i.e. Split target hub).

15.11.4 Port Reset Timer Enhancement

The port connect methods specified by EHCI require setting the port reset bit in the PORTSC register for a duration of 10 ms. The controller has timers that can count the 10 ms reset pulse to alleviate the requirement of the HCD to control this timing. The basic connection for the HCD software:

Example: Port Reset Timer for Discovery

This example show a simple attach event and the step that is made optional because of the Port Reset Timer feature.

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1. 2. 3.

Wait for device to attach. Receive a port connect change [Port Change Interrupt]. Reset the device. Writes a 1 to the usb.PORTSC1 [PR] bit. assumes the Optional Step to de-assert Reset. The HCD normally writes a 0 to the [PR] bit to de-assert the reset after 10 ms. This step, which is necessary in a standard EHCI design, can be omitted. Should the EHCI HCD attempt to write a 0 to the reset bit while a reset is in progress, the write is ignored and the reset continues until completion. Wait for device to be operational. Receive the [PCI] interrupt to indicate the Port Enable Change. The device is now operational and at this point the port speed has been determined.

4.

15.11.5 Port Speed Detection Mechanism

After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the EHCI implementation which re-assign the port owner for any device that does not connect at High-Speed, this host controller supports direct attach of non High-Speed devices. Therefore, the following differences are important regarding port speed detection: Port owner is read-only and always reads 0 . A 2-bit port speed indicator (PSPD) has been added to PORTSC1 to provide the current operating speed of the port to the HCD. A 1-bit High Speed indicator (HSP) has been added to PORTSC1 to signify that the port is in High-Speed vs. Full/Low Speed - This information is redundant with the 2-bit Port Speed indicator above.

15.11.6 FS/LS Data Structures

The data structures used by the TT for FS/LS transactions are similar to an HS hub. The hub address and endpoint speed fields should be set for directly attached FS/LS devices and hubs: QH (FS/LS)- Asynchronous (Bulk and Control endpoints) and Periodic (Interrupt endpoint)

Hub Address = TTHA (default TTHA = 0 ) Transactions to directly attached device or hub. QH.EPS = Port Speed (for both FS and LS) QH.EPS = Downstream Device Speed Transactions to a device downstream from direct attached HS hub. Maximum Packet Size must be less than or equal 64 or undefined behavior might result. When QH.EPS = 01 (LS) and usb.PORTSC1 [PSPD] = 00 (FS), a LS-pre-PID will be sent before the transmitting LS traffic. All FS IsoUSB transactions: Hub Address = (default TTHA = 0 ) siTD.EPS = 00 (full speed)

siTD (FS) - Periodic (ISO endpoint)

Maximum Packet Size must less than or equal to 1023 or undefined behavior might result.

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Note: FSTN data structures are used for FS and LS devices that are downstream of a high speed hub
(not when FS or LS device is connected directly to the host controller.)

15.11.7 Operational Model of the TT

The operational models are well defined for the behavior of the transaction translator (see USB 2.0 specification ) and for the EHCI controller to move packets between system memory and a USB-HS hub. Since the transaction translator exists within the host controller there is no physical bus between EHCI HCD and the USB FS/LS bus. These sections briefly discuss the operational model for how the EHCI and transaction translator operational models are combined without the physical bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0 transaction translator operational models.

Microframe Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between the Host (H) and the Bus (B). The embedded transaction translator shall use the same pipeline algorithms specified in the USB 2.0 specification for a Hub-based Transaction Translator. All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers are complete. As an example of the microframe pipeline implemented in the embedded transaction translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute on the bus in B-frame 0. It is important to note that when programming the S-mask and C-masks in the EHCI data structures to schedule periodic transfers for the embedded transaction translator, the EHCI HCD must follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream hub-based transaction translators. Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to Hframe and B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start of B-frame 0.)

Split Transfer State Machines

When the controller attaches to a downstream FS/LS device via an HS hub, the controller can initiates split transfers to allow for traffic to other devices to be intertwined. The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded transaction translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an internal operation to the embedded transaction translator. Table 15-22 summarizes the conditions where handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.

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Table 15-22:

USB Handshake Emulation Conditions Condition TT Response

NAK ERR ACK No Handshake (OK) Bus Time Out NYET Actual Handshake

Start-Split: All asynchronous buffers full. Start-Split: All periodic buffers full. Start-Split: Success for start of async. transaction. Start-Split: Start periodic transaction. Complete-Split: Failed to find transaction in queue. Complete-Split: Transaction in queue is busy. Complete-Split: Transaction in queue is complete.

Asynchronous Transaction Scheduling and Buffer Management

The following USB 2.0 specification items are implemented in the Transaction Translator: USB 2.0 - 11.17.3 USB 2.0 - 11.17.4 USB 2.0 - 11.17.5 Sequencing is provided and a packet length estimator ensures no full-speed/low-speed packet babbles into SOF time. Transaction tracking for 2 data pipes. Clear_TT_Buffer capability provided through the use of the TTCTRL register.

Periodic Transaction Scheduling and Buffer Management

The following USB 2.0 specification items are implemented in the transaction translator: USB 2.0 - 11.18.6.[1-2] Abort of pending start-splits

EOF (and not started in microframes 6) Idle for more than 4 microframes (Abort of pending complete-splits) EOF Idle for more than 4 microframes Transaction tracking for up to 16 data pipes.

USB 2.0 - 11.18.[7-8]

Caution: L imiting the number of tracking pipes in the embedded -TT to four (4) will impose the restriction that no more than four periodic transactions (INTERRUPT/ISOCHRONOUS) can be scheduled through the TT per frame. the number 16 was chosen in the USB specification because it is sufficient to ensure that the high-speed to full-speed periodic pipeline can remain full. keeping the pipeline full puts no constraint on the number of periodic transactions that can be scheduled in a frame and the only limit becomes the flight time of the packets on the bus.

Note: There is no data schedule mechanism for these transactions other than the microframe

pipeline. The emulated TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior might result.

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15.11.8 Port Test Mode

Port Test Control mode behaves as described by EHCI. The modes are set using the usb.PORTSC1 [PTC] bit field.

15.12 Host Data Structures Reference

These descriptor data structures are compatible with the EHCI specification with some differences as noted in section 15.11 EHCI Implementation. The data structures defined in this section are (from the host controller's perspective) a mix of read-only and read/writable fields. The host controller preserves the read-only fields.

Section Content
15.12.1 Descriptor Usage 15.12.2 Transfer Descriptor Type (TYP) Field 15.12.3 Isochronous (High Speed) Transfer Descriptor (iTD) 15.12.4 Split Transaction Isochronous Transfer Descriptor (siTD) 15.12.5 Queue Element Transfer Descriptor (qTD) 15.12.6 Queue Head (QH) 15.12.7 Transfer Overlay Area 15.12.8 Periodic Frame Span Traversal Node (FSTN)

15.12.1 Descriptor Usage

Table 15-23: USB Host Descriptor Usage Periodic Frame List Isochronous
yes no no yes yes

Descriptors
iTD, siTD QH, qTD FSTN (Low-, Full-speed)

Asynchronous List Bulk

no yes

Interrupt

Control
no yes

15.12.2 Transfer Descriptor Type (TYP) Field

The Transaction Type bit field is defined and used in the situations listed in Table 15-24.

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Table 15-24:

USB Host Transfer Descriptor Type (TYP) Bit Field iTD 00

X X ~ ~ ~

Data Structure
Periodic Frame List iTD siTD QH FSTN

QH 01
X ~ X ~ ~

siTD 10
X ~ ~ X ~

FSTN Description 11
X ~ ~ ~ X Figure 15-15 USB Host Periodic Schedule with Example Table 15-25 USB Host Isochronous Transfer Descriptor (iTD) Format Table 15-29 USB Host Split-Transaction Isochronous Descriptor (siTD) Format Table 15-40 USB Host Queue Head (QH) Descriptor Format Table 15-45 USB Host Frame Span Traversal Node Descriptor (FSTN) Format

15.12.3 Isochronous (High Speed) Transfer Descriptor (iTD)

The format of a high-speed isochronous transfer descriptor is illustrated in Table 15-25. This structure is used only for high-speed isochronous endpoints. The iTDs must be aligned on a 32-byte boundary. Table 15-25:
Reference

USB Host Isochronous Transfer Descriptor (iTD) Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Next Link Pointer Status Status Status Status Status Status Status Status Transaction 0 Length Transaction 1 Length Transaction 2 Length Transaction 3 Length Transaction 4 Length Transaction 5 Length Transaction 6 Length Transaction 7 Length Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) Buffer Pointer (Page 5) Buffer Pointer (Page 6) Host Controller Read/Write
IOC IOC IOC IOC IOC IOC IOC IOC

3 00

0 T

DWord 0 1 2 3 4 5 6 7 8 9 10

Table 15-26 Next dTD Transaction Status and Control

TYP

PG * PG * PG * PG * PG * PG * PG * PG * EndPt IO

Transaction 0 Offset * Transaction 1 Offset * Transaction 2 Offset * Transaction 3 Offset * Transaction 4 Offset * Transaction 5Offset * Transaction 6 Offset * Transaction 7 Offset * R Device Address Maximum Packet Size reserved reserved reserved reserved reserved Host Controller Read-only Mult

Table 15-27

Buffer Pointer List

11 12 13 14 15

Table 15-28

* means these fields may be modified by the Host controller if the IO field indicates an OUT (DWords 1 to 8).

iTD DWord 0: Next Link Pointer

The first DWord of an iTD is a pointer to the next schedule data structure.

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Table 15-26: Bits

31:5 4:3 2:1 0

USB Host iTD DWord 0: Next Link Pointer Description

Next Link Pointer. These bits correspond to memory address signals [31:5], respectively. This field points to another isochronous transaction descriptor (iTD/siTD) or a QH. Reserved. Field reserved and should be set to 0. Transaction Descriptor Type, TYP. Set to 00 (iTD type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. Terminate transfer, T. 0 : link to the Next iTD Pointer field; the address is valid. 1 : end the transaction, the Next iTD Pointer field is not valid.

iTD DWords 1 to 8: Transaction Status and Control List

DWords 1 through 8 are transaction control and status. Each transaction description includes: Status results field Transaction length (bytes to send for OUT transactions and bytes received for IN transactions) Buffer offset. The PG and Transaction x Offset fields are used with the buffer pointer list to construct the starting buffer address for the transaction

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The host controller uses the information in each transaction description plus the endpoint information contained in the first three DWords of the Buffer Page Pointer list, to execute a transaction on the USB. Table 15-27: Bits
31:28

USB Host iTD Dwords 1 to 8: Transaction Status and Control List Description

Status: Active Status [31]. Set to 1 by the HCD to enable the execution of an isochronous transaction. When the transaction associated with this descriptor is completed, the host controller sets this bit to 0 indicating that a transaction for this element should not be executed when it is next encountered in the schedule. Data Buffer Error Status [30]. Set to a 1 by the host controller during status update to indicate that the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, no action is necessary. Babble Detected Status [29]. Set to 1 by the host controller during status update when 'babble' is detected during the transaction generated by this descriptor. Transaction Error Status [28]. Set to 1 by the host controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit can only be set for isochronous IN transactions. Transaction {7:0} Length. For an OUT transaction, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer. For an IN transaction, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the field the number of bytes successfully received. 000h: zero length data. 001h: one byte. 002h: two bytes. ... C00h: 3072 bytes (maximum). Interrupt On Complete, IOC. If this bit is set to 1, it specifies that when this transaction completes, the host controller should issue an interrupt at the next interrupt threshold. Page Select, PG. These bits are set by the HCD to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6. Transaction {7:0} Offset. This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting buffer address for this transaction.

27:16

15 14:12

11:0

iTD DWords 9 to 15: Buffer Page Pointer List

DWords 9-15 of an isochronous transaction descriptor are nominally page pointers (4KB aligned) to the data buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous, but allows the physical memory pages to be non-contiguous. Seven page pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow for 3 (transactions) * 1,024 (maximum packet size) * 8 (transaction records) (24,576 bytes) to be moved with this data structure, regardless of the alignment offset of the first page.

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Since each pointer is a 4KB aligned page pointer, the least significant 12 bits in several of the page pointers are used for other purposes. Table 15-28: Bits USB Host iTD DWords 9 to 15: Buffer Page Pointer List Description

DWord 9
31:12 11:8 7 6:0 Buffer Pointer (Page 0). 4KB-aligned pointer to system memory address bits [31:12]. Endpoint Number (EndPt). Select the endpoint for the device serving as the data source or sink. Reserved. Bit reserved for future use and should be initialized by the HCD to 0. Device Address. Select the specific device serving as the data source or sink.

DWord 10
31:12 11 Buffer Pointer (Page 1). 4KB-aligned pointer to system memory address bits [31:12]. Direction (IO). Select the high-speed transaction for an IN or OUT PID. 0 : OUT 1 : IN Maximum Packet Size. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). This field is used for high-bandwidth endpoints where more than one transaction is issued per transaction description (e.g., per microframe). This field is used with the Multi field to support high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. The HCD should not set a value larger than 1,024 ( 400h ). Any value larger yields undefined results.

10:0

DWord 11
31:12 11:2 1:0 Buffer Pointer (Page 2). 4KB-aligned pointer to system memory address bits [31:12]. Reserved. This bit reserved for future use and should be set to 0. Mult. Selects the number of transactions to execute per transaction description (e.g. per microframe). 00: Reserved. A 0 in this field yields undefined results 01: One transaction to be issued for this endpoint per microframe 10: Two transactions to be issued for this endpoint per microframe 11: Three transactions to be issued for this endpoint per microframe

DWords 12 to 15
31:12 11:0 Buffer Pointer (Pages 3 to 6). 4KB-aligned pointer to memory address bits [31:12]. Reserved. This bit reserved for future use and should be set to 0.

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15.12.4 Split Transaction Isochronous Transfer Descriptor (siTD)

This data structure is used to manage FS isochronous transfers via split transactions to USB 2.0 Hub Transaction Translator. There are additional fields used for addressing the hub and scheduling the protocol transactions (for periodic). Table 15-29:
Reference Table 15-30 Table 15-31 Table 15-32 Table 15-33 Table 15-34

USB Host Split-Transaction Isochronous Descriptor (siTD) Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Next Link Pointer IO P Port Number reserved R reserved
IOC

7 R

3 00

0 T

DWord 0 1 2 3 4

Next Ptr Endpt Cap/Char xfer State Buffer Page Ptrs Back Link

TYP

Hub Addr Total Bytes

reserved

EndPt

Device Address Microframe S-mask Status

Microframe C-mask Microframe C-prog-mask

Buffer Pointer (Page 0) Buffer Pointer (Page 1) Back Pointer Host Controller Read/Write

Current Offset reserved TP 0 Host Controller Read-only T-count T

5 6

siTD DWord 0: Next Link Pointer

DWord 0 of a siTD is a pointer to the next schedule data structure. Table 15-30: Bits
31:5

USB Host siTD DWord 0: Next Link Pointer Description

Next Link Pointer. This field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. Transaction Descriptor Type, TYP. Set to 10 (siTD type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. Terminate transfer, T. 0 : link to the Next Link Pointer field; the address is valid. 1 : end the transaction, the Next Link Pointer field is not valid.

2:1 0

siTD DWords 1 and 2: Endpoint Capabilities and Characteristics

DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent Companion Controller, and microframe scheduling control. Table 15-31: Bits USB Host siTD DWords 1 and 2:Endpoint State Description

DWord 1: Endpoint and Transaction Translator Characteristics

31 Direction, IO. Encodes the FS transaction as an IN or OUT. 0 : OUT 1 : IN Port Number. This field is the port number of the recipient Transaction Translator.

30:24

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Table 15-31:
23 22:16 15:12 11:8 7 6:0

USB Host siTD DWords 1 and 2:Endpoint State

Reserved. Bit reserved and should be set to 0. Hub Address, Hub Addr. Device address of the Companion Controllers hub. Reserved. Field reserved and should be set to 0. Endpoint Number, EndPt. 4-bit field selects the endpoint on the device serving as the data source or sink. Reserved. Bit reserved and should be set to 0. Device Address. Select the specific device serving as the data source or sink.

DWord 2: Microframe Schedule Control

31:16 15:8 Reserved. Field reserved and should be set to 0. Split Completion Mask, Microframe C-mask . This field (along with the Active and SplitXstate fields in the Status byte) is used to determine during which microframes the host controller should execute complete-split transactions. Refer to the text for details. Split Start Mask, Microframe S-mask . This field (along with the Active and SplitX-state fields in the Status byte) is used to determine during which microframes the host controller should execute start-split transactions. Refer to the text for details.

7:0

Microframe C-mask
The split completion mask field, siTD.Microframe C-mask, along with the Active and SplitXstate fields in the Status byte, is used to determine during which microframes the host controller should execute complete-split transactions. This field is a straight bit position field, so if bit [0] is set then the complete-split transaction should occur in the first microframe, if bit [1] is set = 1 then it should occur in the second microframe, and so on. When the criteria for using this field is met, a 0 value has undefined behavior. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the microframe C-Mask field is a 1, then this siTD is a candidate for transaction execution. There can be more than one bit in this mask set. The C-Mask can be set for multiple micro frames, as it is not known in which microframe the transaction will complete. So the C-Mask can be set for the micro frame after the S-Mask and all subsequent micro fames thereafter. The C-Mask field should not have a bit set to the same microframe as the S-Mask is set to.

Microframe S-mask
The split start mask field, siTD.Micro S-mask, along with the Active and SplitX-state fields in the Status byte, is used to determine during which microframes the host controller should execute start-split transactions. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the microframe S-mask field is a 1, then this siTD is a candidate for transaction execution. A 0 value in this field, in combination with existing periodic frame list, has undefined results. This field should have only one bit set to 1 at any given time. Having more than one bit set will result in undefined results.

siTD DWord 3: Transfer Status and Control

DWord 3 is used to manage the state of the split data transfer.

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Table 15-32: Bits

31

USB Host siTD DWord 3: Transfer Status and Control Description

Interrupt On Complete, IOC. 0 : Do not interrupt when transaction is complete 1 : Do interrupt when transaction is complete When the host controller determines that the split transaction has completed it will assert a hardware interrupt at the next interrupt threshold. Page Select, P. Used to indicate which data page pointer should be concatenated with the Current Offset field to construct a data buffer pointer (0 selects Page 0 pointer and 1 selects Page 1). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a 1 to a 0). Reserved. Field reserved and should be set to 0. Total Bytes To Transfer, Total Bytes. This field is initialized by the HCD to the total number of bytes expected in this transfer. Maximum value is 1,023 (3FFh ). Microframe Complete-split Progress Mask, uFrame C prog-mask . This field is used by the host controller to record which split-completes has been executed. Status [7:0]. Refer to text.

30

29:26 25:16 15:8 7:0

Status bits [7:0]

Active Status [7]. Set to 1 by the HCD to enable the execution of an isochronous split transaction by the Host Controller ERR Status [6] . Set to a 1 by the host controller when an ERR response is received from the Companion Controller. Data Buffer Error Status [5] . Set to a 1 by the host controller during status update to indicate that the host controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). In the case of an under run, the host controller will transmit an incorrect CRC (thus invalidating the data at the endpoint). If an overrun condition occurs, no action is necessary. Babble Detected Status [4] . Set to 1 by the Host Controller during status update when 'babble' is detected during the transaction generated by this descriptor. Transaction Error Status [3]. Set to 1 by the host controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit can only be set for isochronous IN transactions. Missed Microframe Status [2]. The host controller detected that a host-induced holdoff caused the host controller to miss a required complete-split transaction. Split Transaction State Status [1]. 0: Do Start Split. This value directs the host controller to issue a Start split transaction to the endpoint when a match is encountered in the S-mask. 1: Do Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint when a match is encountered in the C-mask.

Reserved [0]. Bit reserved for future use and should be set to 0.

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siTD DWords 4 and 5: Buffer Pointer List

DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page cross. The most significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers. The least significant 12 bits of each DWord are used as additional transfer state. Table 15-33: Bits USB Host siTD DWords 4 and 5: Buffer Pointers Description

DWord 4
31:12 11:0 Buffer Pointer (Page 0). 4KB aligned pointer to system memory address bits [31:12]. Current Offset. The 12 least significant bits of the Page 0 pointer is the current byte offset for the current page pointer (as selected with the page select bit (P field)). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a 1 to a 0).

DWord 5
31:12 11:5 4:3 Buffer Pointer (Page 1). 4KB aligned pointer to system memory address bits [31:12]. Reserved. Bit reserved for future use and should be set to 0. Transition position, TP. This field is used with T-count to determine whether to send all, first, middle, or last with each outbound transaction payload. The HCD must initialize this field with the appropriate starting value. The host controller must correctly manage this state during the lifetime of the transfer. The bit encodings are: 00: All. Entire FS transaction data payload is in this transaction (the payload is less than or equal to 188 bytes.) 01: Begin. First data payload for a FS transaction that is greater than 188 bytes. 10: Mid . Middle payload for a FS OUT transaction that is greater than 188 bytes. 11: End. Last payload for a FS OUT transaction that was greater than 188 bytes. Transaction count, T-Count . The HCD initializes this field with the number of OUT start-splits this transfer requires. Any value larger than 6 is undefined.

2:0

siTD DWord 6: Back Link Pointer

DWord 6 of a siTD is simply another schedule link pointer. This pointer is either 0 or references an siTD data structure. This pointer cannot reference any other schedule data structure. Table 15-34: Bits
31:5 4:1 0

USB Host siTD DWord 6: Back Pointer Description

Back Pointer. Physical memory pointer to a siTD. Reserved. Field reserved and should be set to 0. Terminate transfer, T. 0 : link to the Back Pointer field; the address is valid. 1 : end the transaction, the Back Pointer field is not valid.

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15.12.5 Queue Element Transfer Descriptor (qTD)

This data structure is only used with a queue head. This data structure is used for one or more USB transactions. This data structure is used to transfer up to 20,480 (5 times 4,096) bytes. The structure contains two structure pointers used for queue advancement, a DWord of transfer state, and a five-element array of data buffer pointers. This structure is 32 bytes (or one 32-byte cache line). This data structure must be physically contiguous. The buffer associated with this transfer must be virtually contiguous. The buffer can start on any byte boundary. A separate buffer pointer list element must be used for each physical page in the buffer, regardless of whether the buffer is physically contiguous. Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement. References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue head. Table 15-35:
Reference Table 15-36 Transfer Overlay Area Table 15-37 Table 15-38 DT Total Bytes Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) Host Controller Read/Write

USB Host Transfer Descriptor (qTD) Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Next qTD Pointer Alternate Next qTD Pointer
Transfer Results
IOC

0 T T

DWord 0 1 2 3 4 5 6 7

0000 0000 C_Page Cerr PID reserved reserved reserved reserved Host Controller Read-only Status Current Offset

Table 15-39

qTD DWord 0: Next Pointer

The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor. Table 15-36: Bits
31:5

USB Host qTD DWord 0: Next Element Transfer Pointer Description

Next Transfer Element Pointer, Next qTD Pointer. This field contains the physical memory address of the next qTD to be processed. The field corresponds to memory address bits [31:5], respectively. Reserved. Field reserved and should be set to 0. Terminate transfer, T. 0 : link to the Next qTD Pointer field; the address is valid. 1 : end the transaction, the Next qTD Pointer field is not valid.

4:1 0

qTD DWord 1: Alternate Next Element Pointer

The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the data stream to the next client buffer on short packet. To be more explicit the host controller will always use this pointer when the current qTD is retired due to short packet.

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Table 15-37: Bits

31:5

USB Host qTD DWord 1: Alternate Next Element Pointer Description

Alternate Next Transfer Element Pointer, Alternate Next qTD Pointer. This field contains the physical memory address of the next qTD to be processed in the event that the current qTD execution encounters a short packet (for an IN transaction). The field corresponds to memory address signals [31:5], respectively. Reserved. Field reserved and should be set to 0. Terminate transfer, T. 0 : link to the Alternate Next dTD Pointer field; the address is valid. 1 : end the transaction, the Alternate Next dTD Pointer field is not valid.

4:1 0

qTD DWord 2: Token

The third DWord of a queue element transfer descriptor contains most of the information the host controller requires to execute a USB transaction (the remaining endpoint-addressing information is specified in the queue head). The status field reflects the last transaction performed on this qTD.

Note: The field descriptions forward reference fields defined in the queue head. Where necessary,
these forward references are preceded with a QH notation. USB Host qTD DWord 2: DT, Total Bytes Description
Data Toggle, DT. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data Toggle Control bit in the queue head. Total Bytes to Transfer, Total Bytes . This field specifies the total number of bytes to be moved with this transfer descriptor. Refer to section Total Bytes to Transfer Parameter for more info. Interrupt On Complete, IOC. If this bit is set to a 1, it specifies that when this qTD is completed, the host controller should issue an interrupt at the next interrupt threshold. Current Page, C_Page. This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0 to 4. The host controller is not required to write this field back when the qTD is retired.

Table 15-38: Bits

31 30:16

15 14:12

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Table 15-38:
11:10

USB Host qTD DWord 2: DT, Total Bytes

Error Counter, Cerr. This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD. HCD write: 00: the controller will not count errors for this qTD and there will be no limit on the retries of this qTD. 01 to 11: the controller decrements this field for each consecutive USB transaction error [UEI] that occurs while processing this qTD. If the counter counts from 01 to 00, the controller marks the qTD inactive, sets the Halted bit = 1, and sets the usb.USBINTR [CERR] error status bit. Transaction Error Stall Babble Detected No Error Data Buffer Error Notes:
1. Detection of Babble or Stall automatically halts the queue head. Thus, count is not decremented 2. If the QH.EPS field indicates a HS device or the queue head is in the Asynchronous Schedule (and PID code indicates an IN or OUT) and a bus transaction completes and the host controller does not detect a transaction error, then the host controller should reset Cerr to extend the total number of errors for this transaction. For example, Cerr should be reset with maximum value (3) on each successful completion of a transaction. The host controller must never reset this field if the value at the start of the transaction is 00b. 3. Data buffer errors are host problems. They don't count against the device's retries.

Yes No, No, No, No,

see see see see

note note note note

1 1 2 3

below. below. below. below.

Note: The HCD must not program Cerr to a value of 0 when the QH.EPS field is programmed with a value indicating a FS or LS device. This combination could result in undefined behavior. 9:8 PID Code, PID. This field is an encoding of the token, which should be used for transactions associated with this transfer descriptor. Encodings are: 00: DUT. Token generates token (E1h) 01: IN. Token generates token (69h) 10: Setup. Token generates token (2Dh) (undefined if end-point is an Interrupt transfer type, e.g. microFrame S-mask field in the queue head is non-zero.) 11: Reserved. Active Status. Set to 1 by the HCD to enable the execution of transactions by the host controller. Halted Status. Set to a 1 by the host controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to 0, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a 1, the Active bit is also set to 0. Data Buffer Error Status. Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, the Host Controller will force a timeout condition on the USB, invalidating the transaction at the source. If the host controller sets this bit to a 1, then it remains a 1 for the duration of the transfer.

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Table 15-38:
4

USB Host qTD DWord 2: DT, Total Bytes

Babble Detected Status. Set to a 1 by the host controller during status update when babble is detected during the transaction. In addition to setting this bit, the host controller also sets the Halted bit to a 1. Since babble is considered a fatal error for the transfer, setting the Halted bit to a 1 insures that no more transactions occur because of this descriptor. Transaction Error Status. Set to a 1 by the host controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). If the controller sets this bit to a 1, then it remains a 1 for the duration of the transfer. Missed Microframe Status. This bit is ignored unless the QH.EPS field indicates a full- or low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the controller to miss a required complete-split transaction. If the controller sets this bit to a 1, then it remains a 1 for the duration of the transfer. Split Transaction State Status. This bit is ignored by the host controller unless the QH.EPS field indicates a FS or LS endpoint. When a Full- or Low speed device, the host controller uses this bit to track the state of the split transaction. The functional requirements of the controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. 0 : Do Start Split. This value directs the host controller to issue a Start split transaction to the endpoint. 1 : Do Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint. Ping State/ERR Status. If the QH.EPS field indicates a HS device and the PID indicates an OUT endpoint, then this is the state bit for the Ping protocol. 0: Do OUT. This value directs the controller to issue an OUT PID to the endpoint. 1: Do Ping. This value directs the controller to issue a Ping PID to the endpoint. If the QH.EPS field does not indicate a HS device, then this field is used as an error indicator bit. It is set to a 1 by the controller whenever a periodic split-transaction receives an ERR handshake.

qTD DWord 3 to 7: Buffer page Pointer List

The last five DWords of a queue element transfer descriptor is an array of physical memory address pointers. These pointers reference the individual pages of a data buffer. The HCD initializes current offset field to the starting offset into the current page, where current page is selected via the value in the C_Page field. The field C_Page specifies the current active pointer. When the transfer element descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index to select an array element). If a transaction spans a 4 KB buffer boundary, the host controller must detect the page-span boundary in the data stream, increment C_Page and advance to the next buffer pointer in the list, and conclude the transaction via the new buffer pointer.

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Table 15-39: Bits

31:12 11:0

USB Host qTD DWord 3 to 7: Buffer Pointers Description

DWords 3 to 7: Buffer Pointer. 4KB page-aligned memory address. DWord 3: Current Offset. Byte offset into the active page (as selected by C_Page). The host controller is not required to write this field back when the qTD is retired. DWords 4 to 7: Reserved. Field reserved and should be set to 0.

15.12.6 Queue Head (QH)

The first three DWords of the QH include Static State information about the endpoint. The current qTD pointer is the system memory address pointer for the current qTD and is updated by the hardware when a new qTD is written (overlaid) in the QHs overlay area. Table 15-40:
Reference Table 15-41 Table 15-42 Table 15-43

USB Host Queue Head (QH) Descriptor Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Queue Head Horizontal Link Pointer RL Mult C Maximum Packet Length Hub Addr * Current qTD Pointer Next qTD Pointer Alternate Next qTD Pointer DT Total Bytes Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) Host Controller Read/Write reserved S-Bytes *
IOC

0 T

DWord 0 1 2 3

Static Endpoint State

Current Pointer

00 EPS EndPt I

TYP

H DTC

Device Address uFrame S-mask 00000 0000 NakCnt T T P

Port Number *

uFrame C-mask *

4 5 6 7 8 9 10 11

Transfer Overlay Area

Transfer Results Area

Table 15-44

C_Page

Cerr

PID

Status Current Offset C-prog-mask *

Split_Frame_Tag * reserved reserved

Table 15-45

Host Controller Read-only

* means these fields are used exclusively to support Split Transactions to USB 2.0 Hubs.

QH Horizontal Link Pointer, DWord 0

The first DWord of a Queue Head contains a link pointer to the next data object to be processed after any required processing in this queue has been completed, as well as the control bits defined below. This pointer can reference a queue head or one of the isochronous transfer descriptors. It must not reference a queue element transfer descriptor. Table 15-41: Bits
31:5

USB Host QH DWord 0: Link Pointer Description

Queue Head Horizontal Link Pointer. System memory address of the next data object in the periodic list.

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Table 15-41:
4:3 2:1 0

USB Host QH DWord 0: Link Pointer (Contd)

Reserved. Field reserved and should be set to 0. Transaction Descriptor Type, TYP. Set to 01 (QH type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. Termination Bit, T. Periodic List Schedule response: 0: link to the next QH; the Queue Head Horizontal Link Pointer field is valid. 1: end of the periodic list processing; the pointer field is invalid. Asynchronous Schedule response: Ignored.

QH DWords 1 and 2: Endpoint Capabilities and Characteristics

The second and third DWords of a Queue Head specifies static information about the endpoint. This information does not change over the lifetime of the endpoint. The host controller must not modify the bits in these DWords. Table 15-42: Bits USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics Description

DWord 1: Capabilities and Characteristics.

These are the USB endpoint characteristics including addressing, maximum packet size, and endpoint speed. 31:28 27 NAK Count Reload, RL. This field contains a value, which is used by the host controller to reload the NAK Counter field. Control Endpoint Flag, C. If the QH.EPS field indicates the endpoint is not a high speed device, and the endpoint is a control endpoint, then the HCD must set this bit to a 1. Otherwise, it should always set this bit to a 0. Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The maximum value this field can contain is 400h (1,024). Head of Reclamation List Flag, H . This bit is set by the HCD to mark a queue head as being the head of the reclamation list. Data Toggle Control, DTC. This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0 : Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head. 1 : Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue head from the DT bit in the qTD. Endpoint Speed, EPS . Select speed of the associated endpoint. 00: Full-Speed (12 Mb/s) 01: Low-Speed (1.5Mb/s) 10: High-Speed (480 Mb/s) 11: Reserved Endpoint Number, EndPt. This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.

26:16 15 14

13:12

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Table 15-42:
7

USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics

Inactivate on Next Transaction, I. The HCD requests that the host controller set the Active status bit to 0. This field is only valid when the QH is in the Periodic Schedule and the QH.EPS field indicates an FS or LS endpoint. Setting this bit to a 1 when the queue head is in the Asynchronous Schedule or the QH.EPS field indicates a high-speed device yields undefined results. Device Address. Select the specific device serving as the data source or sink.

6:0

DWord 2: Capabilities and Characteristics

These are adjustable parameters of the endpoint. They affect how the endpoint data stream is managed by the host controller. 31:30 High-Bandwidth Pipe Multiplier, Mult . This field is a multiplier used to key the host controller as the number of successive packets the host controller can submit to the endpoint in the current execution. The host controller makes the simplifying assumption that the HCD properly initializes this field (regardless of location of queue head in the schedules or other run time parameters). 00: Reserved. A 0 in this field yields undefined results. 01: One transaction to be issued for this endpoint per microframe. 10: Two transactions to be issued for this endpoint per microframe. 11: Three transactions to be issued for this endpoint per microframe. Port Number. This is used in the split-transaction protocol.This field is ignored by the host controller unless the QH.EPS field indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addr below), below which the full- or low-speed device associated with this endpoint is attached. Hub Address, Hub Addr. This field is used in the split-transaction protocol. This field is ignored by the host controller unless the QH.EPS field indicates a full-or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. Split Completion Mask, uFrame C-Mask . Refer to the text. Interrupt Schedule Mask, uFrame S-mask . Refer to the text.

29:23

22:16

15:8 7:0

uFrame C-Mask
The split completion mask field, QH.uFRAME C-Mask, is ignored by the host controller unless the QH.EPS field indicates this device is LS or FS and this QH is in the periodic list. This field (along with the Active and SplitX-state fields) is used to determine which microframes the host controller should execute a complete-split transaction. This field is a straight bit position field, so if bit [0] is set then the complete-split transaction should occur in the first microframe, if bit 1 is set then it should occur in the second microframe, and so on. When the criteria for using this field are met, a 0 value in this field has undefined behavior. This field is used by the host controller to match against the three low-order bits of the FRINDEX register. If the FRINDEX register bits decode to a position where the QH.uFrame C-Mask field is a 1, then this queue head is a candidate for transaction execution. There can be more than one bit in this mask set. The C-Mask can be set for multiple micro frames, as it is not known in which microframe the transaction will complete. So the C-Mask can be set for the micro frame after the S-Mask and all subsequent micro fames thereafter. The C-Mask field should not have a bit set to the same microframe as the S-Mask is set to.

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uFrame S-mask
The interrupt schedule mask field, QH.uFrame S-mask, is used for all endpoint speeds. The HCD should set this field = 0 when the QH is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint. The host controller uses the value of the three low-order bits of the FRINDEX register as an index into a bit position in this bit vector. If the QH.uFrame S-mask field has a 1 at the indexed bit position then this queue head is a candidate for transaction execution. If the QH.EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is determined by the PID field contained in the execution area. This field is also used to support split transaction types: Interrupt (IN/OUT). This condition is true when this field is non-zero and the QH.EPS field indicates this is either a full- or low-speed device. A 0 value in this field, in combination with existing in the periodic frame list has undefined results. This field should have only one bit set to 1 at any given time. Having more than one bit set will result in undefined results.

QH DWord 3: Current qTD Pointer

The DWord 3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay. The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is complete. Table 15-43: Bits
31:5

USB Host QH DWord 3 Description

Current Element Transaction Descriptor Link Pointer. Current qTD Pointer. This field contains the address Of the current transaction being processed in this queue and corresponds to memory address signals [31:5]. Reserved. Write 0.

4:0

15.12.7 Transfer Overlay Area

The nine DWords in this area represent a transaction working space for the host controller. The general operational model is that the host controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it follows the Queue Head Horizontal Link Pointer to the next queue head. The host controller will never follow the Next Transfer Queue Element or Alternate Queue Element pointers unless it is actively attempting to advance the queue. For the duration of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the transfer is complete, the results are written back to the original queue element.

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Table 15-44: Bits

USB Host Transfer Overlay Descriptors Description qTD DWord QH DWord

Next qTD Pointer

31:5 Next qTD Pointer. This field contains the address of the next transaction being processed in this queue and corresponds to memory address signals [31:5], respectively. Reserved. Write 0. Terminate transfer, T. 0 : link to the Next qTD Pointer field; the address is valid. 1 : end the transaction, the Next qTD Pointer field is not valid.

4:1 0

Alternate Next qTD Pointer

31:5 4:1 Alternate Next qTD Pointer. NAK Counter, NakCnt . This field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a Nak or Nyet response. This counter is reloaded from RL before a transaction is executed during the first pass of the reclamation list (relative to an Asynchronous List Restart condition). It is also loaded from RL during an overlay. Terminate transfer, T. 0 : link to the Alternate Next qTD Pointer field; the address is valid. 1 : end the transaction, the Alternate Next qTD Pointer field is not valid.

Total Bytes
31 30:16 15 14:12 11:10 9:8 7:0 0 Data toggle, DT. The Data Toggle Control controls whether the host controller preserves this bit when an overlay operation is performed. Total Bytes. Refer to section Total Bytes to Transfer Parameter for more info. Interrupt On Complete, IOC. The IOC control bit is always inherited from the source qTD when the overlay operation is performed. C_Page. Error Counter, Cerr. This two-bit field is copied from the qTD during the overlay and written back during queue advancement. Port ID, PID. Reserved. Write 0. Ping State, /PERR. If the QH.EPS field indicates a high-speed endpoint, then this field should be preserved during the overlay operation. 2 6

Buffer Pointer (page 0)

31:12 11:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Current Offset. 3 7

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Table 15-44:

USB Host Transfer Overlay Descriptors (Contd)

Buffer Pointer (page 1)

31:12 11:8 7:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Reserved. QH (split transactions only): C-prog-mask. qTD and non-split QH: Reserved. 4 8

Buffer Pointer (page 2)

31:12 11:5 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. S-bytes. This field is used to keep track of the number of bytes sent or received during an IN or OUT split transaction. The HCD must ensure that the S-bytes field in a qTD is 0 before activating the qTD. Split-transaction Frame Tag, Split_Frame_Tag. This field is used to track the progress of an interrupt split-transaction. This field is initialized to 0 during any overlay. 6 and 7 10 and 11 5 9

4:0

Buffer Pointer (pages 3 and 4)

31:12 11:0 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. Reserved.

15.12.8 Periodic Frame Span Traversal Node (FSTN)

This data structure is to be used only for managing Full- and Low-speed transactions that span a Host-frame boundary. The HCD must not use an FSTN in the Asynchronous Schedule. An FSTN in the Asynchronous schedule results in undefined behavior. Table 15-45:
Reference Table 15-46 Table 15-47

USB Host Frame Span Traversal Node Descriptor (FSTN) Format

Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Normal Path Link Pointer Back Path Link Pointer Host Controller Read-only 8 7 6 5 4 3 00 00 2 1 0 T T DWord 0 1 TYP TYP

FSTN DWord 0: Normal Path Pointer

The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any valid periodic schedule data type. Table 15-46: Bits
31:5

USB Host FSTN DWord: Normal Path Pointer Description

Normal Path Link Pointer. Address of the next data object to be processed in the periodic list and corresponds to memory address bits [31:5], respectively.

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Table 15-46:
4:3 2:1 0

USB Host FSTN DWord: Normal Path Pointer

Reserved. Field reserved and should be set to 0. Transaction Descriptor Type, TYP. Set to 11 (FSTN type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. Terminate bit, T. 0: Link Pointer field points to a valid system memory offset from CTRLDSSEGMENT and the FSTN is a Save-Place indicator. 1: Link Pointer field is invalid and the FSTN is a Restore indicator.

FSTN DWord 1: Back Path Link Pointer

The second DWord of an FTSN node contains a link pointer to a queue head. If the T-bit in this pointer is a 0, then this FSTN is a Save-Place indicator. Its TYP field must be set by the HCD to indicate the target data structure is a queue head. If the T-bit in this pointer is set to a 1, then this FSTN is the Restore indicator. When the T-bit is a 1, the host controller ignores the TYP field. Table 15-47: Bits
31:5 4:3 2:1 0

USB Host FSTN DWord 1: Back Path Link Pointer Description

Back Path Link Pointer. This field contains the address of a Queue Head. This field corresponds to memory address signals [31:5], respectively. Reserved. Field reserved and should be set to 0. Transaction Descriptor Type, TYP. Set to 11 (FSTN type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. Terminate bit, T.

1: Link Pointer field is invalid and the FSTN is a Restore indicator. 0: Link Pointer field points to a valid system memory offset from CTRLDSSEGMENT and the FSTN is a Save-Place indicator.

15.13 Programming Guide for Host Controller

The host controller driver software (HCD) provides a layered software architecture to control all aspects of a USB bus system. The HCD controls the functions of an embedded EHCI host controller. The USB driver layer provides all the USB driver functions to enumerate, manage and schedule a USB bus system, while the upper layers of the stack support standard USB device class interfaces to the device drives running on the embedded system.

15.13.1 Controller Reset

The controller has multiple types of resets, as described in section 15.15.2 Reset Types.

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15.13.2 Run/Stop
When the HCD sets the usb.USBCMD [RS] bit = 1, the controller proceeds to the execute the periodic and asynchronous schedules. The controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the host controller completes the current transaction on the USB and then halts. When the controller is finished with the transaction and has entered the stopped state, it writes a 1 to the usb.USBSTS [HCH] bit. Software should not write a 1 to the [RS] bit to enable the controller unless the controller is in the Halted state, usb.USBSTS [HCH] bit = 1.

15.14 OTG Description and Reference

The register bits that are used for OTG operations are not reset when software writes a 1 to the usb.USBCMD [RST] reset bit. These bits are identified in Table 15-1, page 359.

15.14.1 Hardware Assistance Features

The hardware assist mechanisms provide automated response and sequencing that might not be possible using software due to significant interrupt latency response times. The use of this additional circuitry is optional and can be used to assist the three sequences below. Auto-Reset [HAAR]: Reset after a connect event. Data-Pulse [HADP]: Generates a 7 ms pulse on the DP signal. B-Disconnect to A-Connect Event [HABA].

Auto-Reset Option
When the usb.OTGSC [HAAR] bit is set to 1, the host controller will automatically start a reset after a connect event. This shortcuts the normal process where the software is notified of the connect event and starts the reset. The software will still receive notification of the connect event but should not write the reset bit when the [HAAR] bit is set = 1. The software will be notified again after the reset is complete via the enable change bit in the PORTSC1 register which cause a port change interrupt. This hardware assistance feature will ensure the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met.

Data-Pulse
Writing a 1 to usb.OTGSC [HADP] bit will start a data pulse of approximately 7 ms in duration and then automatically cease the data pulsing. During the data pulse, the DP signal will be set and then cleared. This automation relieves the software from accurately controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the [HADP] and [DP] bits have returned low to recognize the completion or simply launch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-side supplies bus power. This hardware assistance feature will ensure data pulsing meets the OTG requirement of > 5 ms and < 10 ms.

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B-Disconnect to A-Connect
During HNP, the B-Disconnect occurs from the OTG A_suspend state and within 3 ms, the A-device must enable the pull-up on the DP signal in the A-peripheral state. When usb.OTGSC [HABA] is set = 1, the Host Controller port is in suspend mode, and the device disconnects, then this hardware assist begins. 1. 2. 3. 4. 5. 6. Reset the OTG controller. Set the OTG controller into device mode. Write the device run bit to a 1 and enable necessary interrupts including: USB Reset Enable [URE]; enables interrupt on USB bus reset to device Sleep Enable [SLE]; enables interrupt on device suspend Port Change Detect Enable [PCE]; enables interrupt on device connect

When the HCD has enabled this hardware assist, it must not interfere during the transition and should not write any control registers until it gets an interrupt from the device controller signifying that a reset interrupt has occurred or at least first verify that the controller has entered device mode. The HCD must not activate the soft reset at any time since this action is performed by hardware. During the transition, the HCD might see an interrupt from the disconnect and/or other spurious interrupts (i.e., SOF/etc.) that might or might not cascade and can be cleared by the soft reset depending on the HCD response time. After the controller has entered device mode by the hardware assist, the HCD must ensure that the usb.ENDPTLISTADDR is programmed properly before the host sends a setup packet. Since the end of the reset duration, which can be initiated quickly (a few microseconds) after connect, will require at a minimum 50 ms, this is the time for which the HCD must be ready to accept setup packets after having received notification that the reset has been detected or simply that the OTG is in device mode whichever occurs first. In the case where the A-peripheral fails to see a reset after the controller enters device mode and engages the DP-pull-up, the interrupt software signifying that a suspend has occurred. This assist will ensure the parameter TA_BDIS_ACON_MAX = 3 ms is met.

15.14.2 OTG Interrupt and Control Bits

The interrupt and control bits are included in one register, the OTGSC register. Changes in the status activity will latched events. The status bits indicate the current activity. Software reads the latched events and status activity bits to determine there was an event and its status. The IRQ interrupt signal to the GIC interrupt controller will be asserted to the GIC interrupt controller when both the interrupt enable bit (controlled by software) and the associated status activity bit (controlled by hardware) are equal to 1.

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Table 15-48:

USB OTG Status/Interrupt and Control Bits in the OTGSC register Interrupts Control Bits
7 6 5 4 3 2 1 HABA HADP IDPU DP OT HAAR VC 0: VD: Vbus Discharge enable (rw) 1: VC: VBus Charge enable (rw) 2: HAAR: Hardware Auto-Reset enable (rw) 3: OT: OTG Device mode DP M pull-down enable (rw) 4: DP: Assert DP pull-up during SRP (rw) 5: IDPU: ID Pull-up enable (rw) 6: HADP: Hardware Assist Data-pulse generator (rw) 7: HABA: Hardware Assist B-disconnect to A-connect (rw) 0 VD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 r Enable (R/W) r Latched Event (W1C) r Status (read-only) A Session Valid B Session Valid B Session End

Status Activity Latched Events Interrupt Enable

Data Pulse

Interrupts:

A VBus

15.15 System Functions

The system functions include clocks, resets, memory interfaces and system interrupts.
X-Ref Target - Figure 15-18

Zynq-7000
CPU_1x Clock 60 MHz ULPI Clock 8-bit ULPI 60 MHz Single Data Rate 12 MIO Pins Protocol Engine Port Controller and ULPI Link Wrapper 8-bit Data
DIR (direction) NXT (control) STP CLK

USB ID

1 ms

Host, Device or OTG

AHB
32-bit Master Interface

Arbitor Tx FIFO Rx FIFO Descriptors

CPU_1x
DMA Engine

DMA Control

Programmable Timers

MIO or EMIO

reset

External ULPI PHY & Board Logic

PS GPIO controller SelectIO Pins

Clock Domains

60 MHz ULPI

GPIO Clock

PL PS
4 EMIO Signals
Port Indicator x2 Power Control Power Fault

APB
32-bit Slave Interface

CPU_1x

Control and Status Registers

Interrupt

UG585_c15_45_030413

Figure 15-18:

USB Detailed System Block Diagram

15.15.1 Clocks
The vast majority of the controller logic is driven by the 60 MHz clock from the ULPI PHY. The controller's interconnect is driven by the AHB/APB interface CPU_1x clock which is generated by the PS clock subsystem.

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CPU_1x Clock
Refer to section 25.3 System-wide Clock Frequency Examples, for general clock programming information. The CPU_1x clock runs asynchronous to the CAN reference clock.

60 MHz PHY Clock

The external PHY provides a 60 MHz clock that the ULPI is syncd to and is used by the a majority of the controller logic.

15.15.2 Reset Types

To reset the controller, software writes a 1 to the usb.USBCMD [RST] bit. When the reset process is completed, the controller hardware sets this bit to 0. Once the reset is started, the controller cannot stop the process. Writing a 0 has no effect. When software writes a 1 to this bit, the Controller resets its internal pipelines, timers, counters, and state machines to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven to downstream ports. Software should not set this bit to a 1 when the host controller halt bit, usb.USBSTS [HCH], = 0. Attempting to reset an actively running host controller will result in undefined behavior.

Controller Resets
PS Reset System (full controller reset), usb.USBCMD [RST] bit (partial controller reset useful for OTG). OTG Mode Auto-Reset

ULPI PHY Reset

The USB controller does not have a reset output for the ULPI PHY. Instead, a PS GPIO can be connected to the PHY as shown in Figure 15-19, page 427.

USB Bus Reset

The host controller generates the standard USB reset as described in the EHCI specification. The optional light host reset is not supported. The response by the device controller is described in section 15.4.2 USB Bus Reset Response.

Summary of Resets
The controller has multiple reset sources and multiple reset domains. These are summarized in Table 15-49 USB Resets Summary List.

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Table 15-49:

fs

USB Resets Summary List Reset Name Controller State

Yes

Registers
Yes

IRQ
no

Reference
Chapter 26, Reset System. Reset values: Appendix B, Register Details. Device and Host Modes Section 15.14.1 Hardware Assistance Features Chapter 15, USB Host, Device, and OTG Controllers Software Example. Software Example.

PS System Reset AMBA (APB/AHB) Interface Reset slcr.USB_RST_CTRL [USBx_CPU1X_RST] usb.USBCMD [RST] (partial controller reset) OTG mode Auto-Reset Hardware Assistance usb.USBOTG [HAAR] PHY reset Output from PS GPIO controller Send USB Reset (Host Mode) Receive USB Reset (Device Mode)

Partial

no no

no effect no effect no effect

no effect no effect no effect

no no [URI]

15.15.3 PS Interrupts to GIC

Each controller generates its own interrupt to the PS Interrupt controller (GIC). Controller 0 generates IRQ #53 and controller 1 generates IRQ 76. Interrupts are described in section 15.3.5 Interrupt and Status Bits Overview.

15.15.4 APB Slave Interface

The 32-bit APB slave interface is used by the software to read and write the control and status registers. The interface is AMBA 3.0 compatible. All signals are used except PRESET_N and PSLVERR.

15.15.5 AHB Master Interface

The 32-bit AHB master interface is used by the DMA controller to read and write data packets and transfer descriptors. The interface is AMBA 3.0 compatible.

Unused Signals
All of the AHB interface signals are used except: PROT[3:0] are tied to 0001 (non-cacheable transactions).

15.16 I/O Interfaces

The controller has multiple I/O interfaces including the main ULPI that interfaces via MIO to the external PHY and the port indicator and power signals via EMIO. The routing of the ULPI through the MIO must be

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programmed. The routing of the signals through the EMIO is always available to logic in the PL that can route these signals to the SelectIO pins.

15.16.1 Wiring Connections

The wiring connections for both MIO and EMIO are shown in Figure 15-19.
X-Ref Target - Figure 15-19

ULPI PHY Zynq-7000

ULPI ULPI Signals via MIO CLK DIR NXT STP DATA
8-bit 60 MHz Single Data Rate

UTMI PHY Wrapper

UTMI PHY
UTMI Data In UTMI Data Out UTMI Clock UTMI Reset DP DM VBUS ID

Host, Device or OTG

USB D+ USB DVBUS USB ID

Other UTMI Signals

PS GPIO

GPIO

Ex: PHY Reset

Oscillator and PLL

USB Signals via EMIO

Port Indicators Pwr Select Pwr Fault Power, Port Signals

Board Components
UG585_c15_46_030413

Figure 15-19:

USB I/O Signal and PHY Wiring Diagram

15.16.2 MIO-EMIO Programming

MIO Pins
The ULPI signals from each controller are routed to specific MIO pins. In this chapter, refer to Table 15-50 USB ULPI Signals on MIO. A wiring diagram is shown in Figure 15-19, page 427. The general routing concepts and MIO I/O buffer configurations are explained in section 2.5 PS-PL MIO-EMIO Signals and Interfaces. A summary of the MIO pins is shown in section 2.5.4 MIO-at-a-Glance Table.

Example: Program I/O for Controller 1

These steps configure the USB controller 1 onto MIO pins 40 to 51.

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1.

Configure MIO pins 40, 44 - 47 and 49 -51 for data I/O. Write to the associated slcr registers, MIO_PIN_{40, 44-47}: a. c. e. f. Route USB ULPI data signal to I/O buffer. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by USB controller (TRI_ENABLE = 0 ). d. Slow CMOS edge.

2.

Configure MIO pins 41, 43, and 48 for input . Write to each of the slcr.MIO_PIN_{48, 43, 41} registers: a. c. e. f. Route USB ULPI input signals DIR to pin 41, STP to pin 43 and CLK to pin 48. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. Route USB ULPI output signal STP to pin 42. LVCMOS18 (refer to the register definition for other voltage options). Disable internal pull-up resistor. Disable HSTL receiver. b. Disable output (TRI_ENABLE = 1 ). d. Slow CMOS drive edge (benign setting).

3.

Configure MIO pin 42 for output. Write to the slcr.MIO_PIN_42 register: a. c. e. f. b. 3-state controlled by USB Controller (TRI_ENABLE = 0 ). d. Slow CMOS edge.

15.16.3 MIO-EMIO Signals

The ULPI interface signals are listed in Table 15-50. The port indicator and power signals are shown in Table 15-51. The 7z010 CLG225 device supports 32 MIO pins. Pin restrictions are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 15-50: USB ULPI Signals on MIO MIO Pins Default Input Value to Controller
~ 0 ~ 0

USB Port Signals

Transmit and receive data 4 Data bus direction control Stop the Transfer (end/interrupt) Data flow control signal

USB 0 USB 1
28 29 30 31 40 41 42 43

I/O
IO I O I

Name
USB{0,1}_ULPI_DATA4 USB{0,1}_ULPI_DIR USB{0,1}_ULPI_STP USB{0,1}_ULPI_NXT

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Table 15-50:

USB ULPI Signals on MIO MIO Pins Default Input Value to Controller
~ ~ ~ ~ 0 ~ ~ ~

USB Port Signals

Transmit and receive data 0 Transmit and receive data 1 Transmit and receive data 2 Transmit and receive data 3 Transceiver clock for ULPI Transmit and receive data 5 Transmit and receive data 6 Transmit and receive data 7

USB 0 USB 1
32 33 34 35 36 37 38 39 44 45 46 47 48 49 50 51

I/O
IO IO IO IO I IO IO IO

Name
USB{0,1}_ULPI_DATA0 USB{0,1}_ULPI_DATA1 USB{0,1}_ULPI_DATA2 USB{0,1}_ULPI_DATA3 USB{0,1}_ULPI_CLK USB{0,1}_ULPI_DATA5 USB{0,1}_ULPI_DATA6 USB{0,1}_ULPI_DATA7

Table 15-51:

USB Port Indicator and Power Signals on EMIO EMIO Signals Default Input I/O Value to Controller
O I O ~ 0 ~

USB Port Signals

Port Indicator Power Fault Power Select

Name
EMIOUSB{0,1}PORTINDCTL{0,1} EMIOUSB{0,1}VBUSPWRFAULT EMIOUSB{0,1}VBUSPWRSELECT

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Gigabit Ethernet Controller

16.1 Introduction
The Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC compatible with the IEEE 802.3-2008 standard capable of operating in either half or full duplex mode at all three speeds. The PS is equipped with two Gigabit Ethernet Controllers. Each controller can be configured independently. To access pins via MIO, each controller uses an RGMII interface (to save pins). Access to the PL is through the EMIO which provides the GMII interface. Other Ethernet communications interfaces can be created in the PL using the GMII available on the EMIO interface. For example, the PL can be used to implement these interfaces: SGMII and 1000 Base-X, in devices with GTX RGMII v2.0 for PHY devices with HSTL Class 1 drivers and receivers

Registers are used to configure the features of the MAC, select different modes of operation, and enable and monitor network management statistics. The DMA controller connects to memory through an AHB bus interface. It is attached to the controllers FIFO interface of the MAC to provide a scatter-gather type capability for packet data storage in an embedded processing system. The controllers provide MDIO interfaces for PHY management. The PHYs can be controlled from either of the MDIO interfaces.

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16.1.1 Block Diagram

A block diagram of one Ethernet controller is shown in Figure 16-1.
X-Ref Target - Figure 16-1

Device Boundry
MAC Transmitter MAC Receiver EMIO Status and Statistics Registers PL
GMII/MII

AHB Master

DMA Controller

AHB Interface FIFO

GMII to RGMII Adapter

RGMII

MIO Pins

User Defined

PL Signals

APB Slave

Frame Filtering
MDC, MDIO

EMIO

Register Interface

Control Registers

MIO Pins

UG585_c16_01_042512

Figure 16-1:

Ethernet Controller

16.1.2 Features
Each Gigabit Ethernet MAC controller has the following features: IEEE Standard 802.3-2008 compatible, supporting 10/100/1000 Mb/s transfer rates Full and half duplex operation RGMII interface with external PHY when using MIO pins GMII/MII interface to the PL to allow connection of interfaces such as TBI, SGMII, 1000 Base-X and RGMII v2.0 support using soft cores (Note: SGMII and 1000 Base-X interfaces require a gigabit transceiver, MGT) MDIO interface for physical layer management 32-bit AHB DMA master, 32-bit APB bus for control registers access Scatter-gather DMA capability Interrupt generation to signal receive and transmit completion, or errors and wakeup Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames Automatic discard of frames received with errors Programmable IPG stretch Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames

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Address checking logic for four specific 48-bit addresses, four type ID values, promiscuous mode, external address checking, hash matching of unicast and multicast destination addresses and Wake-on-LAN 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames Supports Ethernet loopback mode IPv4 and IPv6 transmit and receive IP, TCP and UDP checksum offload Recognition of 1588 rev. 2 PTP frames Statistics counter registers for RMON/MIB

16.1.3 System Viewpoint

Figure 16-2 shows Zynq system viewpoint for the Gigabit Ethernet controllers.
X-Ref Target - Figure 16-2

Device Boundry
IRQ ID# {54, 77} IRQ ID# {55, 78}
AHB Ethernet Wakeup Master Port

MIO - EMIO Gigabit Ethernet Controllers

Tx, Rx GMII Tx, Rx GMII Tx, Rx

Interconnect

GMII to RGMII Adapter

RGMII Tx, Rx

GigE {0, 1} CPU 1x Clock GigE {0, 1} CPU 1x Reset Slave Port

MIO Pins

Interconnect

APB

Control Registers

Time Stamp Unit

PTP

GigE {0, 1} Rx Reset GigE {0, 1} Ref Reset

EMIO

Management Interface

MDC, MDIO

PL

Tx Clock
GigE {0, 1} Ref Clock Internal Clock Source

Rx Clock
MIO Clock Source EMIO Clock Sources

Rx Clock

Tx, Rx Clocks

UG585_c16_02_071112

Figure 16-2:

System Viewpoint

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16.1.4 Notices
7z010 CLG225 Device
This device supports 32 MIO pins and at most one Ethernet interface through the MIO pins. This is shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. One or both of the Ethernet controllers can interface to logic in the PL. All of the 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

Jumbo Frames
Jumbo frames are not supported.

Half Duplex
Gigabit Half Duplex is not supported.

IEEE 1588 Time Stamp

IEEE 1588 version 2 introduces transparent clocks of which there are two kinds, peer-to-peer (P2P) and end-to-end (E2E). There is no transparent clock support in the time stamp unit.

16.2 Functional Description and Programming Model

The controller comprises four main components: MAC controlling transmit, receive, address checking, and loopback Control and status registers, statistics registers, and synchronization logic DMA controlling data transmit and receive through an AHB master interface Time stamp unit (TSU) for calculating the IEEE 1588 timer values

10/100/1000 Operation
The gigabit enable bit in the Network Configuration register selects between 10/100 Mb/s Ethernet operation and 1000 Mb/s mode. The 10/100 Mb/s speed bit in the network configuration register is used to select between 10 Mb/s and 100 Mb/s.

MDIO Interface
Both controllers provide MDIO interfaces, however, only one interface is needed to control both of the external PHYs due to the difference in PHY address.

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16.2.1 MAC Transmitter

The MAC transmitter can operate in either half duplex or full duplex mode, and transmits frames in accordance with the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the IEEE 802.3 specification is followed. Frame assembly starts by adding the preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. When the controller is configured for gigabit operation, the data output to the PHY uses all eight bits of the txd[7:0] output. In 10/100 mode, transmit data to the PHY is nibble wide and least significant nibble first using txd[3:0] with txd[7:4] tied to logic 0 . If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32 bit polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64 bytes. If the no-CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. The no-CRC bit can also be set through the FIFO. In full duplex mode (at all data rates), frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the back off time has elapsed. If the collision occurs during either the preamble or SFD, then these fields are completed prior to generation of the jam sequence. The back off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error is indicated and no further attempts are made if 16 consecutive attempts cause a collision. This operation is compatible with the description in Clause 4.2.3.2.5 of the IEEE 802.3 standard which refers to the truncated binary exponential back off algorithm. In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry are performed up to 16 times. When operating in gigabit mode, late collisions are treated as an exception and transmission is aborted, without retry. This condition is reported in the transmit buffer descriptor word 1 (late collision, bit 26) and also in the Transmit Status register (late collision, bit 7). An interrupt can also be generated (if enabled) when this exception occurs, and bit 5 in the Interrupt Status Register is set. When bit [28] is set in the Network Configuration register the IPG can be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG_STRETCH register. The least significant 8 bits of the IPG_STRETCH register multiply the previous frame length (including preamble) the next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration register. The IPG_STRETCH register cannot be used to shrink the IPG below 96 bits. If the back pressure bit is set in the Network Control register or if the half_duplex_flow_control_en input is set in 10M or 100M half duplex mode, the transmit block transmits 64 bits of data, which can

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consist of 16 nibbles of 1011 or in bit rate mode 64 1 s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half duplex mode.

16.2.2 MAC Receiver

All processing within the MAC receiver uses 16-bit data paths. The MAC receiver checks for valid preamble, FCS, alignment, and length. It then sends the received frames to the FIFO (to either the DMA controller or external to the IP core) and stores the frames destination address for use by the address checking block. When the TBI is selected, 16 bit words are passed directly from the PCS layer to the MAC receiver, except in 10 and 100 Mb/s SGMII modes when 8 bits are read. In 10 and 100 Mb/s SGMII modes the MAC rx_clk runs more slowly than the PCS rxc clock and the same 8 bits of data is read 5 or 50 times. If, during frame reception, the frame is found to be too long, a bad frame indication is sent to the FIFO. The receiver logic ceases to send data to memory as soon as this condition occurs. At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad. Ethernet frames are normally stored in DMA memory or to the FIFO complete with the FCS. Setting the FCS remove bit in the network configuration register (bit [17]) causes frames to be stored without their corresponding FCS. The reported frame length field is reduced by four bytes to reflect this operation. The receive block signals to the register block to increment the alignment, CRC (FCS), short frame, long frame, jabber or receive symbol errors when any of these exception conditions occur. If bit [26] is set in the network configuration CRC errors are ignored and frames with CRC errors are not discarded, though the Frame Check Sequence Errors Statistic register is still incremented. Bit[13] of the receiver descriptor word 1 is updated to indicate the FCS validity for the particular frame. This is useful for applications where individual frames with FCS errors must be identified. Received frames can be checked for length field error by setting the length field error frame discard bit of the Network Configuration register (bit [16]). When this bit is set, the receiver compares a frame's measured length with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded if the measured length is shorter. This checking procedure is for received frames between 64 bytes and 1,518 bytes in length. Each discarded frame is counted in the 10-bit length field Error Statistics register. Frames where the length field is greater than or equal to 0x0600 are not checked.

16.2.3 MAC Filtering

The MAC filter determines which frames should be written to the AHB interface FIFO and onto the DMA controller. Whether a frame is passed depends on what is enabled in the Network Configuration register, the state of the external matching pins, the contents of the specific address, type, and hash registers and the frame's destination address and type field.

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If bit [25] of the Network Configuration register is not set, a frame is not copied to memory if the Gigabit Ethernet controller is transmitting in half duplex mode at the time a destination address is received. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all-ones address is the broadcast address and a special case of multicast. The Gigabit Ethernet controller supports recognition of four specific addresses. Each specific address requires two registers, Specific Address register bottom and Specific Address register top. Specific address register bottom stores the first four bytes of the destination address and Specific Address register top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the Specific Address registers once they have been activated. The addresses are deactivated at reset or when their corresponding Specific Address register bottom is written. They are activated when Specific Address register top is written. If a receive frame address matches an active address, the frame is written to the FIFO and on to DMA controller, if used. Frames can be filtered using the type ID field for matching. Four type ID registers exist in the register address space and each can be enabled for matching by writing a one to the MSB (bit [31]) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match. The contents of each type ID registers (when enabled) are compared against the length/type ID of the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found. The encoded type ID match bits (Word 0, bit [22] and bit [23]) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, hence each is initially disabled. The following example illustrates the use of the address and type ID match registers for a MAC address of 21:43:65:87:A9:CB
Preamble SFD DA (Octet 0 - LSB) DA (Octet 1) DA (Octet 2) DA (Octet 3) DA (Octet 4) DA (Octet 5 - MSB) SA (LSB) SA SA SA SA SA (MSB) Type ID (MSB) Type ID (LSB) 55 D5 21 43 65 87 A9 CB 00* 00* 00* 00* 00* 00* 43 21

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Note:

contains the address of the transmitting device.

The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: Specific address 1 bottom (Address 0x088 ) Specific address 1 top (Address 0x08C ) 0x87654321 0x0000CBA9

And for a successful match to the type ID, the following type ID match 1 register must be set up: Type ID Match 1 (Address 0x0A8 ) 0x80004321

Broadcast Address
Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the 'no broadcast' bit in the Network Configuration register is set to zero.

Hash Addressing
The Hash Address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in Hash register bottom and the most significant bits in Hash register top. The unicast hash enable and the multicast hash enable bits in the Network Configuration register enable the reception of hash matched frames. The destination address is reduced to a 6 bit index into the 64 bit hash register using the following hash function. The hash function is an XOR of every sixth bit of the destination address.
hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47] hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46] hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45] hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44] hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43] hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]

da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the Hash register then the frame is matched according to whether the frame is multicast or unicast. A multicast match is signaled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the Hash register. A unicast match is signaled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the Hash register. To receive all multicast frames, the Hash register should be set with all ones and the multicast hash enable bit should be set in the Network Configuration register.

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Copy All Frames (or Promiscuous Mode)

If the copy all frames bit is set in the Network Configuration register then all frames (except those that are too long, too short, have FCS errors, or have rx_er asserted during reception) are copied to memory. Frames with FCS errors are copied if bit [26] is set in the Network Configuration register.

Disable Copy of Pause Frames

Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit [23] in the Network Configuration register. When set, pause frames are not copied to memory regardless of the copy all frames bit, whether a hash match is found, a type ID match is identified, or if a destination address match is found.

VLAN Support
An Ethernet encoded 802.1Q VLAN tag is shown in Table 16-1 Table 16-1: VLAN Tag Control Information TCI (Tag Control Information) 16 Bits
First 3 bits priority, then CFI bit, last 12 bits VID

TPID (Tag Protocol Identifier) 16 Bits

0x8100

The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the Gigabit Ethernet controller can accept frame lengths up to 1,536 bytes by setting bit [8] in the Network Configuration register. If the VID (VLAN identifier) is null ( 0x000 ) a priority-tagged frame is indicated. The following bits in the receive buffer descriptor status word provide information about VLAN tagged frames: Bit [21] set if receive frame is VLAN tagged (i.e. type id of 0x8100 ). Bit [20] set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit [20] is set bit [21] is also set). Bits [19], [18] and [17] set to priority if bit [21] is set. Bit [16] set to CFI if bit [21] is set.

The controller can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the Network Configuration register.

16.2.4 Wake on LAN Support

The receive block supports Wake on LAN by detecting the following events on incoming receive frames: Magic packet ARP request to the device IP address Specific address 1 filter match

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Multicast hash filter match

If one of these events occurs, Wake on LAN detection is indicated by asserting the wakeup interrupt. These events can be individually enabled through bits[19:16] of the Wake on LAN register. Also, for Wake on LAN detection to occur receive enable must be set in the Network Control register, however a receive buffer does not have to be available. wakeup interrupt assertion due to ARP request, specific address 1, or multicast filter events occur even if the frame is in error. For magic packet events, the frame must be correctly formed and error free. A magic packet event is detected if all of the following are true: Magic packet events are enabled through bit [16] of the Wake on LAN register The frame's destination address matches specific address 1 The frame is correctly formed with no errors The frame contains at least 6 bytes of 0xFF for synchronization There are 16 repetitions of the contents of Specific Address 1 register immediately following the synchronization

An ARP request event is detected if all of the following are true: ARP request events are enabled through bit [17] of the Wake on LAN register Broadcasts are allowed by bit 5 in the Network Configuration register The frame has a broadcast destination address (bytes 1 to 6) The frame has a typeID field of 0x0806 (bytes 13 and 14) The frame has an ARP operation field of 0x0001 (bytes 21 and 22) The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake on LAN register

The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake on LAN target address value does not cause an ARP request event, even if matched by the frame. A specific address 1 filter match event occurs if all of the following are true: Specific address 1 events are enabled through bit [18] of the Wake on LAN register The frame's destination address matches the value programmed in the Specific Address 1 registers

A multicast filter match event occurs if all of the following are true: Multicast hash events are enabled through bit [19] of the Wake on LAN register Multicast hash filtering is enabled through bit [6] of the Network Configuration register The frame destination address matches against the multicast hash filter The frame destination address is not a broadcast

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16.2.5 DMA Block

The DMA controller is attached to the FIFO to provide a scatter-gather type capability for packet data storage in an embedded processing system.

Packet Buffer DMA

The controller uses a packet buffer which has the following features 32 data bus width support Easier to guarantee maximum line rate due to the ability to store multiple frames in the packet buffer More efficient use of the AHB interface Full store and forward Support for Transmit TCP/IP checksum offload Support for priority queuing When a collision on the line occurs during transmission, the packet is automatically replayed directly from the packet buffer memory rather than having to re-fetch through the AHB interface Received error packets are automatically dropped before any of the packet is presented to the AHB, thus reducing AHB activity Supports manual RX packet flush capabilities RX packet flush when there is lack of AHB resource

DMA Controller
The DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space. The DMA controller performs four types of operation on the AHB bus. In order of priority these are: Receive buffer manager write/read Transmit buffer manager write/read Receive data DMA write Transmit data DMA read

Transfer size is set to 32-bit words using the AHB bus width select bits in the Network Configuration register, and burst size may be programmed to single access or bursts of 4, 8, or 16 words using the DMA Configuration register.

Rx Buffers
Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors

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at an address location pointed to by the receive-buffer queue pointer. The base address for the receive-buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register. Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive status. If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written with zeroes except for the start of frame bit, which is always set for the first buffer in a frame. Bit zero of the address field is written to 1 to show that the buffer has been used. The receive-buffer manager then reads the location of the next receive AHB buffer and fills that with the next part of the received frame data. AHB buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. Refer to Table 16-2 for details of the receive buffer descriptor list. Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by up to three bytes depending on the value written to bits [14] and [15] of the Network Configuration register. If the start location of the AHB buffer is offset the available length of the first AHB buffer is reduced by the corresponding number of bytes. Table 16-2: Bit
31:2 1 0 Address of beginning of buffer. Wrap - marks last descriptor in receive buffer descriptor list. Ownership - needs to be zero for the controller to write data to the receive buffer. The controller sets this to 1 once it has successfully written a frame to memory. Software must clear this bit before the buffer can be used again.

Rx Buffer Descriptor Entry Function

Word 0

Word 1
31 30 29 28 27 26:25 Global all ones broadcast address detected. Multicast hash match. Unicast hash match. External address match. Reserved. Specific address register match. Encoded as follows: 00b : Specific address register 1 match 01b : Specific address register 2 match 10b : Specific address register 3 match 11b : Specific address register 4 match If more than one specific address is matched only one is indicated with priority 4 down to 1. This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit [24] clear in Network Configuration) Type ID register match found, bit [22] and bit [23] indicate which type ID register causes the match. With RX checksum offloading enabled: (bit [24] set in Network Configuration) 0b: The frame was not SNAP encoded and/or had a VLAN tag with the CFI bit set. 1b: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not set.

24

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Table 16-2: Bit

23:22

Rx Buffer Descriptor Entry (Contd) Function

This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit [24] clear in Network Configuration) Type ID register match. Encoded as follows: 00b : Type ID register 1 match 01b : Type ID register 2 match 10b : Type ID register 3 match 11b : Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1. With RX checksum offloading enabled: (bit [24] set in Network Configuration) 00b : Neither the IP header checksum nor the TCP/UDP checksum was checked. 01b : The IP header checksum was checked and was correct. Neither the TCP or UDP checksum was checked. 10b : Both the IP header and TCP checksum were checked and were correct. 11b : Both the IP header and UDP checksum were checked and were correct. VLAN tag detected type ID of 0x8100 . For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100 . Priority tag detected type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier. VLAN priority only valid if bit [21] is set. Canonical format indicator (CFI) bit only valid if bit 21 is set. End of frame when set the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame (bit 14). Start of frame when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the buffer contains a whole frame. This bit has a different meaning depending on whether ignore FCS mode are enabled. This bit is zero if ignore FCS mode is disabled. With ignore FCS mode enabled: (bit [26] set in Network Configuration Register). This indicates per frame FCS status as follows: 0b: Frame had good FCS. 1b: Frame had bad FCS, but was copied to memory as ignore FCS enabled. These bits represent the length of the received frame which might or might not include FCS depending on whether FCS discard mode is enabled. With FCS discard mode disabled: (bit [17] clear in Network Configuration Register) Least significant 12-bits for length of frame including FCS. With FCS discard mode enabled: (bit [17] set in Network Configuration Register) Least significant 12-bits for length of frame excluding FCS.

21 20

19:17 16 15 14 13

12:0

The start location of the receive-buffer descriptor list must be written with the receive-buffer queue base address before reception is enabled (receive enable in the Network Control register). Once reception is enabled, any writes to the Receive-buffer Queue Base Address register are ignored. When read, it returns the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled. If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered.

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An internal counter represents the receive-buffer queue pointer and it is not visible through the CPU interface. The receive-buffer queue pointer increments by two words after each buffer has been used. It re-initializes to the receive-buffer queue base address if any descriptor has its wrap bit set. As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to logic one indicating the AHB buffer has been used. Software should search through the used bits in the AHB buffer descriptors to find out how many frames have been received, checking the start of frame and end of frame bits. Received frames are written out to the AHB buffers as soon as enough frame data exists in the packet buffer. This might mean that several full AHB buffers are used before some error conditions can be detected. If a receive error is detected the receive buffer currently being written is recovered. Previous buffers are not recovered. For example, when receiving frames with CRC errors or excessive length, it is possible that a frame fragment might be stored in a sequence of AHB receive buffers. Software can detect this by looking for the start of frame bit set in a buffer following a buffer with no end of frame bit set. For a properly working 10/100/1000 Ethernet system there should be no excessive length frames or frames greater than 128 bytes with CRC errors. Collision fragments are less than 128 bytes long, therefore it is a rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the receive buffers size. Only good received frames are written out of the DMA, so no fragments exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame. If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive AHB buffer, then the buffer has been already used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the buffer not available bit in the Receive Status register is set and an interrupt is triggered. The receive resource error statistics register is also incremented. The user can optionally select whether received frames should be automatically discarded when no AHB buffer resource is available. This feature is selected via bit [24] of the DMA Configuration register (by default, the received frames are not automatically discarded). If this feature is off, then received packets remain stored in the packet buffer until an AHB buffer resource next becomes available. This can lead to an eventual packet buffer overflow if packets continue to be received when bit zero (used bit) of the receive-buffer descriptor remains set. Note that after a used bit has been read, the receive-buffer manager re-reads the location of the receive buffer descriptor every time a new packet is received. A receive overrun condition occurs when the receive packet buffer is full, or because hresp was not okay. In all other modes, a receive overrun condition occurs when either the AHB bus was not granted quickly enough, or because hresp was not okay, or because a new frame has been detected by the receive block, but the status update or write back for the previous frame has not yet finished. For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer.

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A write to bit [18] of the Network Control register forces a packet from the receive packet buffer to be flushed. This feature is only acted upon when the RX DMA is not currently writing packet data out to AHB i.e., it is in an IDLE state. If the RX DMA is active, a write to this bit is ignored.

Tx Buffers
Frames to transmit are stored in one or more transmit AHB buffers. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit-buffer queue pointer. The base address for this queue pointer is set in software using the Transmit-buffer Queue Base Address register. Each list entry consists of two words. The first is the byte address of the transmit buffer and the second containing the transmit control and status. For the packet buffer DMA, the start location for each AHB buffer is a byte address, the bottom bits of the address being used to offset the start of the data from the data-word boundary For the FIFO based DMA, the address of the buffer is also a byte address. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad will also be automatically generated to take frames to a minimum length of 64 bytes. When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor or through the control bus of the FIFO), the frame is assumed to be at least 64 bytes long and pad is not generated. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in the first word of each descriptor list entry. The second word of the transmit-buffer descriptor is initialized with control information that indicates the length of the frame, whether or not the MAC is to append CRC, and whether the buffer is the last buffer in the frame. After transmission the status bits are written back to the second word of the first buffer along with the used bit. Bit [31] is the used bit which must be zero when the control word is read if transmission is to take place. It is written to one when the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit [30] is the wrap-bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to increment. The Transmit-buffer Queue Base Address register can only be updated while transmission is disabled or halted; otherwise any attempted write is ignored. When transmission is halted the transmit-buffer queue pointer maintains its value. Therefore, when transmission is restarted the next descriptor read from the queue is from immediately after the last successfully transmitted frame. While transmit is disabled (bit [3] of the network control is set Low), the transmit-buffer queue pointer resets to point to the address indicated by the Transmit-buffer Queue Base Address register. Note that disabling receive does not have the same effect on the receive-buffer queue pointer. When the transmit queue is initialized, transmit is activated by writing to the transmit start bit (bit [9]) of the Network Control register. Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or by writing to the transmit halt bit of the Network Control register. Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register. Rewriting the start bit while transmission is active is allowed. This is implemented with a tx_go variable which is readable in the Transmit Status register at bit location 3.

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The tx_go variable is reset when: Transmit is disabled A buffer descriptor with its ownership bit set is read Bit [10], tx_halt, of the Network Control register is written There is a transmit error such as too many retries, late collision (gigabit mode only) or a transmit under-run

To set tx_go, write to bit [9], tx_start, of the Network Control register. Transmit halt does not take effect until any ongoing transmit finishes. The entire contents of the frame are read into the transmit packet buffer memory, so the retry attempt is replayed directly from the packet buffer memory rather than having to re-fetch through the AHB. If a used bit is read mid way through transmission of a multi buffer frame this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad. If transmission stops due to a transmit error or a used bit being read, transmission is restarted from the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten. Refer to Table 16-3 for details of the transmit buffer descriptor list. Table 16-3:
Bit

Tx Buffer Descriptor Entry

Function

Word 0
31:0 Byte address of buffer.

Word 1
31 Used must be zero for the controller to read data to the transmit buffer. The controller sets this to one for the first buffer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer can be used again. Wrap marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame. Retry limit exceeded, transmit error detected. Always set to 0 . Transmit frame corruption due to AHB error set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Late collision, transmit error detected. Late collisions only force this status bit to be set in gigabit mode. Reserved.

30 29 28 27

26 25:23

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Table 16-3:
Bit
22:20

Tx Buffer Descriptor Entry (Contd)

Function

Transmit IP/TCP/UDP checksum generation offload errors: 000b: No Error. 001b: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it. 010b: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it. 011b: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/IPv6. 100b: The Packet was not identified as VLAN, SNAP or IP. 101b: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was generated and inserted. 110b: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not generated. For IPv4 packets, the IP checksum was generated and inserted. 111b: A premature end of packet was detected and the TCP/UDP checksum could not be generated.

19:17 16

Reserved.
No CRC to be appended by MAC. When set this implies that the data in the buffers already contains a valid CRC and hence no CRC or padding is to be appended to the current frame by the MAC. This control bit must be set for the first buffer in a frame and is ignored for the subsequent buffers of a frame. Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution does not occur. Last buffer, when set this bit indicates that the last buffer in the current frame has been reached. Reserved. Length of buffer.

15 14 13:0

DMA Bursting on the AHB

The DMA always uses SINGLE, or INCR type AHB accesses for buffer management operations. When performing data transfers, the AHB burst length used can be programmed using bits [4:0] of the DMA Configuration register so that either SINGLE, INCR or fixed length incrementing bursts (INCR4, INCR8 or INCR16) are used where possible. When there is enough space and enough data to be transferred, the programmed fixed length bursts are used. If there is not enough data or space available, for example when at the beginning or the end of a buffer, SINGLE type accesses are used. SINGLE type accesses are also used at 1,024 byte boundaries, so that the 1 KB boundaries are not burst over per AHB requirements. The DMA does terminate a fixed length burst early, unless an error condition occurs on the AHB or if receive or transmit are disabled in the Network Control register.

DMA Packet Buffer

The DMA uses packet buffers for both transmit and receive paths. This mode allows multiple packets to be buffered in both transmit and receive directions. This allows the DMA to withstand far greater access latencies on the AHB and make more efficient use of the AHB bandwidth. Full packets are buffered which provides the opportunity to:

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Discard packets with error on the receive path before they are partially written out of the DMA thus saving AHB bus bandwidth and driver processing overhead Retry collided transmit frames from the buffer, thus saving AHB bus bandwidth, Implement transmit IP/TCP/UDP checksum generation offload.

With the packet buffers included, the structure of the controller data paths is as shown in Table 16-3.
X-Ref Target - Figure 16-3

Gigabit Ethernet Controller

TX Packet Buffer

MIO or EMIO
MAC Transmitter TX Packet Buffer DPSRAM TX DMA AHB DMA RX DMA RX Packet Buffer DPSRAM
TX GMII

Interconnect
APB

Register Interface

Status and Statistic Registers

Interconnect
AHB

MIO or EMIO
MDIO

Control Registers

RX Packet Buffer

MIO or EMIO
MAC Receive
RX GMII

Frame Filtering

UG585_c16_03_101812

Figure 16-3:

DMA Packet Buffer

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In the transmit direction, the DMA continues to fetch packet data up to a limit of 256 packets, or until the buffer is full. The size of the buffer has a maximum usable size of 4 KB. In the receive direction, if the buffer becomes full, then an overflow occur.s An overflow also occurs if the limit of 256 packets is breached. The size of the external buffer has a maximum usable size of 4 KB.

Tx Packet Buffer
The transmitter packet buffer continues to attempt to fetch frame data from the AHB system memory until the packet buffer itself is full, at which point it attempts to maintain its full level. To accommodate the status and statistics associated with each frame, three words per packet are reserved at the end of the packet data. If the packet was bad and requires to be dropped, the status and statistics are the only information held on that packet. Storing the status in the DPRAM is required to decouple the DMA interface of the buffer from the MAC interface, to update the MAC status/stats, and to generate interrupts in the order in which the packets that they represent were fetched from the AHB memory. If any errors occur on the AHB while reading the transmit frame, the fetching of packet data from AHB memory is halted. The MAC transmitter continues to fetch packet data, thereby emptying the packet buffer and allowing any good non-errored frames to be transmitted successfully. When these have been fully transmitted, the status/stats for the errored frame is updated and software is informed via an interrupt that an AHB error occurred. This way, the error is reported in the correct packet order. The transmit packet buffer only attempts to read more frame data from the AHB when space is available in the packet buffer memory. If space is not available it must wait until the packet fetched by the MAC completes transmission and is subsequently removed from the packet buffer memory. Note that if full store and forward mode is active, and if a single frame is fetched that is too large for the packet buffer memory, the frame is flushed and the DMA is halted with an error status. This is because a complete frame must be written into the packet buffer before transmission can begin, and therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame to be transmitted in the application. When the complete transmit frame is written into the packet buffer memory, a trigger is sent across to the MAC transmitter, which then begins reading the frame from the packet buffer memory. Because the whole frame is present and stable in the packet buffer memory, an underflow of the transmitter is not possible. The frame is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully transmitted or can no longer be re-transmitted (too many retries in half duplex mode). When this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully transmitted or can no longer be re-transmitted (too many retries in half duplex mode). When this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In full duplex mode, the frame is removed from the packet buffer on-the-fly.

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Other than underflow, the only MAC related errors that can occur are due to collisions during half duplex transmissions. When a collision occurs the frame still exists in the packet buffer memory so it can be retried directly from there. Only when the MAC transmitter has failed to transmit after sixteen attempts is the frame finally flushed from the packet buffer.

Rx Packet Buffer
The receive packet buffer stores frames from the MAC receiver along with their status and statistics. Frames with errors are flushed from the packet buffer memory, good frames are pushed onto the DMA AHB interface. The receiver packet buffer monitors the FIFO writes from the MAC receiver and translates the FIFO pushes into packet buffer writes. At the end of the received frame the status and statistics are buffered so that the information can be used when the frame is read out. When programmed in full store and forward mode, if the frame has an error the frame data is immediately flushed from the packet buffer memory allowing subsequent frames to utilize the freed up space. The status and statistics for bad frames are still used to update the controllers registers.

Note: To accommodate the status and statistics associated with each frame, three words per packet
are reserved at the end of the packet data. If the packet was bad and requires to be dropped, the status and statistics are the only information held on that packet. The receiver packet buffer also detects a full condition such that an overflow condition can be detected. If this occurs, subsequent packets are dropped and an RX overflow interrupt is raised. The DMA only begins packet fetches when the status and statistics for a frame are available. If the frame has a bad status due to a frame error, the status and statistics are passed onto the controllers registers. If the frame has a good status, the information is used to read the frame from the packet buffer memory and burst onto the AHB using the DMA buffer management protocol. After the last frame data has been transferred to the FIFO, the status and statistics are updated to the controllers registers.

16.2.6 Checksum Offloading

The controller can be programmed to perform IP, TCP, and UDP checksum offloading in both receive and transmit directions, enabled by setting bit [24] in the Network Configuration register for receive, and bit [11] in the DMA Configuration register for transmit. IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1's complement of the 1's complement sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1's complement of the 1's complement sum of all 16-bit words in the header, the data, and a conceptual IP pseudo header. To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements. For IP, TCP, or UDP checksum offload to be useful, the operating system containing the protocol stack must be aware that this offload is available so that it can make use of the fact that the hardware can either generate or verify the checksum.

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Rx Checksum Offload
When receive checksum offloading is enabled, the IPv4 header checksum is checked per RFC 791, where the packet meets the following criteria: If present, the VLAN header must be four octets long and the CFI bit must not be set Encapsulation must be RFC 894 Ethernet Type encoding or RFC 1042 SNAP encoding IPv4 packet IP header is of a valid length

The controller also checks the TCP checksum per RFC 793, or the UDP checksum per RFC 768, if the following criteria are met: IPv4 or IPv6 packet Good IP header checksum (if IPv4) No IP fragmentation TCP or UDP packet

When an IP, TCP, or UDP frame is received, the receive buffer descriptor provides an indication if the controller was able to verify the checksums. There is also an indication if the frame had LLC SNAP encapsulation. These indication bits replace the type ID match indication bits when receive checksum offload is enabled. If any of the checksums are verified to be incorrect by the controller, the packet is discarded and the appropriate statistics counter is incremented.

Tx Checksum Offload
The transmitter checksum offload is only available when the full store and forward mode is enabled. This is because the complete frame to be transmitted must be read into the packet buffer memory before the checksum can be calculated and written back into the headers at the beginning of the frame. Transmitter checksum offload is enabled by setting bit [11] in the DMA Configuration register. When enabled, it monitors the frame as it is written into the transmitter packet buffer memory to automatically detect the protocol of the frame. Protocol support is identical to the receiver checksum offload. For transmit checksum generation and substitution to occur, the protocol of the frame must be recognized and the frame must be provided without the FCS field, by ensuring that bit [16] of the transmit descriptor word 1 is clear. If the frame data already had the FCS field, this would be corrupted by the substitution of the new checksum fields. If these conditions are met, the transmit checksum offload engine calculates the IP, TCP, and UDP checksums as appropriate. When the full packet is completely written into packet buffer memory, the checksums are valid and the relevant DPRAM locations are updated for the new checksum fields as per standard IP/TCP and UDP packet structures.

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If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of the transmitter DMA writeback status are updated to identify the reason for the error. Note that the frame is still transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized.

16.2.7 IEEE 1588 Time Stamp Unit

IEEE 1588 is a standard for precision time synchronization in local area networks. It works with the exchange of special precision time protocol (PTP) frames. The PTP messages can be transported over IEEE 802.3/Ethernet, over Internet Protocol Version 4 or over Internet Protocol Version 6 as described in the annex of IEEE P1588.D2.1 . The controller detects when the PTP event messages sync, delay_req, pdelay_req and pdelay_resp are transmitted and received. Synchronization between master and slave clocks is a two stage process. First, the offset between the master and slave clocks is corrected by the master sending a sync frame to the slave with a follow up frame containing the exact time the sync frame was sent. Hardware assist modules at the master and slave side detect exactly when the sync frame was sent by the master and received by the slave. The slave then corrects its clock to match the master clock. Second, the transmission delay between the master and slave is corrected. The slave sends a delay request frame to the master which sends a delay response frame in reply. Hardware assist modules at the master and slave side detect exactly when the delay request frame was sent by the slave and received by the master. The slave then has enough information to adjust its clock to account for delay. For example, if the slave was assuming zero delay the actual delay is half the difference between the transmit and receive time of the delay request frame (assuming equal transmit and receive times) because the slave clock is lagging the master clock by the delay time already.

For hardware assist it is necessary to timestamp when sync and delay_req messages are sent and received. The timestamp is taken when the message timestamp point passes the clock timestamp point. The message timestamp point is the SFD and the clock timestamp point is the MII interface. (The 1588 spec refers to sync and delay_req messages as event messages as these require timestamping. Follow up, delay response and management messages do not require timestamping and are referred to as general messages.) 1588 version 2 defines two additional PTP event messages. These are the peer delay request (Pdelay_Req) and peer delay response (Pdelay_Resp) messages. These messages are used to calculate the delay on a link. Nodes at both ends of a link send both types of frames (regardless of whether they contain a master or slave clock). The Pdelay_Resp message contains the time at which a Pdelay_Req was received and is itself an event message. The time at which a Pdelay_Resp message is received is returned in a Pdelay_Resp_Follow_Up message. The controller recognizes four different encapsulations for PTP event messages: 1588 version 1 (UDP/IPv4 multicast) 1588 version 2 (UDP/IPv4 multicast) 1588 version 2 (UDP/IPv6 multicast)

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1588 version 2 (Ethernet multicast)

Note: Only multicast packets are supported.

The TSU consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. These are accessible through the APB interface. An interrupt is issued when a capture register is updated. The MAC provides timestamp registers that capture the departure time (for transmit) or arrival time (for receive) of PTP event packets (sync and delay request) and peer event packets (peer delay request or peer delay response). Interrupts are optionally generated upon timestamp capture. The MAC also provides an option to timestamp all received packets by replacing the packet's FCS word with the nanoseconds portion of the timestamp. This eliminates the need to respond to received timestamp interrupts and to associate the timestamps with the correct received packets. The timestamp unit includes a 62-bit timer counter. The lower 30 bits count nanoseconds and the upper 32 bits count seconds. Every clock cycle the counter is incremented by a programmable number of nanoseconds, and a mechanism is provided to handle fractional values. For example, at 120 MHz, the clock period is 8.333 ns. Every 3 clock cycles the counter is incremented twice by 8 and once by 9, for an average increment of 8.333 ns. The counter is clocked by the CPU 1x which is derived from the CPU clock. There are six additional registers that capture the time at which PTP event frames are transmitted and received. An interrupt is issued when these registers are updated.

IEEE 1588 Limitations

These topics can be addressed by software, but the added software workload limits the capabilities and accuracy of the IEEE1588 support. In many non-real-time operating systems, the interrupt response time is long, making it more difficult to achieve high accuracy.

Time Counter Clock Input

The 62-bit time counter is clocked by the CPU_1x clock and there is no option for a separate clock input. Thus the choice of clock frequency and precision is related to the CPU clock frequency.

62-bit Time Counter Accuracy

The counter accuracy is limited to 62 bits. The least significant bits are in nanosecond units, and there is no direct support for counting fractions of nanoseconds. A mechanism is provided to allow fractional increments by averaging between two integer values, but its accuracy is limited and it creates jitter of up to 128 ns.

Counter Value to the PL

The 62-bit counter value is only accessible by reading a register. It is therefore not directly possible to schedule hardware events upon the counter reaching a specific value.

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One Pulse per Second Output

Because there is no hardware access to the counter value, it is not possible to provide a 1 pps signal that is commonly used for lab tests of the synchronization accuracy.

Event Scheduling
The MAC does not provide event scheduling capability such as generating an interrupt upon the counter reaching a specific value.

Synchronizing the Two Ethernet Controllers

The two Ethernet cores are completely independent, and there is no hardware mechanism provided for synchronizing the counter values of the two Ethernet cores, or for making the counter of one Ethernet core slave to the other.

Single Packet Queue No Tagging

All received packets are written into the same queue (or packet buffer) in memory. Similarly, all transmitted packets are read from the same queue. There is no support for multiple queues. A single queue makes it more difficult for the software to associate (tag) a packet with a timestamp.

FIFO Depth
The timestamp registers are 1-deep, so new events overwrite old values. This requires the software to have a fast enough response time to avoid event overrun.

Designing the Timestamp Unit in the PL

Improvement in performance and accuracy of time stamping can be achieved by implementing the timestamp unit in the PL instead of using the built-in timestamp unit in the MAC. Using this approach, the time counter and the timestamp registers are implemented in the PL, and the PTP frame recognition remains in the Ethernet core. The outputs from the controller can be used to implement the timestamp unit in the PL. The EMIO signals for this are listed in Table 10, Ethernet GMII Interface Signals via EMIO Interface . The following items are not supported: Support of unicast PTP packets Support of transparent clocks Single packet queue no tagging

Designing a PTP Packet Tagging and Capture Module

Designing a separate timestamp unit as described above addresses most of the items, but it does not address the hardware mechanism for tagging the PTP packets, i.e., associating the packets with their corresponding timestamp. For example, if along with the timestamp some identifying packet attribute were captured, it would allow software to easily associate the timestamp with the correct PTP event. Examples of useful packet attributes are packet identification or serial number, or the

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memory address it was read from or written to. It is also possible to capture the entire packet along with its timestamp (for both transmit and receive), and make it available to software, for example via FIFOs or via circular buffers in main memory. Such a function can be implemented in the PL along with the timestamp unit as described above. However, implementation requires access to the packet data stream itself. In order to have access to the packet data stream, the controller needs to be pinned-out through the EMIO using GMII, instead of MIO. By selecting this option, the GMII signals are exposed to the PL and can be used to detect and capture the PTP packets. Note that it is still possible to use the PTP frame recognition in the MAC, or it is possible to design this function in the PL as well (e.g., if support for unicast packets is required).

16.2.8 MAC 802.3 Pause Frame Support

Note: See Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of
pause operation. The start of an 802.3 pause frame is shown in Table 16-4 Table 16-4: Pause Frame Information Source Address
6 bytes

Destination Address
0x0180C2000001

Type
(MAC Control Frame)

Pause Opcode
0x0001

Pause Time
2 bytes

0x8808

The controller supports both hardware controlled pause of the transmitter upon reception of a pause frame and hardware generated pause frame transmission.

802.3 Pause Frame Reception

Bit [13] of the Network Configuration register is the pause enable control for reception. If this bit is set transmission pauses if a non zero pause quantum frame is received. If a valid pause frame is received then the pause time register is updated with the new frame's pause time regardless of whether a previous pause frame is active or not. An interrupt (either bit [12] or bit [13] of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit [12] and bit [13] of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit [12] of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit [13] of the Interrupt Status register. When the pause time register is loaded and the frame currently being transmitted has been sent, no new frames are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the controller is configured for full duplex operation. If the controller is configured for half duplex there is no transmission pause, but the pause frame received interrupt is still triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address register 1 or if it matches the reserved address of 0x0180C2000001 . It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0001 .

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Pause frames that have FCS or other errors are treated as invalid and are discarded. 802.3 Pause frames that are received after priority based flow control (PFC) has been negotiated are also discarded. Valid pause frames received increment the Pause Frames Received Statistic register. The Pause Time register decrements every 512 bit times once transmission has stopped. For test purposes, the retry test bit can be set (bit [12] in the Network Configuration register) which causes the Pause Time register to decrement every tx_clk cycle when transmission has stopped. The interrupt (bit [13] in the Interrupt Status register) is asserted whenever the pause time register decrements to zero (assuming it has been enabled by bit [13] in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received.

802.3 Pause Frame Transmission

Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control register and from the external input pins tx_pause, tx_pause_zero and tx_pfc_sel. If either bit [11] or bit [12] of the Network Control register is written with logic 1 , or if the input signal tx_pause is toggled when tx_pfc_sel is Low, an 802.3 pause frame is transmitted providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. Pause frame transmission occurs immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise of the following: A destination address of 01-80-C2-00-00-01 A source address taken from Specific Address register 1 A type ID of 88-08 (MAC control frame) A pause opcode of 00-01 A pause quantum register Fill of 00 to take the frame to minimum frame length Valid FCS

The pause quantum used in the generated frame depends on the trigger source for the frame as follows: If bit [11] is written with a one, the pause quantum is taken from the Transmit Pause Quantum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as the default. If bit [12] is written with a one, the pause quantum is zero. If the tx_pause input is toggled, tx_pfc_sel is Low and the tx_pause_zero input is held Low until the next toggle, the pause quantum is taken from the Transmit Pause Quantum register. If the tx_pause input is toggled, tx_pfc_sel is Low and the tx_pause_zero input is held High until the next toggle, the pause quantum is zero.

After transmission, a pause frame transmitted interrupt is generated (bit [14] of the Interrupt Status register) and the only statistics register that is incremented is the Pause Frames Transmitted register.

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Pause frames can also be transmitted by the MAC using normal frame transmission methods.

MAC PFC Priority Based Pause Frame Support

Note: Refer to the 802.1Qbb standard for a full description of priority based pause operation.
The controller supports PFC priority based pause transmission and reception. Before PFC pause frames can be received, bit 16 of the Network Control register must be set. The start of a PFC pause frame is shown in Table 16-5. Table 16-5: PFC Priority Based Pause Frame Info Source Address
6 bytes

Destination Address 0x0180C2000001

Type
(MAC Control Frame)

Pause Opcode 0x0101

Priority Enable Vector

2 bytes

Pause Times
8 * 2 bytes

0x8808

PFC Pause Frame Reception

The ability to receive and decode priority based pause frames is enabled by setting bit [16] of the Network Control register. When this bit is set, the controller matches either classic 802.3 pause frames or PFC priority based pause frames. Once a priority based pause frame has been received and matched, then from that moment on the controller only matches on priority based pause frames (this is an 802.1Qbb requirement, known as PFC negotiation). Once priority based pause has been negotiated, any received 802.3x format pause frames are not acted upon. The state of PFC negotiation is identified via the output pfc_negotiate. If a valid priority based pause frame is received then the controller decodes the frame and determines which, if any, of the eight priorities require to be paused. Up to eight Pause Time registers are then updated with the eight pause times extracted from the frame, regardless of whether a previous pause operation is active or not. An interrupt (either bit [12] or bit [13] of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (via bit[12] and bit[13] of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit[12] of the Interrupt Status register. Pause frames received with zero quanta are indicated on bit[13] of the Interrupt Status register. The state of the eight pause time counters are indicated through the outputs rx_pfc_paused. These outputs remain High for the duration of the pause time quanta. The loading of a new pause time only occurs when the controller is configured for full duplex operation. If the controller is configured for half duplex, the pause time counters are not loaded, but the pause frame received interrupt is still triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address register 1 or if it matches the reserved address of 0x0180C2000001 . It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0101 . Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the pAuse Frames Received Statistic register. The Pause Time registers decrement every 512 bit times immediately following the PFC frame reception. For test purposes, the retry test bit can be set (bit [12] in the Network Configuration

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register) which causes the Pause Time register to decrement every rx_clk cycle once transmission has stopped. The interrupt (bit [13] in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit [13] in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received.

PFC Pause Frame Transmission

Automatic transmission of pause frames is supported through the transmit priority based pause frame bit of the Network Control register and from the external input pins tx_pause, tx_pfc_pause[7:0], tx_pfc_pause_zero[7:0], and tx_pfc_sel. If bit 17 of the Network Control register is written with logic 1 , or if the input signal tx_pause is toggled when tx_pfc_sel is High, a PFC pause frame is transmitted providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. When bit 17 of the Network Control register is set, the fields of the priority based pause frame are built using the values stored in the Transmit PFC Pause register. Pause frame transmission occurs immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise of the following: A destination address of 01-80-C2-00-00-01 A source address taken from Specific Address register 1 A type ID of 88-08 (MAC control frame) A pause opcode of 01-01 A priority enable vector taken from tx_pfc_pause or the Transmit PFC Pause register Eight pause quantum registers Fill of 00 to take the frame to minimum frame length Valid FCS

The Pause Quantum registers used in the generated frame depend on the trigger source for the frame as follows: If bit [17] of the Network Control register is written with a one then the priority enable vector of the priority based pause frame is set equal to the value stored in the Transmit PFC Pause register [7:0]. For each entry equal to zero in the Transmit PFC Pause register[15:8], the pause quantum field of the pause frame associated with that entry is taken from the Transmit Pause Quantum register. For each entry equal to one in the Transmit PFC Pause register[15:8], the pause quantum associated with that entry is zero. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default. If the tx_pause input is toggled and tx_pfc_sel is High then the priority enable vector of the priority based pause frame is set equal to the value in tx_pfc_pause [7:0]. For each entry equal to zero in tx_pfc_pause_zero[7:0], the pause quantum field of the pause frame associated with that entry is taken from the Transmit Pause Quantum register. For each entry equal to one in tx_pfc_pause_zero [7:0], the pause quantum associated with that entry is zero.

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After transmission, a pause frame transmitted interrupt is generated (bit 14 of the Interrupt Status register) and the only statistics register that is incremented is the Pause Frames Transmitted register. PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods.

16.3 Programming Guide

The controller functionality is described in detail in section 16.2 Functional Description and Programming Model. All of the controller registers are listed in Table 16-9 and Table 16-10 and are described in detail in Appendix B, Register Details.

Example: Programming Steps

1. 2. 3. 4. 5. 6. 7. 8. 9. 16.3.1 Initialize the Controller 16.3.2 Configure the Controller 16.3.3 I/O Configuration 16.3.4 Configure the PHY 16.3.5 Configure the Buffer Descriptors 16.3.6 Configure Interrupts 16.3.7 Enable the Controller 16.3.8 Transmitting Frames 16.3.9 Receiving Frames

10. 16.3.10 Debug Guide

16.3.1 Initialize the Controller

1. 2. 3. 4. 5. Clear the Network Control register. Write 0x0 to gem.net_ctrl register. Clear the Statistics registers . Write a 1 to gem.net_ctrl[clear_stat_regs]. Clear the Status registers . Write a 1 to the Status registers. gem.rx_status = 0x0F and gem.tx_status = 0xFF. Disable all interrupts . Write 0x7FF_FEFF to the gem.intr_dis register. Clear the buffer queues . Write 0x0 to the gem.rx_qbar and gem.tx_qbar registers.

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16.3.2 Configure the Controller

The following example describes a typical programming sequence for configuration of the controller. Refer to Appendix B, Register Details for further details on the Controller registers. 1. Program the Network Configuration register (gem.net_cfg) . The network configuration register is used to set the mode of operation. Examples: a. c. Enable Full Duplex . Write a 1 to the gem.net_cfg[full_duplex] register. Enable default speed for 100 Mbps . Write a 1 to the gem.net_cfg[speed] register.

b. Enable Gigabit mode . Write a 1 to the gem.net_cfg[gige_en] register.

Note: The speed bit might have to be re-written after PHY auto-negotiation.
d. Enable reception of broadcast or multicast frames . Write a 0 to the gem.net_cfg[no_broadcast] register to enable broadcast frames and write a 1 to the gem.net_cfg[multi_hash_en] register to enable multicast frames. e. f. Enable promiscuous mode . Write a 1 to the gem.net_cfg[copy_all] register. Enable TCP/IP checksum offload feature on receive . Write a 1 to the gem.net_cfg[rx_chksum_offld_en] register. (Refer to section 16.2.6 Checksum Offloading.)

g. Enable Pause frames. Write a 1 to gem.net_cfg[pause_en] register. h. Set the MDC clock divisor. Write the appropriate MDC clock divisor to the gem.net_cfg[mdc_clk_div] register. (Refer to section 16.3.4 Configure the PHY.) 2. Set the MAC address . Write to the gem.spec1_addr1_bot and gem.spec1_addr1_top registers. The least significant 32 bits of the MAC address go to gem.spec1_addr1_bot and the most significant 16 bits go to gem.spec1_addr1_top. Program the DMA Configuration register (gem.dma_cfg). a. Set the receive buffer size to 1,600 bytes . Write a value of 0x19 to the gem.dma_cfg[ahb_mem_rx_buf_size] register.

3.

b. Set the receiver packet buffer memory size to the full configured addressable space of 8 KB . Write 0x3 to the gem.dma_cfg[rx_pktbuf_memsz_sel] register. c. Set the transmitter packet buffer memory size to the full configured addressable space of 4 KB . Write 0x1 to the gem.dma_cfg[tx_pktbuf_memsz_sel] register.

d. Enable TCP/IP checksum generation offload on the transmitter. Write 0x1 to the gem.dma_cfg[csum_gen_offload_en] register. e. f. 4. Configure for Little Endian system . Write 0x0 to the gem.dma_cfg[ahb_endian_swp_pkt_en] register. Configure AHB fixed burst length . Write 0x10 to the gem.dma_cfg[ahb_fixed_burst_len] register to use INCR16 AHB burst for higher performance. Enable MDIO. Write a 1 to the gem.net_ctrl[mgmt_port_en] register. Enable the Receiver. Write a 1 to the gem.net_ctrl[rx_en] register.

Program the Network Control Register (gem.net_ctrl) . a. c. b. Enable the Transmitter. Write a 1 to the gem.net_ctrl[tx_en] register.

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16.3.3 I/O Configuration

The block diagram in section 16.1.1 Block Diagram describes the connection details of the Gigabit Ethernet Controller to the external network.

Gigabit Ethernet Controller using MIO

The controller provides an RGMII interface through the MIO. Pins 16-27 are used for Controller 0 and 28-39 for Controller 1. Refer to section 16.6 Signals and I/O Connections for more information on the pin-out.

Example: Configuring Controllers for MIO

The controllers can be configured to operate in HSTL or CMOS IO standards. Refer to Chapter 2, Signals, Interfaces, and Pins for more information on MIO pin configuration. The following steps illustrate the configuration for Controller 0. 1. Write to the slcr.MIO_PIN{16:21} registers for the transmit signals . This programs the MIO I/O buffers (GPIOB) for the four transmit data signals, transmit clock and transmit control signals. Example : A value of 0x0000_3902 disables the HSTL receiver, specifies HSTL I/O type, enables internal pull-up, disables 3-state control and routes the transmit data, clock, and control signals. 2. Write to the slcr.MIO_PIN{22:27} registers for the receive signals . Example : A value of 0x0000_1903 enables HSTL receiver, specifies HSTL I/O type, enables internal pull-up, disables 3-state control and routes the receive data, clock, and control signals. 3. Write to slcr.MIO_PIN{52:53} registers for the management signals . Example : A value of 0x0000_1280 enables the HSTL receiver, specifies HSTL I/O type, enables internal pull-up, and routes the MDIO clock/data. 4. Write a value of 0x0000_0001 to the slcr.GPIOB register to enable the VREF internal generator.

Similarly, replace SLCR.MIO_PIN{16:27} with SLCR.MIO_PIN{28:39} for Controller 1.

Note: The clock might have to be reprogrammed after auto-negotiation.

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Gigabit Ethernet Controller using EMIO

The EMIO interface allows for derivation of other physical MII interfaces using appropriate shim-logic in the PL. The Controller provides a GMII interface through the EMIO.

Example: Configure Controllers for EMIO

1. 2. 3. 4. 5. 6. 7. Unlock the SLCR module . Write a value of 0xDF0D to the slcr.SLCR_UNLOCK register. Enable the level shifters for PS user inputs to FPGA in FPGA tile 1. Write a value of 0b11 to bit slcr.LVL_SHFTR_EN[USER_INP_ICT_EN_1]. Enable the level shifter for PS user inputs to FPGA in FPGA tile 0 . Write 0b11 to bit slcr.LVL_SHFTR_EN[USER_INP_ICT_EN_0]. Write a value of 0 to the slcr.FPGA_RST_CTRL register. Perform a software reset . Write 0b1 to bits slcr.FPGA_RST_CTRL[FPGA{0-3}_OUT_RST]. Write a value of 0 to the slcr.FPGA_RST_CTRL register. Lock the SLCR module . Write a value of 0x767B to the slcr.SLCR_LOCK register.

Configure Clocks
The Gigabit Ethernet Controller clocks are controlled through four registers in the SLCR module.

Example: Configuring Clocks for MIO

1. 2. Unlock the SLCR module . Write a value of 0xDF0D to slcr.SLCR_UNLOCK register. Configure the clock by writing to the slcr.GEM0_CLK_CTRL register. Example : A value of 0x0050_0801 enables the Controller0 reference clock, first divisor for the source clock is 8 and second divisor is 5. This gives a default speed of 100 Mb/s if the Ethernet source clock is IO PLL which has a frequency of 1,000 MHz. 3. 4. Enable Controller 0 receive clock control . Write a value of 0x0000_0001 to the slcr.GEM0_RCLK_CTRL register. Lock the SLCR module . Write a value of 0x767B to slcr.SLCR_LOCK register.

Similar steps must be followed for Controller 1 by writing to the appropriate registers.

16.3.4 Configure the PHY

The PHY connected to the controller is initialized through the available management interface (MDIO) using the PHY maintenance register (gem.phy_maint). Writing to this register starts a shift operation which is signaled as complete when the bit gem.net_status[phy_mgmt_idle] is set. The MDIO interface clock (MDC) for GigE is generated by dividing down the CPU_1x clock.

Note: MDC is active only during MDIO read or write operations during which the PHY registers are
read or written.

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The MDC must not exceed 2.5 MHz as defined by the IEEE802.3 standard. The gem.net_cfg[mdc_clk_div] bits are used to set the divisor for the CPU_1x clock. Example : Consider a case with the CPU clock set to 666.667 MHz clock and the available CPU_1x clock is 111.11 MHz. The clock divisor, in this case should be set to 48 ( 0b011 ) in gem.net_cfg[mdc_clk_div] to set the maximum possible frequency of 2.314 MHz for the MDC. PHY configuration and initialization is unique for every system. Refer to the vendor data sheet for more information and PHY register details.

Example: PHY Read/Write Operation

1. 2. Check to see that no MDIO operation is in progress . Read until gem.net_status[phy_mgmt_idle] = 1 . Write data to the PHY maintenance register(gem.phy_maint) . This initiates the shift operation over MDIO. Refer to Appendix B, Register Details section B.18 Gigabit Ethernet Controller (GEM)for register information. Wait for completion of operation . Read until gem.net_statusp[phy_mgmt_idle] = 1 . Read data bits for a read operation . The PHY register data is available in gem.phy_maint[data].

3. 4.

Example: PHY Initialization

1. 2. 3. Detect the PHY address . Read the PHY identifier fields in PHY registers 2 and 3 for all the PHY addresses ranging from 1 to 32. The register contents will be valid for a valid PHY address. Advertise the relevant speed/duplex settings . These bits can be set to suit the system. Refer to the PHY vendor data sheet for more information. Configure the PHY as applicable . This could include options to set PHY mode, timing options in the PHY or others as applicable to the system. Refer to the PHY vendor datasheet for more information. Wait for completion of Auto-negotiation . Read the PHY status register. Refer to the PHY vendor data sheet for more information. Update Controller with auto-negotiated speed and duplex settings . Read the relevant PHY registers to determine the negotiated speed and duplex. Set the speed in gem.net_cfg[gige_en] and gem.net_cfg[speed] bits and the duplex in gem.net_cfg[full_duplex].

4. 5.

Note: The SLCR register must be updated for clock updates (refer to Configure Clocks, page 461).

16.3.5 Configure the Buffer Descriptors

Receive Buffer Descriptor List
The data received by the controller is written to pre-allocated buffer descriptors in system memory. These buffer descriptor entries are listed in the receive buffer queue. Refer to section 16.2.5 DMA Block and Table 16-2, page 441 for more information on implementation and structure of the Rx Buffer Descriptor. The Receive-buffer Queue Pointer register (gem.rx_qbar) points to this data structure as shown in Figure 16-4.

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X-Ref Target - Figure 16-4

Rx Descripter List Rx Buffer Queue Pointer

MAC Register

Rx Buffers

List in Main Memory

Buffer in Main Memory

UG585_c16_04_022712

Figure 16-4: To create this list of buffers: 1.

Rx Buffer Queue Structure

Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA Configuration register. Example : This controller assumes that the maximum size of an Ethernet packet without jumbo frame support can reach up to 1,536 bytes. So allocate N number of buffers each with a size of 1,536 bytes in system memory. The buffers typically need to be aligned to cache-line boundaries to improve performance. Typical values of N can be 64 or 128.

2.

Each buffer descriptor is of 8 bytes length. Hence allocate an area of 8N bytes for the receive buffer descriptor list in system memory. This creates N entries in this list.

Note: A single cache line for the Zynq-7000 AP SoC is 32 bytes and can contain 4 buffer

descriptors. This means flushing or invalidating a single buffer descriptor entry in the cache memory results in flushing or invalidation of a cache line which in turn affects the adjacent buffer descriptors. This can result in undesirable behavior. It is typical to allocate the buffer descriptor list in an un-cached memory region.

3. 4. 5. 6. 7.

Mark all entries in this list as owned by controller. Set bit 0 of word 0 of each buffer descriptor to 0. Mark the last descriptor in the buffer descriptor list with the wrap bit (bit 1 in word 0) set. Write the base address of receive buffer descriptor list to controller register gem.rx_qbar. Fill the addresses of the allocated buffers in the buffer descriptors (bits 31-2, Word 0). Write the base address of this buffer descriptor list to the gem.rx_qbar register.

Transmit Buffer Descriptor List

The data to be transmitted is read from buffers present in system memory. These buffers are listed in the transmit buffer queue. Refer to section 16.2.5 DMA Block and Table 16-2, page 441 for more information on implementation and structure of the Tx buffer descriptor.

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The Transmit Buffer Queue Pointer register (gem.tx_qbar) register points to this data structure. To create this list of buffer descriptors with N entries: 1. Each buffer descriptor is 8 bytes in length. Hence allocate an area of 8N bytes for the transmit buffer descriptor list in system memory which creates N entries in this list. It is advisable to use un-cached memory for allocating the complete buffer descriptor list for the reasons already described for the Receive Buffer Descriptor List. Mark all entries in this list as owned by the controller. Set bit[31] of word 1 to 0 . Mark the last descriptor in the list with the wrap bit. Set bit[30] in word 1 to 1 . Write the base address of transmit buffer descriptor list to Controller register gem.tx_qbar.

2. 3. 4.

16.3.6 Configure Interrupts

There are 26 interrupt conditions that are detected within the controller which are OR-ed to generate a single interrupt. Additionally there is a Wake-on-LAN interrupt driven from the Ethernet controller. These two interrupts are then passed to the GIC pl390 interrupt controller. Refer to the description of register, gem.intr_status in Appendix B, Register Details for more information on the list of interrupt conditions identified by the controller. An appropriate handler for the interrupt should be registered with the CPU for processing an interrupt condition. The CPU suspends its normal activity, moves to interrupt processing mode and executes the corresponding handler for an interrupt condition.

Example: Configuring Interrupts

1. Register a handler. There are two interrupts generated by the controller - Wake-on-LAN and another interrupt for all other functions. Register the handler for each of these interrupt types with the CPU.

Note: In a typical case, a single handler is used for both transmission and reception of packets. Once the control reaches the handler, the software should read the gem.intr_status register to determine the source and perform the relevant function.
2. Enable the necessary interrupt conditions . The relevant bits in the gem.intr_en register must be set. The interrupt conditions necessary are determined by the system architecture.

Note: Read the read-only register gem.intr_mask for current the mask state of each interrupt.

16.3.7 Enable the Controller

The receiver and transmitter must be enabled after configuration: 1. 2. Enable the Transmitter. Write a 1 to gem.net_ctrl[tx_en]. Enable the Receiver. Write a 1 to gem.net_ctrl[rx_en].

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16.3.8 Transmitting Frames

Example: Transmitting a Frame
1. Allocate buffers in system memory to contain the Ethernet frame . GigE supports scatter-gather functionality; hence an Ethernet frame can be split into multiple buffers with each buffer processed by a buffer descriptor. Write the Ethernet frame data in the allocated buffers . These Ethernet frames should have their header fields such as destination MAC address, source MAC address and type/length field set appropriately.

2.

Notes:

The FCS field is added by the MAC in most cases. However if there is a need to append a custom FCS, bit 16 in word 1 of the corresponding buffer descriptor must be set. The buffer that contains the Ethernet frame data should be flushed from cache if cached memory is being used.

3.

Allocate buffer descriptor(s) for the Ethernet frame buffers . This involves setting bits 0-31 in the buffer descriptor word 0 with the address of the buffer and setting bits 0-13 in word 1 with the length of the buffer to be transmitted.

Notes:

For single buffer Ethernet frames, bit 15 (Last buffer bit) of the word 1 must also be set. For Ethernet frames scattered across multiple buffers the buffer descriptors must be allocated serially and the buffer descriptor containing the last buffer should have the bit 15 of word 1 set.

Example : For an Ethernet frame of 1,000 bytes split across two buffers with the first buffer containing the Ethernet header (14 bytes) and the next buffer containing the remaining 986 bytes, the buffer descriptor with index N should be allocated for the first buffer and the buffer descriptor with index N+1 should be allocated for the second buffer. Bit 15 of word 1 of the N+1 buffer descriptor must also be set to mark it as the last buffer in the scattered list of Ethernet frames. 4. 5. 6. Clear the used bit (bit 31) in the word 1 of the allocated buffer descriptors . Enable transmission . Write a 1 to gem.net_ctrl[start_tx]. Wait until the transmission is complete . An interrupt is generated by the controller upon successful completion of the transmission. Read and clear the gem.intr_status[tx_complete] bit by writing a 1 to the bit In the interrupt handler. Also read and clear the gem.tx_status register by writing a 1 to gem.tx_status[tx_complete] bit. Clear all bits in the BD except the used and wrap bits.

16.3.9 Receiving Frames

When a frame is received with the receive circuits enabled, the controller checks the address and the frame is written to system memory in the following cases: The destination address matches one of the four specific address registers. This is applicable for cases where the MAC address for the controller is set in thr gem.spec_addr{1:4}_bot and gem.spec_addr{1:4}_top registers.

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The received frame's type/length field matches one of the four type ID registers. The available type id registers are gem.type_id_match{1:4}. This is applicable for cases where Ethernet type/length field based filtering is required. Unicast or Multicast hash is enabled through gem.net_cfg[uni_hash_en] or gem.net_cfg[multi_hash_en] register bits, then the received frame is accepted only if the hash is matched. The destination address is a broadcast address ( 0xFFFFFFFFFFFF ) and broadcasts are allowed. This option is set using the gem.net_cfg[no_broadcast] register bit. The controller is configured for promiscuous mode with the gem.net_cfg[copy_all] register bit set. A match is found in the external address filtering interface.

The register gem.rx_qbar points to the next entry in the receive buffer descriptor list and the controller uses this as the address in system memory to write the frame. When the frame has been completely received and written to system memory, the controller then updates the receive buffer descriptor entry with the reason for the address match, marks the area as being owned by software, and sets the receive complete interrupt (gem.intr_status[rx_complete] = 1 ). Software is then responsible for copying the data to the application area and releasing the buffer. If the controller is unable to write the data at a rate to match the incoming frame, then the receiver overrun interrupt is set (gem.intr_status[rx_overrun] = 1 ). If there is no receive buffer available, i.e., the next buffer is still owned by software, a receive-buffer not available interrupt is set. If the frame is not successfully received, a Statistic register is incremented and the frame is discarded without informing software.

Example: Handling a Received Frame

1. 2. Wait for the controller to receive a frame . The receive complete interrupt, gem.intr_status[rx_complete], is generated when a frame is received. Service the interrupt . Read and clear the gem.intr_status[rx_complete] register bit writing a 1 to the bit in the interrupt handler. Also read and clear the gem.rx_status register by writing a 1 to gem.rx_status[frame_recd] bit. Process the data in the buffer. Scan the buffer descriptor list for the buffer descriptors with the ownership bit (bit 0, Word 0) set. When the DMA receive buffer size programmed to 1,600 bytes (gem.dma_cfg[ahb_mem_rx_buf_size] = 0x19 ), the packets on the receive side are not scattered and always go into a single buffer. For a buffer descriptor with the ownership bit set, process the buffer allocated in the corresponding buffer descriptor and set the ownership bit to 0 . Read other bit fields in the relevant buffer descriptor word 1, take necessary action, and clear them.

3.

16.3.10 Debug Guide

The GigE can encounter different kinds of errors while receiving or transmitting Ethernet frames. Refer to Appendix B, Register Details for more information on the transmit and receive error conditions listed in the description for gem.tx_status and gem.rx_status registers, respectively. Some common errors and the action necessary is described in Table 16-6 and Table 16-7.

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Table 16-6:

RX Status Errors Necessary Action

This is a condition from which the controller cannot recover easily. Re-initialize the controller and buffer descriptors for receive and transmit paths after clearing the relevant register status bits: gem.rx_status[hresp_not_ok] and gem.intr_status[hresp_not_ok]. This condition implies that the packet is dropped because the packet buffer is full and occurs occasionally when the controller is unable to process the packets when they arrive very fast. In most conditions, no action for error recovery needs to be taken. Ensure that the packet buffer is configured for 8 KB (see section 16.3.2 Configure the Controller) and clear bits gem.rx_status[rx_overrun] and gem.intr_status[rx_overrun]. This condition implies that the controller could not get a buffer descriptor with the ownership bit set to 0. It can also mean that the software is unable to keep pace with the incoming packet rate. Clear bits gem.rx_status[buffer_not_avail] and gem.intr_status[rx_used_read] in the interrupt handler. Attempt increasing the number of buffer descriptors on the receive path to allocate more number of buffers. The software processing can be optimized further to accelerate processing of received frames.

Error Condition
Hresp not OK

Receive overrun

Buffer not available

Table 16-7:

TX Status Errors Necessary Action

This is a condition from which the controller cannot recover easily. Re-initialize the controller and buffer descriptors for receive and transmit paths after clearing the relevant register status bits: gem.tx_status[hresp_not_ok] and gem.intr_status[hresp_not_ok]. This implies a severe error condition on the transmit side in processing of the transmit buffers and buffer descriptors. For effective error recovery, the software must disable the transmitter by writing a 0 to the gem.net_ctrl[tx_en] bit, then re-initialize the buffer descriptors on the transmit side and enable the transmitter by writing a 1 to the gem.net_ctrl[tx_en] bit. The bit gem.tx_status[tx_under_run] must be cleared in the interrupt handler. This is a severe error condition on the transmit side. For effective error recovery, the software must disable the transmitter by writing a a 0 to the gem.net_ctrl[tx_en] bit, then re-initialize the transmit buffer descriptors and transmitter. The register bits gem.tx_status[tx_corr_ahb_err] and gem.intr_status[tx_corrupt_ahb_error] must be cleared in the interrupt handler. This implies there are a series of collisions for which an Ethernet frame could not be sent out even with a number of retries in half-duplex communication. This Ethernet frames are dropped at the transmitter. The bits gem.tx_status[retry_limit_exceeded] and gem.intr_status[retry_ex_late_collision]must be cleared in the interrupt handler. No drastic measures need to be taken for this error. However it could also mean that there is a duplex setting mismatch. This error indicates that there are collisions for half duplex communication. Some collisions are expected in half duplex mode and can be ignored. When a collision occurs, the frame is retransmitted after a while and the frame is not dropped. The register bit gem.tx_status[collision] must be cleared in the interrupt handler.

Error Condition
Hresp not OK

Transmit underrun

Transmit buffer exhausted

Retry limit exceeded

Collisions

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16.4 IEEE 1588 Time Stamping

16.4.1 Overview
Refer to the IEEE 1588 standard specification for more information on the protocol and section 16.2.7 IEEE 1588 Time Stamp Unit for more information on the implementation of the Timestamp Unit. The following section briefly reviews the essential terms prior to discussion of the programming model. The PTP system deals with the following different entities: A grandmaster clock . This is typically the IEEE1588 master clock which is the ultimate source of time on the network. A boundary clock . It is a multi-port switch containing one port that is a PTP slave to a master clock, while the other ports are masters to downstream slave clocks. A transparent clock . This is a PTP enhanced switch which modifies the precise time stamps within relevant PTP packets to account for transmit and receive delays within the individual switch itself. An ordinary clock . This is the typical PTP client.

For more information on different types of PTP clocks refer to the IEEE1588-2008 standard specification. Synchronization and management of a PTP system is achieved through the exchange of messages across the network. PTP uses the following message types: Sync, Delay_Req, Follow_up, and Delay_Resp messages are used by ordinary and boundary clocks. They are used to communicate timing information for clock synchronization. Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up are used to measure path delays across the communication medium so that they can be compensated for by the system. These are extensively used by transparent clocks and are available only in PTPv2. Announce messages are used by best master clock algorithm (BMCA) to build a clock hierarchy and select the grandmaster clock. Management messages are used for network monitoring and management. Signaling frames are used for non -time critical communication across clocks.

Refer to IEEE1588-2008 Clause 13 for more information on message types and formats.

PTP Message Format

All PTP messages contain a header, body and suffix. The PTP message header is 34 bytes long. Please refer to IEEE1588-2008 Clause 13 for more information on message formats. The important fields in the message header are described briefly as follows: Each clock port is identified by Source Port Identity (sourcePortIdentity) which is a 10 byte address. The sourcePortIdentity is common for all PTP messages.

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Each PTP message is identified with a message Type which is a 4 bit field in the PTP message header. Message Types are identified in Table 16-8 Message Types Message Type
0x0 0x1 0x2 0x3 0x8 0x9 0xA 0xB 0xC 0xD

Table 16-8:
Sync Delay_Req PDelay_Req

PTP Frames

PDelay_Resp Follow_up Delay_Resp PDelay_Resp_Follow_Up Announce Management Signaling

The versionPTP field signifies which PTP version is being used PTPv1 or PTPv2. The messageLength field signifies the total length of the PTP message. It is different for different PTP messages. The flag field is used for various purposes and can carry different values for different types of frames. An example of use for this field as a twoStepFlag in Sync and PDelay_Req frames is to distinguish one-step and two-step time stamping. If the sending master clock can perform one-step time stamping, the twoStepFlag carries a value of 0 .

Note: The Zynq-7000 AP SoC supports two-step timestamping the twoStepFlag should always
be 1 . The correctionField is generally significant for transparent clocks. The transparent clocks update the correctionField to specify the slave regarding the exact time the PTP frames took to traverse through the transparent clocks. If transparent clocks are not present in the path of a PTP message, the correctionField can have a zero value. The sequenceId field is extensively used in the PTP messages. The originator of certain PTP frames message Types assigns a sequence ID to the corresponding message through the sequenceId field. The controlField is provided to maintain backward compatibility with PTPv1 based hardware designs. It contains different values for different types of PTP frames. The logMessageInterval field is provided to represent the mean time interval between successive PTP messages.

The steps to develop a simple and typical non-OS standalone example which can be used to synchronize PTP clocks between two Zynq-7000 AP SoC systems are described in the following sections. This information should be used for reference purpose only and is not meant to provide the best possible implementation for accuracy. Please refer to the IEEE1588 standard specification for more information. The IEEE1588 implementation involves the following. 1. Controller initialization

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2. 3. 4. 1. 2. 3.

Best master clock algorithm (BMCA) PTP packet handling at the master port PTP packet handling at the slave port The following sections do not describe the handling of management and signaling frames because they are not integral to the implementation of the core PTP functionality. The illustrations in these sections do not describe an implementation-specific mechanism to change clock attributes dynamically. The PTP packets processed here are simple Ethernet multicast packets. The scope of the following sections do not include UDP based multicast packets. The explanation refers to non-OS based standalone implementation which does not implement a TCP/IP stack.

Notes:

16.4.2 Controller Initialization

The controller must be initialized with the interrupts, timer and PTP. 1. 2. 3. Initialize the controller with interrupts and timers . Refer to section 16.3 Programming Guide. Enable the PTP interrupts . Refer to section 16.3.6 Configure Interrupts Setup a timer with interrupts and appropriate interrupt handlers to enable periodic transmission of packets . TTC timers or CPU private timers can be used for this purpose. For a typical case, interrupts can be generated every 500 ms. Setup the UART to monitor debug messages from the application. Refer to Chapter 19, UART Controller to program the UART.

4.

The following steps are specifically for the PTP functionality: 1. 2. Initialize the seconds and nanoseconds timers . Write appropriate values to the gem.timer_s and gem.timer_ns registers, respectively. Program the timer increment value in the gem.timer_incr register. Example : For a CPU clock that runs at 666.67 MHz and PTP clocked with CPU_1x clock of 111.11 MHz, 1 PTP clock cycle corresponds to 9 ns. The gem.timer_incr[ns_delta] register bit in this case should be set to 9. As another example, consider a CPU_1x clock of 120 MHz, 1 PTP clock cycle corresponds to 8.33 ns. In this case, the counter should increment by 8 ns for 2 clock cycles and 9 ns for 1 clock cycle to average 8.33 ns in 3 clock cycles. For such a setting, register bit gem.timer_incr[ns_delta] is set to 8, gem.timer_incr[alt_ct_ns_delta] is set to 9, and gem.timer_incr[incr_b4_alt] is set to 2. 3. Initialize the common fields of data structures used for various PTP packets . All PTP packets have a common message header.

Timer Interrupt Handler

A timer is initialized to generate interrupts at pre-defined intervals. The operation of the interrupt handler at the master and slave clock ports are briefly illustrated.

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Example: Master Clock Port

1. 2. Initiate a transmission of Sync and Announce frames at pre-defined intervals. Initiate a transmission of PDelay_Req frames at regular intervals.

Example: Slave Clock Port

1. 2. 3. Initiate a transmission of PDelay_Req frames at regular intervals. Wait for Sync frame for a predefined interval of time. If a Sync timeout occurs, change to become a PTP master. Wait for an Announce frame for a pre-defined interval of time. If an Announce timeout occurs, change to become a PTP master.

If a PDelay_Req frame is not received for a predefined period of time, or no Pdelay_resp and PDelay_resp_Follow_Up were received for a PDelay_Req packet, then there is a grave error. As part of error handling, the whole PTP state machine can be stopped (for both PTP master and slave) and no clock synchronization done (if it is a slave port). The intervals as mandated by the protocol range from 2-128 to 2127 seconds. The interval is decided by the system specification. Since the same timer is used for Sync, Announce and PDelay_Req frames, the timer expiry duration is decided by the minimum time interval for all these frames. In a typical use case, the Sync frames can be sent out every 125 milliseconds, Announce frames and PDelay_Req frames every 1 second. Similarly, typical Announce frame timeouts can be 2-3 seconds and PDelay_Req, PDelay_Resp , PDelay_Resp_Follow_up timeouts can be 3-5 seconds.

16.4.3 Best Master Clock Algorithm (BMCA)

The BMCA performs a distributed selection of the best candidate clock (which becomes the grandmaster clock) based on different clock properties for the available clocks in the network: Priority1 Clock class Clock accuracy Clock variance (offset scaled log variance) Priority2 Clock identity (to break the tie)

Refer to the IEEE 1588 Standard Specification for more information on clock attributes and BMCA. In a typical implementation, each clock port can be identified with a structure which has fields for the above clock properties. Other than these properties, the BMCA clock port can also be identified with the steps removed field. For more information regarding this field refer to the IEEE1588 specifications. When a slave receives Announce frames from multiple master hosts, the steps removed field can become significant in deciding the master clock. The implementation should maintain an identical structure to identify the current grandmaster clock properties. The BMCA is invoked when an Announce frame is received by the slave.

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Example: BMCA
1. 2. Compare the fields of the Announce frame received with that of the current grandmaster starting with Priority1, progressing to the next field in the event of a tie. The one with a higher priority becomes the new grandmaster.

16.4.4 PTP Packet Handling at the Master

Refer to IEEE 1588 Standard Specification for more information on packet formats and protocol. 1. Form and send Sync frames at regular intervals . For two-step clocks (as in the Zynq-7000 AP SoC) the originTimestamp field should be zero. The sequenceId should be 1 greater than the sequenceId of the last Sync frame transmitted from the same master port. Refer to section 16.4.1 Overview for some examples on setting header fields. Read and store exact time stamp for the transmitted Sync frame . The Controller generates an interrupt on successful transmission of a Sync frame. The registers gem.ptp_tx_s and gem.ptp_tx_ns are read and stored to represent the exact time stamp for the transmitted Sync frame in the interrupt handler. Form and send the Follow_Up frame immediately after the successful transmission of the Sync frame . The sequenceId should be the same as that of the just transmitted Sync frame. The 10 byte preciseOriginTimestamp field should be created using the stored seconds and nanoseconds timestamp for the Sync frame. The Follow_Up frame is transmitted and since it is not an event message, it is not time stamped by the hardware.

2.

3.

Note: The clock time stamp point for the AP SoCs GigE is the MII interface. Since the Sync frame
travels through the external PHY after this time stamp point, the hardware observed time stamp does not take care of the delay introduced by the external PHY. Users should determine the typical external PHY latencies for their systems and add the same to the preciseOriginTimestamp field.

4.

Form and send Announce frames at regular intervals . The Announce frame should be set with the clock attributes for the PTP master clock. The Announce frame is transmitted and since it is not an event message, it is not time stamped by the hardware. Send PDelay_Req frames at regular intervals . The master, acting as a peer for the PDelay measurement state machine must send PDelay_Req frames at regular intervals. The sequenceId field is assigned with a value of 1 greater than the last sent PDelay_Req frame. The field originTimestamp can typically be filled up with a zero value along with the reserved field. Read and store the exact time stamp for the transmitted PDelay_Req frame . The controller generates an interrupt on successful transmission of the PDelay_Req frame. The registers gem.ptp_peer_tx_s and gem.ptp_peer_tx_ns are read and stored to represent the time stamp of the transmitted PDelay_Req frame in the interrupt handler. Let this time stamp be t1.

5.

6.

Note: Since the clock time stamp point is the MII interface and the PDelay_Req frame travels

through the external PHY after this point, the exact time stamp should be created by adding the introduced delays by the external PHY. Store the time stamp for the received PDelay_Resp frame . The Master receives a PDelay_Resp frame from the peer clock. The controller generates a PDelay_Resp received interrupt. The master reads the registers gem.ptp_peer_rx_s and gem.ptp_peer_rx_ns registers and stores them as the received timestamp for the PDelay_Resp frame. Let this timestamp be t4.

7.

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Note: Since the PTP message first travels through the external PHY before being time stamped

at the MII interface by the hardware, for calculating the exact time stamp for the received packet, the delay introduced by the external PHY must be subtracted from the hardware reported time stamp to reach at the exact time stamp.

8.

Read the time stamp for the PDelay_Req frame received at the slave (peer). The master validates the received PDelay_Resp for correct sequenceId which should be the same as that for the PDelay_Req frame sent by the master. Similarly the master validates the PTP message body field requestingPortIdentity for the correct value which should be same as the sourcePortIdentity of the master. The master reads the PTP message body field requestReceiptTimestamp and stores it. This is the timestamp when the slave (peer) received the PDelay_Req packet. Let this time stamp be t2. Process the received PDelay_Resp_Follow_Up frame. The Master receives a PDelay_Resp_Follow_Up frame from the slave (peer) clock port. This is a general PTP message and hence no PTP event interrupt is generated. The master validates for sequenceId and requestingPortIdentity fields as described above. The master reads the PTP message body field responseOriginTimestamp to get the exact timestamp when the last received PDelay_Resp message was transmitted from the slave (peer). Let the time stamp be t3.

9.

10. Calculate the peer delay. The master calculates the peer delay as (t4-t1) - (t3-t2). The calculated peer delay is not used by the master; however every node on a PTP network should maintain peer delays with other PTP peers on the network.
X-Ref Target - Figure 16-5

Port-1 Time

Port-2 Time

t1 tms

Pdelay_Req

t2

tsm T4

Pdelay_Resp

t3

Pdelay_Resp_Follow_Up

UG585_c16_08_100512

Figure 16-5:

Link Delay Measurement

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16.4.5 PTP Packet Handling at the Slave

Refer to IEEE 1588 Standard Specification for more information on packet formats and protocol. 1. Calculate the peer delay as described in steps 5-9 in section 16.4.4 PTP Packet Handling at the Master.

Note: When the slave sends timestamps, the delays introduced by the external PHY at the slave
clock port should be taken care of. 2. Read and store timestamp for the received Sync frame . The controller generates an interrupt for PTP Sync frame received. The slave reads the gem.ptp_rx_s and gem.ptp_rx_ns registers and stores them. Let this time stamp be t5. Process the Follow_Up frame received . The controller does not generate a PTP event interrupt for a received Follow_Up frame. The Slave does a validation for the sequenceId field which should match with that for the previously received Sync frame. The slave extracts the preciseOriginTimestamp field from the Follow_up frame and stores it. This is the time at which the Sync frame left the master. The slave then adds the peer delay calculated in step (1) with this time to take care of the path delay of the PTP frame from master to slave. Let this time be t6. Calculate the final clock offset . This is the difference between t6 and t5 and is typically represented in nanoseconds. Adjust the PTP clock . The slave adjusts the PTP clock by writing to the gem.ptp_adjust register. If t6 is greater than t5, the gem.ptp_adjust[add_subn] is written as 0 , otherwise it is written as 1 . The actual nanosecond difference is written in the gem.ptp_adjust[ns_delta] register bits. Become the master in the event of a Sync or Announce timeout .

3.

4. 5.

6.

16.5 Register Overview

16.5.1 Control Registers
Control registers drive the management data input/output (MDIO) interface, set-up DMA activity, start frame transmission, and select the different modes of operation such as full duplex, half duplex and 10/100/1000 Mb/s operation. (See Table 16-9.)

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Table 16-9:

Ethernet Control Register Overview Register Name

net_{cfg,ctrl,status} tx_pauseq rx_pauseq tx_pfc_pause ipg_stretch stacked_vlan tx_status rx_status tx_qbar tx_qbar_q{1:7} rx_qbar rx_qbar_q{1:7} dma_cfg intr_{status,en,dis, mask} intr_dis_pq{1:7} intr_en_pq{1:7} intr_mask_pq{1:7} wake_on_lan isr_pq{1:7}

Function

Description
Network control, configuration and status. Rx, Tx Pause clocks. IPG stretch.

MAC Configuration

DMA Unit

Control. Receive, Transmit Status. Receive, Transmit Queue Base Address Control.

Interrupt status, enable/disable, and mask

Interrupts

PHY Maintenance MAC Address Filtering and ID Match

phy_maint hash_{top,bot} spec_addr{1:4}_{bot,top} spec_addr1_mask_{bot,top} type_id_match{1:4} timer_{s,ns} timer_{adjust,incr} timer_strobe_{s,ns} ptp_tx_{s,ns} ptp_peer_tx_{s,ns} ptp_rx_{s,ns} ptp_peer_rx_{s,ns} slcr.GEM{1,0}_CLK_CTRL slcr.GEM{1,0}_RCLK_CTRL slcr.GEM{1,0}_CPU_1XCLKACT slcr.GEM_RST_CTRL slcr.MIO_PIN_{xxx}

PHY maintenance Hash address, Specific {4:1} addresses High/Low. Match Type.

IEEE 1588 second, nanosecond counter and adjustment, increment. IEEE 1588 Tx normal/peer second, nanosecond counter. IEEE 1588 Rx normal/peer second, nanosecond counter. Refer to Chapter 25, Clocks and Chapter 26, Reset System for more information. Refer to IOP Interface Connections, page 47 for MIO pin programming information.

IEEE 1588 Precision Time Protocol

Clocks and Reset

I/O Signal Routing

16.5.2 Status and Statistics Registers

The statistics registers hold counts for various types of events associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable

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software to generate network management statistics compatible with IEEE 802.3. (See Table 16-10). Table 16-10: Ethernet Status and Statistics Register Overview Hardware Register Name
frames_tx broadcast_frames_tx multi_frames_tx frames_64b_tx frames_65to127b_tx frames_128to255b_tx frames_256to511b_tx frames_512to1023b_tx frames_1024to1518b_tx octets_tx_{top,bot} deferred_tx_frames pause_frames_tx tx_under_runs Frame Tx Statistics for Half Duplex Transmission {multi,single}_collisn_frames excessive_collisns late_collisns carrier_sense_errs frames_rx bdcast_fames_rx multi_frames_rx frames_64b_rx frames_65to127b_rx frames_128to255b_rx frames_256to511b_rx frames_512to1023b_rx frames_1024to1518b_rx Frame Rx Statistics {undersz,oversz,jab}_rx fcs_errors length_field_errors octets_rx_{top,bot} rx_symbol_errors align_errors rx_resource_errors rx_overrun_errors Frame Rx Checksum Error Statistics ip_hdr_csum_errors tcp_csum_errors udp_csum_errors Octets received High/Low, Under-run error count.

Function

Description
Error-free Tx frame, pause frame counts and bytes counts.

Frame Tx Statistics

Error-free frames transmitted: totals by size.

Octets transmitted.

Single/multiple frame, excessive/late collisions, deferred Tx frames, Tx carrier sense error counters.

Error-free frames received: normal, broadcast, multicast, pause.

Error-free frames received: totals by size.

Undersize, oversize and jabber frames. Frame sequence, length, symbol, alignment error counters.

Rx resource, overrun and last statistic clearing offset for clearing.

Checksum error counters: IP Header, TCP, UDP

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16.6 Signals and I/O Connections

16.6.1 MIOEMIO Interface Routing
The I/O interface is routed to the MIO for RGMII, and to the EMIO for GMII/MII connectivity. The PL can modify the GMII/MII interface from the MAC to construct other Ethernet interfaces that connect to external devices via PL pins. The routing of the Ethernet communications signals are shown in Figure 16-6. The Ethernet communications ports are independently routed to the MIO pins (as RGMII) or to a set of EMIO interface signals (as GMII). When using the EMIO interface both the TX and RX clocks are inputs to the PS.
X-Ref Target - Figure 16-6

RGMII
GMII Tx

GMII / RGMII Adapter

(MIO)

MAC
GMII / MII
GMII Rx (EMIO)

Ethernet Controller

slcr.GEM{1:0}_RCLK_CTRL[SRC_SEL]
UG585_c16_05_013013

Figure 16-6:

Interface Select Multiplexer

16.6.2 Precision Time Protocol

The PTP signals connected to the Ethernet controller provide the capability to handle IEEE-1588 precision time protocol (PTP) signaling.

16.6.3 Programmable Logic (PL) Implementations

There are options to provide further external interface standard support by linking the GMII signals on the EMIO interface to the PL. Users can design and connect logic to generate other interface standards on the PL pins. TBI support can be provided by connecting the GMII to a TBI compatible logic core in the PL which provides the PCS functions required for ten-bit interfacing to an external PHY via the PL pins. SGMII or 1000 Base-X support can be provided by connecting the GMII to an SGMII or 1000 Base-X compatible logic core which provides the required PCS functions and signal adaptation and drives an MGT for serial interfacing to an external PHY.

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16.6.4 RGMII Interface via MIO

An example Ethernet communications wiring connection is shown in Figure 16-7
X-Ref Target - Figure 16-7

ENET_RGMII_TX_CLK ENET_RGMII_TXD[3:0] MDI 0 P/N ENET_RGMII_TX_CTL RGMII ENET_RGMII_RX_CLK MDI 1 P/N

Ethernet Controller
MD

MIO Multiplexer

ENET_RGMII_RXD[3:0] ENET_RGMII_RX_CTL

External PHY Device

MDI 2 P/N

RJ-45 Conn.

MDI 3 P/N ENET_MDC ENET_MDIO

Zynq Device Boundary

UG585_c16_06_022712

Figure 16-7:

Ethernet Communications Wiring Connections

All Ethernet I/O pins routed through the MIO are on MIO Bank 1 (see Table 16-11).The MIO pins and restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 16-11: Ethernet RGMII Interface Signals via MIO Pins Controller Signal Signal Description
Tx clock to PHY Tx control to PHY Tx data 0 to PHY Tx data 1 to PHY Tx data 2 to PHY Tx data 3 to PHY Rx clock from PHY Rx control from PHY Rx data 0 from PHY Rx data 1 from PHY

MIO Pins GigE 0

16 21 17 18 19 20 22 27 23 24

Default Controller Input Value

~ ~ ~ ~ ~ ~

GigE 1
28 33 29 30 31 32 34 39 35 36

Name
RGMII_TX_CLK RGMII_TX_CTL RGMII_TX_D0 RGMII_TX_D1 RGMII_TX_D2 RGMII_TX_D3 RGMII_RX_CLK RGMII_RX_CTL RGMII_RX_D0 RGMII_RX_D1

I/O
O O O O O O I I I I

0 0 0 0

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Table 16-11:

Ethernet RGMII Interface Signals via MIO Pins (Contd) Controller Signal MIO Pins GigE 0
25 26

Signal Description
Rx data 2 from PHY Rx data 3 from PHY

Default Controller Input Value

0 0

GigE 1
37 38

Name
RGMII_RX_D2 RGMII_RX_D3

I/O
I I

16.6.5 GMII/MII Interface via EMIO

An example illustrating the GMII interface connections through the PL to the PL pins is shown in Figure 16-8. Ethernet GMII/MII interface signals routed through the EMIO are identified in Table 16-12.
X-Ref Target - Figure 16-8

Zynq-7000 AP SoC Device

PS

PL
GMII: Tx Signals GMII: Rx Signals
2.5 or 25 MHz Clock 125 MHz Clock
Without Tx Clock

MAC

Optional PS7 Wrapper

TX clock

EMIOENETxGMIITXCLK

0
Tx Clock

Ethernet

PHY
Auto-negotiated Speed Detection Logic
MDIO MDC

EMIOENETxMDIO{I, O, TN}

MDIO

EMIOENETxMDIOMDC

MDIO

GIC

IRQF2Px

INTERRUPT
UG585_c16_07_100212

Figure 16-8: Table 16-12:

GMII Interface via EMIO Connections

Ethernet GMII/MII Interface Signals via EMIO Interface Reference Clock

~ ~ ~

Interface Signal
Carrier sense Collision detect Controller Interrupt input

Default Controller Input Value

EMIO Interface Signals Name

EMIOENET[1,0]GMIICRS EMIOENET[1,0]GMIICOL EMIOENET[1,0]EXTINTIN

I/O
I I I

Tx Signals
Tx Clock Tx Data (7:0) ~ Tx Clk ~ EMIOENET[1,0]GMIITXCLK EMIOENET[1,0]GMIITXD[7:0] I O

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Table 16-12:

Ethernet GMII/MII Interface Signals via EMIO Interface (Contd) Reference Clock
Tx Clk Tx Clk

Interface Signal
Tx Enable Tx Error

Default Controller Input Value

~ ~

EMIO Interface Signals Name

EMIOENET[1,0]GMIITXEN EMIOENET[1,0]GMIITXER

I/O
O O

Tx Timestamp Signals
Tx Start-of-Frame Tx PTP delay req frame detected Tx PTP peer delay frame detect Tx PTP pear delay response frame detected Tx PTP sync frame detected Tx Clk Tx Clk Tx Clk Tx Clk Tx Clk ~ ~ ~ ~ ~ EMIOENET[1,0]SOFTX EMIOENET[1,0]PTPDELAYREQTX EMIOENET[1,0]PTPPDELAYREQTX EMIOENET[1,0]PTPPDELAYRESPTX EMIOENET[1,0]PTPSYNCFRAMETX O O O O O

Rx Signals
Rx Clock Rx Data (7:0) Rx Data valid Rx Error ~ Rx Clk Rx Clk Rx Clk EMIOENET[1,0]GMIIRXCLK EMIOENET[1,0]GMIIRXD[7:0] EMIOENET[1,0]GMIIRXDV EMIOENET[1,0]GMIIRXER I I I I

Rx Timestamp Signals
Rx Start of Frame Rx PTP delay req frame detected Rx PTP peer delay frame detected Rx PTP peer delay response frame detected Rx PTP sync frame detected Notes:
1. If using MII connect the RX[7:4] bits to logic zero.

Rx Clk Rx Clk Rx Clk Rx Clk Rx Clk

~ ~ ~ ~ ~

EMIOENET[1,0]GMIISOFRX EMIOENET[1,0]PTPDELAYREQRX EMIOENET[1,0]PTPPDELAYREQRX EMIOENET{0.1}PTPPDELAYRESPRX EMIOENET{0.1}PTPSYNCFRAMERX

O O O O O

16.6.6 MDIO Interface Signals via MIO and EMIO

MDIO interface signals routed through the MIO and EMIO are identified in Table 16-13. Table 16-13: MDIO Interface Signals via MIO and EMIO Default Controller Input Value
~ ~ ~ 0 53 53 IO MDIO_IO

MIO Pins GigE 0

52

EMIO Interface Signals

Name
EMIOENET[1:0]MDIOMDC EMIOENET[1:0]MDIOO EMIOENET[1:0]MDIOTN EMIOENET[1:0]MDIOI

MDIO Interface
MD clock output MD data output MD data 3-state MD data input

GigE 1 I/O Name

52 O MDIO_CLK

I/O
O O O I

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16.6.7 MIO Pin Considerations

LVCMOS33 is not supported for the RGMII interface. Recommendation is to use 1.8/2.5V I/O standards.

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Chapter 17

SPI Controller
17.1 Introduction
The SPI bus controller enables communications with a variety of peripherals such as memories, temperature sensors, pressure sensors, analog converters, real-time clocks, displays, and any SD card with serial mode support. The SPI controller can function in master mode, slave mode or multi-master mode. The Zynq-7000 devices include two SPI controllers. The controller is based on the Cadence SPI core. In master mode, the controller drives the serial clock and slave selects with an option to support SPIs multi-master mode. The serial clock is derived from the PS clock subsystem. The controller initiates messages using up to 3 individual slave select (SS) output signals that can be externally expanded. The controller reads and writes to slave devices by writing bytes to the 32-bit read/write data port register. In multi-master mode, the controller three-states its output signals when the controller is not active and can detect contention errors when enabled. The outputs are three-stated immediately by resetting the SPI enable bit. An Interrupt Status register indicates a mode fault. In slave mode, the controller receives the serial clock from the external device and uses the SPI_Ref_Clk to synchronize data capture. The slave mode includes a programmable start detection mechanism when the controller is enabled while the SS is asserted. The read and write FIFOs provide buffering between the SPI I/O interface and the software servicing the controller via the APB slave interface. The FIFO are used for both slave and master I/O modes. This chapter is organized into the following sections: 17.1 Introduction 17.2 Functional Description 17.3 Programming Guide 17.4 System Functions 17.5 I/O Interfaces

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17.1.1 Features
Each SPI controller is configured and controlled independently, They include the following features: Four wire bus MOSI, MISO, SCLK, and SS

up to 3 slave selects for master mode

Full-duplex operation offers simultaneous receive and transmit 32-bit register programming via APB slave interface Memory mapped read/write data ports for Rx/Tx FIFOs (byte-wide)

128-byte read and 128-byte write FIFOs Programmable FIFO thresholds status and interrupts Manual and auto start transmission of data Manual and auto slave select (SS) mode Slave select signals can be connected directly to slave devices or expanded externally Programmable SS and MOSI delays Programmable start detection mode Drives I/O buffers into 3-state if controller is not enabled Generates a Mode Failure interrupt when another master is detected 25 MHz SCLK when the I/O signals are routed via the EMIO interface to the PL pins

Master I/O mode

Slave I/O mode

Multi-master I/O Capable

50 MHz SCLK clock frequency when I/O signals are routed to the MIO pins

Programmable clock phase and polarity (CPHA, CPOL) Programmable interrupt-driven device or poll status

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17.1.2 System Viewpoint

The system viewpoint diagram of the SPI controller is shown in Figure 17-1.
X-Ref Target - Figure 17-1

IRQ ID# {58, 81} Slave port

MIO EMIO Routing SPI Interface Controller

Device Boundary

Interconnect

APB

MIO Pins

CPU_1x clock SPI{0, 1} CPU_1x reset

Control Registers

EMIO Signals

SPI REF reset SPI REF clock Clocking

PL

UG585_c17_01_030212

Figure 17-1:

SPI System Block Diagram

SPI Interface Controller

There are two independent SPI interface controllers (SPIx; where x = 0 or 1 ). The I/O signals of each independent controller can be routed to MIO pins or the EMIO interface. Each controller also has individual interrupts signals to the PS interrupt controller and a separate reset signal. Each controller has its own set of control and status registers.

Clocking
The PS clock subsystem provides a reference clock to the SPI controller. The SPI_Ref_Clk clock is used for the controller logic and by the baud rate generator to create the SCLK clock for master mode.

MIO-EMIO
The SPI I/O signals can be routed to the MIO pins or the EMIO interface to the PL, as explained in 17.5 I/O Interfaces. The general routing of signals is explained in Chapter 2, Signals, Interfaces, and Pins.

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17.1.3 Block Diagram

A functional block diagram of the SPI controller is shown in Figure 17-2.
X-Ref Target - Figure 17-2

MO TxFIFO Transmit SO SS[2:0] SPI Master APB Interface SPI CTRL SPI Slave SCLK SCLK
APB

SPI Interface Pins MOSI SCLK SS MISO

SS

RxFIFO
Interrupts

Receive

Slave Sync

SI MI

Interrupts
UG585_c17_02_072512

Figure 17-2:

SPI Peripheral Block Diagram

APB Slave Interface

The 32-bit APB slave interface responds to register reads and writes, including data ports for reading and writing commands and data from and to the FIFOs. All registers transactions are 32 bits. The data ports use bits [7:0] of these ports. The configuration and status registers are listed in Appendix B, Register Details.

SPI Master Mode

When the controller operates in master mode, it drives the SCLK clock and up to 3 slave select output signals.The SS and start of transmission on MOSI can be manually controlled by software or automatically controlled by the hardware.

SPI Slave Mode

When the controller operates in slave mode, it uses a single slave select input (SS 0). The SPI signals are shown in Figure 17-2 and listed in section 17.5 I/O Interfaces. The SCLK is synchronized to the controller reference clock (SPI_Ref_Clk). Refer to section 17.2.3 Slave Mode.

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Tx and Rx FIFOs
Each FIFO is 128 bytes. Software reads and writes these FIFOs using the register mapped data port registers. FIFO management for master mode is described in 17.3.3 Master Mode Data Transfer and for slave mode in 17.3.4 Slave Mode Data Transfer. The FIFOs bridge two clock domains; APB interface and the controllers SPI_Ref_Clk. Software writes to the TxFIFO in the APB clock domain and the controller reads the TxFIFO in the SPI_Ref_Clk domain. The controller fills the RxFIFO in the SPI_Ref_Clk domain and software reads the RxFIFO in the APB clock domain.

17.1.4 Notices
7z010 CLG225 Device
The 7z010 CLG225 device supports 32 MIO pins (not 54). This is shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. The 7z010 CLG225 device restricts the available MIO pins so connections through the EMIO should be considered. All of the 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

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17.2 Functional Description

17.2.1 Master Mode 17.2.2 Multi-Master Capability 17.2.3 Slave Mode 17.2.4 FIFOs 17.2.5 FIFO Interrupts 17.2.6 Interrupt Register Bits, Logic Flow 17.2.7 SPI-to-SPI Connection

17.2.1 Master Mode

In master mode, the SPI I/O interface can transmit data to a slave or initiate a transfer to receive data from a slave. The controller selects one slave device at the time using one of the three slave select lines. If more than three slave devices need to be connected to the master, it is possible to add an external peripheral select 3-to-8 decode on the board.

Data Transfer
The SCLK clock and MOSI signals are under control of the master. Data to be transmitted is written into the TxFIFO by software using register writes and then unloaded for transmission by the controller hardware in a manual or automatic start sequence. Data is driven onto the master output (MOSI) data pin. Transmission is continuous while there is data in the TxFIFO. Data is received serially on the MISO data pin and is loaded 8 bits at a time into the RxFIFO. Software reads the RxFIFO using register reads. For every n bytes written to the TxFIFO, there will be n bytes stored in RxFIFO that must be read by software before starting the next transfer.

Auto/Manual SS and Start

Data transfers on the I/O interface can be manually started using software or automatically started by the controller hardware. In addition, the slave select assertion/de-assertion can be done by the controller hardware or from software. These four combinations are shown in Table 17-1. Table 17-1: SPI Master Mode SS and Start Modes Data Transfer Start Control
Manual Start Manual SS (software) Auto Start

Slave Select Control

Manual Manual Start Slave Enable & Select Command

1 1

Operation
Software controls the slave select and must issue the start command to serialize data. Software controls the slave select, but the controller hardware automatically starts to serialize data when there is data in the TxFIFO.

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Table 17-1:

SPI Master Mode SS and Start Modes (Contd) Data Transfer Start Control
Manual Start Auto Start

Slave Select Control

Manual Manual Start Slave Enable & Select Command

0 1

Operation
Controller hardware controls the slave select, but the software must issue the start command to serialize data in the TxFIFO. Controller hardware controls the slave select and serializes data when there is data in the TxFIFO.

Auto SS (controller)

Manual SS
Software selects the manual slave select method by setting the spi.Config_reg0 [Manual_CS] bit = 1 . In this mode, software must explicitly control the slave select assertion/de-assertion. When the [Manual_CS] bit = 0 , the controller hardware automatically asserts the slave select during a data transfer.

Automatic SS
The SPI controller asserts/de-asserts the slave select for each transfer of TxFIFO content on to the MOSI signal. Software writes data to the TxFIFO and the controller asserts the slave select automatically, transmits the data in the TxFIFO and then de-asserts the slave select. The slave select gets de-asserted after all the data in the Tx FIFO is transmitted. This is the end of the transfer. Software ensures the following in automatic slave select mode. Software continuously fills the TxFIFO with the data bytes to be transmitted, without the TxFIFO becoming empty, to maintain an asserted slave select. Software continuously reads data bytes received in the RxFIFO to avoid overflow.

Software uses the TxFIFO and RxFIFO threshold levels to avoid FIFO under- and over-flows. The TxFIFO empty condition is flagged when the number of bytes in TxFIFO is less than the TxFIFO threshold level. The RxFIFO full condition is flagged when the number of bytes in RxFIFO is more than the RxFIFO threshold level.

Manual Start
Enable
Software selects the manual transfer method by setting the spi.Config_reg0 [Man_start_en] bit = 1 . In this mode, software must explicitly start the data transfer using manual start command mechanism. When the [Man_start_en] bit = 0 , the controller hardware automatically starts the data transfer when there is data available in the TxFIFO.

Command
Software starts a manual transfer by writing a 1 to the spi.Config_reg0 [Man_start_com] bit. When the software writes the 1 , the controller hardware starts the data transfer and transfers all the data

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bytes present in the TxFIFO. The [Man_start_com] bit is self-clearing. Writing a 1 to this bit is ignored if [Man_start_en] = 0 . Writing a 0 to [Man_start_com] has no effect, regardless of mode.

17.2.2 Multi-Master Capability

For Multi-master mode, the controller is programmed for master mode [MODE_SEL] and can initiate transfers on any of the slave selects. When the software is ready to initiate a transfer, it enables the controller using the [SPI_EN] bit. When the transaction is done, the software disables the controller. The controller cannot be selected by an external master when the controller is in Master Mode. The controller detects another master on the bus by monitoring the open-drain slave select signal (active Low). The detection mechanism is enabled by the [Modefail_gen_en]. When the controller detects another master, it sets the spi.Intr_status_reg0 [MODE_FAIL] interrupt status bit and clears the spi.En_reg0 [SPI_EN] control bit. The software can receive the [MODE_FAIL] interrupt so it can abort the transfer, reset the controller, and re-send the transfer.

17.2.3 Slave Mode

In slave mode, the controller receives messages from the external master and outputs a simultaneous reply. The controller enters slave mode when spi.Config_reg0 [MODE_SEL] = 0 and spi.En_reg0 [SPI_EN] = 1 . The SCLK latches data on the MOSI input. If the slave select input signal is High (inactive), the controller ignores the MOSI input. When the slave select is asserted, it must be held active for the duration of the transfer. If SS de-asserts during the transfer, the controller sets the spi.Intr_status_reg0 [MODE_FAIL] interrupt bit. The software receives the [MODE_FAIL] interrupt so it can abort the transfer, reset the controller, and re-send the transfer. The error mechanism is enabled by the [Modefail_gen_en] bit. Data to be sent to the master is written into the TxFIFO by software and then serialized onto the master input (MISO) signal by the controller. Transmission continues while there is still data in the TxFIFO and the slave select signal remains asserted (active Low).

Clocking
The slave select input pin must be driven synchronously to the SCLK input. The controller operates in the SPI_Ref_Clk clock domain. The input signals are synchronized and analyzed in the SPI_Ref_Clk domain.

Word Detection
The start of a word is detected in th SPI_Ref_Clk clock domain. Detection when Controller is enabled: If the controller is enabled (from a disabled state) at a time when SS is Low (active), the controller will ignore the data and wait for the SCLK to be inactive (a word boundary) before capturing data. The controller counts SCLK inactivity in the SPI_Ref_Clk domain. A new word is assumed when the SCLK idle count reaches the value programmed into the [Slave_Idle_coun] bit field.

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Detection when SS asserts: With the controller enabled and SS is detected High (inactive), the controller will assume the start of the word occurs on the next active edge of SCLK after SS transitions Low (active).

Note: The start condition must be held active for at least four SPI_Ref_Clk cycles to be detected.
If slave mode is enabled at a time when the external master is very close to starting a data transfer, there is a small probability that false synchronization will occur, causing packet corruption. This issue can be avoided by any of the following means: Ensure that the external master does not initiate data transfer until at least ten SPI_Ref_Clk cycles have passed after slave mode has been enabled. Ensure that slave mode is enabled before the external master is enabled. Ensure that the slave select input signal is not active when the slave is enabled.

17.2.4 FIFOs
The Rx and Tx FIFOs are each 128 bytes deep.

RxFIFO
If the controller attempts to push data into a full RxFIFO then the content is lost and the sticky overflow flag is set. No data is added to a full RxFIFO. Software writes a 1 to the bit to clear the [RX_OVERFLOW] bit.

TxFIFO
If software attempts to write data into a full TxFIFO then the write is ignored. No data is added to a full TxFIFO. The [TX_FIFO_full] bit is asserted until the TxFIFO is read and the TxFIFO is no longer full. If the TxFIFO overflows, the sticky [RX_OVERFLOW] bit is set = 1.

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17.2.5 FIFO Interrupts

The Rx and Tx FIFO interrupts are illustrated in Figure 17-3.
X-Ref Target - Figure 17-3

RxFIFO (128 bytes)

Overflow Interrupt
[RX_OVERFLOW]

TxFIFO (128 bytes)

Full Interrupt
[TX_FIFO_full]

Full Interrupt
[RX_FIFO_full]

TxFIFO Threshold
spi.TX_thres_reg0

Not Full = 0 (full) Not Full Interrupt

[TX_FIFO_not_full]

Not Empty = 1 Not Empty Interrupt

[RX_FIFO_not_empty]

Not Full = 1

RxFIFO Threshold
spi.RX_thres_reg0

Not Empty = 0 (empty)

Underflow Interrupt
[TX_FIFO_underflow]
UG585_c17_03_022613

Figure 17-3:

SPI Rx and Tx FIFO Interrupts

17.2.6 Interrupt Register Bits, Logic Flow

The interrupt status bits (sticky and dynamic) are filtered by the mask register and then sent to the system interrupt controller. The mask register is controlled by the en/dis interrupt control registers (see Figure 17-4).
X-Ref Target - Figure 17-4

Interrupts:
spi.Intrpt_status_reg0
Bit 6: [TX_FIFO_underflow] (sticky) Bit 5: [RX_FIFO_full] Bit 4: [RX_FIFO_not_empty] Bit 3: [TX_FIFO_full] Bit 2: [TX_FIFO_not_full] Bit 1: [MODE_FAIL] (sticky) Bit 0: [RX_OVERFLOW] (sticky)

spi.Intrpt_mask_reg0
0: masked 1: enabled

PS Interrupt IRQ ID #58 / #81

Mask Enable spi.Intrpt_en_reg0 0 1 spi.Intrpt_dis_reg0 1 0

UG585_c17_04_022613

Figure 17-4:

SPI Interrupt Register Bits, Logic Flow

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17.2.7 SPI-to-SPI Connection

The I/O signals of the two SPI controller in the PC are connected together signals when the slcr.MIO_LOOPBACK [SPI_LOOP_SPI1] bit is set = 1. In this mode, the clock, slave select, MISO, and MOSI signals from one controller are connected to the other controllers clock, slave, MISO, and MOSI signals. respectively.

17.3 Programming Guide

17.3.1 Start-up Sequence 17.3.2 Controller Configuration 17.3.3 Master Mode Data Transfer 17.3.4 Slave Mode Data Transfer 17.3.5 Interrupt Service Routine 17.3.6 Register Overview

17.3.1 Start-up Sequence

Example: Start-up Sequence
1. 2. 3. 4. 5. Reset controller: Assert and de-assert the Ref and CPU_1x resets, refer to section 17.4.1 Resets. Program clocks: Program the SPI_Ref_Clk, refer to section 17.4.2 Clocks. Tx/Rx signal routing: Refer to section 17.5 I/O Interfaces. Controller configuration: Refer to section 17.3.2 Controller Configuration. Interrupt configuration: Configure the ISR to handle the interrupt conditions. The simplest ISR reads data from the RxFIFO and writes content to the TxFIFO. The PS interrupt controller is described in Chapter 7, Interrupts. The interrupt mechanism for the SPI controller is described in section 17.3.5 Interrupt Service Routine. Start data transfers:

6.

Master Mode operation select: Manual/Auto start and SS, refer to section 17.3.3 Master Mode Data Transfer. Slave Mode operation, refer to section 17.3.4 Slave Mode Data Transfer.

17.3.2 Controller Configuration

Set controller parameters by writing to the spi.Config_reg register: Set baud rate [BAUD_RATE_DIV]. Set clock phase [CLK_PH] and Polarity [CLK_POL]. Select Master/Slave mode [MODE_SEL].

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Set Mode fail generation, [Modefail_gen_en], for multi-master mode systems. Set SS to 0b1111 to de-assert all the slave selects before the start of transfers.

Example: SPI 0 Configuration for Master Mode

This example uses a single chip select, a baud rate of 12.5 Mb/s, a clock phase set to inactive, and a clock polarity of quiescent High. 1. Configure the controller: Write 0x0002_FC0F to the spi.Config_reg register. a. c. De-assert all chip selects (for now): [CS] = 1111 . Set baud rate to 12.5 Mbps. [BAUD_RATE_DIV] = 1 . This example assumes a 50 MHz SPI_Ref_Clk. Baud rate generator description is in section 17.3.3 Master Mode Data Transfer.

b. No external 3-to-8 chip select decoder. [PERI_SEL] = 0 .

d. Set clock phase, [CLK_PH] and Polarity, [CLK_POL] to 1 . These parameters are discussed in section 17.5.1 Protocol. e. f. Select Master mode: [MODE_SEL] = 1 . Look for bus collisions: [Modefail_gen_en] = 1 .

g. Do not initiate a transmission. [Man_start_com] = 0 .

17.3.3 Master Mode Data Transfer

The four combinations of master operating mode are described in section 17.2.1 Master Mode. The examples below illustrate the programming steps for each mode.

Example: Master Mode Manual SS and Manual Start

1. 2. 3. 4. 5. Enable manual SS: Write 1 to spi.Config_reg [Manual_CS]. Select manual start: Write 1 to spi.Config_reg [Man_start_en]. Assert slave select: Set spi.Config_reg [CS] = 1101 to assert slave select 1. Enable the controller: Write 1 to spi.EN_reg0 [SPI_EN]. Write bytes to the TxFIFO: a. Write the data to the TxFIFO using the register spi.Tx_data_reg. b. Continue to write data to the TxFIFO to its full depth or until no further data is needed to be written. c. 6. 7. 8. Increment the data byte counter in the driver software after each byte is written to the TxFIFO.

Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enableRxFIFO full, RxFIFO overflow, TXFIFO empty, and fault conditions. Start the data transfer: Set spi.Config_reg0 [Man_start_com] = 1 . Wait for interrupts.

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9.

Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using the interrupt handler.

10. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow, TxFIFO empty, and fault conditions. 11. Disable the controller: Set spi.En_reg0 [SPI_EN] = 0 . 12. De-assert slave select: Set spi.Config_reg0 [CS] = 1111 .

Example: Master Mode Manual SS and Auto Start

1. 2. 3. 4. Enable manual SS: Write 1 to spi.Config_reg [Manual_CS]. Assert slave select: Set spi.Config_reg [CS] = 1101 to use slave select 1. Enable the controller: Write 1 to spi.EN_reg0 [SPI_EN]. Write bytes to the TxFIFO: a. Write the data to the TxFIFO using the register spi.Tx_data_reg. b. Continue to write data to the TxFIFO to its full depth or until no further data is needed to be written. c. 5. 6. 7. 8. 9. Increment the data byte counter in the driver software after each byte is written to the TxFIFO.

Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enable RxFIFO full, RxFIFO overflow, TxFIFO empty, and fault conditions. Wait for interrupts. Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using the interrupt handler. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow, TxFIFO empty and fault conditions. Disable the controller: Set spi.En_reg0 [SPI_EN] = 0.

10. De-assert slave select: Set spi.Config_reg0 [CS] = 1111.

Example: Master Mode Auto SS and Manual Start

1. 2. 3. 4. Select manual start: Write 1 to spi.Config_reg0 [Man_start_en]. Assert slave select: Set spi.Config_reg0 [CS] = 1101 to use slave select 1. Enable the controller: Write 1 to spi.EN_reg0 [SPI_EN]. Write bytes to the TxFIFO: a. Write the data to the TxFIFO using the register spi.Tx_data_reg. b. Continue to write data to the TxFIFO to its full depth or until no further data is needed to be written. c. 5. Increment the data byte counter in the driver software after each byte is written to the TxFIFO.

Set the FIFO threshold levels: Set spi.TX_thres_reg0 and spi.RX_thres_reg0 threshold levels. Refer to the description at automatic mode of operation section.

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6. 7. 8. 9.

Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enable RxFIFO full, RxFIFO overflow, TxFIFO empty, and fault conditions. Start the data transfer: Set spi.Config_reg0 [Man_start_com] = 1 . Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using the interrupt handler. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow, TxFIFO empty, and fault conditions.

10. Disable the controller: Set spi.En_reg0 [SPI_EN] = 0 . 11. De-assert slave select: Set spi.Config_reg0 [CS] = 1111 .

17.3.4 Slave Mode Data Transfer

Example: Slave Mode - Interrupt Driven
Ensure that the controller configuration is done and then: 1. 2. 3. 4. 5. 6. Slave configuration: Write 0 to spi_Config_reg0. Enable the interrupts: Write 0x37 to spi.Intrpt_en_reg to enable RxFIFO Not empty, RxFIFO full, RxFIFO overflow, TxFIFO empty, and fault conditions. Enable the controller: Write 1 to spi.En_reg [SPI_EN]. Interrupt Handler: Receive data from master using the interrupt handler. Disable the interrupts: Write 0x37 to spi.Intrpt_DIS_reg to disable RxFIFO Not empty, RxFIFO full, RxFIFO overflow, TxFIFO empty, and fault conditions. Disable the controller: Write 0 to spi_En_reg0 [SPI_EN].

17.3.5 Interrupt Service Routine

Example: Interrupt Service Routine
This example handles RxFIFO overflow/underflow, multi-master collision (mode fail) and handles Rx and Tx data transfers. 1. 2. 3. 4. Disable all interrupts except TxFIFO Full and RxFIFO Not Empty: Write 0x027 to spi.Intr_dis_REG. Determine the source of the interrupt: Read the interrupt status register spi.Intr_status_reg0. Clear the interrupts: Write 1 s to the interrupt status register spi.Intr_status_reg0. Check for Mode fail Interrupt: (multi-master operation). On mode fail, abort the current transfer: a. c. 5. Reset the controller Re-send the data. b. Re-configure the controller Empty the RxFIFO: Read spi.Intr_status_reg0 [RX_FIFO_full] bits:

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a. 6.

Read data from the spi.Rx_Data_reg register. Continue to receive bytes using the data byte counter. Write data to the spi.Tx_Data_reg0 register. Increment the data byte counter after each byte is pushed.

Fill the TxFIFO: More data can be written to the TxFIFO, if needed: a. c. b. Continue to fill data until FIFO depth is reached or there is no further data.

7. 8. 9.

Check for overflow or underflow: Read the [TX_FIFO_underflow] or [RX_OVERFLOW] status bits. Handle the overflow and underflow conditions accordingly. Enable the interrupts: If more data need to be transmitted or received, set spi.Intrpt_en_reg0 [TX_FIFO_not_full] and [RX_FIFO_full] both = 1 . If there is data to be transferred (Sent/Received), then start the data transfer:

When in master mode, and data transfer is done using manual start (for both manual/auto SS), set spi.Config_reg [Man_start_en] = 1 .

17.3.6 Register Overview

The SPI registers are detailed Appendix B, Register Details. The register overview is provided in Table 17-2. Table 17-2: SPI Register Overview Register Name
Config_reg0 En_reg0 Intr_status_reg0 Interrupt Intrpt_en_reg0 Intrpt_dis_reg0 Intrpt_mask_reg0 FIFO thresholds Master mode FIFO data ports Slave mode TX_thres_reg0 RX_thres_reg0 Delay_reg0 Tx_data_reg0 Rx_data_reg0 Slave_Idle_count_reg0 Configuration SPI controller enable Interrupt status (Rx full, not empty and Tx full, not full) Interrupt enable Interrupt disable Interrupt mask/enable TxFIFO threshold level for not full RxFIFO Threshold level for not empty SS delays and separation counts in master mode Transmit data (TxFIFO) Receive data (RxFIFO) Slave idle count detects inactive SCLK

Type
Controller Configuration Controller enable

Description

17.4 System Functions

17.4.1 Resets 17.4.2 Clocks

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17.4.1 Resets
The controller has two reset domains: the APB interface and the controller itself. They can be controlled together or independently. The effects for each reset type are summarized in Table 17-3. Table 17-3: SPI Reset Effects Name
ABP Interface Reset slcr.SPI_RST_CTRL [SPIx_CPU1X_RST] PS Reset Subsystem slcr.SPI_RST_CTRL [SPIx_REF_RST]

APB Interface
Yes No

TxFIFO and RxFIFO

Yes Yes

Protocol Engine
No Yes

Registers
Yes No

Example: Reset the APB Interface and SPI 0 Controller

1. Write to the slcr reset register for SPI. Write a 1 , and after some delay write a 0 to the slcr.SPI_RST_CTRL [SPI0_REF_RST] and [SPI0_CPU1X_RST] bit fields.

17.4.2 Clocks
The core of each SPI controller is driven by the same reference clock (SPI_Ref_Clk) that is generated by the PS clock subsystem, Chapter 25, Clocks. The APB interface is clocked by the CPU_1x clock. The CPU_1x clock runs asynchronous to the reference clock. The operating frequency specifications for the controller clocks are defined in the data sheet. The I/O signals are clocked synchronously by the SCLK.

CPU_1x
The CPU_1x clock part of the CPU clock domain, refer section 25.2 CPU Clock.

SPI_Ref_Clk
The clock enable, PLL select and divisor settings are programmed using the slcr.SPI_CLK_CTRL register as described in section 25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks. Frequency Restriction Note: The SPI_Ref_Clk must be always be set to a higher frequency than the CPU_1x clock frequency.

Master Mode SCLK

The SCLK is driven by the controller in master mode. It is generated by the a divided-down SPI_Ref_Clk using the spi.Config_reg0 [BAUD_RATE_DIV] bit field. Frequency Ratio Note: The range of the baud rate divider is from a minimum of 4 to a maximum of 256 in binary steps (i.e., divide by 4, 8, 16,... 256).

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Example: SCLK for Master Mode

This example shows how to program the SPI_Ref_Clk to 100 MHz and the SCLK to 25 MHz. The example assumes the I/O PLL is at 1,000 MHz. The CPU_1x clock frequency must be less than 100 MHz. 1. Program SPI_Ref_Clk: Select PLL source, divisors and enable: Write 0x0000_0A01 to the slcr.SPI_CLK_CTRL register. a. c. 2. Select the I/O PLL: [SRCSEL] = 00 . Enable the SPI 0 reference clock: [CLKACT0] = 1 . b. Divide the I/O PLL clock by 10: [DIVISOR] = 0x0A . Program the Baud Rate Generator: Write 001 to the spi.Contro_reg0 [BAUD_RATE_DIV] when configuring the controller, refer to section 17.3.2 Controller Configuration.

Slave Mode SCLK

The controller clocks the MOSI and SS signals with the SCLK from the external master. These signals are synchronized to the SPI_Ref_Clk and processed by the controller. Frequency Ratio Note: The SPI_Ref_Clk frequency should be at least 2x the SCLK frequency in order for the controller to properly detect the start of the word transfer on the SPI bus.

17.5 I/O Interfaces

17.5.1 Protocol 17.5.2 Back-to-Back Transfers 17.5.3 MIO/EMIO Routing 17.5.4 Wiring Connections 17.5.5 MIO/EMIO Signal Tables

17.5.1 Protocol
Master Mode
The controller supports various I/O signaling relationships for master mode. There are four combinations for setting the phase and polarity control bits, spi.Config_reg0 [CLK_PH] and [CLK_POL]. These parameters affect the active edge of the serial clock, the assertion of the slave select and the idle state of the SCLK. The clock phase parameter defines the state of the SS between words and the state of SCLK when the controller is not transmitting bits. The phase and polarity parameters are summarized in Table 17-4 and illustrated in Figure 17-2.

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Table 17-4:

SPI Clock Phase and Polarity Controls CLK_PH = 0 CLK_POL = 0 CLK_POL = 1

positive negative active active

CLK_PH = 1 CLK_POL = 0
positive negative inactive inactive

CLK_POL = 1
negative positive

Driving Edge Sampling Edge SS State between Words SCLK State outside of Word

negative positive

Clock Phase Setting, CPHA (CLK_PH)

In master mode, the value of the clock phase bit, spi.Config_reg0 [CLK_PH] affects the I/O protocol using parameters in the spi.Delay_reg0 register as follows (see Figure 17-5):

CLK_PH = 0
SS Activity: The master automatically drives the SS outputs inactive (High) for a the time programmed into the spi.Delay_reg0 [d_nss] bit field: Time = (1 + [d_nss]) * SPI_Ref_Clk clock period. The minimum time is 2 SPI_Ref_Clk clock periods. Delay between Words: The delay between the last bit period of the current word and the first bit period on the next word: Time = (2 + [d_btwn]) * SPI_Ref_Clk clock period. The minimum time is 3 SPI_Ref_Clk clock periods. This delay enables the TxFIFO to be unloaded and ready for the next parallel-to-serial conversion and to toggle slave select inactive High.

CLK_PH = 1
SS Activity: The SS output signals are not driven inactive between words. Delay between Words: The minimum delay between the last bit period of the current word and the first bit period on the next word is, by default, one SPI_Ref_Clk cycles (configurable by the spi.Delay_reg0 register). This allows the TxFIFO to be unloaded and ready for the next parallel-to serial-conversion.

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X-Ref Target - Figure 17-5

CLK_PH = 0
SCLK SS

MOSI MISO

0 0

1 1

2 2

3 3

4 4

5 5

6 6

7 7

CLK_PH = 1
SCLK SS MOSI MISO
Figure 17-5:
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7

UG585_c17_05_022613

SPI I/O Signal Waveforms for Clock Phase and Polarity

17.5.2 Back-to-Back Transfers

(See Figure 17-6.)

Slave Mode Requirements

In slave mode, the controller can accept back-to-back transfers.

Master Mode Options

Auto SS, auto start (order these four starting with importance and include cross-reference for each) Auto SS, manual start Manual SS, auto start Manual SS, manual start

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X-Ref Target - Figure 17-6

CLK_PH = 0
MOSI MISO SS
Word 0 Word 1 Word 2 Word 3

CLK_PH = 1
MOSI MISO SS
UG585_c17_06_022613

Word 0

Word 1

Word 2

Word 3

Figure 17-6:

SPI Back-to-Back Transfers

17.5.3 MIO/EMIO Routing

The SPI interface signals can be routed either through the MIO pins or the EMIO interface. When the system is reset (e.g., PS_POR_B, PS_SRST_B and other methods), all of the I/O signals are routed to the EMIO interface by default. The SPI bus can operate up to 50 MHz when the bus signals are routed via the MIO. When the signals are routed via EMIO to the PL pins, the nominal clock rate is 25 MHz. Refer to the frequency specifications that are defined in the data sheet. To use the EMIO interface, the user must create logic in the PL to directly connect the SPI EMIO interface to PL I/O buffers attached to PL pins. The EMIO route supports up to 25 MHz I/O clocking. The SPI signals can be routed to specific MIO pins. Wiring diagrams are shown in section 17.5.4 Wiring Connections. The general routing concepts and MIO I/O buffer configurations are explained in section 2.5 PS-PL MIO-EMIO Signals and Interfaces.

Example: Program the I/O for SPI 0 on to MIO pins 16 to 21

This example enables Master SPI 0 onto pins 16 to 21 using up to three slave selects. 1. Configure MIO pin 16 for clock output. Write 0x0000_22A0 to the slcr.MIO_PIN_16 register. a. c. e. f. Route SPI 0 clock to pin 16. LVCMOS18: [IO_TYPE] = 001 Disable internal pull-up resistor. Disable HSTL receiver. b. Enable output, [TRI_ENABLE] = 0 . d. Slow CMOS drive edge.

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2.

Configure MIO pins 17 for MISO input. Write 0x0000_02A0 to each of the slcr.MIO_PIN_17 register. a. c. e. f. Route SPI 0 MISO to pin 17. LVCMOS18: [IO_TYPE] = 001 . Disable internal pull-up resistor. Disable HSTL receiver. b. Disable output. [TRI_ENABLE] = 1. d. Slow CMOS drive edge.

3.

Configure MIO pin 18, 19 and/or 20 for Slave Select outputs . Write 0x0000_32A0 to the slcr.MIO_PIN_18, 19 and/or 20 registers. The internal pull-up is enabled. a. Route SPI 0 slave selects signal(s) to pins 18, 19 and/or 20. Any and all of the slave selects can be activated for master mode. In slave mode, SS 0 must be used. LVCMOS18: [IO_TYPE] = 001 . Enable internal pull-up resistor. Disable HSTL receiver. Route SPI 0 MOSI to pin 21. LVCMOS18: [IO_TYPE] = 001 . Disable internal pull-up resistor. Disable HSTL receiver.

b. 3-state controlled by SPI: [TRI_ENABLE] = 0 . c. e. f. 4. a. c. e. f. d. Slow CMOS drive edge.

Configure MIO pins 21 for MOSI . Write 0x0000_22A0 to each of the slcr.MIO_PIN_21 register: b. 3-state controlled by SPI [TRI_ENABLE] = 0 . d. Slow CMOS drive edge.

17.5.4 Wiring Connections

The user can connect the each SPI controller to external SPI slaves or an SPI master via the MIO pins or the EMIO interface to PL pins. Wiring examples: Master Mode via MIO, Figure 17-7 Master Mode via EMIO, Figure 17-8 Slave Mode via MIO, Figure 17-9

The I/O signals of the two SPI controllers in the PS can be connected together as described in section 17.2.7 SPI-to-SPI Connection.

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Master Mode via MIO

X-Ref Target - Figure 17-7

Zynq-7000 AP SoC

MIO
SCLK MOSI

External Devices

Slave 0

SPI Master Controller

SCLK MOSI MISO SS 0 SS 1 SS 2

MISO SS 0

Connect up to 3 slave devices (directly). For one slave device, connect it to any of the slave selects.

Slave 1
SS 1

Slave 2
SS 2

Device Boundary
UG585_c17_07_022613

Figure 17-7:

PI Master Mode Wiring Diagram via MIO

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Master Mode via EMIO

X-Ref Target - Figure 17-8

I/O Select PL EMIO

EMIO SPI x SCLKO EMIO SPI x SCLKTN

SCLK

PS IOP

EMIO SPI x SCLKI EMIO SPI x MO EMIO SPI x MOTN

MOSI

SPI Master Controller

EMIO SPI x SI EMIO SPI x MI EMIO SPI x SOTN EMIO SPI x SO EMIO SPI x SSNTN EMIO SPI x SSON 0 EMIO SPI x SSON 1 EMIO SPI x SSON 2 EMIO SPI x SSIN Device Boundary
UG585_c17_08_022613

MISO
nc nc

SS 0 SS 1 SS 2

Figure 17-8:

SPI Master Mode Wiring Diagram via EMIO

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Slave Mode via MIO

X-Ref Target - Figure 17-9

Zynq-7000 AP SoC MIO

SCLK MOSI MISO SS 0

External Master Device

SCLK MOSI MISO SS a SS b SS c SS d

SPI Slave Controller

SCLK MOSI MISO SS 0 SS 1 nc SS 2 nc

Other External Slave Devices

Device Boundary
UG585_c17_09_022613

Figure 17-9:

SPI Slave Mode Wiring Diagram via MIO

17.5.5 MIO/EMIO Signal Tables

The SPI I/O interface signals routing has some options. The routing options include multiple positions in the MIO pins. The options are illustrated in section 2.5.4 MIO-at-a-Glance Table and in Table 17-5. Default Input Signal Routing: If the I/O signals are not routed to a set of MIO pins (MIO_PIN_xx register programming), then the EMIO interface input signals are enabled.

MIO Pin Limitation

Small Package Note: The MIO pin restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Each SPI I/O interface is selected as a group.

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Table 17-5:

SPI MIO Pins SPI Signals Clock MOSI

IO 0 21 33 45 10 22 34 46

SPI Interface I/O

Signal Type IO 0 16 28 40 12 24 36 48

Slave or Master Mode MISO

IO 0 17 29 41 11 23 35 47

Master Mode SS 1
O ~ 19 31 43 14 26 38 50

SS 0
IO 1 18 30 42 13 25 37 49

SS 2
O ~ 20 32 44 15 27 39 51

Controller Default Input Value

SPI 0, choice 1 SPI 0, choice 2 SPI 0, choice 3 SPI 1, choice 1 SPI 1, choice 2 SPI 1, choice 3 SPI 1, choice 4

EMIO Signals
The SPI I/O interface signals available on the EMIO interface are identified in Table 17-6. Table 17-6: SPI EMIO Signals Controller Default Input Value
0 0 0 1 ~ ~ ~ 0 0 0 1 ~ ~ ~ EMIOSPI1SCLKI EMIOSPI1SI EMIOSPI1MI EMIOSPI1SSIN EMIOSPI1SCLKO EMIOSPI1MO EMIOSPI1SO EMIOSPI1SSON0 EMIOSPI1SSON1 EMIOSPI1SSON2 EMIOSPI1SSNTN

SPI Interface
SPI 0 Clock SPI 0 MOSI SPI 0 MISO SPI 0 Slave Select 0 SPI 0 Slave Select 1 SPI 0 Slave Select 2 SPI 0 SS 3-state SPI 1 Clock SPI 1 MOSI SPI 1 MISO SPI 1 Slave Select 0 SPI 1 Slave Select 1 SPI 1 Slave Select 2 SPI 1 SS 3-state

EMIO Signals Input Name (I)

EMIOSPI0SCLKI EMIOSPI0SI EMIOSPI0MI EMIOSPI0SSIN

Output Name (O)

EMIOSPI0SCLKO EMIOSPI0MO EMIOSPI0SO EMIOSPI0SSON0 EMIOSPI0SSON1 EMIOSPI0SSON2

3-state Name (O)

EMIOSPI0SCLKTN EMIOSPI0MOTN EMIOSPI0STN

EMIOSPI0SSNTN EMIOSPI1SCLKTN EMIOSPI1MOTN EMIOSPI1STN

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CAN Controller
18.1 Introduction
This chapter describes the architecture and features of the CAN controllers and the functions of the various registers in the design. There are two nearly identical CAN controllers in the PS that are independently operable. Defining the CAN protocol is outside the scope of this document, and knowledge of the specifications is assumed.

18.1.1 Features
CAN Controller features are summarized as follows: Compatible with the ISO 11898 -1, CAN 2.0A , and CAN 2.0B standards Standard (11-bit identifier) and extended (29-bit identifier) frames Bit rates up to 1 Mb/s Transmit message FIFO (TxFIFO) with a depth of 64 messages Transmit prioritization through one high-priority transmit buffer (TxHPB) Watermark interrupts for TxFIFO and RxFIFO Automatic re-transmission on errors or arbitration loss in normal mode Receive message FIFO (RxFIFO) with a depth of 64 messages Four Rx acceptance filters with enables, masks and IDs Loopback and snoop modes for diagnostic applications Maskable error and status interrupts 16-Bit time stamping for receive messages Readable Rx/Tx error counters

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18.1.2 System Viewpoint

The system viewpoint of the CAN controller is shown in Figure 18-1.
X-Ref Target - Figure 18-1

IRQ ID# {60, 83} Slave port CAN Controllers

Tx, Rx

MIO EMIO Routing Tx, Rx EMIO PL

Interconnect

APB

Tx, Rx
Control Registers

CAN{0, 1} CPU_1x clock CAN{0, 1} CPU_1x reset

MIO Pins Clock

External Clock Source

CAN{0, 1} REF clock

Clocking

Device Boundary
UG585_c18_01_071612

Figure 18-1:

CAN Controller System Viewpoint

18.1.3 Block Diagram

The high-level architecture of the CAN core is shown in Figure 18-2. The sub-modules are described in subsequent sections.
X-Ref Target - Figure 18-2

Object Layer - Data Buffer and Filtering APB Interface Data Write TX Storage Tx FIFO TX Priority Logic

Transfer Layer - Protocol Engine

Tx HPB

Bit Stream Processor CAN Tx

Register R/W

Configuration Registers Bit Timing Logic

CAN Rx

Data Read

Rx FIFO

Acceptance Filter

UG585_c18_02_021213

Figure 18-2:

CAN Controller Block Diagram

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Configuration Registers
The CAN Controller Configuration register defines the configuration registers. This module allows for read and write access to the registers through the APB interface. An overview of the CAN controller registers are shown in section 18.3.8 Register Overview.

Transmit and Receive Messages

Separate storage buffers exist for transmit (TxFIFO) and receive (RxFIFO) messages through a FIFO structure. Each buffer can store up to 64 messages. Once a message is written into the TxFIFO it takes a total delay of 2*(Tx Driver delay + Propagation delay + Rx Driver delay) to transmit over the CAN bus.

Tx High Priority Buffer

Each controller also has a transfer high priority buffer (TxHPB) provides storage for one transmit message. Messages written on this buffer have maximum transmit priority. They are queued for transmission immediately after the current transmission is complete, preempting any message in the TxFIFO.

Acceptance Filters
Acceptance filters sort incoming messages with the user-defined acceptance mask and ID registers to determine whether to store messages in the RxFIFO, or to acknowledge and discard them. Messages passed through acceptance filters are stored in the RxFIFO.

18.1.4 Notices
Restrictions
There is a single PS clock generator for both controllers. When the internal clock is used, it will be of the same clock frequency, but the clock to each controller can be individually enabled using the slcr register, see section 25.6.4 CAN Clocks. Also, either or both controllers can be clocked from an external source via an MIO pin, see section 18.4.1 Clocks. It is recommended that a BRPR value of greater than 2 be used.

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18.2 Functional Description

Each controller is independently configured and controlled. There are two CAN controllers (CANx; where x = 0 or 1). The register name preface for the CAN registers is 'can' (e.g., can.MSR register).

18.2.1 Controller Modes

The CAN controller supports the following modes of operation: Configuration Normal Sleep Loop Back Snoop mode

Configuration Mode
The CAN controller enters the Configuration mode when any of the following actions are performed, regardless of the operation mode: Writing a 0 to the CEN bit in the SRR register. Writing a 1 to the SRST bit in the SRR register. The core enters the Configuration mode immediately following the software reset. Driving a 0 on the reset input. The core continues to be in reset as long as reset is 0 . The core enters Configuration mode after reset is negated to 1 .

Normal Mode
Normal mode transmits and receives messages on the Tx and Rx I/O signals as defined by the Bosch and IEEE specifications.

Sleep Mode
Sleep mode can be used to save a small amount of power during idle times. When in sleep mode, the controller can transition to normal mode or configuration mode. In sleep mode: When another node transmits a message, the controller receives the message and exits sleep mode. If there is a new Tx request then the hardware switches the controller to normal mode and the controller services the request(s). An interrupt can be generated when the controller enters sleep mode. An interrupt can be generated when the controller wakes up.

Sleep mode is exited by the hardware when there is CAN bus activity or a request in either TxFIFO or

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TxHPB. When the controller exits sleep mode, can.MSR[SLEEP] is set to 0 by the hardware and an interrupt can be generated. The CAN controller enters Sleep mode from Configuration mode when the LBACK bit in MSR is 0 , the SLEEP bit in MSR is 1 , and the CEN bit in SRR is 1 . The CAN controller enters Sleep mode only when there are no pending transmission requests from either the TX FIFO or the TX High Priority Buffer. The CAN controller enters Sleep mode from Normal mode only when the SLEEP bit is 1, the CAN bus is idle, and there are no pending transmission requests from either the TX FIFO or TX High Priority Buffer. When another node transmits a message, the CAN controller receives the transmitted message and exits Sleep mode. When the controller is in Sleep mode, if there are new transmission requests from either the TX FIFO or the TX High Priority Buffer, these requests are serviced, and the CAN controller exits Sleep mode. Interrupts are generated when the CAN controller enters Sleep mode or wakes up from Sleep mode. From sleep mode, the CAN controller can enter either the Configuration or Normal modes.

Loop Back Mode (Diagnostics)

Loop back mode is used for diagnostic purposes. When in loop back mode, the controller must only be programmed to enter configuration mode or issue reset. In loop back mode: The controller transmits a recessive bitstream onto the CAN_TX bus signal. Tx messages are internally looped back to the Rx line and are acknowledged. Tx messages are not sent on the CAN_TX bus signal. The controller receives all message that it transmits. The controller does not receive any messages transmitted by other CAN nodes.

Snoop Mode (Diagnostics)

Snoop mode is used for diagnostic purposes. When in snoop mode, the controller must only be programmed to enter configuration mode or be held in reset. In snoop mode: The controller transmits a recessive bitstream onto the CAN bus. The controller does not participate in normal bus communication. The controller receives messages that are transmitted by other CAN nodes. Software can program acceptance filters to dynamically enable/disable and change criteria. Error counters are disabled and cleared to 0 . Reads to error counter registers return 0 .

Mode Transitions
The supported mode transitions are shown in Figure 18-3. The transitions are primarily controlled by the resets, the CEN bit, the MSR register settings, and a hardware wake up mechanism. To enter normal mode from configuration mode: Clear can.MSR[LBACK, SNOOP, SLEEP] = 0

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Set can.SRR[CEN] = 1

To enter sleep mode from normal mode (interrupt generated): Set can.MSR[SLEEP] = 1

Events that cause the controller to exit sleep mode (interrupt generated): Rx signal activity (hardware sets can.MSR[SLEEP] = 0 ) TxFIFO or TxHPB activity (hardware sets can.MSR[SLEEP] = 0 ) Software writes 0 to can.MSR[SLEEP]
Reset:
slcr.CAN_RST_CTRL[CANx_CPU1x_RST] =1 OR can.SRR[SRST] = 1 (Self-clearing) Reset Hardware Forces can.SRR[CEN] = 0 Reset

X-Ref Target - Figure 18-3

slcr.CAN_RST_CTRL[CANx_CPU1x_RST] = 0

Configuration can.SRR[CEN] = 0

Snoop Normal Sleep Loop Back Diagnostics

UG585_c18_05_021113

Figure 18-3:

CAN Operating Mode Transitions

Mode Settings
Table 18-1 defines the CAN controller modes of operation and corresponding control and status bits. Table 18-1:
.

CAN Controller Modes of Operation

Software Reset Mode Select Register Status Register (SR) CAN Register (can.SRR) (MSR) (Read/Write bits) (Read Only bits) CPU_1x SRST CEN PS Reset (CAN (CAN LBACK SLEEP SNOOP CONFIG LBACK SLEEP NORMAL SNOOP (slcr) Reset) Enable)
1 0 X 1 X X X X X X X X 1 1 0 0 0 0 0 0 0 0

Operational Mode
Reset Reset

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Table 18-1:

CAN Controller Modes of Operation

Software Reset Mode Select Register Status Register (SR) CAN Register (can.SRR) (MSR) (Read/Write bits) (Read Only bits) CPU_1x SRST CEN PS Reset (CAN (CAN LBACK SLEEP SNOOP CONFIG LBACK SLEEP NORMAL SNOOP (slcr) Reset) Enable)
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 X 1 0 0 0 X X 1 0 0 X X 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0

Operational Mode
Configuration Loop back Sleep Snoop Normal

18.2.2 Message Format

The same message format is used for RxFIFO and Tx (FIFO and HPB). Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. The message words, fields and structure are shown in Table 18-2. The details of each field are in Table 18-3. Table 18-2: CAN Message Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Length Code [DLCR] Data Word 1 [DW1R] Data Word 2 [DW2R] DLC[3:0] Reserved Time Stamp (Rx only, Reserved for Tx) DB0[7:0] DB1[7:0] DB2[7:0] DB3[7:0] DB4[7:0] DB5[7:0] DB6[7:0] DB7[7:0]

Bit Field Details

Writes
If a bit field or data byte is not required, then write zeros. Software should write the default values shown in Table 18-3 for unused functions.

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RTR

ID[28:18]

STR/RTR IDE

Message Identifier [IDR}

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Reads
Data starts at byte 0 and continues for the number of counts in DLC. Software should read both data words, but the only valid bytes are determined by DLC. Table 18-3 provides bit descriptions for the identifier word bits, the DLC word bits, and data word 1 and data word 2 bits. Table 18-3: Bits
Identifier Word
Standard Message ID The identifier portion for a standard frame is 11 bits. These bits indicate the standard frame ID. This field is valid for both standard and extended frames. Substitute Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for standard frames. For extended frames this bit is 1 . 1 : Indicates that the message frame is a Remote Frame. 0 : Indicates that the message frame is a Data Frame. Identifier Extension This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1 : Indicates the use of an extended message identifier. 0 : Indicates the use of a standard message identifier. Extended Message ID This field indicates the extended identifier. Valid only for extended frames. For standard frames, reads from this field return 0 s. For Standard frames, writes to this field should be 0 s. Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for extended frames. 1 : Indicates the message object is a remote frame. 0 : Indicates the message object is a data frame. For standard frames, reads from this bit returns 0. For standard frames, writes to this bit should be 0.

CAN Message Word Register Bit Fields Name Default Value Description

31:21

ID[28:18]

20

SRR/RTR

19

IDE

18:1

ID[17:0]

RTR

DLC Word
Data Length Code This is the data length portion of the control field of the CAN frame. This indicates the number valid data bytes (0 to 8) that are in the Data Word 1 and Data Word 2 registers.

31-28

DLC

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Table 18-3: Bits

27-0

CAN Message Word Register Bit Fields (Contd) Name

Reserved

Default Value
0

Description
Reads from this field return 0 s. Writes to this field should be 0s.

Data Word 1
DW1R[31:24] DW1R[23:16] DW1R[15:8] DW1R[7:0] DB0[7:0] DB1[7:0] DB2[7:0] DB3[7:0] 0 0 0 0 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3

Data Word 2
DW2R[31:24] DW2R[23:16] DW2R[15:8] DW2R[7:0] DB4[7:0] DB5[7:0] D6[7:0] DB7[7:0] 0 0 0 0 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7

18.2.3 Message Buffering

Rx Messages
The RxFIFO can store up to 64 Rx CAN messages that are received and optionally filtered. Rx messages that pass any of the acceptance filters are stored in the RxFIFO. When no acceptance filter has been selected, all received messages are stored in the RxFIFO. Software reads these messages as described in 18.3.7 Read Messages from RxFIFO. A timestamp is added to each successfully stored Rx message. A free running 16-bit counter is clocked using the CAN bit time clock. The rules for time stamping an Rx message are: The counter rolls over. There is no status bit to indicate that the roll over condition occurred. The timestamp included when a Rx message is successfully collected. The sampling of the counter takes place at the last bit of EOF. The counter is cleared when CEN= 0 or by software writing a 1 to the can.TCR register.

Software must read all four registers of an Rx message in the RxFIFO, regardless of how many data bytes are in the message. The first word is read using the RXFIFO_ID register and contains the identifier of the received message (IDR). The second word is read using the RXFIFO_DLC register and contains the 16-bit timestamp and data length code (DLC) field. The third and fourth words contain data word 1 (DW1R) and data word 2 (DW2R). Writes to the RxFIFO registers are ignored. Read data from an empty RxFIFO are invalid and may generate an interrupt. The messages in the RxFIFO are retained even if the CAN controller enters Bus off state or Configuration mode.

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Tx Messages
The controller has a configurable TxFIFO that software can use buffer up to 64 Tx CAN messages. The controller also has a high priority transmit buffer (Tx HPB), with storage for one message. When a higher priority message needs to be sent, software writes the message to the high priority transmit buffer when it is available. The message in the TxHPB has higher priority over messages in the TxFIFO. When arbitration loss or errors occur during the transmission of a message, the controller tries to retransmit the message. No subsequent message, even a newer, higher priority message is transmitted until the original message is transmitted without errors or arbitration loss. The controller transmits the message starting with bit 31 of the IDR word, see table 18-2, CAN Message Format. After the identifier word is transmitted, the DLCR word is transmitted. This is followed by the data bytes in this order: DB0, DB1, ... DB7. The last bit in the data portion of the message is DB7, bit 0. Refer to Table 18-2. The status bit, can.ISR[TXOK] is set = 1 after the controller successfully transmits a message from either the TxFIFO or TxHPB. The messages in the TxFIFO and TxHPB are retained even if the CAN controller enters Bus off state or Configuration mode. The message format is described in 18.2.2 Message Format.

Reads from RxFIFO

All 16 bytes must be read from the RxFIFO to receive the complete message. The first word read (4 bytes) returns the identifier of the received message (IDR). The second read returns the 16-bit receive time stamp and data length code (DLC) field of the received message (DLCR). The third read returns data word 1 (DW1R), and the fourth read returns data word 2 (DW2R). A free running 16-bit counter provides a time stamp relative to the time the message was successfully received. All four words must be read for each message, even if the message contains less than eight data bytes. Write transactions to the RxFIFO are ignored. Reads from an empty RxFIFO return invalid data and generates an Rx Underflow interrupt.

Rx and Tx Error Counters

When an Rx or Tx error occurs, the associated error counters in the protocol engine (see section 18.2.6 Protocol Engine) are incremented. The two error counters are 8 bits wide and are read using the read-only can.ECR register, bit fields REC and TEC. The Rx and Tx counters are reset when any the these situations occur: After a 1 is written to can.SRR[SRST] field = 1 . This bit write is self-clearing. Anytime can.SRR[CEN] = 0 (configuration mode). When the controller enters Bus Off state.

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18.2.4 Interrupts
Each CAN controller has a single interrupt signal to the GIC interrupt controller. CAN 0 connects to IRQ ID#60 and CAN 1 connects to ID #83. The source of an interrupt can be grouped into one of the following: TxFIFO and TxHPB RxFIFO Message passing and arbitration Sleep mode and bus off

Enable and disable interrupts using the can.IER register. Check the raw status of the interrupt using can.ISR. Clear interrupts by writing a 1 to can.ICR. Some interrupt sources have an additional method to clear the interrupt as shown in Table 18-4.

List of Interrupts
All of the CAN interrupts are sticky; that is, once the hardware sets them they stay set until cleared by software. CAN status and interrupts are identified in Table 18-4. Table 18-4: List of CAN Status and Interrupts Bit Number
13 14 2 3 12 7 6 5 4 1 8 0 10

Name
TxFIFO Watermark TxFIFO Empty TxFIFO Full TxHPB Full RxFIFO Watermark RxFIFO Not Empty RxFIFO overflow RxFIFO underflow Message Rx Message Tx Message Error Arbitration Lost Enter Sleep Mode

Additional Method to Clear Interrupt

none none none none none none Write 0 to can.SRR[CEN] none Write 0 to can.SRR[CEN] Write 0 to can.SRR[CEN] Write 0 to can.SRR[CEN] none Write 0 to can.SRR[CEN] Empty indicator. Full indicator.

Usage
Operational threshold.

This status indicates if the buffer is in-use and should not be written. Operational threshold. One or more messages can be read. FIFO was full and message(s) likely lost. Programming error, message read from RxFIFO when no messages were there.

Any of the five CAN errors in the Error Status register.

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Table 18-4:

List of CAN Status and Interrupts Bit Number

11 9

Name
Exit Sleep Mode Bus Off

Additional Method to Clear Interrupt

Write 0 to can.SRR[CEN] Write 0 to can.SRR[CEN]

Usage
Controller can go to normal or configuration mode.

RxFIFO and TxFIFO Interrupts

The FIFO watermark levels and all the FIFO interrupts are illustrated in Figure 18-4, CAN RxFIFO and TxFIFO Watermark Interrupts.
X-Ref Target - Figure 18-4

RxFIFO (64 messages)

FIFO is Filling Overflow Interrupt can.ISR[6] Watermark Interrupt can.ISR[12] Interrupt bit RXFWMFLL is asserted when the number of messages in RxFIFO exceeds the can.WIR[FW, bits 5:0] threshold. Underflow Interrupt can.ISR[5]

TxFIFO (64 messages)

FIFO is Emptying Full Interrupt can.ISR[2]

Not Empty Interrupt can.ISR[7]

Watermark Interrupt can.ISR[13] Empty Interrupt can.ISR[14]

Interrupt bit TXFWMEMP is asserted when the number of messages in TxFIFO is less than the can.WIR[EW, bits 13:8] threshold.

UG585_c18_06_071012

Figure 18-4:

CAN RxFIFO and TxFIFO Watermark Interrupts

Example: Program RxFIFO Watermark Interrupt (12)

The following steps can be used to setup and control the RxFIFO watermark interrupt. See Figure 18-4. The watermark status and control interrupts are described in Protocol Engine, page 522. 1. 2. 3. 4. 5. Disable RxFIFO watermark interrupt . Write a 0 to can.IER[12]. Program RxFIFO full watermark level . Write to can.WIR[FW]. Clear RxFIFO watermark interrupt . Write a 1 to can.ICR[12]. Read RxFIFO watermark status . Read can.ISR[12]. Enable RxFIFO watermark interrupt . Write a 1 to can.IER[12].

Example: Program TxFIFO Watermark Interrupt (13)

The following steps can be used to setup and control the TxFIFO watermark interrupt. See Figure 18-4. The watermark status and control interrupts are described in Protocol Engine, page 522. 1. 2. Disable TxFIFO watermark interrupt. Write a 0 to can.IER[13]. Program TxFIFO empty watermark level . Write to can.WIR[EW].

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3. 4. 5.

Clear TxFIFO watermark interrupt . Write a 1 to can.ICR[13]. Read TxFIFO watermark status . Read can.ISR[13]. Enable TxFIFO watermark interrupt. Write a 1 to can.IER[13].

Example: Program TxFIFO Empty Interrupt (14)

The following steps can be used to control the TxFIFO empty interrupt: 1. 2. 3. 4. Disable TxFIFO empty interrupt. Write a 1 to can.IER[14]. Clear TxFIFO empty interrupt . Write a 1 to can.ICR[14]. Enable TxFIFO empty interrupt. Write a 1 to can.IER[14]. Read TxFIFO empty status . Read can.ISR[14]. It indicates the status whether TxFIFO is empty or not.

18.2.5 Rx Message Filtering

To filter Rx messages, configure and enable up to four acceptance filters with acceptance mask and ID registers to determine whether to store messages in the RxFIFO, or to acknowledge and discard them. Acceptance filtering is performed in the following sequence: 1. 2. 3. 4. 5. The incoming identifier is masked with the bits in the Acceptance Filter Mask register. The Acceptance Filter ID register is also masked with the bits in the Acceptance Filter Mask register. Both resulting values are compared. If both these values are equal, then the message is stored in the RxFIFO. Acceptance filtering is processed by each of the defined filters. If the incoming identifier passes through any acceptance filter, then the message is stored in the RxFIFO.

Acceptance Filter Enable

The Acceptance Filter register (AFR) defines which acceptance filters to use. It includes four enable bits that correspond to the four acceptance filters. Each Acceptance Filter ID register (AFIR) and Acceptance Filter Mask register (AFMR) pair is associated with a use acceptance filter (UAF) bit. When the UAF bit is 1 , the corresponding acceptance filter pair is used for acceptance filtering. When the UAF bit is 0 , the corresponding acceptance filter pair is not used for acceptance filtering. To modify an acceptance filter pair in normal mode, the corresponding UAF bit in this register must first be set to 0 . After the acceptance filter is modified, the corresponding UAF bit must be set to 1 for the filter to be enabled. The UAF bits in the can.AFR register enable the Rx acceptance filters: If all UAF bits are set to 0 , then all received messages are stored in the RxFIFO. If the UAF bits are changed from a 1 to 0 during reception of a CAN message, the message will not be stored in the RxFIFO.

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If any of the enabled filters (up to four) satisfy this equation, then the Rx message is stored in the RxFIFO: If (AFMR & Message_ID) == (AFMR & AFIR) then Capture Message Each acceptance filter is independently enabled. The filters are selected by the can.AFR register. Set can.AFR[UAF4] = 1 to enable AFMR4 and AFID4. Set can.AFR[UAF3] = 1 to enable AFMR3 and AFID3. Set can.AFR[UAF2] = 1 to enable AFMR2 and AFID2. Set can.AFR[UAF1] = 1 to enable AFMR1 and AFID1.

If all can.AFR[UAFx] bits are set = 0 , then all received messages are stored in the RxFIFO. The UAF bits are sampled by the hardware at the start of an incoming message.

Acceptance Filter Mask

The Acceptance Filter Mask registers (AFMR) contain mask bits used for acceptance filtering. The incoming message identifier portion of a message frame is compared with the message identifier stored in the Acceptance Filter ID register. The mask bits define which identifier bits stored in the Acceptance Filter ID register are compared to the incoming message identifier. There are four AFMRs. These registers are stored in a memory. Reads from AFMRs return 'X's if the memory is uninitialized. Asserting a software reset or hardware reset does not clear register contents. These registers can be read from and written to. These registers are written to only when the corresponding UAF bits in the can.AFR register are 0 and the ACFBSY bit in the can.SR register is 0. The following conditions govern AFMRs: Extended Frames Standard Frames All bit fields (AMID [28:18], AMSRR, AMIDE, AMID [17:0] and AMRTR) need to be defined. Only AMID [28:18], AMSRR and AMIDE need to be defined. AMID [17:0] and AMRTR should be written as 0 .

Acceptance Filter Identifier

The Acceptance Filter ID registers (AFIR) contain Identifier bits, which are used for acceptance filtering. There are four Acceptance Filter ID registers. These registers can be read from and written to. These registers should be written to only when the corresponding UAF bits in the SR are 0 and the ACFBSY bit in the SR is 0 . The following conditions govern the use of the AFIRs: Extended Frames Standard Frames All the bit fields (AIID [28..18], AISRR, AIIDE, AIID [17:0] and AIRTR) must be defined. Only AIID [28:18], AISRR and AIIDE need to be defined. AIID [17:0] and AIRTR should be written with 0 .

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The user must ensure proper programming of the IDE bit for standard and extended frames. If the user sets the IDE bit in AMIR to 0, then it is considered to be a standard frame ID check only.

Example: Program Acceptance Filter

Each acceptance filter has its own mask, can.AFMR{1,2,3,4}, and ID register, can.AFIR{1,2,3,4}. 1. 2. 3. 4. 5. Disable acceptance filters . Write 0 to the can.AFR register. Wait for filter to be not busy. Poll on can.SR[ACFBSY] for 0 . Write a filter mask and ID. Write to a pair of AFMR and AFIR registers (refer to the example below). Write additional filter masks and IDs. Go to step 2. Enable one or more Filters . To enable all filters, write 0x0000_000F to the can.AFR register.

Program the AFMR and AFIR Registers

The valid fields for sending Tx messages to the controller are summarized in Table 18-5. These fields are described in section 18.2.2 Message Format. Table 18-5: CAN Message Identifier Register (IDR) Fields ID[28:18] Standard Frame Extended Frame
Valid Valid

STR/RTR
Valid Valid

IDE
Valid Valid

ID[17:0]
Ignored Valid

RTR
Ignored Valid

In the AFMR mask register, enable (unmask) the compare functions for each field for the incoming Rx CAN message by writing a 1 to the bit field. In the AFIR register, write the values that are to be compared to the in-coming Tx CAN message.

Example: Program the AFMR and AFIR for Standard Frames

This example sets up the acceptance filter for standard frames. The frame ID number is shown to be 0x5DF, but could be set to desired value for the application. 1. Configure filter mask for standard frames . Write 0xFFF8_0000 to the can.AFMR register: a. c. 2. Enable the compare for the standard message ID, [AMIDE] = 1 . Enable the compare for substitute remote transmission request, [AMSRR] = 1 . b. Compare all bits in the standard message ID, [AMIDH] = 0x7FF. d. Zero-out the extended frame bits, [AMIDL, AMRTR] = 0 . Configure filter ID for standard frames . Write 0xABC0_0000 to the can.AFIR register: a. c. Select the standard frame message mode, [AIIDE] = 0. Disable substitute remote transmission request, [AISRR] = 0 . b. Program the standard message ID, [AIIDH] = 0x55E . d. Zero-out extended frame bits, [AIIDL, AIRTR] = 0 .

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Example: Program the AFMR and AFIR for Extended Frames

This example setups up the acceptance filter for extended frames. The Frame ID number is shown to be 0x5DF, but could be set to desired value for the application. 1. Configure filter mask for extended frames . Write 0xFFFF_FFFF to the can.AFMR register: a. c. e. 2. a. c. e. Enable the substitute remote transmission request mask for frame, [AMSRR] = 1 . Enable the extended frame, [AIIDE] = 1. Remote transmission request bit for extended frame, [AIRTR] = 1. Standard ID, [AIIDH] = 0x55E . Select standard/extended frame, [AIIDE] = 1 . Remote transmission request bit for extended frame, [AIRTR] = 0 b. Compare all bits in the compare for the standard message ID, [AMIDH] = 0x7FF. d. Extended ID, [AIIDL] = 0x3FFFF Configure filter ID for extended frames . Write 0xABDF_9BDE to the can.AFIR register: b. Remote transmission request bit for standard frame, [AISRR] = 1 . d. Extended ID, [AIIDL] = 3CDEF.

18.2.6 Protocol Engine

The CAN protocol engine consists primarily of the bit timing logic (BTL) and the bitstream processor (BSP) modules. Figure 18-5 shows a block diagram of the CAN protocol engine.
X-Ref Target - Figure 18-5

Protocol Engine - Data Layer Physical Layer

TX CAN BUS

Buffer and Filter TX Message

TX Bit Control

Bit Timing Logic

Control / Status

PHY Bitstream Processor

RX Bit Sampling Clock RX

RX Message

Device Boundary

Reference Clock

Clock Prescalar

UG585_c18_03_101012

Figure 18-5:

CAN Protocol Engine

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Rx/Tx Bit Timing Logic

The primary functions of the bit timing logic (BTL) module include: Generate the Rx sampling clock for the bitstream processor (BSP) Synchronize the CAN controller to CAN traffic on the bus Sample the bus and extracting the data stream from the bus during reception Insert the transmit bit stream onto the bus during transmission

The nominal length of the bit time clock period is based on the CAN_REF_CLK clock frequency, the baud rate generator divider (can.BRPR register) and the segment lengths (can.BTR register). The bit timing logic module manages the re-synchronization function for CAN using the sync width parameter in the can.BTR[SJW] bit field. The CAN bit timing is shown in Figure 18-6.
X-Ref Target - Figure 18-6

Nominal Bit Time

TS1

TS2

Sync Segment

Propagation Segment

Phase Segment 1

Phase Segment 2

.
Time Quanta Clock (TQ_CLK)

.
Sample Point

UG585_c18_04_073012

Figure 18-6:

CAN Bit Time

Sync Segment count always equals one time quanta period. The TS 1 and TS 2 period counts are programmable using the can.BTR[TS1, TS2] bit fields. These registers are written when the controller is in Configuration mode. The width of the propagation segment (PROP_SEG) must be less than the actual propagation delay.

Time Quanta Clock

The time quanta clock (TQ_CLK) is derived from the controller reference clock (CAN_REF_CLK) divided by the baud rate prescaler (BRP). tTQ_CLK = tCAN_REF_CLK * (can.BRPR[BRP] + 1) freqTQ_CLK = freqCAN_REF_CLK / (can.BRPR[BRP] + 1) tSYNC_SEGMENT = 1 * tTQ_CLK tTIME_SEGMENT1 = tTQ_CLK * (can.BPR[TS1] + 1) tTIME_SEGMENT2 = tTQ_CLK * (can.BPR[TS2] + 1)

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tBIT_RATE = tSYNC_SEGMENT + tTIME_SEGMENT1 + tTIME_SEGMENT2 freqBIT_RATE = freqCAN_REF_CLK / (3 + can.BPR[TS1] + can.BPR[TS2])

Note: A given bit-rate can be achieved with several bit-time configurations, but values should be

selected after careful consideration of oscillator tolerances and CAN propagation delays. For more information on CAN bit-time register settings, refer to the CAN 2.0A, CAN 2.0B, and ISO 11898-1 specifications.

Bitstream Processor
The bitstream processor (BSP) module performs several functions while sending and receiving CAN messages. The BSP obtains a message for transmission from either the TxFIFO or the TxHPB and performs the following functions before passing the bitstream to the BTL. Serializing the message Inserting stuff bits, CRC bits, and other protocol defined fields during transmission

During transmission the BSP simultaneously monitors Rx data and performs bus arbitration tasks. It then transmits the complete frame when arbitration is won, and retrying when arbitration is lost. During reception the BSP removes stuff bits, CRC bits, and other protocol fields from the received bitstream. The BSP state machine also analyses bus traffic during transmission and reception for Form, CRC, ACK, Stuff, and Bit violations. The state machine then performs error signaling and error confinement tasks. The CAN controller does not voluntarily generate overload frames but does respond to overload flags detected on the bus. This module determines the error state of the CAN controller: error active, error passive or bus-off. When Tx or Rx errors are observed on the bus, the BSP updates the transmit and receive error counters according to the rules defined in the CAN 2.0 A, CAN 2.0 B and ISO 11898-1 standards. Based on the values of these counters, the error state of the CAN controller is updated by the BSP.

18.2.7 CAN0-to-CAN1 Connection

The I/O signals of the two CAN controllers in the PS can be connected together. In this mode, the RX signal of one CAN controller is connected to the TX signal of the other controller. These connections are enabled using the slcr.MIO_LOOPBACK [CAN0_LOOP_CAN1] bit.

18.3 Programming Guide

18.3.1 Overview
The controller has several operating modes and different ways to receive and transmit messages. The low-level functions were described in 18.2 Functional Description. The system-level operations are described in section 18.4 System Functions.

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All the controller registers are listed in Table 18-6 and are described in detail in Appendix B, Register Details.

18.3.2 Configuration Mode State

The CAN controller enters configuration mode, irrespective of the operation mode, when any of these actions are performed: Writing a 0 to the CEN bit in the SRR register. Writing a 1 to the SRST bit in the SRR register. The controller enters Configuration mode immediately following the software reset. Driving a 1 on the Reset input controlled via SLCR. The controller continues to be in reset as long as Reset is 1 . The controller enters configuration mode after Reset is negated to 0 .

In configuration mode the following apply: The CAN controller loses synchronization with the CAN bus and drives a constant recessive bit on the bus line. The Error Count register (ECR) is reset. The Error Status register (ESR) is reset. The Bit Timing register (BTR) and Baud Rate Prescaler register (BRPR) can be modified. The CAN controller does not receive any new messages. The CAN controller does not transmit any messages. Messages in the TxFIFO and the TxHPB are appended. These packets are sent when normal operation is resumed. Reads from the RxFIFO can be performed. Writes to the TxFIFO and TxHPB can be performed (provided the SNOOP bit is not set). Interrupt Status register bits ARBLST, TXOK, RXOK, RXOFLW, ERROR, BSOFF, SLP, and WKUP are be cleared. Interrupt Status register bits RXNEMP and RXUFLW can be set due to read operations to the RxFIFO. Interrupt Status register bits TXBFLL and TXFLL, and Status register bits TXBFLL and TXFLL can be set due to write operations to the TX HPB and TX FIFO, respectively. Interrupts are generated if the corresponding bits in the Interrupt Enable register (IER) are 1 . All Configuration registers are accessible.

When in configuration mode, the CAN controller stays in this mode until the CEN bit in the SRR register is set to 1 . After the CEN bit is set to 1 the CAN controller waits for a sequence of 11 recessive bits before exiting configuration mode. The CAN controller enters normal, loop back, snoop, or sleep modes from configuration mode, depending on the LBACK, SNOOP, and SLEEP bits in the MSR register.

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18.3.3 Start-up Controller

The controller can operate in Normal, Sleep, Snoop and Loop Back modes. Refer to Figure 18-3 for supported transitions. On start-up the controller clocks and configuration bits are programmed. Then the operating mode is selected and enabled.

Example: Start-up Sequence

1. 2. 3. 4. 5. 6. 7. 8. 9. Configure clocks . Refer to section 18.4.1 Clocks. Configure Tx/Rx signals . Refer to section 18.5.1 MIO Programming. Wait for configuration mode. Read can.SR[CONFIG] until it equals 1. Reset the controller. The controller comes up in Configuration mode. Refer to section 18.4.2 Resets. Program the bit sampling clock . Refer to section Rx/Tx Bit Timing Logic. Program the interrupts, as needed . Refer to section 18.2.4 Interrupts. Program the acceptance filters . Refer to section 18.2.5 Rx Message Filtering. Select operating mode . Normal, Sleep, Snoop or LoopBack. Refer to section 18.3.4 Change Operating Mode. Enable the controller. Write a 1 to can.SRR[CEN].

18.3.4 Change Operating Mode

Example: Normal to Sleep Mode
Sleep mode is entered from Normal Mode when the following conditions are met: 1. 2. 3. Select Sleep Mode . Write 1 to can.MSR[SLEEP]. Wait for CAN bus to go idle . Wait for all TxFIFO and TxHPB messages to be transmitted .

care.

Note: In normal mode, can.MSR[LBACK] = 0 and can.SSR[CEN] = 1. Also, can.MSR[SNOOP] = don't

Example: Configuration to Sleep Mode

Sleep mode is entered from Configuration Mode when the following conditions are met: 1. 2. 3. Select Sleep Mode . Write 1 to can.MSR[SLEEP] and write 0 to can.MSR[LBACK]. Enable the controller. Write 1 to can.SSR[CEN]. Wait for TxFIFO or TxHPB to empty.

Note: In configuration mode, can.MSR[SNOOP] = don't care.

Sleep mode is exited when I/O bus activity is detected or when software writes a message to either the TxFIFO or the TxHPB. When the controller exits sleep mode, can.MSR[SLEEP] is set to 0 by the hardware and an interrupt can be generated.

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18.3.5 Write Messages to TxFIFO

With either option, can.SR[TXFLL] can be polled before writing a message. All messages written to the TxFIFO should follow the format defined in Message Structure.

Example: Write Message to TxFIFO Using Polling Method

1. 2. Poll the TxFIFO status. Read can.SR[TXFLL] for 0 and can.SR[TXFEMP] for 1 and then message can be written into the TxFIFO. Write message to TxFIFO. Write to all four data registers (can.TXFIFO_ID, can.TXFIFO_DLC, can.TXFIFO_DATA1, and can.TXFIFO_DATA2).

Example: Write Message to TxFIFO Using Interrupt Method

In interrupt mode, writes can continue until can.ISR[TXFLL] generates an interrupt. Messages can be continuously written to the TxFIFO until the TxFIFO is full. When the TxFIFO is full the can.ISR[TXFLL] and can.SR[TXFLL] are set to 1 . When the TxFIFO is empty, can.ISR[TXFEMP] is set to 1 .

18.3.6 Write Messages to TxHPB

All messages written to the TxHPB use the polling method. The format should follow section 18.2.2 Message Format.

Example: Write Message to TxHPB

1. 2. Poll the TxHPB status . Read can.SR[TXBFLL] until it equals 0 and then write the message into the TxHPB. Write message to TxHPB . Write to all four data registers (can.TXHPB_ID, can.TXHPB_DLC, can.TXHPB_DATA1, and can.TXHPB_DATA2).

18.3.7 Read Messages from RxFIFO

Whenever a new message is received and put into the RxFIFO, the can.ISR[RXNEMP] and can.ISR[RXOK] bits are set to 1 . If the RxFIFO is empty when the message is read, then the can.ISR[RXUFLW] is also set to 1.

Example: Read Message from RxFIFO Using Polling Method

1. 2. 3. Poll the RxFIFO status . Read can.ISR[RXOK] or can.ISR[RXNEMP] register until a message is received. Proceed to step 2 when a bit is set. Read message from the RxFIFO. Read all four of the registers (can.RXFIFO_ID, can.RXFIFO_DLC, can.RXFIFO_DATA1, can.RXFIFO_DATA2). Determine if more messages are in the RxFIFO. Read can.ISR[RXNEMP].

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Example: Read Message from RxFIFO Using Interrupt Method

The can.ISR[RXOK] and/or can.ISR[RXNEMP] bit fields can generate the interrupt. 1. 2. 3. 4. 5. 6. 7. Program RxFIFO watermark level interrupt . Write to can.WIR[FW] to set watermark can.ISR[RXFWMFLL] interrupt. Proceed to step 3 when an interrupt is received . Wait until a message is received. Read can.ISR[RXOK] or can.ISR[RXFWMFLL]. Read message from the RxFIFO. Read all four of the registers (can.RXFIFO_ID, can.RXFIFO_DLC, can.RXFIFO_DATA1, can.RXFIFO_DATA2). Determine if RxFIFO is not empty. Read can.ISR[RXNEMP]. Repeat until the RxFIFO is empty. Clear the interrupt .

18.3.8 Register Overview

The control and status registers are listed in see Table 18-6. Each of these registers is 32-bits wide. Any read operations to reserved bits or bits that are not used return 0 . A 0 should be written to reserved bits and bit fields not used. Writes to reserved locations are ignored. Table 18-6: CAN Register Overview Function
Configuration and Control

Register Names (CAN registers, except where noted)

SRR MSR BRPR BTR ECR TCR ISR IER ICR WIR ECR ESR SR TXFIFO_ID TXFIFO_DLC TXFIFO_DATA1 TXFIFO_DATA2 TXHPB_ID TXHPB_DLC TXHPB_DATA1 TXHPB_DATA2

Overview
Enable/disable and reset the controller. Setup baud rate and timing. Clear timestamp counter.

Interrupt Processing

Enable/disable the interrupt detection, mark interrupt sent to the interrupt controller, read raw interrupt status. Inform about the status of the controller.

Status

Transmit FIFO

Write message to be transmitted.

Transmit High Priority Buffer

Store one high priority transmit message.

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Table 18-6:

CAN Register Overview (Contd) Function Register Names (CAN registers, except where noted)
RXFIFO_ID RXFIFO_DLC RXFIFO_DATA1 RXFIFO_DATA2 AFR AFMR[4:1] AFIR[4:1] slcr.CAN_CLK_CTRL slcr.CAN_MIOCLK_CTRL slcr.CAN_RST_CTRL

Overview
Read received message.

Receive FIFO

Acceptance Filter

Configure and control the four acceptance filters. A controller reset and clock control.

System level

18.4 System Functions

18.4.1 Clocks
The controller and I/O interface are driven by the reference clock (CANx_REF_CLK). The controller's interconnect also requires an APB interface clock. The APB interconnect clock (CPU_1x) always comes from the PS clock subsystem. The reference clock normally comes from the PS clock subsystem, but it can alternatively be driven by an external clock source via any available MIO pin. The reference clock is used by the protocol engine, the baud rate generator, and the datapath. The controllers share the same reference clock frequency from the PS clock subsystem. If the reference clock is from an MIO pin, then the frequencies can be different.

CPU_1x Clock
Refer to Chapter 25, Clocks, for general clock programming information. The CPU_1x clock runs asynchronous to the CAN reference clock.

Reference Clock
CAN_REF_CLK is normally sourced from the PS clock subsystem, but it can alternatively be driven by an external clock source via an MIO pin. Internally, the PS has three PLLs and two clock divider pairs. The clock source choice, PS clock subsystem or external MIO pin, is controlled by the CAN_MIOCLK_CTRL register. The CAN clocks in the PS are controlled by slcr.CAN_CLK_CTRL. The generation of the CAN reference clock by the PS is described in section 25.6.4 CAN Clocks. There is one clock generator in the PS for both CAN controllers. If an MIO pins is used instead, the selected MIO_PIN Mux register is programmed as an input.

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Example: Configure and Route Internal Clock for Reference Clock

Configure the clock and disable MIO path. Assume the PLL is operating at 1000 MHz and the required CAN reference clock is 24 MHz (23.8095 MHz). 1. Program the clock subsystem. Write 0x0030_0E03 to the slcr.CAN_CLK_CTRL register: a. Enable both CAN reference clocks. b. Divide the I/O PLL clock by 42 (0x02A ): DIVISOR0= 0x0E and DIVISOR1= 0x03 used by both controllers. 2. Disable the MIO path . Write 0x0000_0000 to the slcr.CAN_MIOCLK_CTRL register to select the clock from the internal clock subsystem/PLL for both controllers.

Example: Source Controller Clock from MIO Pin

This example uses MIO pin 45 as a controller clock reference. 1. Configure MIO device pin. Write 0x0000_1200 to the slcr.MIO_PIN_45 register: a. c. e. f. 2. Route MIO pin 45 to the GPIO controller (this is overridden in the next step). LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. b. Disable the output driver (TRI_ENABLE = 1 ). d. Slow CMOS edge (benign setting).

Enable MIO path . Write to the slcr.CAN_MIOCLK_CTRL register to override the MIO PIN register setting that was written in the previous step. Write a 1 to slcr.CAN_MIOCLK_CTRL[CANx__REF_SEL] and write the desired MIO pin number into the slcr.CAN_MIOCLK_CTRL[CANx_MUX] bit field to match the pin in the previous step.

18.4.2 Resets
The effects for each reset type are summarized in Table 18-7. Table 18-7: CAN Reset Effects Name
Local CAN Reset can.SRR[SRST] PS Reset Subsystem slcr.CAN_RST_CTRL[CANx_CPU1X_RST]

APB Rx and Tx Protocol Interface FIFOs Engine

Yes Yes Yes Yes Yes Yes

Control and Acceptance Filters Status (ID and Mask) Registers

Yes Yes No No

Example: Reset using Local CAN Reset

1. Write to the Local CAN reset register. Write a 1 to can.SRR[SRST] bit field. This bit is self-clearing.

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Example: Reset using Reset Subsystem

1. Write to the slcr reset register for CAN . Write a 1 then a 0 to the slcr.CAN_RST_CTRL[CANx_CPU1X_RST] bit field.

18.5 I/O Interface

18.5.1 MIO Programming
Each set of controller Rx/Tx signals is connected to either MIO pins or the EMIO interface, refer to Table 18-8, page 532. The general routing concepts and MIO I/O buffer configurations are explained in section 2.4 PSPL Voltage Level Shifter Enables. The MIO routing to use an external reference clock (CAN_REF_CLK) is described in section 18.4.1 Clocks.

Example: Configure Rx/Tx Signals to MIO Pins

1. Configure MIO pin 46 for the Rx signal . Write 0x0000_1221 to the slcr.MIO_PIN_46 register: a. c. e. f. 2. a. c. e. f. Route CAN0 Rx signal to pin 46. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Diable HSTL receiver. Route CAN0 Tx signal to pin 47. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. b. Output disabled (set TRI_ENABLE = 1 ). d. Slow CMOS edge (benign setting).

Configure MIO pin 47 for the Tx signal. Write 0x0000_1220 to the slcr.MIO_PIN_47 register: b. 3-state controlled by CAN (TRI_ENABLE = 0). d. Slow CMOS drive edge.

18.5.2 MIO-EMIO Signals

The CAN I/O Signals are identified in Table 18-8. Refer to section 2.4 PSPL Voltage Level Shifter Enables for routing details. The MIO pins and any restrictions based on device versions are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table.

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Table 18-8: CAN Interface

CAN 0 Rx CAN 0 Tx CAN 0 CLK CAN 1 Rx CAN 1 Tx CAN 1 CLK

CAN MIO Pins and EMIO Signals Default Controller Input Value
0 ~ ~ 0 ~ ~

MIO Pins Numbers

10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51 Any MIO pin 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52 Any MIO pin

EMIO Signals I/O

I O I I O I

Name
EMIOCAN0PHYRX EMIOCAN0PHYTX ~ EMIOCAN1PHYRX EMIOCAN1PHYTX ~

I/O
I O ~ I O ~

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UART Controller
19.1 Introduction
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. The controller can accommodate automatic parity generation and multi-master detection mode. The UART operations are controlled by the configuration and mode registers. The state of the FIFOs, modem signals and other controller functions are read using the status, interrupt status and modem status registers. The controller is structured with separate Rx and Tx data paths. Each path includes a 64-byte FIFO. The controller serializes and de-serializes data in the Tx and Rx FIFOs and includes a mode switch to support various loopback configurations for the RxD and TxD signals. The FIFO interrupt status bits support a polling or interrupt driven handler. Software reads and writes data bytes using the Rx and Tx data port registers. When the UART is being used in a modem-like application, the modem control module detects and generates the modem handshake signals and also controls the receiver and transmitter paths according to the handshaking protocol.

19.1.1 Features
Each UART controller (UART 0 and UART 1) has the following features: Programmable baud rate generator 64-byte receive and transmit FIFOs Programmable protocol:

6, 7, or 8 data bits 1, 1.5, or 2 stop bits Odd, even, space, mark, or no parity

Parity, framing and overrun error detection Line-break generation and detection Interrupts generation RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch

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Loop UART 0 with UART 1 option Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface

19.1.2 System Viewpoint

The system viewpoint diagram for the UART controllers is shown in Figure 19-1.
X-Ref Target - Figure 19-1

IRQ ID# {59, 82} UART REF_RST UART REF_CLK Slave ports
Tx, Rx, CTSN, DCDN, DSRN, RIN, DTRN, RTSN

UART Interface Controller

MIO EMIO Routing

Tx, Rx

PS Slave APB Interconnect CPU_1x clock UART{0, 1} CPU1X_RST

MIO Pins

Control And Status Registers

EMIO Signals

PL

UG585_c19_01_010112

Figure 19-1:

UART System Viewpoint

The slcr register set (refer to section 4.3 SLCR Registers) includes control bits for the UART clocks, resets and MIO-EMIO signal mapping. Software accesses the UART controller registers using the APB 32-bit slave interface attached to the PS AXI interconnect. The IRQ from each controller is connected to the PS interrupt controller and routed to the PL.

19.1.3 Notices
Reference Clock Operating Restrictions
There is a single PS clock generator for both UART controllers. The reference clocks (UART_Ref_Clk) going to the baud rate generator of each UART controller are of the same clock frequency, but are individually enabled, refer to section 25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks. The controllers are always clocked by the internal, PS clock generator.

Note: There are no frequency restrictions in the relationship between the CPU_1x and UART_Ref_clk
clocks.

7z010 CLG225 Device

The 7z010 CLG225 device supports 32 MIO pins as shown in the MIO-at-a-Glance Table, page 51. This restricts the availability of the UART signals on the MIO pins. If needed, the TxD and RxD UART signals can be routed through the EMIO interface and passed-through to the PL pins. All of the 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

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19.2 Functional Description

19.2.1 Block Diagram
The block diagram for the UART module is shown in Figure 19-2
X-Ref Target - Figure 19-2

PS AXI Interconnect

APB Slave Interface

TxFIFO RxFIFO

Transmitter Receiver

UART TxD Mode Switch UART RxD MIO/EMIO

Control and Status Registers Interrupt Controller (GIC)

CTS, RTS, DSR, DCD, RI, DTR

EMIO

Interrupts

UART Ref Clock

Optional Divide by 8

Baud Rate Generator

UG585_c19_02_020613

Figure 19-2:

UART Block Diagram

19.2.2 Control Logic

The control logic contains the Control register and the Mode register, which are used to select the various operating modes of the UART. The Control register enables, disables, and issues soft resets to the receiver and transmitter modules. In addition, it restarts the receiver timeout period, and controls the transmitter break logic. Receive line break detection must be implemented in Software. It will be indicated by a Frame Error followed by one or more zero bytes in the RxFIFO. The Mode register selects the clock used by the baud rate generator. It also selects the bit length, parity bit and stop bit to be used by transmitted and received data. In addition, it selects the mode of operation of the UART, switching between normal UART mode, automatic echo, local loopback, or remote loopback, as required.

19.2.3 Baud Rate Generator

The baud rate generator furnishes the bit period clock, or baud rate clock, for both the receiver and the transmitter. The baud rate clock is implemented by distributing the base clock uart_clk and a single cycle clock enable to achieve the effect of clocking at the appropriate frequency division. The effective logic for the baud rate generation is shown in Figure 19-3.

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X-Ref Target - Figure 19-3

uart.mode_reg0[0] UART Ref clock 0 Sel Clk 1 sel_clk CD Programmable Divider

uart.Baud_rate_divider_reg0[7:0]

uart.Baud_rate_gen_reg0[15:0] BDIV Programmable Divider Rx and Tx Baud rate Baud Sample

UG585_c19_03_071912

Divide by 8

Figure 19-3:

UART Board Rate Generator

The baud rate generator can use either the master clock signal, uart_ref_clk, or the master clock divided by eight, uart_ref_clk/8. The clock signal used is selected according to the value of the CLKS bit in the Mode register (uart.mode_reg0). The resulting selected clock is termed sel_clk in the following description. The sel_clk clock is divided down to generate three other clocks: baud_sample, baud_tx_rate, and baud_rx_rate. The baud_tx_rate is the target baud rate used for transmitting data. The baud_rx_rate is nominally at the same rate, but gets resynchronised to the incoming received data. The baud_sample runs at a multiple ([BDIV] + 1) of baud_rx_rate and baud_tx_rate and is used to over-sample the received data. The sel_clk clock frequency is divided by the CD field value in the Baud Rate Generator register to generate the baud_sample clock enable. This register may be programmed with a value between 1 and 65535. The baud_sample clock is divided by [BDIV] plus 1. BDIV is a programmable field in the Baud Rate Divider register and can be programmed with a value between 4 and 255. It has a reset value of 15, inferring a default ratio of 16 baud_sample clocks per baud_tx_clock / baud_rx_rate. Thus the frequency of the baud_sample clock enable is shown in Equation 19-1. sel_clk ----baud_sample = CD

Equation 19-1

The frequency of the baud_rx_rate and baud_tx_rate clock enables is show in Equation 19-2. sel_clk ----------baud_rate = -CD ( BDIV + 1 )

Equation 19-2

It is essential to disable the transmitter and receiver before writing to the Baud Rate Generator register (uart.Baud_rate_gen_reg0), or the baud rate divider register (uart.Baud_rate_divider_reg0). A soft reset must be issued to both the transmitter and receiver before they are re-enabled. Some examples of the relationship between the uart_ref_clk clock, baud rate, clock divisors (CD and BDIV), and the rate of error are shown in Table 19-1. The highlighted entry shows the default reset values for CD and BDIV. For these examples, a system clock rate of UART_Ref_Clk = 50 MHz and Uart_ref_clk/8 = 6.25 MHz is assumed. The frequency of the UART reference clock can be changed to

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get a more accurate Baud rate frequency, refer to Chapter 25, Clocks for details to program the UART_Ref_Clk. Table 19-1: Clock
UART Ref clock UART Ref clock /8 UART Ref clock UART Ref clock UART Ref clock UART Ref clock UART Ref clock UART Ref clock

UART Parameter Value Examples Baud Rate

600 9,600 9,600 28,800 115,200 230,400 460,800 921,600

Calculated CD
10416.667 81.380 651.041 347.222 62.004 31.002 27.127 9.042

Actual CD
10417 81 651 347 62 31 9 9

BDIV
7 7 7 4 6 6 11 5

Actual Baud Rate

599.980 9,645.061 9,600.614 28,818.44 115,207.37 230,414.75 462,962.96 925,925.92

Error (BPS)
0.020 45.061 0.614 18.44 7.373 14.75 2,162.96 4,325.93

% Error
-0.003 0.469 0.006 0.064 0.0064 0.006 0.469 0.469

19.2.4 Transmit FIFO

The transmit FIFO (TxFIFO) stores data written from the APB interface until it is removed by the transmit module and loaded into its shift register. The TxFIFOs maximum data width is eight bits. Data is loaded into the TxFIFO by writing to the TxFIFO register. When data is loaded into the TxFIFO, the TxFIFO empty flag is cleared and remains in this Low state until the last word in the TxFIFO has been removed and loaded into the transmitter shift register. This means that host software has another full serial word time until the next data is needed, allowing it to react to the empty flag being set and write another word in the TxFIFO without loss in transmission time. The TxFIFO full interrupt status (TFULL) indicates that the TxFIFO is completely full and prevents any further data from being loaded into the TxFIFO. If another APB write to the TxFIFO is performed, an overflow is triggered and the write data is not loaded into the TxFIFO. The transmit FIFO nearly full flag (TNFULL) indicates that there is not enough free space in the FIFO for one more write of the programmed size, as controlled by the WSIZE bits of the Mode register. The TxFIFO nearly-full flag (TNFULL) indicates that there is only byte free in the TxFIFO. A threshold trigger (TTRIG) can be setup on the TxFIFO fill level. The Transmitter Trigger register can be used to setup this value, such that the trigger is set when the TxFIFO fill level reaches this programmed value.

19.2.5 Transmitter Data Stream

The transmit module removes parallel data from the TxFIFO and loads it into the transmitter shift register so that it can be serialized. The transmit module shifts out the start bit, data bits, parity bit, and stop bits as a serial data stream. Data is transmitted, least significant bit first, on the falling edge of the transmit baud clock enable (baud_tx_rate). A typical transmitted data stream is illustrated in Figure 19-4.

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X-Ref Target - Figure 19-4

baud_tx_rate

TXD START

D0

D1

D2

D3

D4

D5

D6

D7

PA

S STOP

UG585_c19_04_020613

Figure 19-4:

Transmitted Data Stream

The uart.mode_reg0[CHRL] register bit selects the character length, in terms of the number of data bits. The uart.mode_reg0[NBSTOP] register bit selects the number of stop bits to transmit.

19.2.6 Receiver FIFO

The RxFIFO stores data that is received by the receiver serial shift register. The RxFIFOs maximum data width is eight bits. When data is loaded into the RxFIFO, the RxFIFO empty flag is cleared and this state remains Low until all data in the RxFIFO has been transferred through the APB interface. Reading from an empty RxFIFO returns zero. The RxFIFO full status (Chnl_int_sts_reg0 [RFUL] and Channel_sts_reg0 [RFUL] bits) indicates that the RxFIFO is full and prevents any further data from being loaded into the RxFIFO. When a space becomes available in the RxFIFO, any character stored in the receiver will be loaded. A threshold trigger (RTRIG) can be setup on the RxFIFO fill level. The Receiver Trigger Level register (Rcvr_FIFO_trigger_level0) can be used to setup this value, such that the trigger is set when the RxFIFO fill level transitions this programmed value. The Range is 1 to 63.

19.2.7 Receiver Data Capture

The UART continuously over-samples the UARTx_RxD signal using UARTx REF_CLK and the clock enable (baud_sample). When the samples detect a transition to a Low level, it can indicate the beginning of a start bit. When the UART senses a Low level at the UART_RxD input, it waits for a count of half of BDIV baud rate clock cycles, and then samples three more times. If all three bits still indicate a Low level, the receiver considers this to be a valid start bit, as illustrated in Figure 19-5 for the default BDIV of 15.
X-Ref Target - Figure 19-5

10

11

12

13

14

15

16

baud_sample

rxd Start Bit

Data (LSB)
UG585_c19_05_022612

Figure 19-5:

Default BDIV Receiver Data Stream

When a valid start bit is identified, the receiver baud rate clock enable (baud_rx_rate) is re-synchronised so that further sampling of the incoming UART RxD signal occurs around the theoretical mid-point of each bit, as illustrated in Figure 19-6.

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X-Ref Target - Figure 19-6

baud_rx_rate

10

11

12

13

14

15

16

baud_sample

rxd

Data Bit
UG585_c19_06_022612

Figure 19-6:

Re-synchronized Receiver Data Stream

When the re-synchronised baud_rx_rate is High, the last three sampled bits are compared. The logic value is determined by majority voting; two samples having the same value define the value of the data bit. When the value of a serial data bit has been determined, it is shifted to the receive shift register. When a complete character has been assembled, the contents of the register are then pushed to the RxFIFO.

Receiver Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits in accordance with the uart.mode_reg0 [PAR] bit field. It then compares the result with the received parity bit. If a difference is detected, the parity error bit is set = 1 , uart.Chnl_int_sts_reg0 [PARE]. An interrupt is generated, if enabled.

Receiver Framing Error

When the receiver fails to receive a valid stop bit at the end of a frame, the frame error bit is set =1 , uart.Chnl_int_sts_reg0 [FRAME]. An interrupt is generated, if enabled.

Receiver Overflow Error

When a character is received, the controller checks to see if the RxFIFO has room. If it does, then the character is written into the RxFIFO. If the RxFIFO is full, then the controller waits. If a subsequent start bit on RxD is detected and the RxFIFO is still full, then data is lost and the controller sets the Rx overflow interrupt bit, uart.Chnl_int_sts_reg0 [ROVR] = 1 . An interrupt is generated, if enabled.

Receiver Timeout Mechanism

The receiver timeout mechanism enables the receiver to detect an inactive RxD signal (a persistent High level). The timeout period is programmed by writing to the uart.Rcvr_timeout_reg0 [RTO] bit field. The timeout mechanism uses a 10-bit decrementing counter. The counter is reloaded and starts counting down whenever a new start bit is received on the RxD signal, or whenever software writes a 1 to uart.Control_reg0 [RSTTO] (regardless of the previous [RSTTO] value). If no start bit or reset timeout occurs for 1,023 bit periods, a timeout occurs. The Receiver timeout error bit [TIMEOUT] will be set in the interrupt status register, and the [RSTTO] bit in the Control register should be written with a 1 to restart the timeout counter, which loads the newly programmed timeout value.

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The upper 8 bits of the counter are reloaded from the value in the [RTO] bit field and the lower 2 bits are initialized to zero. The counter is clocked by the UART bit clock. As an example, if [RTO] = 0xFF, then the timeout period is 1,023 bit clocks (256 x 4 minus 1). If 0 is written into the [RTO] bit, the timeout mechanism is disabled. When the decrementing counter reaches 0, the receiver timeout occurs and the controller sets the timeout interrupt status bit uart.Chnl_int_sts_reg0 [TIMEOUT] = 1 . If the interrupt is enabled (uart.Intrpt_mask_reg0 [TIMEOUT] = 1 ), then the IRQ signal to the PS interrupt controller is asserted. Whenever the timeout interrupt occurs, it is cleared with a write back of 1 to the Chnl_int_sts_reg0 [TIMEOUT] bit. Software must set uart.Control_reg0 [RSTTO] = 1 to generate further receive timeout interrupts.

19.2.8 I/O Mode Switch

The mode switch controls the routing of the RxD and TxD signals within the controller as shown in Figure 19-7 . The loopback using the mode switch occurs regardless of the MIO-EMIO routing of the UARTx TxD/RxD I/O signals. There are four operating modes as shown in Figure 19-7. The mode is controlled by the uart.mode_reg0 [CHMODE] register bit field: normal, automatic echo, local loopback and remote loopback.
X-Ref Target - Figure 19-7

TxFIFO

Transmit Mode Switch

UARTx TxD

RxFIFO

Receive

UARTx RxD

TxFIFO

Transmit Mode Switch

UARTx TxD UARTx RxD

TxFIFO

Transmit Mode Switch

UARTx TxD UARTx RxD

RxFIFO

Receive

RxFIFO

Receive

Normal Mode
TxFIFO Transmit Mode Switch RxFIFO Receive

Automatic Echo Mode

UARTx TxD UARTx RxD
TxFIFO Transmit Mode Switch RxFIFO Receive

UARTx TxD UARTx RxD

Local Loopback Mode

Figure 19-7:

Remote Loopback Mode

UG585_c19_13_100512

UART Mode Switch for TxD and RxD

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Normal Mode
Normal mode is used for standard UART operations.

Automatic Echo Mode

Echo mode receives data on RxD and the mode switch routes the data to both the receiver and the TxD pin. Data from the transmitter cannot be sent out from the controller.

Local Loopback Mode

Local loopback mode does not connect to the RxD or TxD pins. Instead, the transmitted data is looped back around to the receiver.

Remote Loopback Mode

Remote loopback mode connects the RxD signal to the TxD signal. In this mode, the controller cannot send anything on TxD and the controller does not receive anything on RxD.

19.2.9 UART0-to-UART1 Connection

The I/O signals of the two UART controllers in the PS can be connected together. In this mode, the RxD and CTS input signals from one controller are connected to the TxD and RTS output signals of the other UART controller by setting the slcr.LOOP [UA0_LOOP_UA1] bit = 1 . The other flow control signals are not connected. This UART-to-UART connection occurs regardless of the MIO-EMIO programming.

19.2.10 Status and Interrupts

Interrupt and Status Registers
There are two status registers that can be read by software. Both show raw status. The Chnl_int_sts_reg0 register can be read for status and generate an interrupt. The Channel_sts_reg0 register can only be read for status. The Chnl_int_sts_reg0 register is sticky; once a bit is set, the bit stays set until software clears it. Write a 1 to clear a bit. This register is bit-wise AND'ed with the Intrpt_mask_reg0 mask register. If any of the bit-wise AND functions have a result = 1 , then the UART interrupt is asserted to the PS interrupt controller. Channel_sts_reg0 : Read-only raw status. Writes are ignored.

The various FIFO and system indicators are routed to the uart.Channel_sts_reg0 register and/or the uart.Chnl_int_sts_reg0 register as shown in Figure 19-8.

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X-Ref Target - Figure 19-8

Status uart.Channel_sts_reg0[14:10, 4:0] (all bits are dynamic) uart.Intrpt_mask_reg0 0: Masked 1: Enabled

FIFO and other System Indicators

Interrupts uart.Chnl_int_sts_reg0[12:0] (all bits are sticky)

PS Interrupt IRQ ID #59 / #82

Mask Enable 0 1 uart.Intrpt_en_reg0 1 0

uart.Intrpt_dis_reg0

UG585_c19_03_010613

Figure 19-8:

Interrupts and Status Signals

The interrupt registers and bit fields are summarized in Table 19-2. Table 19-2: UART Interrupt Status Bits

Interrupt Register Names and Bit Assignments 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

uart.Intrpt_en_reg0 uart.Intrpt_dis_reg0 uart.Intrpt_mask_reg0 uart.Chnl_int_sts_reg0
x x TOVR TNFUL TTRIG DMSI TIME OUT PARE FRAME ROVR TFUL TEMPTY RFUL REMPTY RTRIG

uart.Channel_sts_reg0
TNFUL TTRIG FDELT TACTIVE RACTIVE X X X X X TFUL TEMPTY RFUL REMPTY RTRIG

Interrupt Mask Register

Intrpt_mask_reg0 is a read-only interrupt mask/enable register that is used to mask individual raw interrupts in the Chnl_int_sts_reg0 register: If the mask bit = 0 , the interrupt is masked. If the mask bit = 1 , the interrupt is enabled.

This mask is controlled by the write-only Intrpt_en_reg0 and Intrpt_dis_reg0 registers. Each associated enable/disable interrupt bit should be set mutually exclusive (e.g., to enable an interrupt, write 1 to Intrpt_en_reg0[x] and write 0 to Intrpt_dis_reg0[x]).

Channel Status
These status bits are in the Channel_sts_reg0 register. TACTIVE : Transmitter state machine active status. If in an active state, the transmitter is currently shifting out a character. RACTIVE : Receiver state machine active status. If in an active state, the receiver is has detected a start bit and is currently shifting in a character.

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FDELT: Receiver flow delay trigger continuous status. The FDELT status bit is used to monitor the RxFIFO level in comparison with the flow delay trigger level.

Non-FIFO Interrupts
These interrupt status bits are in the Chnl_int_sts_reg0 register. TIMEOUT: Receiver Timeout Error interrupt status. This event is triggered whenever the receiver timeout counter has expired due to a long idle condition. PARE : Receiver Parity Error interrupt status. This event is triggered whenever the received parity bit does not match the expected value. FRAME : Receiver Framing Error interrupt status. This event is triggered whenever the receiver fails to detect a valid stop bit. Refer to section 19.2.7 Receiver Data Capture. DMSI : indicates a change of logic level on the DCD, DSR, RI or CTS modem flow control signals. This includes High-to-Low and Low-to-High logic transitions on any of these signals.

FIFO Interrupts
The status bits for the FIFO interrupts listed in Table 19-2 are illustrated in Figure 19-9. These interrupt status bits are in the Channel Status (uart.Channel_sts_reg0) and Channel Interrupt Status (uart.Chnl_int_sts_reg0) registers with the exception that the [TOVR] and [ROVR] bits are not part of the uart.Channel_sts_reg0 register.
X-Ref Target - Figure 19-9

RxFIFO (64 bytes)

Full Interrupt [RFUL] Trigger Interrupt [RTRIG] Overflow Interrupt [ROVR]

TxFIFO (64 bytes)

Full Interrupt [TFUL] Overflow Interrupt [TOVR] Nearly Full Interrupt [TNFUL] Trigger Interrupt [TTRIG] uart.Rcvr_FIFO_trigger_level0 uart.Tx_FIFO_trigger_level0

Empty Interrupt [REMPTY]

Empty Interrupt [TEMPTY]

UG585_c19_12_102912

Figure 19-9:

UART RxFIFO and TxFIFO Interrupt

The FIFO trigger levels are controlled by these bit fields: uart.Rcvr_FIFO_trigger_level0[RTRIG], a 6-bit field uart.Tx_FIFO_trigger_level0[TTRIG], a 6-bit field

19.2.11 Modem Control

The modem control module facilitates the control of communication between a modem and the UART. It contains the Modem Status register, the Modem Control register, the DMSI bit in interrupt

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status register, and FDELT in the channel status register. This event is triggered whenever the DCTS, DDSR, TERI, or DDCD in the modem status register are being set. The read-only Modem Status register is used to read the values of the clear to send (CTS), data carrier detect (DCD), data set ready, (DSR) and ring indicator (RI) modem inputs. It also reports changes in any of these inputs and indicates whether automatic flow control mode is currently enabled. The bits in the Modem Status register are cleared by writing a 1 to the particular bit. The read/write only Modem Control register is used to set the data terminal ready (DTR) and request to send (RTS) outputs, and to enable the Automatic Flow Control Mode register. By default, the automatic flow control mode is disabled, meaning that the modem inputs and outputs work completely under software control. When the automatic flow control mode is enabled by setting the FCM bit in the Modem Control register, the UART transmission and reception status is automatically controlled using the modem handshake inputs and outputs. In automatic flow control mode the request to send output is asserted and de-asserted based on the current fill level of the receiver FIFO, which results in the far-end transmitter pausing transmission and preventing an overflow of the UART receiver FIFO. The FDEL field in the Flow Delay register (Flow_delay_reg0) is used to setup a trigger level on the Receiver FIFO which causes the de-assertion of the request to send. It remains Low until the FIFO level has dropped to below four less than FDEL. Additionally in automatic flow control mode, the UART only transmits while the clear to send input is asserted. When the clear to send is de-asserted, the UART pauses transmission at the next character boundary. If flow control is selected as automatic, then Flow Delay register must be programmed in order to have a control on the inflow of data, which is done by de-asserting RTS signal. The value corresponds to the RxFIFO level at which RTS signal will be de-asserted. It will be re-asserted when the RxFIFO level drops to four below the value programmed in the Flow Delay register. The uart.Channel_sts_reg0 [FDELT] register bit is used to monitor the RxFIFO level in comparison with the flow delay trigger level. The [FDELT] bit is set whenever the RxFIFO level is greater than or equal to trigger the level programmed in the Flow Delay register. The trigger level programmed in the Flow Delay register has no dependency on the Rx Trigger Level register. This is to only control the inflow of data using the RTS modem signal. The CPU will be interrupted by receive data only on receipt of an Rx Trigger interrupt. Data is retrieved based on the trigger level programmed in the Rx Trigger Level register.

Programmable Parameters
The UART flow control signals, DTR and RTS are generated by the UART controller. The RTS flow control signal is used to signal for Rx (ready to send signal to the attached terminal). The DTR flow control signal indicates the status of the UART controller (data terminal ready).

The DTR and RTS can be controlled manually by software or automatically by the controller. In automatic mode, the modem control unit asserts and de-asserts the RTS and DTR signals.

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In manual mode, software controls the RTS and DTR signals using uart.Modem_ctrl_reg0.

uart.Modem_ctrl_reg0 : [DTR]: Data Terminal Ready output signal [RTS]: Request to Send output signal [FCM]: Select Automatic or Manual flow control.

uart.Modem_sts_reg0 : [DCTS]: Delta Clear To Send (input) status [DDSR]: Delta Data Set Ready (input) status [TERI]: Trailing-edge Ring Indicator (input) status [DDCD]: Delta Data Carrier Detect (input) status

Select one of the following operating options:

Example: Automatic Flow Control

1. 2. 3. Set RTS trigger level. Write to the uart.Flow_Delay_reg0 register. This is the trigger level to de-assert modem signal RTS. Select automatic flow control . Write a 1 to uart.Modem_ctrl_reg0 [FCM]. Verify the mode change to automatic . Read uart.Modem_sts_reg0 [FCMS] until it equals 1 .

When software writes a 1 to uart.Modem_ctrl_reg0 [FCM], the modem changes to automatic mode. The change of mode from manual to automatic is verified by reading the status bit FCMS in the Modem Status register.

Example: Manual Flow Control

1. Select manual flow control . Write a 0 to uart.Modem_ctrl_reg0 [FCM]. Option a. Control the DTR output signal using uart.Modem_ctrl_reg0 [DTR]. Option b. Control the RTS output signal using uart.Modem_ctrl_reg0 [RTS].

Example: Monitor for a Change in the DCD DSR RI CTS Flow Control Signals
A logic level change to the DCD DSR RI CTS flow control signals is detected by the controller. When a logic level change is detected, the hardware sets the uart.Chnl_int_sts_reg0 [DMSI] bit. This change, or channel status can optionally generate an interrupt. 1. Check flow control signal status . uart.Modem_sts_reg0 register reports the modem status.

In interrupt mode, the ISR can run when the DMSI interrupt occurs when there is a change of status on modem lines.

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19.3 Programming Guide

19.3.1 Start-up Sequence
Main Example: Start-up Sequence
1. 2. 3. 4. Reset controller : The reset programming model is described in section 19.4.2 Resets. Configure I/O signal routing : Rx/Tx can be routed to either MIO or EMIO. The modem control signals are only available on the EMIO interface. Refer to section 19.5.1 MIO Programming. Configure UART_Ref_Clk : The UART clock architecture and programming model are described in section 19.4.1 Clocks. Configure controller functions: Program the I/O signal characteristics and controller functions using the uart.Control_reg0 and uart.mode_reg0 registers. Examples are shown in section 19.3.2 Configure Controller Functions. Configure interrupts : Interrupts are used to manage the Rx/Tx FIFOs in all modes. Refer to section 19.2.10 Status and Interrupts and the program example in section 19.3.5 RxFIFO Trigger Level Interrupt. Configure modem controls (optional) : Polling and interrupt driven options. Refer to section 19.2.11 Modem Control. Manage transmit and receive data : Polling and interrupt driven handlers are supportable. Refer to sections 19.3.3 Transmit Data and 19.3.4 Receive Data.

5.

6. 7.

19.3.2 Configure Controller Functions

Example: Configure Controller Functions
This example configures the character frame, the baud rate, the FIFO trigger levels, the Rx timeout mechanism, and enables the controller. All of these steps are necessary after a reset, but not necessary between enabling and disabling the controller. 1. Configure UART character frame . Write 0x0000_0020 into the uart.mode_reg0: a. c. e. 2. Disables clock pre-divider, UART_REF_CLK/8: [CLKS] = 0 Selects no parity: [PAR] = 100 Selects normal channel mode (Mode Switch): [CHMODE] = 00 b. Selects 8-bit character length: [CHRL] = 00 d. Selects 1 stop bit: [NBSTOP] = 00 Configure the Baud Rate . Write to three registers: uart.Control_reg0, uart.Baud_rate_gen_reg0, and uart.Baud_rate_divider_reg0. Examples for the calculated CD and BDIV values are shown in table Table 19-1, page 537. The baud rate generator is described in section 19.2.3 Baud Rate Generator. a. Disable the Rx path: set uart.Control_reg0 [RXEN] = 0 and [RXDIS] = 1.

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b. Disable the Txpath: set uart.Control_reg0 [TXEN] = 0 and [TXDIS] = 1 . c. e. f. 3. Write the calculated CD value into the uart.Baud_rate_gen_reg0 [CD] bit field. Reset Tx and Rx paths: uart.Control_reg0 [TXRST] and [RXRST] = 1 . These bits are self-clearing. Enable the Rx path: Set [RXEN] = 1 and [RXDIS] = 0 . d. Write the calculated BDIV value into the uart.Baud_rate_divider_reg0 [BDIV] bit value.

g. Enable the Tx path: Set [TXEN] = 1 and [TXDIS] = 0 . Set the level of the RxFIFO trigger level . Write the trigger level into the uart.Rcvr_FIFO_trigger_level0 register.

Option a: Enable the Rx trigger level: Write a value of 1 to 63 into the [RTRIG] bit field. Option b: Disable the Rx trigger level : Write 0 into the [RTRIG] bit field.

4.

Program the Receiver Timeout Mechanism . Write the timeout value into the uart.Rcvr_timeout_reg0 register. Refer to Receiver Timeout Mechanism, page 539. a. To enable the timeout mechanism, write a value of 1 to 255 into the [RSTTO] bit field. b. To disable the timeout mechanism, write a 0 into the [RSTTO] bit field.

5.

Enable the Controller. Write 0x0000_0117 into the uart.Control_reg0 register.

Note: Ensure that the Receiver Timeout register is programmed to a valid value before resetting
the timeout counter (previous step). a. Reset Tx and Rx paths: uart.Control_reg0 [TXRST] and [RXRST] = 1 . These bits are self-clearing. Enables the Tx path: [TXEN] = 1 and [TXDIS] = 0 . Does not start to transmit a break: [STTBRK] = 0 . Stop Break transmitter: [STPBRK] = 1

b. Enables the Rx path: [RXEN] = 1 and [RXDIS] = 0 . c. e. f. d. Restarts the Receiver Timeout Counter: [RSTTO] = 1 .

19.3.3 Transmit Data

Software can used polling or interrupts to control the flow of data to the TxFIFO and RxFIFO.

Note: When the TxFIFO Empty status is true, software can write 64 bytes (the size of the TxFIFO)
without checking the TxFIFO status. In reality, software can write more than 64 bytes when the transmitter is active because while the software is writing data to the TxFIFO, the controller is removing data and serializing it onto the TxD signal.

Example: Transmit Data using the Polling Method

In this example, the software can choose to fill the TxFIFO until the Full status bit is set or wait for the TxFIFO to be empty (and write up to 64 bytes). The software can always write a byte when the TxFIFO is nearly full. 1. Check to see if the TxFIFO is empty. Wait until uart.Channel_sts_reg0[TEMPTY] = 1 .

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2. 3.

Fill the TxFIFO with data . Write 64 bytes of data to the uart.TX_RX_FIFO0 register. Write more data to the TxFIFO. There are two methods: Option A: Check to see if the TxFIFO has room to another byte of data (i.e., the TxFIFO is not full) : Read uart.Channel_sts_reg0 [TFUL] until it equals 0 . When [TFUL] = 0 , write a single byte of data into the TxFIFO and then read [TFUL] again. Option B: Wait until the TxFIFO goes empty. Read uart.Channel_sts_reg0 [TEMPTY] until it equals 1 , then go to step 2 to fill the TxFIFO with 64 bytes of data.

Example: Transmit Data using the Interrupt Method

This example initially fills the TxFIFO in a similar way as the polling method. Then, software enables the TxFIFO Empty interrupt to alert the software to fill-up the TxFIFO again. 1. 2. 3. Disable the TxFIFO Empty interrupt . Write a 1 to uart.Intrpt_dis_reg0 [TEMPTY]. Fill the TxFIFO with data . Write 64 bytes of data to the uart.TX_RX_FIFO0 register. Check to see if the TxFIFO has room to another byte of data (i.e., the TxFIFO is not full) : read uart.Channel_sts_reg0 [TFUL] until it equals 0 . When [TFUL] = 0 , write a single byte of data into the TxFIFO and then read [TFUL] again. Repeat step 2 and 3 . Repeat until uart.Channel_sts_reg0 [TFUL] is not set. Enable the interrupt . Enable the interrupt with a write of 1 to uart.Intrpt_en_reg0 [TEMPTY]. Wait until the TxFIFO is empty. Repeat from step 1 when uart.Channel_int_sts_reg0 [TEMPTY] is set to 1 .

4. 5. 6.

19.3.4 Receive Data

Example: Receive Data using the Polling Method
1. 2. 3. 4. Wait until the RxFIFO is filled up to the trigger level. Check to see if uart.Channel_sts_reg0[RTRIG] = 1 or uart.Chnl_int_sts_reg0 [TIMEOUT] = 1 . Read data from the RxFIFO. Read data from the uart.TX_RX_FIFO0 register. Repeat step 2 until FIFO is empty. Check that uart.Channel_sts_reg0 [REMPTY] = 1. Clear if Rx timeout interrupt status bit is set . Write 1 to Chnl_int_sts_reg0 [TIMEOUT].

Example: Receive Data using the Interrupt Method

1. 2. 3. 4. 5. Enable interrupts . Write a 1 to uart.Intrpt_en_reg0 [TIMEOUT] and uart.Intrpt_en_reg0[RTRIG]. Wait until the RxFIFO is filled up to the trigger level or Rx timeout . Check that uart.Chnl_int_sts_reg0 [RTRIG] = 1 or uart.Chnl_int_sts_reg0 [TIMEOUT] = 1 . Read data from the RxFIFO. Read data from the uart.TX_RX_FIFO0 register. Repeat step 2 and 3 until the FIFO is empty. Check that uart.Channel_sts_reg0 [REMPTY] = 1 . Clear the interrupt status bits if set. Write a 1 to Chnl_int_sts_reg0 [TIMEOUT] or Chnl_int_sts_reg0 [RTRIG].

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19.3.5 RxFIFO Trigger Level Interrupt

Example: Set the RxFIFO Trigger Level and Enable the Interrupt
The Intrpt_en_reg0 register has bits to enable the interrupt mask and Intrpt_dis_reg0 has bits to forcefully disable the interrupts. Each pair of bits should be set mutually exclusive (i.e., one register has a 1 for the bit and the other register has a 0 ): 1. 2. Intrpt_en_reg0: Write-only. Enable interrupt bit(s). Intrpt_dis_reg0: Write-only. Force disable of interrupt bit(s). Program the Trigger Level. Write to the 6-bit field, uart.Rcvr_FIFO_trigger_level0[RTRIG]. Enable the RTRIG interrupt. Set the enable bit, clear the disable bit, and verify the mask value: a. c. 3. a. c. 4. Set uart.Intrpt_en_reg0[RTRIG] = 1 . The uart.intrpt_mask_reg0[RTRIG] read back = 1 (enabled interrupt). Set uart.Intrpt_dis_reg0[RTRIG] = 1 . The uart.intrpt_mask_reg0[RTRIG] read back = 0 (disabled interrupt). b. Clear uart.Intrpt_dis_reg0[RTRIG] = 0 . Disable the RTRIG interrupt. Set the disable bit, clear the enable bit, and verify the mask value: b. Clear uart.Intrp_en_reg0[RTRIG] = 0 . Clear the RTRIG interrupt . Write a one to the uart.Intrpt_dis_reg0[RTRIG] bit field.

When both the enable and disable bits are set for an interrupt, the interrupt is disabled. The state of the interrupt enable/disable mechamism can be determined by reading the uart.Intrpt_mask_reg0 register. If the mask bit = 1 , then the interrupt is enabled.

19.3.6 Register Overview

An overview of the UART registers is shown in Table 19-3. Details are provided in Appendix B, Register Details. Table 19-3: UART Register Overview uart. Register Names
Control_reg0 mode_reg0 Baud_rate_gen_reg0 Baud_rate_divider_reg0 Intrpt_en_reg0 Intrpt_dis_reg0 Intrpt_mask_reg0 Chnl_int_sts_reg0 Channel_sts_reg0

Function
Configuration

Overview
Configure mode and baud rate.

Interrupt processing

Enable/disable interrupt mask, channel interrupt status, channel status

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Table 19-3:

UART Register Overview (Contd) uart. Register Names

TX_RX_FIFO0 Rcvr_timeout_reg0 Rcvr_FIFO_trigger_level0 Tx_FIFO_trigger_level0 Modem_ctrl_reg0 Modem_sts_reg0 Flow_delay_reg0

Function
Rx and Tx Data Receiver Transmitter Modem

Overview
Read data Received. Write data to be Transmitted. Configure receiver timeout and RxFIFO trigger level value. Configure TxFIFO trigger level value. Configure modem-like application.

19.4 System Functions

19.4.1 Clocks
The controller and I/O interface are driven by the reference clock (UART_REF_CLK). The controller's interconnect also requires an APB interface clock (CPU_1x). Both of these clocks always come from the PS clock subsystem.

CPU_1x Clock
Refer to section 25.2 CPU Clock, for general clock programming information. The CPU_1x clock runs asynchronous to the UART reference clock.

Reference Clock
The generation of the reference clock in the PS clock subsystem is controlled by the slcr.UART_CLK_CTRL register. This register can select the PLL that the clock is derived from and sets the divider frequency. This register also controls the clock enables for each UART controller. The generation of the UART reference clock is described in section 25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks.

Operating Restrictions
Note: The clock operating restrictions are described in section 19.1.3 Notices.

Example: Configure Reference Clock

The clock can be based on any of the PLLs in the PS clock subsystem. In this example, the I/O PLL is used with a 1,000 MHz clock and the clock divisor is 0x14 to generate a 50 MHz clock for the UART controllers. 1. Program the UART Reference clock . Write 0x0000_1401 to the slcr.UART_CLK_CTRL register.

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a. c.

Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14 . Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1 .

b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0. d. Disable UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] bit = 0 .

19.4.2 Resets
The controller reset bits are generated by the PS, see Chapter 26, Reset System.

Example: Controller Reset

Option 1. Assert Controller Reset : Set both slcr.UART_RST_CTRL[UARTx_REF_RST, UARTx_CPU1X_RST] bits = 1 . Option 2. De-assert Controller Reset: Clear both slcr.UART_RST_CTRL[UARTx_REF_RST, UARTx_CPU1X_RST] bits = 0 .

19.5 I/O Interface

19.5.1 MIO Programming
The UART RxD and TxD signals can be routed to one of many sets of MIO pins or to the EMIO interface. All of the modem flow control signals are always routed to the EMIO interface and are not available on the MIO pins. All of the UART signals are listed in Table 19-4. The routing of the RxD and TxD signals are described in section 2.4 PSPL Voltage Level Shifter Enables.

Example: Route UART 0 RxD/TxD Signals to MIO Pins 46, 47

In this example, the UART 0 RxD and TxD signals are routed through MIO pins 46 and 47. Many other pin options are possible. 1. Configure MIO pin 46 for the RxD signal. Write 0x0000_12E1 to the slcr.MIO_PIN_46 register: a. c. e. f. 2. a. Route UART 0 RxD signal to pin 46. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. Route UART 0 TxD signal to pin 47. b. Output disabled (set TRI_ENABLE = 1 ). d. Slow CMOS edge (benign setting).

Configure MIO pin 47 for the TxD signal . Write 0x0000_12E0 to the slcr.MIO_PIN_47 register:

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b. 3-state controlled by the UART (TRI_ENABLE = 0 ). c. e. f. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. d. Slow CMOS drive edge.

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19.5.2 MIO EMIO Signals

The UART I/O signals are identified in Table 19-4. The MIO pins and any restrictions based on device versions are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 19-4: UART MIO Pins and EMIO Signals Default Controller Input Value Numbers
~

UART Interface Signal

UART 0 Transmit UART 0 Receive UART 0 Clear to Send UART 0 Ready to Send UART 0 Data Set Ready UART 0 Data Carrier Detect UART 0 Ring Indicator UART 0 Data Terminal Ready UART 1 Transmit UART 1 Receive UART 1 Clear to Send UART 1 Ready to Send UART 1 Data Set Ready UART 1 Data Carrier Detect UART 1 Ring Indicator UART 1 Data Terminal Ready

MIO Pins I/O

O I ~ ~ ~ ~ ~ ~ O I ~ ~ ~ ~ ~ ~

EMIO Signals
Name
EMIOUART0TX EMIOUART0RX EMIOUART0CTSN EMIOUART0RTSN EMIOUART0DSRN EMIOUART0DCDN EMIOUART0RIN EMIOUART0DTRN EMIOUART1TX EMIOUART1RX EMIOUART1CTSN EMIOUART1RTSN EMIOUART1DSRN EMIOUART1DCDN EMIOUART1RIN EMIOUART1DTRN

I/O
O I I O I I I O O I I O I I I O

11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50 ~

~ ~ ~ ~

~ ~

~ 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53 ~

~ ~ ~ ~

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I2C Controller
20.1 Introduction
This I2C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range from DC (almost) up to 400 Kb/s. In master mode, a transfer can only be initiated by the processor writing the slave address into the I2C address register. The processor is notified of any available received data by a data interrupt or a transfer complete interrupt. If the HOLD bit is set, the I2C interface holds the SCL line Low after the data is transmitted to support slow processor service. The master can be programmed to use both normal (7-bit) addressing and extended (10-bit) addressing modes. In slave monitor mode, the I2C interface is set up as a master and continues to attempt a transfer to a particular slave until the slave device responds with an ACK. In slave mode, the extended address support is automatic by detecting a specific code in bits [7:3] of the first address byte. The HOLD bit can be set to prevent the master from continuing with the transfer, preventing an overflow condition in the slave. A common feature between master mode and slave mode is the timeout (TO) interrupt flag. If at any point the SCL line is held Low by the master or the accessed slave for more than the period specified in the Timeout register, a timeout (TO) interrupt is generated to avoid stall conditions.

20.1.1 Features
The PS supports two I2C devices with these key features: I2C bus specification version 2 Supports 16-byte FIFO Programmable normal and fast bus data rates Master mode

Write transfer Read transfer Extended address support Support HOLD for slow processor service Supports TO interrupt flag to avoid stall condition

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Slave monitor mode Slave mode

Slave transmitter Slave receiver Extended address support (10-bit address) Fully programmable slave response address Supports HOLD to prevent overflow condition Supports TO interrupt flag to avoid stall condition

Software can poll for status or function as interrupt-driven device Programmable interrupt generation

20.1.2 System Block Diagram

The system viewpoint diagram for the I2C module is shown in Figure 20-1.
X-Ref Target - Figure 20-1

IRQ ID# {57, 80} Slave port I2C Controllers

MIO EMIO Routing

SCL, SDA

Device Boundary

Interconnect

APB

SCL, SDA, SCL_T

MIO Pins

I2C{0, 1} CPU1x reset I2C{0, 1} CPU_1x clock

Control Registers

EMIO PL

Clocking
UG585_c20_01_030612

Figure 20-1:

I2C System Block Diagram

20.1.3 Notices
The 7z010 CLG225 device supports 32 MIO pins as shown in section 2.5.4 MIO-at-a-Glance Table. This restricts the availability of the I2C signals on the MIO pins. As needed, I2C signals can be routed through the EMIO interface and passed-through to the PL pins. All 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

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20.2 Functional Description

20.2.1 Block Diagram
X-Ref Target - Figure 20-2

Clock Enable Generator Control Register

APB

APB Interface

TX Data Register RX Data Register

Control FSM SCL/SDA Interface RX Shift Register

UG585_c20_02_030612

Interrupts

Interrupts

Status Register

Figure 20-2:

I2C Peripheral Block Diagram

20.2.2 Master Mode

An I2C transfer can only be initiated by the APB host, and two types of transfers can be performed: Write transfer, where the I2C becomes master transmitter Read transfer, where the I2C becomes master receiver

Write Transfer
To accomplish an I2C write transfer, the host must perform these steps: 1. 2. 3. 4. 5. Write to the control register to set up SCL speed and addressing mode. Set the MS, ACKEN, and CLR_FIFO bits and clear the RW bit in the Control register. If required, set the HOLD bit. Otherwise write the first byte of data to the I2C Data register. Write the slave address into the I2C address register. This initiates the I2C transfer. Continue to load the remaining data to be sent to the slave by writing to the I2C Data register. The data is pushed in the FIFO each time the host writes to the I2C Data register.

When all data is transferred successfully, the COMP bit is set in the interrupt status register. A data interrupt is generated whenever there are only two bytes left for transmission in the FIFO. When all data is transferred successfully, If the HOLD bit is not set, the I2C interface generates a STOP condition and terminates the transfer. If the HOLD bit is set, the I2C interface holds the SCL line Low

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after the data is transmitted. The host is notified of this event by a transfer complete interrupt (COMP bit set) and the TXDV bit in the status register is cleared. At this point, the host can proceed in three ways: 1. 2. 3. Clear the HOLD bit. This causes the I2C interface to generate a STOP condition. Supply more data by writing to the I2C address register. This causes the I2C interface to continue with the transfer, writing more data to the slave. Perform combined format transfer. This is accomplished by first writing to the Control register and, if necessary, changing the transfer direction or addressing mode. The host must then write to the I2C Address register. This leads to a RESTART condition being generated by the I2C interface.

If at any point the slave responds with a NACK, the transfer automatically terminates and a transfer NACK interrupt is generated (the NACK bit set). When a NACK is received the Transfer Size register indicates the number of bytes that still need to be sent minus one. Unless the very last byte written by the host into the FIFO was a NACK byte, TXDV remains High. In this case, the host must clear the FIFO by setting the CLR_FIFO bit in the Control register. If at any point the SCL line is held Low by the master or the accessed slave for more than the period specified in the Timeout register, a TO interrupt is generated and the outstanding amount of data minus one is then read from the Transfer Size register.

Read Transfer
To accomplish an I2C read transfer, the host must perform these steps: 1. 2. 3. 4. 5. Write to the Control register to set up the SCL speed and addressing mode. Set the MS, ACKEN, CLR_FIFO bits, and the RW bit in the Control register. If the host wants to hold the bus after the data is received, it must also set the HOLD bit. Write the number of requested bytes in the Transfer Size register. Write the slave address in the I2C Address register. This initiates the I2C transfer.

The host is notified of any available received data in two ways: 1. 2. If an outstanding transfer size is more than the FIFO size -2, a data interrupt is generated (DATA bit set) when there are two free locations available in the FIFO. If an outstanding transfer size is less than FIFO size -2, a transfer complete interrupt is generated (COMP bit set) when the outstanding transfer size bytes are received.

In both cases, the RXDV bit in the status register is set. The I2C interface automatically returns a NACK after receiving the last expected byte and terminates the transfer by generating a STOP condition. If the HOLD bit is set during a master read transfer, the I2C interface drives the SCL line Low. If at any point the slave responds with NACK while the master transmits a slave address for a master read transfer, the transfer automatically terminates and a transfer NACK interrupt is generated (NACK bit is set). The outstanding amount of data can be read from the Transfer Size register.

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If at any point the SCL line is held Low by the master or the accessed slave for more than the period specified in the Timeout register, a TO interrupt is generated. The I2C module, as a master, is capable of performing combined transfers as specified by the I2C specification. It can perform more than one transfer without releasing the I2C bus and these transfers are separated by a repeated START condition. The host can realize combined transfers by writing to the Address register before the end of the previous transfer. The correct transfer direction and slave addressing mode must be set by writing to the Control register, and then the Address register can be accessed for the second part of a combined transfer. For combined transfers, the host must set the HOLD bit in the beginning of the first part of a transfer. When the host receives a transfer complete interrupt, it can then initiate the second part of a combined transfer.

20.2.3 Slave Monitor Mode

This mode is meaningful only when the module is in master mode and bit SLVMON in the control register is set. The host must set the MS and SLVMON bits and clear the RW bit in the Control register. Also, it must initialize the Slave Monitor Pause register. The master attempts a transfer to a particular slave whenever the host writes to the I2C Address register. If the slave returns a NACK when it receives the address, the master waits for the time interval established by the Slave Monitor Pause register and attempts to address the slave again. The master continues this cycle until the slave responds with an ACK to its address or until the host clears the SLVMON bit in the Control register. If the addressed slave responds with an ACK, the I2C interface terminates the transfer by generating a STOP condition and a SLV_RDY interrupt.

20.2.4 Slave Mode

The I2C interface is set up as a slave by clearing the MS bit in the Control register. The I2C slave must be given a unique identifying address by writing to the I2C address register. The SCL speed must also be set up at least as fast as the fastest SCL frequency expected to be seen. When in slave mode, the I2C interface operates as either a slave transmitter or a slave receiver.

Extended Address Support

Extended addresses beyond seven bits are supported via the 10-bit address mode.

Slave Transmitter
The slave becomes a transmitter after recognizing the entire slave address sent by the master and when the R/W field in the last address byte sent is High. This means that the slave has been requested to send data over the I2C bus and the host is notified of this through an interrupt through an interrupt to the GIC (refer to Figure 20-1, page 555). At the same time, the SCL line is held Low to allow the host to supply data to the I2C slave before the I2C master starts sampling the SDA line. The host is notified of this event by setting the DATA interrupt flag.

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At the same time, the SCL line is held Low to allow the host to supply data to the I2C slave before the I2C master starts sampling the SDA line. The host must supply data for transmission through the I2C data register so that the SCL line is released and transfer continues. If it does not write to the I2C data register before the timeout period expires, an interrupt is generated and a TO interrupt flag is set. After the host writes to the I2C data register, the transfer continues by loading data in the FIFO while the transfer is in progress. The amount of data loaded in the FIFO might be a known system parameter or communicated in advance through a higher level protocol using the I2C bus. When there are only two valid bytes left in the FIFO for transmission, an interrupt is generated and the DATA interrupt flag is set. If the I2C master returns a NACK on the last byte transmitted from the FIFO, an interrupt is generated, and the COMP interrupt flag is set as soon as the I2C master generates a STOP condition. The transfer must continue if the master acknowledges on the last byte sent out from the FIFO. At that moment, the DATA interrupt flag is set. The TXDV flag in the Status register is cleared because the FIFO is empty. If the I2C master terminates the transfer before all of the data in the FIFO is sent by the slave, the host is notified, and the NACK interrupt flag is set while TXDV remains set and the Transfer Size register indicates the remaining bytes in the FIFO. The host must set the CLR_FIFO bit in the Control register to clear the FIFO and the TXDV bit.

Slave Receiver
The slave becomes a receiver after recognizing the entire slave address sent by the master and when the R/W bit in the first address byte is Low. This means that the master is about to send one or more data bytes to the slave over the I2C bus. After a byte is acknowledged by the I2C slave, the RXDV bit in the Status register is set, indicating that new data has been received. The host reads the received data through the I2C Data register. An interrupt is generated and the DATA interrupt flag is set when there are only two free locations left in the FIFO. Whenever the I2C master generates a STOP condition, an interrupt is generated and the COMP interrupt flag is set. The Transfer Size register then contains the number of bytes received that are available in the FIFO. This number is decremented by the host on each read of the I2C Data register. If the FIFO is full when one or more bytes are received by the I2C interface, an interrupt is generated and the RX_OVF interrupt flag is set. The last byte received is not acknowledged and the data in the FIFO is kept intact. The HOLD bit can be set in the Control register to avoid overflow conditions when it is impossible to respond to interrupts in a reasonable time. If the HOLD bit is set, the I2C interface keeps the SCL line Low until the host clears resources for data reception. This prevents the master from continuing with the transfer, causing an overflow condition in the slave. The host clears resources for data reception by reading the data register. If the HOLD bit is set and the I2C interface keeps the SCL line Low for longer than the timeout period, an interrupt is generated and the TO interrupt flag is set.

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20.2.5 I2C Speed

The main clock used within the I2C interface is the clock enable signal (see Figure 20-3). In slave mode, the clock enable is used to extract synchronization information for correct sampling of the SDA line. In master mode, the clock enable is used to establish a time base for generating the desired SCL frequency.
divisor_a divisor_b

X-Ref Target - Figure 20-3

Clock_Enable CPU_1x Clock

1 to 4 divider

1 to 64 divider

UG585_c20_03_022912

Figure 20-3:

I2C Clock Generator

The frequency of the clock_enable signal is defined by the frequency of the CPU_1x clock and the values of divisor_a and divisor_b using Equation 20-1

FreqCPU_ 1 x FreqClock_Enable = ( divisor_a + 1 ) ( divisor_b + 1 )

Equation 20-1

Note: As seen from the above calculation, the SCL clock frequency range is limited by the cpu_1x

clock. This means that for some cpu_1x clock rates there will be some SCL frequencies that are not possible. See I2C register map in Appendix B, Register Details for details of register fields.

Table 20-1 lists the calculated values for standard and high speed SCL clock values. A programming example is provided in Section 20.3.2. I2C SCL Clock = CPU_1X_Clock / (22 * (divisor_a + 1) * (divisor_b + 1)) Table 20-1:
100 KHz 400 KHz 100 KHz 400 KHz 100 KHz

Calculated Values for Standard and High Speed SCL Clock Values CPU_1X_Clock
111 MHz 111 MHz 133 MHz 133 MHz 166 MHz

I2C SCL Clock

divisor_a
2 0 0 2 3

divisor_b
16 12 60 4 16

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20.2.6 Multi-Master Operation

In I2C multi master mode, the bus is shared with other masters. In this mode, the I2C clock (I2C_SCL)is driven by the device that acts as the master.

20.2.7 I2C0-to-I2C1 Connection

The I/O signals of the two I2C controllers in the PS are connected together when the slcr.MIO_LOOPBACK [I2C0_LOOP_I2C1] bit is set = 1 . In this mode, the serial clocks are connected together and the serial data signals are connected together.

20.2.8 Status and Interrupts

The registers i2c.Interrupt_status_reg0, i2c.Intrpt_mask_reg0, i2c.Intrpt_enable_reg0 and i2c.Intrpt_disable_reg0 provide interrupt capability. See Table 20-2 for Interrupt and Status register names and bit assignments. Table 20-2: Interrupt and Status Register Names and Bit Assignments 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10
i2c.Interrupt_status_reg0 i2c.Intrpt_mask_reg0 i2c.Intrpt_enable_reg0 i2c.Intrpt_disable_reg0 X X X X X X X X X X X X

ARB_LOST X

X BA

RX_UNF RXOVF

TX_OVF TXDV

RX_OVF RXDV

SLV_RDY X

TO RX_RW

NACK X

DATA X

COMP X

i2c.Status_reg0

Interrupt Mask Register

Intrpt_mask_reg0 is a read-only interrupt mask register used to enable/disable individual interrupts in the i2c.interrupt_status_reg0 register: If the mask bit = 0 , the interrupt is enabled. If the mask bit = 1 , the interrupt is disabled.

This mask is controlled by the write-only Intrpt_enable_reg0 and Intrpt_disable_reg0 registers. Each associated enable/disable interrupt bit should be set mutually exclusive (e.g., to enable an interrupt, write 1 to Intrpt_enable_reg0[x] and write 0 to Intrpt_disable_reg0[x]).

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Interrupt Status Register

All the bits are sticky. Read: Reads interrupt status. Write: Write 1 to clear

Status Register
All bits present the raw status of the interface. Bits in this register dynamically change based on FIFO and other conditions.

20.3 Programmers Guide

20.3.1 Start-up Sequence
1. 2. Reset controller: Programming resets is described in section 20.4.2 Reset Controller. Configure I/O signal routing : I2C signals SCL and SDA can be routed to either MIO or EMIO. Refer to Table 20-4. Example of I2C SCL and SDA signal routed to MIO is provided in section 20.5.1 Pin Programming. Configure Clocks: The I2C clock architecture is described in section 20.4.1 Clocks. Controller Configuration: Program I2C transfer parameters using i2c.Control_reg0 etc. Refer to section 20.4.2 Reset Controller. Configure Interrupts: Interrupts help to control data in FIFO. Refer to section 20.2.8 Status and Interrupts and programming example in section 20.3.3 Configure Interrupts. Data Transfers: Transfers in master mode and slave monitor mode can be referred in section 20.3.4 Data Transfers.

3. 4. 5. 6.

20.3.2 Controller Configuration

The user should choose interface mode, addressing mode, direction of transfer, timeout, and program the I2C bus speed before initiating an I2C transfer. Optionally, the user can clear FIFOs and hold the bus if required, in case of large data or combined transfers.

Example: Master Write Transfer

1. Configure the Control parameters . Write 0x0000_324E to the i2c.Control_reg0 register: a. c. Select Master mode: Set i2c.Control_reg0[MS] = 1 . Select Normal Addressing [7-bit] mode: Set i2c.Control_reg0[NEA] = 1 . b. Set Direction of transfer as Master Transmitter: Set i2c.Control_reg0[RW] = 0 . d. Enable the transmission of ACK: Set i2c.Control_reg0[ACKEN] = 1 .

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e. f.

Clear the FIFOs: Set i2c.Control_reg0[CLR_FIFO] = 1 . Program the clock divisors: Set i2c.Control_reg0[divisor_a] = 0. Set i2c.Control_reg0[divisor_b] = 50.

These divisors generate an I2C SCL of 99 KHz using the CPU_1X clock of 111 MHz. For further details refer to section 20.2.5 I2C Speed . 2. Configure Timeout. Write 0x0000_00FF to the i2c.Time_out_reg0 register. Wait 255 SCL cycles when the SCL is held Low, before generating a timeout interrupt.

20.3.3 Configure Interrupts

The interrupts are described in section 20.2.8 Status and Interrupts . The i2c.Intrpt_enable_reg0 register has bits to enable the interrupt mask and i2c.Intrpt_disable_reg0 has bits to forcefully disable the interrupts. Each pair of bits should be set mutually exclusive:

Example: Program Example to Configure Completion Interrupt

1. Enable the completion interrupt . Set the enable bit, clear the disable bit, and verify the mask value: a. c. 2. Set i2c.Intrpt_enable_reg0[COMP] = 1. i2c.intrpt_mask_reg0[COMP] reads back = 1 . b. Clear i2c.Intrpt_disable_reg0[COMP] = 0 . Disable the completion interrupt . Set the enable bit, clear the disable bit, and verify the mask value: a. c. 3. Set i2c.Intrpt_disable_reg0[COMP] = 1 . i2c.Intrpt_mask_reg0[COMP] reads back = 0 . b. Clear i2c.Intrpt_enable_reg0[COMP] = 0 . Monitor completion interrupt . I2c.Interrupt_status_reg0 provides status of completion interrupt.: a. 4. Read i2c.Interrupt_status_reg0 [COMP]. 1 indicates that an interrupt occurred. Clear completion interrupt . Write 1 to the i2c.Interrupt_status_reg0[COMP] bit field.

20.3.4 Data Transfers

Transfers can be achieved in polled mode or interrupt driven mode. Limitation on data count while performing a master read transfer is 255 bytes. Below are examples of read and write transfer in Master mode and example for Slave Monitor mode. Refer to section 20.2.3 Slave Monitor Mode for details.

Example: Master Read Using Polled Method

1. Set direction of transfer as read and clear the FIFOs. Write 0x41 to i2c.Control_reg0.

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2. 3.

Clear interrupts. Read and write back the read value to i2c.Interrupt_status_reg0. Write read data count to transfer size register and hold bus if required. Write read data count value to i2c.Transfer_size_reg0. If read data count greater than FIFO depth , set i2c.Control_reg0 [HOLD] = 1 . Write the slave address . Write the address to the i2c.I2C_address_reg0 register. Wait for data to be received into the FIFO. Poll on i2c.Status_reg0 [RXDV] = 1 . a. If i2c.Status_reg0 [RXDV] = 0 , and any of i2c.Interrupt_status_register [NACK], i2c.Interrupt_status_register [ARB_LOST], i2c.Interrupt_status_register [RX_OVF], i2c.Interrupt_status_register [RX_UNF] interrupts are set, then stop the transfer and report the error, otherwise continue to poll on i2c.Status_reg0 [RXDV].

4. 5.

b. If i2c.Status_reg0 [RXDV] = 1 , and if any of i2c.Interrupt_status_register [NACK], i2c.Interrupt_status_register [ARB_LOST], i2c.Interrupt_status_register [RX_OVF], i2c.Interrupt_status_register [RX_UNF] interrupts are set, then stop the transfer and report the error. Otherwise, go to step c. c. If read data count is less than or equal to FIFO depth, count of bytes to read is equal to read data count and go to step 7.

d. Subtract value of i2c.Transfer_size_reg0 from read data count to get count of bytes to read. 6. 7. 8. Update Read data count . Subtract count of bytes to read from read data count. Check if read data count is less than or equal to FIFO depth, clear i2c.Control_reg0[HOLD]. Read data from FIFO. Read data using count of bytes to read in step 5c or 5d from i2c.I2C_data_reg0. Check for Completion of transfer. If total read count is reached, poll on i2c.Interrupt_status_reg0 [COMP] = 1 . Otherwise continue from step 5.

Example: Master Write Using Polled Method

1. 2. 3. 4. 5. 6. Set Direction of transfer as write and Clear the FIFOs . Write 0x40 to i2c.Control_reg0. Clear Interrupts. Read and write back the read value to i2c.Interrupt_status_reg0. Calculate the space available in FIFO. Subtract i2c.Transfer_size_reg0 value from FIFO depth. Fill the data into FIFO. Write the data to i2c.I2C_data_reg0 based on the count obtained in step 3. Write the Slave Address . Write the address to i2c.I2C_address_reg0 register. Wait for TX FIFO to be empty. Poll on i2c.Status_reg0 [TXDV] = 0 . a. If i2c.Status_reg0 [TXDV] = 1 , any of i2c.Interrupt_status_register [NACK], i2c.Interrupt_status_register [ARB_LOST], i2c.Interrupt_status_register [RX_OVF], i2c.Status_register [TX_OVF] are set, then stop the transfer and report the error otherwise continue to poll.

b. If i2c.Status_reg0 [TXDV] = 0 , repeat step 3, 4 and 6 until there is no further data. 7. Wait for completion of transfer. Check for i2c.Interrupt_status_reg0 [COMP] = 1 .

Example: Master Read Using Interrupt Method

1. 2. Set direction of transfer as read and clear the FIFOs. Write 0x41 to i2c.Control_reg0. Clear interrupts. Read and write back the read value to i2c.Interrupt_status_reg0.

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3. 4.

Enable Timeout, NACK, Rx overflow, Arbitration lost, DATA, Completion interrupts . Write 0x22F to i2c.Intrpt_en_reg0. Write read data count to transfer size register and hold bus if required. Write read data count value to i2c.Transfer_size_reg0. If read data count greater than FIFO depth , set i2c.Control_reg0 [HOLD]. Write the slave address . Write the address to the i2c.I2C_address_reg0 register. Wait for data to be received into FIFO. a. If read data count is greater than FIFO depth, wait for i2c.Interrupt_status_reg0 [DATA] = 1 . Subtract the value of i2c.Transfer_size_reg0 from the read data count to get the count of bytes to read.

5. 6.

b. Otherwise, wait for i2c.Interrupt_status_reg0 [COMP] = 1 and go to step 8. Here the count of bytes to read is equal to the read data count. 7. 8. 9. Update read data count . Subtract the count of bytes to read from the read data count. Check if the read data count is less than or equal to FIFO depth, clear i2c.Control_reg0[HOLD]. Read data from FIFO. Read data based on the count of bytes to read in step 6a or 6b from i2c.I2C_data_reg0. Check for completion of transfer. Check if the bytes read matches the total read count. Otherwise repeat from step 6.

Example: Master Write Using Interrupt Method

1. 2. 3. 4. 5. 6. 7. 8. Set direction of transfer as write and clear the FIFOs . Write 0x40 to i2c.Control_reg0. Clear Interrupts. Read and write back the read value to i2c.Interrupt_status_reg0. Enable Timeout, NACK, Tx Overflow, Arbitration lost, DATA, Completion interrupts . Write 0x24F to the i2c.Intrpt_en_reg0 register. Enable bus HOLD logic . Set i2c.Control_reg0 [HOLD] if the write data count is greater than the FIFO depth. Calculate the space available in FIFO. Subtract the i2c.Transfer_size_reg0 value from the FIFO depth. Fill the data into FIFO. Write the data to i2c.I2C_data_reg0 based on the count obtained in step 5. Write the slave address . Write the address to the i2c.I2C_address_reg0 register. Wait for data to be sent . Check for i2c.Interrupt_status_reg0 [COMP] to be set. a. 9. If further data is to be written, repeat steps 5, 6 and 8. b. If there is no further data, set i2c.Control_reg0 [HOLD] = 0 . Wait for completion of transfer. Check for i2c.Interrupt_status_reg0 [COMP] to be set.

Example: Slave Monitor Mode

Slave monitor mode helps to monitor when the slave is in the busy state. The slave ready interrupt occurs only when slave is not busy. This can be done only in master mode: 1. 2. Select slave monitor mode and clear the FIFOs. Write 0x60 to i2c.Control_reg0. Clear interrupts. Read and write back the read value to i2c.Interrupt_status_reg0.

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3. 4. 5. 6.

Enable Interrupts . Set i2c.Intrpt_en_reg0 [SLV_RDY] = 1 . Set slave monitor delay. Set i2c.Slave_mon_pause_reg0 with 0xF. Write the Slave Address . Write the address to the i2c.I2C_address_reg0 register. Wait for slave to be ready. Poll on i2c.Interrupt_status_reg0 [SLV_RDY] = 1 .

20.3.5 Register Overview

An overview of the I2C registers is provided in Table 20-3. Table 20-3: I2C Register Overview Register Names
Control_reg0 I2C_address_reg0 I2C_data_reg0 Transfer_size_register0 Slave_mon_pause_reg0 Time_out_reg0 Staus_reg0 Interrupt_status_reg0 Interrupt_mask_reg0 Interrupt_enable_reg0 Interrupt_disable_reg0

Function
Configuration Data

Overview
Configure the operating mode Transfer data and monitors status.

Interrupt Processing

Enable/disable interrupt detection, mask interrupt set to the interrupt controller, read raw interrupt status.

20.4 System Functions

20.4.1 Clocks
The controller, I/O interface and APB interconnect are driven by CPU_1X clock. This clock comes from the PS clock subsystem.

PS Clock Subsystem
CPU_1x Clock
Refer to section 25.2 CPU Clock, for general clock programming information.

Operating Restrictions
The clock operating restrictions are described in section 20.1.2 Notices.

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20.4.2 Reset Controller

The controller reset bits are generated by the PS, see Chapter 26, Reset System.

Example: Controller Reset

1. 2. Assert Controller Reset : Set slcr.I2C_RST_CTRL[I2Cx_CPU1X_RST] bit = 1. De-assert Controller Reset : Clear slcr.I2C_RST_CTRL[I2Cx_CPU1X_RST] bit = 0 .

20.5 I/O Interface

20.5.1 Pin Programming
The I2C SCL and SDA signals can be routed to one of many sets of MIO pins or to the EMIO interface. All of the I2C signals are listed in Table 20-2. The routing of the SCL and SDA signals are described in section 2.5 PS-PL MIO-EMIO Signals and Interfaces.

Example: Route I2C 0 SCL and SDA Signals to MIO Pins 50, 51
In this example, the I2C 0 SCL and SDA signals are routed through MIO pins 50 and 51. Many other pin options are possible. 1. Configure MIO pin 50 for the SCL signal. Write 0x0000_1240 to the slcr.MIO_PIN_50 register: a. c. e. f. 2. a. c. e. f. Route I2C 0 SCL signal to pin 50. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. Route I2C 0 SDA signal to pin 51. LVCMOS18 (refer to the register definition for other voltage options). Enable internal pull-up resistor. Disable HSTL receiver. b. 3-state controlled by I2C (set TRI_ENABLE = 0 ). d. Slow CMOS edge (benign setting).

Configure MIO pin 51 for the SDA signal. Write 0x0000_1240 to the slcr.MIO_PIN_51 register: b. 3-state controlled by the I2C (set TRI_ENABLE = 0 ). d. Slow CMOS drive edge.

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20.5.2 MIO-EMIO Interfaces

Table 20-4 identifies the interface signals to the I2C controller. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 20-4: I2C MIO Pins and EMIO Signals Default Controller Input Value Numbers MIO Pins EMIO Signals I/O Name
EMIOI2C0SCLI I2C 0, Serial Clock 0 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50 IO EMIOI2C0SCLO EMIOI2C0SCLTN EMIOI2C0SDAI I2C 0, Serial Data ~ 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51 IO EMIOI2C0SDAO EMIOI2C0SDATN EMIOI2C1SCLI I2C 1, Serial Clock 0 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52 IO EMIOI2C1SCLO EMIOI2C1SCLTN EMIOI2C1SDAI I2C 1, Serial Data ~ 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53 IO EMIOI2C1SDAO EMIOI2C1SDATN

I2C Interface

I/O
O I I O I I O I I O I I

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Programmable Logic Description

21.1 Introduction
The Zynq-7000 AP SoC devices integrates a feature-rich dual-core ARM Cortex-A9 MPCore based processing system (PS) and Xilinx programmable logic (PL) in a single device. Each Zynq-7000 device contains the same PS while the PL and I/O resources vary between the devices. The PL of the two smallest devices, the 7z010 and the 7z020 is based on Artix-7 FPGA logic. The three biggest devices, the 7z030, 7z045, and 7z100 are based on Kintex-7 FPGA logic. For details about resources, refer to DS190, Zynq-7000 All Programmable SoC Overview. The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals that have a combined total of over 3,000 connections. This enables the designer to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors and can also access memory resources in the PS. Zynq customers are able to differentiate their product in hardware by customizing their applications using PL. The processors in the PS always boot first, allowing a software centric approach for PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplex the PL resources by swapping in new algorithms as needed. This latter capability is analogous to the dynamic loading and unloading of software modules. The PL configuration data is referred to as a bitstream. The PL can be on a separate power domain from the PS. This enables users to save power by completely shutting down the PL. In this mode, the PL consumes no static or dynamic power, thus significantly reducing the power consumption of the device. The PL must be reconfigured when coming out of this mode. Users need to take into account the re-configuration time of the PL for their particular application as this varies depending on the size of the bitstream for their application.

21.1.1 Features
The PL provides a rich architecture of user-configurable capabilities. The key features are: Configurable logic blocks (CLB)

6-input look-up tables (LUTs) Memory capability within the LUT Register and shift register functionality

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Cascadable adders Dual port Up to 72 bit-wide Configurable as dual 18 KB Programmable FIFO logic Built-in error correction circuitry 25 18 two's complement multiplier/accumulator high-resolution 48-bit multiplier/accumulator Power saving 25-bit pre-adder to optimize symmetrical filter applications Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading High-speed buffers and routing for low-skew clock distribution Frequency synthesis and phase shifting Low-jitter clock generation and jitter filtering High-performance SelectIO technology High-frequency decoupling capacitors within the package for enhanced signal integrity Digitally controlled impedance that can be 3-stated for lowest power, high-speed I/O operation High-range (HR) I/O supporting 1.2V to 3.3V High performance (HP) I/Os support 1.2V to 1.8V (7z030, 7z045, and 7z100 devices) High-performance transceivers capable of up to 12.5 Gb/s (GTX) Low-power mode optimized for chip-to-chip interfaces Advanced transmit pre and post emphasis, and receiver linear (CTLE) and decision feedback equalization (DFE), including adaptive equalization for additional margin Compatible with the PCI Express Base Specification 2.1 with Endpoint and Root Port capability Supports Gen2 (5.0 Gb/s) Advanced configuration options, advanced error reporting (AER), and end-to-end CRC (ECRC) advanced error reporting and ECRC features

36 KB block RAM

Digital signal processing DSP48E1 Slice

Clock management

Configurable I/Os

Low-power serial transceivers (Z-7030 and Z-7045 devices)

Integrated interface block for PCI Express designs

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21.1.2 PL Resources by Device Type

The PL resources on a per-device type are summarized in Table 21-1. Table 21-1:
PL Resource Logical Resources
Slices SLICEL SLICEM 6-input LUTs Distributed RAM (Kb) Shift Register (Kb) 4400 2900 1500 17600 375 187 13300 8950 4350 53200 1088 522 19650 13000 6650 78600 1663 831 54650 37050 17600 218600 4400 2200 69350 42300 27050 277400 6763 3381

PL Resources by Device Type 7z010 7z020 7z030 7z045 7z100

Memory Resources
Block RAMs per device Number of 36 Kb block RAM columns per device Number of 36 Kb block RAMs per column 60 5 Varies, usually 20 140 6 Varies, usually 30 265 8 Varies, usually 40 545 9 Varies, usually 70 755 12 Varies, usually 70

DSP Resources
Total DSP48E1 slices per device Number of DSP48E1 columns per device Number of DSP48E1 slices per column 80 4 Varies, usually 40 220 5 Varies, usually 60 400 6 Varies, usually 80 900 7 Varies, usually 140 2020 15 Varies, usually 140

Clocking Resources
MMCM PLL 2 2 4 4 5 5 8 8 8 8

I/O Resources(1)
HR I/O HP I/O GTX Transceivers Notes:
1. This table shows the maximum I/Os that are available for each device type (those available in the devices largest package.) Refer to the Zynq-7000 AP SoC Overview for I/O counts of all packages.

100 -

200 -

100 150 4

212 150 16

250 150 16

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21.1.3 Notices
XADC Analog Mixed Signal Module (AMS)
The XADC is physically located in the PL and is powered by the PL. To use the XADC module, the PL must be powered up, but the PL does not need to be configured. The XADC is explained in Chapter 30, XADC Interface.

Device Configuration (DevC)

The device configuration module (with option to use AES/HMAC decryption) is physically located in the PL and is powered by the PL. To use the device configuration module, the PL must be powered up but does not need to be configured. Device configuration is explained in section 6.4 Device Configuration Interface.

21.2 PL Components
21.2.1 CLBs, Slices, and LUTs
Some key features of the Configurable Logic Blocks (CLB) architecture include: True 6-input Look Up Tables (LUT)s Memory capability within the LUT Register and shift register functionality

The LUTs in the Zynq-7000 AP SoC can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be configured to drive a flip-flop. A single LUT contains two flip-flops, a multiplexer (mux), and arithmetic carry logic. Two LUTs form a slice. And two slices form a Configurable Logic Block (CLB). Each LUT can have one of its two flip-flops configured as a latch. Between 2550% of all slices can use their LUTs as distributed 64-bit RAM, as 32-bit shift register (SRL32), or as two 16-bit shift registers (SRL16). Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. For more details on Configuration Logic Blocks, see UG474 , 7 Series FPGAs Configurable Logic Block User Guide.

21.2.2 Clock Management

Some of the key highlights of the clock management architecture include: High-speed buffers and routing for low-skew clock distribution

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Frequency synthesis and phase shifting Low-jitter clock generation and jitter filtering

Each Zynq-7000 AP SoC device has up to eight clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL).

Mixed-Mode Clock Manager and Phase-Locked Loop

The mixed-mode clock manager (MMCM) and the phase-locked loop (PLL) share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD). There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via Dynamic Configuration Port (DRP)) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. The values of D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0,45, 90, 135, 180, 225, 270, and 315). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: Low-bandwidth mode which has the best jitter attenuation; high-bandwidth mode, which has the best phase offset; and optimized mode, which allows the tools to find the best setting.

MMCM Additional Programmable Features

The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of eight. The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1,600 MHz, the phase-shift timing increment is 11.2 ps.

Clock Distribution
Each Zynq-7000 AP SoC device provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.

Global Clock Lines

In each Zynq-7000 AP SoC device, 32 global clock lines have the highest fanout and can reach every flip-flop clock, clock enable, and set/reset as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be

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independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.

Regional Clocks
Regional clocks can drive all clock destinations in their region. A region is defined as any area that is 50 I/O and 50 CLB high and half the device wide. Zynq-7000 AP SoC devices have between eight and twenty-four regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8.

I/O Clocks
I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in Input/Output. Direct connection from the MMCM to the I/O is provided for low-jitter, high-performance interfaces. For more details on clocking resources, see UG472 , Series FPGAs Clocking Resources User Guide .

21.2.3 Block RAM

Some of the key features of the block RAM include: Dual-port 36 KB block RAM with port widths of up to 72 Programmable FIFO logic Built-in optional error correction circuitry

Every Zynq-7000 AP SoC device has between 60 and 465 dual-port block RAMs, each storing 36 Kb. Each block RAM has two completely independent ports that share nothing but the stored data.

Synchronous Operation
Each memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.

Programmable Data Width

Each port can be configured as 32K 1, 16K 2, 8K 4, 4K 9 (or x8), 2K 18 (or x16), 1K 36 (or 32), or 512 72 (or x64). The two ports can have different widths without any constraints.

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Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any aspect ratio from 16K 1 to 512 36. Everything described previously for the full 36 Kb block RAM also applies to each of the smaller 18 Kb block RAMs. Only in simple dual-port (SDP) mode can data widths of greater than 18 bits (18 Kb RAM) or 36 bits (36 Kb RAM) be accessed. In this mode, one port is dedicated to read operations, the other to write operations. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72. Both sides of the dual-port 36 Kb RAM can be of variable width. Two adjacent 36 Kb block RAMs can be configured as one 64K 1 dual-port RAM without any additional logic.

Error Detection and Correction

Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.

FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width. First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode. For more details on Block RAM, see UG473, 7 Series FPGAs Memory Resources User Guide.

21.2.4 Digital Signal Processing DSP Slice

Some highlights of the DSP functionality include: 25 18 two's complement multiplier/accumulator high-resolution (48 bit) signal processor Power saving pre-adder to optimize symmetrical filter applications Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All Zynq-7000 AP SoC devices have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining system design flexibility. Each DSP slice fundamentally consists of a dedicated 25 18 bit two's complement multiplier and a 48-bit accumulator. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit or quad 12-bit

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adder/subtracter/accumulator), or a logic unit that can generate any one of ten different logic functions of the two operands. The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide pattern detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing 96-bit-wide logic functions when used in conjunction with the logic unit. The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter. For more details on DSP slices, see UG479 , 7 Series FPGAs DSP48E1 User Guide.

21.3 Input/Output
21.3.1 PS-PL Interfaces
The PS-PL interface contains all the signals available to the PL designer for integrating the PL-based functions and the PS. There are two types of interfaces between the PL and the PS: 1. Functional interfaces available for connecting with user-designed IP blocks in the PL a. c. e. f. 2. AXI interconnect Interrupts Clocks Debug interfaces b. Extended MIO interfaces for most of the I/O Peripherals d. DMA flow control

Configuration interface connected to fixed logic within the PL configuration block, providing PS control a. c. PCAP SEU b. Configuration status d. Program/Done/Init

For details on PS-PL interfaces refer to Chapter 2, Signals, Interfaces, and Pins.

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Voltage Level Shifters

All of the signals between the PS and PL pass through voltage level shifters. The programming of these level shifters is explained in section PS-PL Voltage Level Shifters, page 41.

21.3.2 SelectIO
Some highlights of the input/output functionality include: High-performance SelectIO technology with support for 1,866 Mb/s DDR3 High-frequency decoupling capacitors within the package for enhanced signal integrity Digitally controlled impedance that can be 3-stated for lowest power, high-speed I/O operation

The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other PL pins have the same I/O capabilities, constrained only by certain banking rules. The SelectIO resources in Zynq-7000 AP SoC devices are classed as either high range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.2V to 1.8V. All I/O pins are organized in banks, with 50 pins per bank. Each bank has one common VCCO output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an externally applied reference voltage (V REF). There are two VREF pins per bank (except configuration bank 0). A single bank can have only one V REF voltage value. Zynq-7000 AP SoC devices use a variety of package types to suit the needs of the user, including small form factor wire-bond packages for lowest cost; conventional, high performance flip-chip packages; and lidless flip-chip packages that balance smaller form factor with high performance. In the flip-chip packages, the silicon device is attached to the package substrate using a high-performance flip-chip process. Controlled ESR discrete decoupling capacitors are mounted on the package substrate to optimize signal integrity under simultaneous switching of outputs (SSO) conditions.

I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure driving High towards VCCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-down resistor. Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be terminated with a 100 internal resistor. All Zynq-7000 AP SoC devices support differential standards beyond LVDS: HT, RSDS, BLVDS, differential SSTL, and differential HSTL. Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to 1,866 Mb/s for DDR3 interfacing applications.

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3-State Digitally Controlled Impedance and Low-Power I/O Features

The 3-state digitally controlled impedance (T_DCI) can control the output drive impedance (series termination) or can provide parallel termination of an input signal to VCCO or split (Thevenin) termination to VCCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board space savings, the termination automatically turns off when in output mode or when 3-stated, saving considerable power compared to off-chip termination. The I/Os also have low-power modes for IBUF and IDELAY to provide further power savings, especially when used to implement memory interfaces.

I/O Logic
Input and Output Delay
All inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input and some outputs can be individually delayed by up to 32 increments of 78 ps or 52 ps each. Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by configuration and can also be incremented or decremented while in use. ODELAY is only available for HP Select I/O. It is not available for HR select I/Os. This means that it is only available for Z-7030 and Z-7045 devices.

ISERDES and OSERDES

Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This requires a serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin possesses an 8-bit IOSERDES (ISERDES and OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5, 6, 7, or 8 bits. By cascading two IOSERDES from two adjacent pins (default from differential I/O), wider width conversions of 10 and 14 bits can also be supported. The ISERDES has a special oversampling mode capable of asynchronous data recovery for applications like a 1.25 Gb/s LVDS I/O-based SGMII interface. For more details on Select I/Os, see UG471 , 7 Series FPGAs SelectIO Resources User Guide.

21.3.3 Low-Power Serial Transceivers

Low-power serial gigabit transceivers are only available in the 7z030, 7z045, and 7z100 devices. The 7z030 has 4 transceivers. The 7z045 and 7z100 devices each has 16 transceivers. Some highlights of the low-power gigabit transceivers include: High-performance transceivers capable of up to 12.5 Gb/s line rates with flipchip packages and up to 6.6Gb/s with bare-die flipchip packages. Low-power mode optimized for chip-to-chip interfaces. Advanced Transmit pre and post emphasis, and receiver linear (CTLE) and decision feedback equalization (DFE), including adaptive equalization for additional margin

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Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the backplane, or over longer distances is becoming increasingly popular and important to enable customer line cards to scale to 200 Gb/s. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity issues at these high data rates. The Zynq-7000 AP SoC devices transceiver counts range from 0 to 16 transceiver circuits. Each serial transceiver is a combined transmitter and receiver. The various Zynq-7000 serial transceivers can use a combination of ring oscillators and LC tank architecture to allow the ideal blend of flexibility and performance while enabling IP portability across the family members. Lower data rates can be achieved using logic-based oversampling of PL. The serial transmitter and receiver are independent circuits that use an advanced PLL architecture to multiply the reference frequency input by certain programmable numbers between 4 and 25 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation.

Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, 40, 64, or 80. This allows the designer to trade-off datapath width for timing margin in high-performance designs. These transmitter outputs drive the PC board with a single-channel differential output signal. TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from the internal logic. The incoming parallel data is fed through an optional FIFO and has additional hardware support for the 8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a sufficient number of transitions. The bit-serial output signal drives two package pins with differential signals. This output signal pair has programmable signal swing as well as programmable pre- and post-emphasis to compensate for PC board losses and other interconnect characteristics. For shorter channels, the swing can be reduced to reduce power consumption.

Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential signal into a parallel stream of words, each 16, 20, 32, 40, 64, or 80 bits. This allows the designers to trade-off internal datapath width versus logic timing margin. The receiver takes the incoming differential data stream, feeds it through programmable linear and decision feedback equalizers (to compensate for PC board and other interconnect characteristics), and uses the reference clock input to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into the PL using the RXUSRCLK clock. For short channels, the transceivers offers a special low power mode (LPM) for additional power reduction.

Out-of-Band Signaling
The transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the transmitter to the receiver while high-speed serial data transmission is not active. This is typically done when the link is in a powered-down state or has not yet been initialized. This benefits PCI Express and SATA/SAS applications.

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For more details on GTX Transceivers, see UG476 , 7 Series FPGAs GTX Transceiver User Guide.

21.3.4 Integrated I/O Block for PCIe

The integrated PCI Express I/O block is only available in Z-7030 and Z-7045 devices. Highlights of the integrated blocks for PCI Express include: Compatible with the PCI Express Base Specification 2.1 with Endpoint and Root Port capability Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) Advanced configuration options, advanced error reporting (AER), and end-to-end CRC (ECRC) advanced error reporting and ECRC features in the integrated block depending on family

All Zynq-7000 AP SoC devices with transceivers include an integrated block for PCI Express technology that can be configured as an Endpoint or Root Port, compatible with the PCI Express Base Specification Revision 2.1. The Root Port can be used to build the basis for a compatible Root Complex, to allow custom communication between the Zynq-7000 AP SoC device and other devices via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet controllers or fibre channel HBAs, to the Zynq-7000 devices. This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s and 5.0 Gb/s data rates. For high-performance applications, advanced buffering techniques of the block offer a flexible maximum payload size of up to 1,024 bytes. The integrated block interfaces to the integrated high-speed transceivers for serial connectivity and to block RAMs for data buffering. Combined, these elements implement the physical layer, data link layer, and transaction layer of the PCI Express protocol. Xilinx provides a light-weight, configurable, easy-to-use LogiCORE IP wrapper that ties the various building blocks (the integrated block for PCI Express, the transceivers, block RAM, and clocking resources) into an Endpoint or Root Port solution. The system designer has control over many configurable parameters: lane width, maximum payload size, programmable logic interface speeds, reference clock frequency, and base address register decoding and filtering. Xilinx offers AXI4 memory mapped wrapper for the integrated block. AXI4 (memory mapped) is designed for Xilinx Platform Studio/EDK design flow and MicroBlaze processor based designs. For more details on PCIe, see UG477, 7 Series FPGAs Integrated Block v1.3 for PCI Express User Guide.

21.4 Configuration
Xilinx 7 series FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 17 and 107 Mbits, depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. The Processing System can reload the configuration at any time. For details about different boot and configuration modes refer to Chapter 6, Boot and Configuration.

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Table 21-2:

PL Bitstream Lengths Length (Mbits)

16,669,920 32,364,512 47,839,328 106,571,232

Zynq 7000 AP SoC Device

7z010 7z020 7z030 7z045 7z100

Length, rounded up (MBs)

2 3.9 5.8 12.8

In all Zynq-7000 AP SoC devices, the PL bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. The PL performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in battery-backed RAM or in nonvolatile eFUSE bits. Most configuration data can be read back without affecting the system's operation. Typically, configuration is an all-or-nothing operation, but Zynq-7000 AP SoC devices also support partial reconfiguration. This is an extremely powerful and flexible feature that allows the user to change portions of the logic in the PL while other portions remain static. Users can time-slice these portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can greatly improve the versatility of the Zynq-7000 AP SoC device.

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22.1 Introduction
This chapter covers the following topics: Programmable Logic for Software Offload is intended to introduce the user to high-level concepts of using the Programmable Logic (PL) to offload CPU functions. PL and Memory System Performance Overview discusses various performance-related behaviors of memory paths through the PS. Choosing a Programmable Logic Interface contrasts different PL interfaces available and shows typical uses.

22.2 Programmable Logic for Software Offload

Zynq devices have the unique capability of mapping software algorithms directly to programmable logic. Benefits may include reduced execution time, reduced operating power per function, reduced memory traffic and predictable low latency. This section describes these benefits from a general perspective. Later sections describe specific performance and potential programmable logic topologies.

22.2.1 Benefits of Using PL to Implement Software Algorithms

Performance
Algorithms implemented in programmable logic can often be scaled to a full parallel implementation delivering maximum throughput, or to an intermediate throughput level at lower area cost. This allows the performance of an algorithm to be scaled well beyond what is achievable on the A9 or NEON units. For example, consider an algorithm which requires 100 basic operations roughly equivalent to 100 instructions or lines of C code on the A9. A fully parallel programmable logic implementation might implement these operations using CLBs, DSP slices, and block RAMs. If the PL executes these 100 operations in parallel and is clocked at the rate of the ARM clock, this function would have a potential speedup of 25x. This assumes that the PL implementation is not limited by I/O or resources.

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Power
An additional benefit of moving operations to the programmable logic is a reduction in power. Depending on the operations, programmable logic can reduce power per OP by 10-100x. Thus it may be useful to implement algorithms in the PL solely to reduce system power. One issue to be aware of is that if the algorithm requires access to external memory, the energy cost of accessing the external memory could dominate the energy budget making a reduction in the operation power irrelevant.

Latency
Parallel logic in the PL has a low predictable delay, and cannot be interrupted. For this reason algorithms which are used to respond to real time events originating the in PL might best be serviced by algorithms in the programmable logic. This approach can reduce response time from thousands of clocks to tens of clocks.

22.2.2 Designing PL Accelerators

Programmable logic accelerators are typically created in the RTL languages Verilog or VHDL. Experienced RTL engineers can use C-code as a golden model to create an efficient hardware implementation of the algorithm in programmable logic. For software programmers who are more comfortable with the C language, C-to-Gates compilers exist which can allow a user to build HW accelerators using the C language. Keeping in mind that C is a sequential language, automated compiler methods can be used to map the sequential code to parallel hardware without user intervention. For instance, a FOR loop such as for(i=0; i<10; i++){ x[i]=a[i]+b[i]; } can be unrolled to create 10 individual adders all operating in parallel. For video and DSP algorithms, tools such as Matlab Simulink and Xilinx System Generator can be used to directly create logic from algorithmic flowgraphs. A primary advantage of using Matlab Simulink is the rich library of functions which can be used to model, simulate and verify the hardware implementation.

Dataflow
Regardless of how an accelerator or offload engine is designed, once implemented it requires efficient dataflow to and from the accelerator. In many cases, scheduling the dataflow between the accelerator and DRAM can be more of a design challenge than implementing the actual algorithm. The word dataflow is used to reference the motion of data between system memories and PL functional units using AXI interconnect and local interconnect.

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22.2.3 PL Acceleration Limits

The achievable speedup of an accelerator can be limited by I/O, resource, and latency requirements.

I/O Rate Limits

A key observation is that processing cannot proceed faster than the speed of the data transfers to and from the functional unit. For functions with a high ratio of operations to I/O the data rates will not be a limiting factor, however for operations with a low ratio of operations to I/O, dataflow will limit the maximum performance attainable. For example, assume 12 bytes of input data is being read from DDR and 4 bytes of results are written back to DDR. DDR3 at 32-bits, 1,066 Mb/s and 75% utilization is limited to roughly 3,200 Mb/s. If 16 bytes are required per operation, the dataflow limits the performance to 3,200/16, or 200M function/sec. Note that this is independent of the complexity of the function. Even a simple 3 input adder is limited by the DDR bandwidth to 200M operations/sec and is not likely to be faster than an ARM A9 CPU. If however, the function consists of several thousands of operations all of which can proceed in parallel, or in a pipelined fashion, then the PL can often achieve speedups of a 10-100x.

Resource Limits
While potential speedup can be quite high, the amount of logic in the PL can limit the achievable speedup. For instance, an application which requires 100 DSP slices to achieve a speedup of 24x might be limited to a 12x speedup if only 50 DSP slices are available.

Latency Limits
The examples above assume that the PL can effectively proceed without intervention by the ARM processor. This is the case in situations where the PL implements a predetermined algorithm and dataflow using pre-allocated buffers and data is not resident in caches. In cases where the processor is creating data for the PL accelerator, additional CPU tasks might be required before the PL can begin working on the data. The CPU might need to allocate buffers and pass physical buffer addresses to the PL, or data might be flushed from cache to DDR or OCM or signal the PL to start processing. These additional steps add delays (called latency) to the total processing time. If these delays are significant, the potential acceleration is reduced. Typically it takes 100-200 clocks for the ARM processor to write a few words of data to a PL function. In general, CPU to PL calling latency is not a significant impact for applications processing more than 4 KB of data.

22.2.4 Power Offload

The PL can be used to implement individual functions at lower energy cost than when executed on the ARM A9 application processors. Less energy per operation is required because when a function is implemented in the PL, data is transferred from operator to operator in a local assembly line fashion using short, low capacitance local connections. The same function implemented on a processor requires an instruction and data fetch from local caches or external memory and a result to be written back to registers or the memory system over longer, higher capacitance interfaces. When functions require data to be stored in memory, block

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RAM can be used at lower energy cost than processor caches. Table 22-1 summarizes the approximate energy cost for various functions implemented on both the A9 processor and the 7 series programmable logic. Table 22-1: Estimated Energy Costs for Common Operations PL Resource
LUT/FF LUT/FF DSP LUTRAM LUT/FF BRAM AXI/OCM AXI/DDR

Operation
Logical Op of 2 var 32-bit ADD 16x16 Mult 32-bit Read/Write register 32-bit Read/Write AXI register 32-bit Read/Write local RAM 32-bit Read/Write OCM 32-bit Read/Write DDR3 Notes:

ARM A9 Resource
ALU ALU ALU L1 AXI L2 CPU/OCM CPU/DDR

ARM A9 energy/OP (pico Joules or mW/GOP/sec)

PL energy/OP (pico Joules op mW/GOP/sec)

1.3 1.3 8.0 1.4 30 23.7/17.2 44 541/211

1. A9 energy costs estimated from ARM power indicative benchmarks. 2. PL Energy costs for custom programmable logic functions are estimated using the Xilinx XPE power estimator http://www.xilinx.com/ise/power_tools/license_7series.htm.

Typically, the energy cost to read or write external DDR memory is roughly the same and much larger than the operation cost. As a consequence the energy required by functions which require even a small percentage of external access is dominated by the energy cost of the external access and the total cost will be the same in both PL and CPU implementations. Thus a key to minimizing energy cost is to localize data movement to the PL. If space allows, rather than storing data structures off chip, store them in OCM, BRAM, LUTRAM or flip-flops and avoid the use of unnecessary storage. This approach may require code to be restructured to avoid the use of unnecessary buffers.

22.2.5 Real Time Offload

The ARM A9 CPUs are optimized for application processing rather than real-time response and are often running an operating system such as Linux. The PL can be used augment the A9s with excellent real time response.

MicroBlaze Assisted Real Time Processing

One or more MicroBlaze processors can be used to as microcontrollers to manage reatime events. MicroBlaze offers excellent real-time response and can be dedicated to particular tasks. MicroBlaze controllers can typically use a few block RAMs, approximately 2,000 LUTs, and run at 100-200 MHz. Interrupt response times are in the 10s of clocks. Alternately the MicroBlaze can poll for events which can be serviced in just a few clocks. Code can be written in C or for ultimate real time control in assembly. Unlike the Cortex-A9 CPUs, MicroBlaze has a fixed execution pipeline and offers predictable response times. For many applications a PicoBlaze processor may be adequate and uses just a few hundred LUTs.

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PL Interrupt Servicing
PS interrupts are routed to the PL and can be serviced by a MicroBlaze processor or by hardware state machines.

HW State Machines
When programmable response times from a MicroBlaze or PicoBlaze CPU are not sufficient, hardware state machines can be created to respond to events. These state machines are generally created in RTL, but can also be generated using MATLAB Simulink and Labview graphical design languages.

22.2.6 Reconfigurable Computing

The programmable logic in each Zynq device can be reconfigured as needed to provide new hardware accelerators. Either the entire device can be reconfigured, or a selected portion of the PL can be reconfigured. This allows for a library of accelerator functions to be stored on disk, flash memory, or DRAM and downloaded on demand. The PS can be used to orchestrate this reconfiguration over the PCAP interface and manage the allocation of PL resources.

Programmable Engines
Typically programmable logic based accelerators implement a specific data flow graph which directly converts input data to output data. An example would be a matrix multiply which pushes data from an input buffer through an array of multipliers and adders and stores the result in a result buffer. An alternative approach might be to build a programmable engine with multipliers and adder instructions to implement the algorithms and general purpose memories to store the data. While not generally as efficient as fixed function flowgraphs, programmable engines have the advantage of being reprogrammable to implement alternate algorithms. An additional advantage is that they can be used to implement complex functions as the number of operations is limited only by the instruction memory or the bandwidth required to fetch instructions from DRAM. Also a programmable engine may more easily match the required computational rate than a fixed function flowgraph. In general, programmable engines require access to local memories for code and data storage and can require significantly more memory than fixed function flowgraphs as well as additional logic for address generation and instruction decoding. OpenCL has been used as a programming language for these types of engines, but assembly code is also viable. These engines are an area of active research and some IP is now commercially available.

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22.3 PL and Memory System Performance Overview

This section provides a comparison of various performance-related behaviors of memory paths through the PS. It is intended to familiarize the designer with the performance-related behaviors of the PL and PS memory system.

22.3.1 Theoretical Bandwidth

Table 22-2 and Table 22-3 provide a basic introduction of relative performance capabilities between various programmable interfaces, DMA, and memory controllers. The bandwidth are calculates as the interface width multiplied by a typical clock rate, not including any protocol overhead. Table 22-2: Theoretical Bandwidth of PS-PL and PS Memory Interfaces Type
PS Slave PS Master PS Slave PS Slave External Memory Internal Memory

Interface
General Purpose AXI General Purpose AXI High Performance (AFI) AXI_HP AXI _ACP DDR OCM

Bus Width (bits)

32 32 64 64 32 64

IF Clock (MHz)
150 150 150 150 1,066 222

Read Total Write R+W of Bandwidth Bandwidth Bandwidth Bandwidth Number Interfaces (MB/s) (MB/s) (MB/s) (MB/s)
600 600 1,200 1,200 4,264 1,779 600 600 1,200 1,200 4,264 1,779 1,200 1,200 2,400 2,400 4,264 3,557 2 2 4 1 1 1 2,400 2,400 9,600 2,400 4,264 3,557

Table 22-3: DMA

DMAC Gigabit Ethernet USB SD

Theoretical Bandwidth of PS DMA Controllers Type

ARM PL310 PS Master PS Master PS Master

IF Width (Bits)
64 4 8 4

IF Clock (MHz)
222 250 60 50

Read BW (MB/s)
1,776 125 60 25

Write BW (MB/s)
1,776 125 60 25

R+W BW (MB/s)
3,552 250 60 25

Number of Interfaces
1 2 2 2

Total Bandwidth (MB/s)

3,552 500 120 50

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Table 22-4:

Theoretical Bandwidth of PS Interconnect

Clock Domain CPU_2x CPU_1x CPU_1x CPU_2x CPU_2x DDR_2x IF Width (Bits) 64 32 32 32 32 64 IF Clock (MHz) 222 111 111 222 222 355 Read BW (MB/S) 1,776 444 444 888 888 2,840 Read BW (MB/S) 1,776 444 444 888 888 2,840 R+W BW (MB/s) 3,552 888 888 1,776 1,776 5,680

Interconnect Central Interconnect Masters Slaves Master Interconnect Slave Interconnect Memory Interconnect

A few performance insights can be inferred from these relative throughputs. The OCM or DDR memories are not able to be fully utilized by a single master, except if a low DDR clock rate is used. For example, DDR read bandwidth is limited to 2,840 MB/s on a particular port by the memory interconnect. The interconnect generally provides enough bandwidth to sustain access to the memory devices.

22.3.2 DDR Efficiency

One design consideration when using the PL to access external memory is the total amount of DDR memory bandwidth that is available. One useful metric of DDR bandwidth is the efficiency of the controller. Efficiency is the total data passed through the controller versus its theoretical throughput during a test period. Table 22-5 and Table 22-6 lists the efficiency the DDR controller under various access types. The system is configured according to Table 22-7. Table 22-5: DDR Efficiency (System #1, 4 HP/AFI masters, AXI Burst Length of 16) Address Pattern
Sequential Random Sequential Random Sequential Random

Access Type
Reads Reads Writes Writes Reads and Writes Reads and Writes

Efficiency (%)
97 92 90 87 87 79

From a design planning perspective, accesses tested in Table 22-5 could be described as optimistic to near-typical values. The random read/write pattern is not worst case as the DDR controller optimization features are still able to improve efficiency; there may be other more pessimistic access patterns. Overall, the DDR controller was designed to have a maximum efficiency of approximately 75%. Table 22-6 lists a DDR efficiency versus burst length example. It illustrates that moderate length bursts do not result in significant DDR efficiency loss. These moderate burst lengths can be useful in latency-sensitive environments where longer bursts can increase latency for higher-priority masters in the system.

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Table 22-6: DDR Efficiency versus AXI Burst Length (System #1, 4 HP/AFI masters, Sequential Read/Writes) Burst Length
4 8 16

DDR Efficiency (%)

87 87 87

Table 22-7:

Latency Example Measurement Systems PL AXI Clock (MHz)

150

System
#1

CPU_6x4x (MHz)
675

CPU_2x (MHz)
225

DDR_3x (MHz)
525

DDR_2x (MHz)
350

DRAM
DDR3

DRAM (Mb/s)
1,050

22.3.3 OCM Efficiency

A similar efficiency test to the DDR example above using four high-performance ports to OCM show a maximum efficiency of 80%.

22.3.4 Interconnect Throughput Bottlenecks

At typical high-performance clock ratios, the PS interconnect is not typically the limiting factor in a high-performance system. One exception to this is when using two high-performance (HP/AFI) ports to DDR. Since ports 0/1 and 2/3 are arbitrated before the DDR controller, it is beneficial in the two port case to use one port each from these pairs, such as port 0 and 2.

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22.4 Choosing a Programmable Logic Interface

This section discusses various options to connecting Programmable Logic (PL) to the Processing System (PS). The main emphasis is on data movement tasks such as direct memory access (DMA).

22.4.1 PL Interface Comparison Summary

Table 22-8 presents a qualitative overview of data transfer use cases. The estimated throughput column reflects suggested maximum throughput in a single direction (read/write). Table 22-8: Data Movement Method Comparison Summary Benefits
Simple Software Least PL Resources Simple PL Slaves Least PL Resources Medium Throughput Multiple Channels Simple PL Slaves

Method
CPU Programmed I/O

Drawbacks
Lowest Throughput

Suggested Uses
Control Functions

Estimated Throughput
<25 MB/s

PS DMAC

Somewhat complex DMA programming

Limited PL Resource DMAs

600 MB/s

PL AXI_HP DMA

Highest Throughput Multiple Interfaces Command/Data FIFOs Highest Throughput Lowest Latency Optional Cache Coherency

OCM/DDR access only More complex PL Master design Large burst may cause cache thrashing Shares CPU Interconnect bandwidth More complex PL Master design More complex PL Master design

High Performance DMA for large datasets High Performance DMA for smaller, coherent datasets Medium granularity CPU offload PL to PS Control Functions PS I/O Peripheral Access

1,200 MB/s (per interface) 1,200 MB/s

PL AXI_ACP DMA

PL AXI_GP DMA

Medium Throughput

600 MB/s

22.4.2 Cortex-A9 CPU via General Purpose Masters

The least intrusive method from a software perspective is to use the Cortex-A9 to move data between the PS and PL (see Figure 22-1). Data flow is directly moved by a CPU, removing the need to handle events from a separate DMA. Access to the PL is provided through the two M_AXI_GP master ports, which each have a memory address range to originate PL AXI transactions. The PL design is also simplified since as little as a single AXI slave can be implemented to service the CPU requests.

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Drawbacks of using a CPU to move data is that a sophisticated CPU is spending cycles performing simple data movement instead of complex control and computation tasks, and the limited throughput available. Transfer rates less than 25 MB/s are reasonable with this method.
X-Ref Target - Figure 22-1

Quad-SPI 1,2,4,8 bit Parallel 8-bit NOR/SRAM NAND 8,16-bit USB USB GigE GigE SD SD MIO Pins DMA DMA DMA DMA DMA DMA

SLCR
System Level Control Registers

NEON
SP, DP FPU 128-bit Vector DSP

NEON
SP, DP FPU 128-bit Vector DSP

Processing System (PS)

PS_POR_B PS_SRST_B

ARM A9 APB
Register Access 32 KB I-Cache 32 KB D-Cache

ARM A9
32 KB I-Cache 32 KB D-Cache

Reset

IRQ
20 I, 29 O

SCU Snoop Control Unit

CLK / PLL
ARM, I/O, DDR

PS_CLK

GPIO x54, x64 UART UART I2C I2C SPI SPI CAN CAN TTC/WDT PJTAG DAP

L2
Cache Memory 512 KB

OCM
On Chip Memory 256 KB

DDR
Memory Controller DDR2 DDR3 LPDDR2 16-bit 32-bit 16-bit w/ECC 32-bit AXI

Centrtal Interconnect

DDR

DMA 8 channel

Mem Switch

CoreSight EMIO
GTX GTX Control GTX GTX PCIe Block RAM Trace In Trace Out Cross Trigger M_AXI_GP x 2 General Purpose 32-bit AXI Master S_AXI_GP x 2 General Purpose 32-bit AXI Slave S_AXI_ACP AXI Coherent 64-bit Slave S_AXI_HP x 4 AXI Data 32/64-bit Slave

64-bit AXI PCAP Processor Config Access Port XADC 16 ch ADC

User IP I/O Interface

Config

Programmable Logic (PL)

Security

UG585_c22_03_021913

Figure 22-1:

Example Cortex-A9 PL Data Movement Topology

22.4.3 PS DMA Controller (DMAC) via General Purpose Masters

The PS DMA controller (DMAC) provides a flexible DMA engine that can provide moderate levels of throughput with little PL logic resource usage (see Figure 22-2). The DMAC resides in the PS and must be programmed via DMA instructions residing in memory, typically prepared by a CPU. With support for up to eight channels, multiple DMA fabric cores can potentially be served in the single DMAC. However, the flexible programmable model may increase software complexity relative to CPU transfer or specialized PL DMA. The DMAC interface to the PL is through the general purpose AXI master interfaces, whose 32-bit width along with the centralized DMA nature (a read and write transaction for each movement) of the DMAC to limit the DMAC from highest throughput. A peripheral request interface also allows PL slaves to provide status to the DMAC on buffer state, to prevent transactions involving a stalled PL peripheral from unnecessarily also stalling interconnect and DMAC bandwidth. See Chapter 9, DMA Controller for more information on the DMAC controller. More information on the M_AXI_GP interfaces can be found in Chapter 5, Interconnect.

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X-Ref Target - Figure 22-2

Quad-SPI 1,2,4,8 bit Parallel 8-bit NOR/SRAM NAND 8,16-bit

SLCR
System Level Control Registers

NEON
SP, DP FPU 128-bit Vector DSP

NEON
SP, DP FPU 128-bit Vector DSP

Processing System (PS)

PS_POR_B PS_SRST_B

APB
USB USB GigE GigE SD SD MIO Pins DMA DMA DMA DMA DMA DMA Register Access

ARM A9
32 KB I-Cache 32 KB D-Cache

ARM A9
32 KB I-Cache 32 KB D-Cache

Reset

IRQ
20 I, 29 O

SCU Snoop Control Unit

CLK / PLL
ARM, I/O, DDR

PS_CLK

GPIO x54, x64 UART UART I2C I2C SPI SPI CAN CAN TTC/WDT PJTAG DAP

L2
Cache Memory 512 KB

OCM
On Chip Memory 256 KB

DDR
Memory Controller DDR2 DDR3 LPDDR2 16-bit 32-bit 16-bit w/ECC 32-bit AXI

Central Interconnect

DDR

DMA 8 channel

Mem Switch

CoreSight EMIO
GTX GTX Control GTX GTX PCIe Block RAM Trace In Trace Out Cross Trigger M_AXI_GP x 2 General Purpose 32-bit AXI Master S_AXI_GP x 2 General Purpose 32-bit AXI Slave S_AXI_ACP AXI Coherent 64-bit Slave Row Control User IP I/O Interface S_AXI_HP x 4 AXI Data 32/64-bit Slave

64-bit AXI PCAP Processor Config Access Port XADC 16 ch ADC Config

Programmable Logic (PL)

Security

UG585_c22_04_021913

Figure 22-2:

Example DMAC DMA Topology

22.4.4 PL DMA via AXI High-Performance (HP) Interface

The high-performance (S_AXI_HP) PL interfaces provide high-bandwidth PL slave interfaces to OCM and DDR memories. The AXI_HP ports are unable to access any other slaves. With four, 64-bit wide interfaces, the AXI_HP provide the greatest aggregate interface bandwidth. The multiple interfaces also save PL resources by reducing the need to a PL AXI interconnect. Each AXI_HP contains control and data FIFOs to provide buffering of transactions for larger sets of bursts, making it ideal for workloads such as video frame buffering in DDR. This additional logic and arbitration does result in higher minimum latency than other interfaces. The user IP logic residing in the PL will generally consist of a low-speed control interface and higher performance burst interface, as shown in Figure 22-3. If control flow is orchestrated by the Cortex-A9 CPU, the general purpose M_AXI_GP port can be used for tasks such as configuring the memory addresses the User IP should access and transaction status. Transaction status can also be conveyed via PL to PS interrupts. Higher performance devices connected to AXI_HP should be able to issue multiple outstanding transactions to take advantage of the AXI_HP FIFOs. The PL design complexity of multiple AXI interfaces along with the associated PL utilization are the primary drawbacks of implementing a DMA engine in the PL for both S_AXI_HP and S_AXI_ACP interfaces. See Chapter 5, Interconnect for more information on the AXI_HP interface.

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X-Ref Target - Figure 22-3

Quad-SPI 1,2,4,8 bit Parallel 8-bit NOR/SRAM NAND 8,16-bit

SLCR
System Level Control Registers

NEON
SP, DP FPU 128-bit Vector DSP

NEON
SP, DP FPU 128-bit Vector DSP

Processing System (PS)

PS_POR_B PS_SRST_B

APB
USB USB GigE GigE SD SD MIO Pins DMA DMA DMA DMA DMA DMA Register Access

ARM A9
32 KB I-Cache 32 KB D-Cache

ARM A9
32 KB I-Cache 32 KB D-Cache

Reset

IRQ
20 I, 29 O

SCU Snoop Control Unit

CLK / PLL
ARM, I/O, DDR

PS_CLK

GPIO x54, x64 UART UART I2C I2C SPI SPI CAN CAN TTC/WDT PJTAG DAP

L2
Cache Memory 512 KB

OCM
On Chip Memory 256 KB

DDR
Memory Controller DDR2 DDR3 LPDDR2 16-bit 32-bit 16-bit w/ECC 32-bit AXI

Central Interconnect

DDR

DMA 8 channel

Mem Switch

CoreSight EMIO
GTX GTX GTX GTX PCIe Trace In Trace Out Cross Trigger M_AXI_GP x 2 General Purpose 32-bit AXI Master S_AXI_GP x 2 General Purpose 32-bit AXI Slave S_AXI_ACP AXI Coherent 64-bit Slave S_AXI_HP x 4 AXI Data 32/64-bit Slave

64-bit AXI PCAP Processor Config Access Port XADC 16 ch ADC

DMA

Programmable Logic (PL)

I/O Interface

Control Block RAM

User IP

Config Security

UG585_c22_05_021913

Figure 22-3:

Example High-Performance (HP) DMA Topology

22.4.5 PL DMA via AXI ACP

The AXI ACP interface (S_AXI_ACP) provides a similar user IP topology as the high performance S_AXI_HP interfaces. Also 64 bits wide, the ACP also provides highest throughput capability for a single AXI interface. As shown in Figure 22-4, the User IP topology is likely often similar to the S_AXI_HP example in the previous section. The ACP differs from the HP performance ports due to its connectivity inside of the PS. The ACP connects to the snoop control unit (SCU) which is also connected to the CPU L1 and the L2 cache. This connectivity allows ACP transactions to interact with the cache subsystems, potentially decreasing total latency for data to be consumed by a CPU. These optionally cache-coherent operations can prevent the need to invalidate and flush cache lines. The ACP also has the lowest memory latency to memory of the PL interfaces. The connectivity of the ACP is similar to that of the CPUs. The drawbacks from using the ACP besides those shared with the S_AXI_HP interfaces also stem from the locality to the cache and CPUs. Memory accesses through the ACP utilize the same interconnect paths as the APU, potentially decreasing CPU performance. Large, coherent ACP transfers can cause thrashing of the cache. Thus ACP coherent transfers are best suited for less than the largest data-sets. The ACP low-latency access allows opportunity for algorithm acceleration of medium granularity.

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For more information on S_ACI_ACP, see Chapter 3, Application Processing Unit. See Chapter 29, On-Chip Memory (OCM) when using ACP with OCM.
X-Ref Target - Figure 22-4

Quad-SPI 1,2,4,8 bit Parallel 8-bit NOR/SRAM NAND 8,16-bit

SLCR
System Level Control Registers

NEON
SP, DP FPU 128-bit Vector DSP

NEON
SP, DP FPU 128-bit Vector DSP

Processing System (PS)

PS_POR_B PS_SRST_B

APB
USB USB GigE GigE SD SD MIO Pins DMA DMA DMA DMA DMA DMA Register Access

ARM A9
32 KB I-Cache 32 KB D-Cache

ARM A9
32 KB I-Cache 32 KB D-Cache

Reset

IRQ
20 I, 29 O

SCU Snoop Control Unit

CLK / PLL
ARM, I/O, DDR

PS_CLK

GPIO x54, x64 UART UART I2C I2C SPI SPI CAN CAN TTC/WDT PJTAG DAP

L2
Cache Memory 512 KB

OCM
On Chip Memory 256 KB

DDR
Memory Controller DDR2 DDR3 LPDDR2 16-bit 32-bit 16-bit w/ECC 32-bit AXI

Central Interconnect

DDR

DMA 8 channel

Mem Switch

Coresight EMIO
GTX GTX GTX GTX PCIe Trace In Trace Out Cross Trigger M_AXI_GP x 2 General Purpose 32-bit AXI Master S_AXI_GP x 2 General Purpose 32-bit AXI Slave S_AXI_ACP AXI Coherent 64-bit Slave S_AXI_HP x 4 AXI Data 32/64-bit Slave

64-bit AXI PCAP Processor Config Access Port XADC 16 ch ADC

DMA

Programmable Logic (PL)

I/O Interface

Control Block RAM

User IP

Config Security

UG585_c22_06_021913

Figure 22-4:

Example ACP DMA Topology

22.4.6 PL DMA via General Purpose AXI Slave (GP)

While the general purpose AXI Slave (S_AXI_GP) has reasonably low latency to OCM and DDR, its narrow 32-bit interface limits its utility as a DMA interface. The two S_AXI_GP interfaces are more likely to be used for lower-performance control access to the PS memories, registers and PS peripherals. More information on the S_AXI_GP interfaces can be found in Chapter 5, Interconnect.

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Programmable Logic Test and Debug

23.1 Introduction
Zynq-7000 AP SoC devices provides extensive debug capability for accessing the PS debug structure (see Chapter 28, System Test and Debug) from the PL. This allows for integrated test and debug on both PS and PL simultaneously. Xilinx provides the fabric trace monitor (FTM) for programmable logic test and debug. It is based on the ARM CoreSight architecture, and is a component of the trace source class (see Chapter 28, System Test and Debug) in the CoreSight system within Zynq-7000 AP SoC devices. The FTM receives trace data from the PL and formats it into trace packets to be combined with the trace packets from other trace source components such as PTM and ITM. With this capability, PL events can easily be traced simultaneously with PS events. The FTM also supports cross-triggering between the PS and PL, except for the trace dumping feature. In addition, the FTM provides general-purpose debug signals between the PS and PL.

23.1.1 Features
The key features of the PL test and debug are as follows: ARM CoreSight compliant 32-bit trace data from the PL 4-bit trace ID from the PL Clock domain crossing between the PL and PS FIFO buffering for trace packets to absorb bursts of trace data from the PL Indication of FIFO overflow via generation of an overflow packet Trace packets are compatible with ARM trace port software and hardware Trigger signals to/from the PL General-purpose I/Os to/from the PL

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23.1.2 Block Diagram

A block diagram of the FTM is shown in Figure 23-1.
X-Ref Target - Figure 23-1

APB Interface FTM Registers

APB

PL Debug
FTMTP2FDEBUG[31:0] FTMTF2PDEBUG[31:0] FTMTP2FTRIGACK[3:0] FTMTP2FTRIG[3:0] FTMTF2PTRIGACK[3:0] FTMTF2PTRIG[3:0] FTMTF2PTRIG[0] Cross Trigger Interface

CTI

PL Trace
FTMDTRACEINDATA[31:0] FTMDTRACEINATID[3:0] FTMDTRACEINVALID FTMDTRACEINCLOCK Clock Domain Crossing Cycle Count Generator Packet Formatter ATB Interface

FIFO

ATB

FPGA Clock Domain

Debug APB Clock Domain

ATB Clock Domain

UG585_c23_01_030312

Figure 23-1:

FTM Block Diagram

As shown in Figure 23-1, the following functional blocks comprise the FTM: APB Interface

This is the interface to the CoreSight debug APB, through which CPUs and JTAG can interact with the FTM. These are programmable registers. This block synchronizes signals between the PL clock domain and the PS clock domain. This block provides: General purpose I/Os, 32 bits to the PL and 32 bits from the PL. These are accessed through reads and writes to registers. Trigger signals, 4 pairs to the PL and 4 pairs from the PL. Each pair consists of a trigger signal and an acknowledge signal, and follows ARM standard CTI handshake protocol.

FTM Registers

Clock Domain Crossing

PL Debug Ports

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Trigger input 0 (FTMTF2PTRIG[0]) can be used to generate trigger packets.

Packet Formatter

This block is responsible for gathering trace data and formatting the data into trace packets. In addition to trace packets, the packet formatter can also generate various other types of packets to convey additional information to the CoreSight system within the PS. This block is used to provide a binary count value for time stamping packets. This is achieved by a counter, which is: 32-bit, free-running, clocked by CPU_2x Pre-scaled by 2^CYCOUNTPRE (range:1 to 32,768) Reset by POR, FTMGLBCTRL[FTMENABLE]==0, CoreSight reset request through JTAG

Cycle Count Generator

FIFO

The FIFO is used to buffer packets before they are sent to the ATB. The FIFO has these properties: 64-packets deep When the FIFO overflows, it signals the packet formatter to generate an overflow packet. In this case, some trace data is lost.

ATB Interface

This is the interface to the CoreSight ATB, over which packets are sent. This block is the interface to the CoreSight ECT system (see Chapter 28, System Test and Debug).

Cross Trigger Interface

23.1.3 System Viewpoint

For details on how the FTM is connected to, and interacts with, the rest of the CoreSight system within the PS, see Chapter 28, System Test and Debug.

23.2 Functional Description

23.2.1 Basic Operation
The PL trace module captures the trace data from the PL. The user supplies the trace data, trace ID, valid, and clock signals to the FTM at the PL-PS boundary. All data, ID, and valid signals must be stable on the rising edge of the FTMDTRACEINCLOCK signal for the FTM to correctly sample them. When FTMDTRACEINVALID is asserted, the PL trace signals are available to the clock domain crossing interface, which synchronizes the data and ID, and sends them to the packet formatter.

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The packet formatter generates packets and submits them to the FIFO. The packet formatter can generate the following types of packets: Trace packets: These packets are generated when valid trace data is available from the PL. Trigger packets: These trigger packets can only be generated by the FTMTF2PTRIG[0] signal. Cycle count packets: These packets provide continuous timestamps that are used to reconstruct a real-time trace. Overflow packets: These packets are generated when the FIFO overflows. Synchronization packets: These packets are for packet analysis tools to re-align to packet boundaries.

The cross trigger interface communicates with the CoreSight ECT structure. This interface passes re-synchronized trigger signals between the PL and the ECT. This provides the capability of cross-triggering each other between the PS and PL.

23.2.2 Packet Generation

The following are some common scenarios that illustrate packet generation by the FTM.

Typical Case Trace Enabled, Cycle Count Enabled

When a valid PL trace (FTMDTRACEINVALID is asserted) is captured, a trace packet and a cycle count packet are generated and sent to the ATB. When a trigger occurs (via the FTMTF2PTRIG[0] signal), a trigger packet and a cycle count packet are generated and sent to the ATB.
X-Ref Target - Figure 23-2

Trigger PL Activity PL Trace Valid PL Trace Valid PL Trace Valid Time

Packets Generated

Trace Packet

Cycle Count Packet

Trace Packet

Cycle Count Packet

Trigger Packet

Cycle Count Packet

Trace Packet

Cycle Count Packet

UG585_c23_02_030312

Figure 23-2:

Packet Generation, Typical Case

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No Cycle Count Case Trace Enabled, Cycle Count Disabled

This is similar to the preceding case, except that cycle count packets are not generated.
X-Ref Target - Figure 23-3

Trigger PL Activity PL Trace Valid PL Trace Valid PL Trace Valid Time

Packets Generated

Trace Packet

Trace Packet

Trigger Packet

Trace Packet
UG585_c23_03_030312

Figure 23-3:

Packet Generation, No Cycle Count Case

FIFO Overflow Case Lost Trace

In this scenario, trace packets are not generated until the FIFO is no longer in an overflow condition. An overflow packet is generated to indicate that there was an overflow condition and some trace packets are lost.
X-Ref Target - Figure 23-4

Time PL Activity PL Trace Valid PL Trace Valid PL Trace Valid

PL Trace Valid (lost)

PL Trace Valid (lost)

PL Trace Valid (lost)

PL Trace Valid

PL Trace Valid

PL Trace Valid

Packets Generated

Trace Packet

Cycle Count Packet

Trace Packet

Cycle Count Packet

Overflow Packet

Trace Packet

Cycle Count Packet

UG585_c23_04_030712

Figure 23-4:

Packet Generation, FIFO Overflow Case

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Synchronization Case
This scenario illustrates how a synchronization packet is generated amid other types of packets. The FTMSYNCRELOAD register sets the number of packets for which a synchronization packet must be generated.
X-Ref Target - Figure 23-5

Trigger

Sync Time

PL Activity PL Trace Valid PL Trace Valid PL Trace Valid

Packets Generated

Trace Packet

Cycle Count Packet

Trace Packet

Cycle Count Packet

Trace Packet

Cycle Count Packet

Sync Packet

Trace Packet

Cycle Count Packet

UG585_c23_05_030712

Figure 23-5:

Packet Generation, Synchronization Case

23.2.3 Packet Format

General Format
A packet consists of a number of bytes. Table 23-1 shows the basic format of a packet. Except for the synchronization packet and the cycle count packet, the first and the last bytes of a packet have their MSB set to 0 to signify the start/stop of the packet; all bytes between the first and the last bytes have their MSB set to 1 . Table 23-1: General Packet Format [7]
0 1 1 0

Byte
0 1 n

[6:0]
type data data data

Table 23-2 shows the encoding values for the type byte. Table 23-2:
Trace packet Trigger packet Cycle count packer

Type Byte Encoding Type [7]

0 0 1

[6:3]
trace[3:0] 0100 count[3:0]

[2:0]
101 000 100

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Table 23-2:

Type Byte Encoding (Contd) Type [7]

0 0

[6:3]
1101 0000

[2:0]
000 000

FIFO overflow packet Synchronization packet

Trace Packet
A trace packet contains the 32-bit value from each captured FTMDTRACEINDATA[31:0] from the PL. The MSB of the last byte is determined by the presence of an immediately following cycle count packet. If a cycle count packet follows, the MSB is 1 , otherwise it is 0. Table 23-3:
0 1 2 3 4

Trace Packet Format [7]

0 1 1 1 count

Byte

[6:0]
data[3:0], 101 data[10:4] data[17:11] data[24:18] data[31:25]

Trigger Packet
A trigger packet is generated for each acknowledged trigger input [0] from the PL, i.e., when both FTMTF2PTRIG[0] and FTMTF2PTRIGACK[0] are High. Table 23-4: Trigger Packet Format Byte
0 1 2 3

[7:0]
0x20 0xA0 0xA0 0x20 or 0xA0

Cycle Count Packet

A cycle count packet is generated when FTMCONTROL[CYCEN] is set, and a trace packet or a trigger packet is generated. It contains a binary count value taken from the current value of the internal 32-bit free-running counter. It is always a continuation of an immediately preceding trace packet or trigger packet. Table 23-5:
0 1 2

Cycle Count Packet Format [7]

1 1 1

Byte

[6:0]
count[3:0], 100 count[10:4] count[17:11]

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Table 23-5:
3 4

Cycle Count Packet Format (Contd) [7]

1 0

Byte

[6:0]
count[24:18] count[31:25]

FIFO Overflow Packet

A FIFO overflow packet is generated when a FIFO overflow occurs. Table 23-6: Overflow Packet Format Byte
0 1 2 3

[7:0]
0x68 0xE8 0xE8 0x68

Synchronization Packet
A synchronization packet allows the packet analysis tools to periodically re-align to correct packet boundaries, because the packet formatter does not maintain 32-bit word boundaries for packets. The synchronization packet follows the same format as other CoreSight components. Table 23-7: Synchronization Packet Format Byte
0-7 8

[7:0]
0x00 0x80

23.3 Signals
The FTM control signals are described in the following sections.

23.3.1 General-Purpose Debug Signals

Table 23-8: General-Purpose Debug Signals PS-PL Signal
FTMTP2FDEBUG[7:0] General purpose debug output FTMTP2FDEBUG[15:8] FTMTP2FDEBUG[23:16] FTMTP2FDEBUG[31:24]

Group

IO
O O O O

Description
The FTMP2FDBG0 register controls its value. The FTMP2FDBG1 register controls its value. The FTMP2FDBG2 register controls its value. The FTMP2FDBG3 register controls its value.

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Table 23-8:

General-Purpose Debug Signals PS-PL Signal

FTMTF2PDEBUG[7:0] FTMTF2PDEBUG[15:8] FTMTF2PDEBUG[23:16] FTMTF2PDEBUG[31:24]

Group

IO
I I I I

Description
The FTMF2PDBG0 register shows its value. The FTMF2PDBG1 register shows its value. The FTMF2PDBG2 register shows its value. The FTMF2PDBG3 register shows its value.

General purpose debug input

23.3.2 Trigger Signals

Table 23-9: Trigger Signals PS-PL Signal
FTMTP2FTRIG[3:0]

Group

IO
O

Description
Each bit is an asynchronous trigger signal from the CoreSight ECT structure in the PS to the PL. Users must program the CTI connected to the FTM to enable these trigger output signals. Each bit is the asynchronous acknowledge signal for the corresponding FTMTP2FTRIG signal. Each bit is an asynchronous trigger signal from the PL to the CoreSight ECT structure in the PS. Users must program the CTI connected to FTM to enable these trigger input signals. Each bit is the asynchronous acknowledge signal for the corresponding FTMTF2PTRIG signal.

Trigger from PS to PL

FTMTP2FTRIGACK[3:0]

Trigger from PL to PS

FTMTF2PTRIG[3:0]

FTMTF2PTRIGACK[3:0]

23.3.3 Trace Signals

Table 23-10: Group Trace Signals PS-PL Signal
FTMDTRACEINCLOCK FTMDTRACEINVALID FTMDTRACEINDATA[31:0] FTMDTRACEINATID[3:0]

IO
I I I I

Description
Clock signal for the trace data interface. Asynchronous to the PS. When this signal is sampled High by the PS using FTMDTRACEINCLOCK, the values on TRMDTRACEINDATA and FTMDTRACEINATID are valid. Trace data. All 32 bits must be provided. Trace ID to be carried over to the ATB. All 4 bits must be provided.

Trace from PL to PS

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23.4 Register Overview

Table 23-11: Register Overview Name
FTMGLBCTRL FTMCONTROL FTMSTATUS FTMP2FDBG FTMF2PDGB FTMCYCCOUNTPRE FTMSYNCRELOAD FTMSYNCCOUNT FTMATID Peripheral ID Component ID Device ID, type Authentication Integration test

Function
Control Status General debug Cycle counter prescaler Synchronization counter Configuration

Overview
Enable FTM, enable cycle count packets, enable trace packets. Idle status, security signal values, FIFO full/empty. Set the values of the signals presented to the PL. Read the values of the signals from the PL. Set the prescaler value for the cycle counter. Set how often synchronization packets should be generated. Set the ATID value to the ATB bus. These registers provide: Identification information Authentication and access control Integration test

CoreSight management

23.5 Programming Model

23.5.1 FTM Security
FTM security is controlled through the use of the standard CoreSight mechanisms, the SPNIDEN, SPIDEN, NIDEN, and DBGEN signals from the DevC module. The following actions are taken by the FTM when the corresponding signals are asserted: SPNIDEN: SPIDEN: NIDEN: DBGEN: FTM trace operations can be enabled. The FTMP2FDBG registers can be modified. No effect. No effect.

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Power Management
24.1 Introduction
Power optimization can start with selecting the right Zynq-7000 AP SoC device. For low-power applications, choose either the 7z010 or 7z020 device. Power can dramatically be reduced by shutting-down the PL side of the device. I/O voltage and termination choice also affects power consumption. The clocks to individual PS subsystems can be stopped. The functionality of the PS is the same for all Zynq-7000 AP SoC devices, but the PL resources and clocking frequency varies with device type. The PL resource counts are listed in section 21.1.2 PL Resources by Device Type. The clock frequencies are listed in the device data sheets. Detailed device level power estimates for the PS and PL can be obtained using the XPE power estimator spreadsheet. Power specifications are found in the Zynq-7000 AP SoC device datasheets (see Appendix A, Additional Resources for a list of related documents).

24.1.1 Features
Key system power management features are as follows. Choose between device technology:

7z010 and 7z020 (derived from Artix AP FPGA technology) 7z030, 7z045, and 7z100 (derived from Kintex AP FPGA technology)

PL power-off Cortex A9 processor standby mode Clock gating for most PS subsystems Three PLLs can be programmed to minimize power consumption Subsystem clocks can be programmed for optional clock frequency Programmable voltage for I/O Banks:

MIO: HSTL 1.8V, LVCMOS 1.8V, 2.5V and 3.3V DDR: DDR2 1.8V, DDR3 1.5V and LPDDR2 1.2V

DDR3 and LPDDR2 low power mode DDR 16 or 32-bit data I/O Internal and external voltage measurements using XADC

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24.2 System Design Considerations

The section includes these system design considerations: 24.2.1 Device Technology Choice 24.2.2 PL Power-down Control 24.2.3 APU Maximum Frequency 24.2.4 DDR Memory Clock Frequency 24.2.5 DDR Memory Controller Modes and Configurations 24.2.6 Boot Interface Options 24.2.7 PS Clock Gating

24.2.1 Device Technology Choice

There is a power and performance distinction between the low power devices (7z010, 7z020) and the high performance devices (7z030, 7z045, and 7z100). The low power devices are derived from the 7 series Artix AP FPGAs. The larger and higher performance devices are derived from the Kintex AP FPGAs. Within the PS and PL, multiple power supplies are used to power core logic, I/Os, and auxiliary circuits. Independent I/O banks allow a mix of 1.8V, 2.5V, and 3.3V I/O standards. The PS also contains a DDR interface supporting DDR2, DDR3, and LPDDR2 which operate at 1.8V, 1.5V and 1.2V, respectively. The Zynq-7000 AP SoC family supports voltage and temperature monitoring by utilizing the sensors in the Xilinx ADC (XADC) subsystem (refer to Chapter 30, XADC Interface). The XADC provides real-time monitoring of voltage and temperature levels within the device.

24.2.2 PL Power-down Control

The PS must be powered up before powering-up and using the PL. In an application that does not require the PL, the PL can be powered off. This requires independently connected power supplies for the PS and PL. The PL supplies that can be powered off include VCCINT, VCCAUX , VCCBRAM and VCCO. Refer to the data sheets for the power sequencing. For example, the PL power system can be controlled via GPIOs, the I2C controller, or an external processor. When the PL is powered off all PS to PL signals, including EMIO, PL AXI, should not be accessed. The PL loses its configuration when powered down and must be reconfigured when it is powered on again. Software should determine when it is safe to power down the PL.

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24.2.3 APU Maximum Frequency

For applications which do not require the maximum amount of processing performance, the APU maximum frequency can be reduced to meet application needs. A lower clock frequency can significantly reduce the operating power when compared to operating at a higher frequency.

24.2.4 DDR Memory Clock Frequency

For applications which do not require the maximum amount of DDR bandwidth, the DDR bandwidth can be reduced to meet application needs. This can reduce operating power significantly compared operating at a higher frequency, but more importantly, allows the use of lower power DDR standards and configurations.

24.2.5 DDR Memory Controller Modes and Configurations

The DDR2, DDR3, and LPDDR2 DDR standards are supported in both 16- and 32-bit data operation. DDR power can be a significant percentage of total power, so minimizing DDR power is an important means of reducing system power. The following features impact DDR power: The highest power DDR standard is a DDR2 due to the 1.8V operating voltage and the termination requirements. The highest speed DDR standard is DDR3 operating up to 1,066 Mb/s in -1 devices. The lowest power interface DDR standard is LPDDR2 due to the 1.2V operating voltage and the unterminated I/Os, however rates are limited compared to DDR3. DDR width can be set to 16 or 32 bits. Note that, for ECC, use a 32-bit bus width (16-bit data, 10-bit ECC). The total number of DDR devices in the system impacts system power. For example, four 8-bit DDR devices have a higher system power than two 16-bit devices. 32-bit DDR devices are available only for LPDDR2. Termination strength: If possible use the highest possible termination value. A termination value of 40 is 50% more termination power than 60 .

24.2.6 Boot Interface Options

The PS supports boot from Quad-SPI, NAND, and NOR devices. Boot devices do not impact system level dynamic power as the boot process only occurs once at device power up. Lower voltage 1.8V devices are of lower static power than higher 3.3V devices.

24.2.7 PS Clock Gating

The PS supports many clock domains, each with independent clock gating control. When the system is in run mode, the user is allowed to shut down the clock domains that are not used and reduce the dynamic power dissipation.

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24.3 Programming Guides

24.3.1 System Modules
Table 24-1: Power Management for System Modules Clocked in Standby Mode
Yes Yes Yes Yes Depends Partial

System Module
APU SCU (with GIC) L2-Cache Interconnect Peripherals Clocks

Description
Clocks are stopped automatically if enabled, refer to text. Clocks are stopped automatically if enabled, refer to text. Clocks are stopped automatically if enabled, refer to text. Clocks are stopped automatically if enabled, refer to Chapter 25, Clocks. Peripheral used as a wake up source must be clocked, refer to Table 24-2.

Cortex-A9 Power Reduction

The APU supports dynamic clock gating. This feature can be enabled in the CP15 Power Control Register. If enabled, the clocks to the CPU internal blocks are dynamically disabled in idle periods. The gated blocks are: Integer core System control block Data engine

SCU Dynamic Power Reduction

The SCU features a standby mode which is enabled by setting the corresponding bit in the mpcore.SCU_CONTROL_REGISTER. When this feature is enabled the SCU stops its internal clocks when the following conditions are met: CPUs are in WFI mode. No pending requests on the ACP No remaining activity in the SCU

The SCU resumes normal operation when a CPU leaves WFI mode or a request on the ACP occurs.

L2 Cache Controller Dynamic Power Reduction

The L2 cache controller supports dynamic power reduction features which allow saving power when the CPUs are in WFI or WFE modes. These features are controlled by their corresponding enable bit in the l2cpl310.reg15_power_ctrl register.

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Dynamic Clock Gating

When the dynamic high-level clock-gating feature is enabled, the cache controller stops its clock when it is idle. It does not stop the clock immediately when it is idle, but after it counts several clock cycles.

Standby Mode
The L2 cache controllers standby mode can be used in conjunction with the WFI mode of the processor that drives the L2 cache controller. When a processor is in the WFI mode, and standby mode is enabled the L2 cache controller stops its internal clocks. These two power saving modes are very similar and the dynamic clock gating feature is a superset of the standby mode. In standby mode, though, clock gating is limited to WFI states, thus making L2 cache accesses more predictable under normal run conditions.

24.3.2 Peripherals
The primary peripheral power management mechanisms are clock scaling and gating. Chapter 25, Clocks describes the system clocks and how they can be controlled through dividers, gates, and multiplexers. Table 24-2 gives a brief overview of the power management capabilities for the device subsystems. Every peripheral includes clock gating and, in some cases, low-power states. With all these pieces working together, the system-level sleep mode is defined. (Refer to section 24.4 Sleep Mode.) In sleep mode the whole chip enters a low-power state, waiting for a wake-up event to continue operation. Table 24-2: Power Management for Peripheral Controls Wake-up Source
No Yes Chapter 8, Timers No

Peripheral
PCAP Timers DMA Controller

Clock Gating Low-Power Mode

No Yes Chapter 25, Clocks Yes Section 9.6 System Functions Yes Chapter 25, Clocks Yes Chapter 25, Clocks Yes Section 12.4 System Functions Yes Chapter 25, Clocks

Other Low-Power Modes

None None None Precharge Power Down, refer to text Self Refresh, refer to text

DDR Controller

No

Static Memory Controller Quad-SPI Controller SDIO Controller

No No No

Not supported None None

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Table 24-2:

Power Management for Peripheral Controls (Contd) Wake-up Source

Yes Section 14.4 System Functions

Peripheral
GPIO Controller

Clock Gating Low-Power Mode

Yes Section 14.4 System Functions Yes Chapter 15, USB Host, Device, and OTG Controllers Yes Chapter 25, Clocks

Other Low-Power Modes

None Suspened/Resume Chapter 15, USB Host, Device, and OTG Controllers

USB Controller

Ethernet Controller SPI Controller CAN Controller UART Controller I2C Controller Programmable Logic Yes 19.3.5 RxFIFO Trigger Level Interrupt No No

Yes 18.4 System Functions Yes 18.4 System Functions Yes 19.3.4 Receive Data Yes 20.4 System Functions Yes Chapter 25, Clocks Sleep Mode 18.2.1 Controller Modes None None User Defined

DDR Power Reduction

Clock Stop When this feature is enabled, the DDR PHY is allowed to stop the clocks going to the DRAM. For DDR2 and DDR3 this feature is effective in self refresh mode only. For LPDDR2 this feature becomes effective in: Idle periods Power down mode Self refresh mode Deep power down mode

Precharge Power Down

When enabled, the DDR memory controller dynamically uses precharge power down mode to reduce power consumption during idle periods. Normal operation continues when a new request is received by the DDRC.

Self Refresh
When enabled the DDRC dynamically puts the DRAM into self-refresh mode during idle periods. Normal operation continues when a new request is received by the DDRC. In this mode DRAM contents are maintained even when the DDRC core logic is fully powered down, thus allowing to stop

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the DDR2X and DDR3X clocks. Also the DCI clock, which controls the DDR termination, can be shut down. Self Refresh Sequence To put the DDR memory into self-refresh mode the following sequence can be used. When executing these steps, the executing CPU should be the only still active master, to guarantee that no new requests are issued to the DDR memory. This mode is typically used in sleep mode.
ddrc.ctrl_reg1[reg_ddrc_selfref_en] = 1 ddrc.DRAM_param_reg3[reg_ddrc_clock_stop_en] = 1 while (slcr.DDR_CMD_STA[CMD_Q_NEMPTY] != 0) while (ddrc.mode_sts_reg[ddrc_reg_operating_mode] != 3) slcr.DDR_CLK_CTRL[DDR_2XCLKACT] = 0 slcr.DDR_CLK_CTRL[DDR_3XCLKACT] = 0 slcr.DCI_CLK_CTRL[CLKACT] = 0

To resume normal DDR operation the clocks must be re-enabled first. Then DRAM is accessible again and the clock stop and self-refresh features can be disabled.

Note: Precharge power down and self refresh modes are mutually exclusive and must not be
activated at the same time.

24.3.3 I/O Buffers

Power management for I/O buffer controls are shown in Table 24-3. Table 24-3:
DDR MIO0 and MIO1

Power Management for I/O Buffer Controls Signal Voltage

1.8V/1.5V/1.2V 1.8V/2.5V/3.3V

I/O Buffer

Termination and Mode

See section 10.6.3 DDR IOB Configuration

24.4 Sleep Mode

Sleep mode is defined at the system level to include the APU in standby mode and multiple controllers being held in reset without a clock. Going into sleep mode can greatly reduce power consumption. In sleep mode, most function clock groups are turned off or powered off. The only required active devices are one CPU, the snoop control unit (SCU), and a wake-up device. Ideally, the only devices causing dynamic power consumption should be the SCU and the wake-up peripheral device. The wake-up device can be UART, GPIO, or any device that can generate an interrupt. If wake-up device is an AXI bus master, which can start transactions targeting the DRAM, additional limitations apply. Because the whole interconnect and the DDR memory are in low power modes and

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inaccessible, it must be assured that the CPU goes through the full wake-up process before any transactions to the DRAM take place. This guarantees that potential transactions targeting the DRAM are served correctly.

24.4.1 Setup Wake-up Events

Every interrupt signaled to the PS can be used as wake-up event. To make this happen, the wanted interrupt must be enabled in the peripheral and the GIC. A wake-up device must be able to generate the interrupt in sleep mode, which means, that its clocks might not be gated off. Refer to the respective chapter for information about available interrupts and how to configure the peripherals to generate them.

Example: GPIO Wake Up Interrupt

The simplest example for a wake-up device is GPIO. Assuming a correctly set up GIC and GPIO, all that must be done to configure the GPIO as wake-up device is: 1. 2. 3. Enable GPIO interrupt in the GIC. Enable GPIO interrupt for the wanted pin(s) in the GPIO block, gpio.INT_EN_{0..3}. Do not turn off any GPIO related clocks.

Although an ISR is not required (refer to section 24.3.2 Peripherals), it is recommended to attach a proper handler to acknowledge and clear the interrupt.

24.4.2 Programming Guide

The following shows the preliminary steps to enter PS sleep mode from normal running mode and exit from it. In sleep mode, the master CPU is responsible for shutting down all non-wake up devices, including all other masters in the system and the PL, if possible. Since clock frequencies change when clock dividers and PLL configurations are changed, configuring a wake-up device might not only mean activating the wanted wake-up interrupt, but also changing the peripheral configuration to be able to cope with the modified clock frequency. If both CPUs are running, the master CPU should shut down the secondary CPU first before proceeding with the steps described below. It is users choice, which CPU acts as master CPU. Furthermore, precautions must be taken to keep code which is executed while the DDR clocks are disabled accessible in this period e.g., by placing those code-segments in OCM, or locking the L2 cache and TLB. Depending on the actual implementation this can, amongst others, apply to: Code executed when DDR is not available Routine for entering and exiting standby mode Translation table Stacks

The location of the currently used translation table(s) and stacks are controllable through the TTBR and SP registers, respectively. This allows switching between different structures for normal running mode and standby mode if needed.

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During the standby sequence interrupts are disabled in the CPUs. This way execution cannot be interrupted while entering standby mode and once the wake up event occurs execution resumes right after the wfi instruction instead of jumping to a vector table. The wake up interrupt must be enabled in the corresponding wake up device and in the GIC interrupt controller to cause a qualified wake up event. Once interrupts are re-enabled after waking up, the wake up interrupt is still pending and causes the CPU to jump to its interrupt handler, as usual.

Enter Sleep Mode

A CPU must execute the following steps to enter sleep mode from normal run mode: 1. 2. 3. 4. 5. 6. 7. 8. 9. Disable interrupts. Execute cpsid if. Configure wake-up device. Enable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en] = 1. Enable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 1 . Enable topswitch clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 1 . Enable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] = 1 . Put the external DDR memory into self-refresh mode. Refer to section 24.2.4 DDR Memory Clock Frequency. Put the PLLs into bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 1 . Shut down the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 1 .

10. Increase the clock divisor to slow down the CPU clock. Set slcr.ARM_CLK_CTRL[DIVISOR] = 0x3f. 11. Execute the wf i instruction to enter WFI mode.

Exit Sleep Mode

Exiting sleep mode is triggered by the configured interrupt occurring. The interrupt wakes up the CPU which resumes execution. The newly starting activity also triggers the topswitch, SCU, and L2 cache controller to leave their idle states and continue normal operation. The procedure for waking up is outlined below. To exit from sleep mode: 1. 2. 3. 4. 5. 6. 7. Restore CPU clock divisor setting. Set slcr.ARM_CLK_CTRL[DIVISOR] = <original value>. Power on the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 0 . Wait for PLL power-on and lock. Wait for slcr.PLL_STATUS[{ARM, DDR, IO}_PLL_LOCK] == 1 . Disable PLL bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 0 . Disable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en] = 0. Disable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 0 . Disable Interconnect clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 0 .

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8. 9.

Disable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] = 0 . Enable all required peripheral devices, including DDR controller clocks.

10. Re-enable and serve interrupts. Execute cpsie if. By executing these steps the core systems normal operating mode is restored. Software then can re-enable peripheral clocks and devices, and the second CPU if applicable, as needed.

Note: Bypassing the PLLs and modifying clock dividers change the clock frequencies in the system.
Proper care must be taken clocking the wake-up device, and watchdog timers (if used), etc., under these conditions.

24.5 Register Overview

Table 24-4 provides an overview of the power management registers. Table 24-4: Power Management Register Overview Register
APU
cp15.Power Control register cp15.TTBR mpcore.SCU_CONTROL_REGISTER l2cpl310.reg15_power_ctrl Power Control register Translation Table Base register Enable/disable SCU standby mode Control APU power management features

Description

Comment

DDR
ddrc.ctrl_reg1 ddrc.DRAM_param_reg3 ddrc.mode_sts_reg DDRC control register (1) DRAM parameters (3) Controller operation mode status Set DDRC operating mode (e.g. self-refresh) Enable/disable clock stop

PS Clock Module
slcr.{ARM, DDR, IO}_PLL_CFG slcr.xxx_CLK_CTRL slcr.PLL_STATUS slcr.DDR_CMD_STA Program PLL clock generators Enable CPU_1x and reference clocks PLL stable/lock status DDR command store status

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Clocks
25.1 Introduction
All of the clocks generated by the PS clock subsystem are derived from one of three programmable PLLs: CPU, DDR and I/O. Each of these PLLs is loosely associated with the clocks in the CPU, DDR and peripheral subsystems.

25.1.1 System Block Diagram

The major components of the clock subsystem are shown in Figure 25-1.
X-Ref Target - Figure 25-1

PLLs
PS_CLK
en

ARM PLL

Mux
I/O PLL
en Glitch-Free

6-bit Programmable Divider 6-bit Programmable Divider 6-bit Programmable Divider

Gate
Glitch-Free

Clock Ratio Generator

cpu_6x4x CPU, SCU, OCM cpu_3x2x

Sync

cpu_2x AXI cpu_1x Interconnect ddr_3x

Async

DDR PLL
en

Boot Mode Pin PLL Bypass

Gate
Glitch-Free

POR Latch

Gate
Glitch-Free

ddr_2x
Async

Bypass Control

Glitch-Free

Bypass Control Registers: ARM_PLL_CTRL DDR_PLL_CTRL IO_PLL_CTRL

Mux

6-bit Programmable Divider (s)

I/O Peripherals (IOP)

USB, Ethernet SDIO, SMC, SPI, QSPI, UART CAN, I2C

PL
PL Clocks
UG585_c25_01_041212

Figure 25-1:

PS Clock System Block Diagram

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25.1.2 Clock Generation

During normal operation, the PLLs are enabled, driven by the PS_CLK clock pin. In bypass mode, the clock signal on the PS_CLK pin provides the source for the various clock generators instead of the PLLs. (Refer to the applicable Zynq-7000 AP SoC data sheet for PS_CLK characteristics.) When the PS_POR reset signal deasserts, the PLL bypass boot mode pin is sampled and selects between PLL bypass and PLL enabled for all three PLLs. The bypass mode runs the system significantly slower than normal mode, but is useful for low-power applications and debug. After the boot process and when the user code executes, the bypass mode and output frequency of each PLL can be individually controlled by software. The clock generation paths include glitch-free multiplexers and glitch-free clock gates to support dynamic clock control.

Three Programmable PLLs

Single external reference clock input for all three PLLs

ARM PLL: Recommended clock source for the CPUs and the interconnect DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces I/O PLL: Recommended clock for I/O peripherals

Individual PLL bypass control and frequency programming Shared bandgap reference voltage circuit for VCOs

Clock Branches
Six-bit programmable frequency dividers Dynamic switching on most clock circuits Four clock generators for the PL

Reset
The clock subsystem is an integral part of the PS and is only reset when the entire system is reset. When this occurs, all of the registers that control the clocking module return to their reset values.

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25.1.3 System Viewpoint

Figure 25-1 shows the clock network and related domains from a system viewpoint.
X-Ref Target - Figure 25-2

A9 MP Core
32K I-Cache 32L D-Cache

A9 MP Core
32K I-Cache 32L D-Cache

CPU CLK (CPU_6x, CPU_2x, and CPU_1x) DDR 3X CLK

AS: Async Domain US: Up Sync DS: Down Sync UZ: Up Size DZ: Down Size Peripheral + PL Interrupts EVENT

M0

M1 Coherent

M0

M1 Coherent

DDR 2X CLK FPGA CLKs

I-AXI D-AXI S0 S1

I-AXI D-AXI

TAG

TAG CTRL M1

Snoop Control Unit (SCU)

M0 ACP AXI

GIC ACP EVT

S0

S0 DS M0

S0 AS M2 M1 US M0 US

S3 S2 S1 S0 AFI AFI AFI AFI

L-2 Cache Controller

512 KB Cache

256 KB OCM RAM

M0 AS

M1

OCM Interconnect 64-bit CPU_2x

s1

AXI_HP 64/32
Async QoS

DVC S0 US M0 M0 M1 M2 M3 M0 Event

DMAC

S2 QoS

Central Interconnect (3x3) 64-Bit CPU_2x

S1 UZ

Master Interconnect S1 AS 32-Bit S2 AS CPU_2x

M0 S1 DS/DZ S3 US M0 AS M1 AS DAP

M0 M1

S1 S0

M0

S0 QoS US/UZ

IOP 32-Bit CPU_1x

S0

M2 AS

M1 DS/DZ

Top Bus Switch

Async Bridge Async Bridge Async Bridge

Slave Interconnect M2 DS 32-Bit CPU_2x

S0 M3

PL

Peripheral Interrupts

Peripheral APB

S0

S1

S2

S3

DDR Controller

UG585_c25_02_021213

Figure 25-2:

System Clock Domains

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A version of the CPU clock is used for most of the internal clocking. The asynchronous DMA peripheral request interfaces between the DMAC and the PL are not shown in Figure 25-2. In addition, PL AXI channels (AXI_HP, AXI_ACP and AXI_GP) have asynchronous interfaces between the PS and PL. The synchronization, where the clock domain crossing occurs, is located inside the PS. Therefore, the PL provides the interface clock to the PS. Each of the aforementioned interfaces could use unique clocks in the PL.

25.1.4 Power Management

The overall approach to power management is described in Chapter 24, Power Management. The clock generation subsystem facilitates clock disabling and frequency control which affects power consumption. The PLL power consumption is directly related to the PLL output frequency. The power consumption can be reduced by using a lower PLL output frequency. Power can also be reduced if one or two of the PLLs are not required. For example, if all of the clock generators can be driven by the DDR PLL, then the ARM and I/O PLLs can be disabled to reduce power consumption. The DDR PLL is the only unit that can drive all of the clock generators. Each clock can be individually disabled when not in use. In some cases, individual subsystems contain additional clock disabling and other power reduction features.

Central Interconnect Clock Disable

The CPU clocks for the central interconnect (CPU_2x and CPU_1x) can be stopped by setting the TOPSW_CLK_CTRL [0] bit to a 1. When this bit is set, the clock controller waits for the AXI interfaces to the L2-cache and SCU to become idle and for the FPGAIDLEN signal from the PL to assert before shutting off the clock to the central interconnect. For the other interfaces, the system software must ensure that the interfaces are idle before disabling the interconnect clock. As soon as the PS detects traffic on the L2-cache or the SCU, or the FPGAIDLEN is deasserted, the clocks will be re-enabled.

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25.2 CPU Clock

Figure 25-3 shows the clock generation network in the CPU clock domains.
X-Ref Target - Figure 25-3

ARM_CLK_CTRL [24] CLK_621_TRUE [0] 1 ARM_CLK_CTRL [25] GlitchFree GlitchFree 2:1 GlitchFree 0 1 0

CPU_6x4x
Closely Coupled, Always 2:1 Ratio

ARM PLL DDR PLL IO PLL

CPU_3x2x

6-bit Programmable Divider

Clock Ratio Generator

Glitch-Free ARM_CLK_CTRL [26]

1 2:1 or 3:1 ARM_CLK_CTRL [27]

CPU_2x
Closely Coupled, Always 2:1 Ratio

[4]

[5]

[13:8]

ARM_CLK_CTRL

ARM_CLK_CTRL
6:1 or 4:1

CPU_1x
UG585_c25_03_022912

Figure 25-3:

CPU Clock Generation and Domains

Ratio Examples
The CPU clock domain operates in two modes 6:2:1 and 4:2:1. Table 25-1 shows example frequencies for these modes and modules operating in each clock domain. (See the applicable Zynq-7000 AP SoC data sheet for the specific allowed frequencies for each clock.) Table 25-1: CPU Clock
CPU_6x4x CPU_3x2x CPU_2x

CPU Clock Frequency Ratio Examples 6:2:1

800 MHz (6 times faster than CPU_1x) 400 MHz (3 times faster than CPU_1x) 266 MHz (2 times faster than CPU_1x) 133 MHz

4:2:1
600 MHz (4 times faster than CPU_1x) 300 MHz (2 times faster than CPU_1x) 300 MHz (2 times faster than CPU_1x) 150 MHz

Clock Domain Modules

CPU clock frequency, SCU, and OCM arbitration L2 cache memory, APU timers I/O peripherals, central interconnect, master interconnect, slave interconnect, and OCM RAM I/O peripherals AHB and APB interface busses

CPU_1x

CPU Clock Divisor Restriction

To improve the quality of the high speed clocks going to the CPU and DDR, there is a requirement that they get divided by an even number in the slcr.ARM_CLK_CTRL [DIVISOR] bit field. For the slcr.ARM_CLK_CTRL [DIVISOR], software must program the following values: DIVISOR =2, =4, or >4.

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Clock Usage
During normal usage, most system clocks will be derived by taking the input clock PS_CLK, sending it through the PLL, and finally dividing it down to be used within the PS. While the PS generates many different clocks, as shown in Figure 25-1, there are three clock domains that have the largest interaction and importance in the system: These are the DDR_3x domain, the DDR_2x domain, and the CPU clock domain. The DDR_3x clock domain includes the DDR memory controller. The DDR_2x domain is primarily used for the high performance AXI interfaces to the PL (AXI_HP{0:3}) and the interconnect. The CPU clock domain controls the ARM processors along with many of the CPU peripherals. The CPU clock domain is composed of four separate clocks: CPU_6x4x, CPU_3x2x, CPU_2x, and CPU_1x. These four clocks are named according to their frequencies, which are related by one of two ratios: 6:3:2:1 or 4:2:2:1 (abbreviated 6:2:1 and 4:2:1). The operating clock ratio is determined by the CLK_621_TRUE [0] bit value. In the 6:2:1 mode, the frequency of the CPU_6x4x clock is 6 times as fast as the CPU_1x clock. Table 25-1, page 619 shows examples of how these clocks are related. Refer to the applicable Zynq-700 AP SoC data sheet for the maximum clock frequency of each clock domain. All the CPU clocks are synchronous to each other; while the DDR clocks are independent of each other and the CPU clocks. The I/O peripheral clocks, such as CAN reference clocks and SDIO reference clocks, are all generated by a similar method, starting from the PS_CLK pin, through a PLL, then a divider, and finally to the peripheral destination. Each peripheral clock is completely asynchronous to all other clocks.

Interconnect Clock Domains

The individual clock domains are shown in Figure 25-2. The central interconnect has two main clock domains: the DDR_2x and the CPU_2x. For the five sub-switches, four clocks are in the CPU_2x clock domain, while the memory interconnect clock is in the DDR_2x clock domain. The direct path between the CPU (via the L2 cache) and DDR controller is in the DDR_3x clock domain, ensuring maximum throughput.The direct path between CPU and OCM is in the CPU_6x4x clock domain. The direct path between the SCU ACP and the PL is in the CPU_6x4x clock domain (clock domain crossing between the PL clock domain and the CPU clock domain is done in an asynchronous AXI bridge on the PS side of the PL).

CPU Clock Stop

Each CPU clock can be individually stopped using slcr.A9_CPU_RST_CTRL.A9_CLKSTOP{0,1}.

PS Peripheral Clocks
Every peripheral within the PS is supplied with its own independently gated version of the CPU clock. This gating is applied with a glitch-free clock gate as shown in Table 25-2.

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Table 25-2:

PS Peripheral Clock Control Base Clock

CPU_2x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x CPU_1x

AMBA Bus Peripheral

DMAC USB 0 USB 1 GigE 0 GigE 1 SDIO 0 SDIO 1 SPI 0 SPI 1 CAN 0 CAN 1 I2C 0 I2C 1 UART 0 UART 1 GPIO Quad-SPI SMC

Control Bits in APER_CLK_CTRL 0: Disable 1: Enable

DMA_CPU_2XCLKACT USB0_CPU_1XCLKACT USB1_CPU_1XCLKACT GEM0_CPU_1XCLKACT GEM1_CPU_1XCLKACT SDI0_CPU_1XCLKACT SDI1_CPU_1XCLKACT SPI0_CPU_1XCLKACT SPI1_CPU_1XCLKACT CAN0_CPU_1XCLKACT CAN1_CPU_1XCLKACT I2C0_CPU_1XCLKACT I2C1_CPU_1XCLKACT UART0_CPU_1XCLKACT UART1_CPU_1XCLKACT GPIO_CPU_1XCLKACT LQSPI_CPU_1XCLKACT SMC_CPU_1XCLKACT [0] [2] [3] [6] [7] [10] [11] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]

System Performance
The clock frequencies of the different clock domains of the PS help dictate total system performance. In many cases, the highest frequency CPU clock results in the highest performance. However, some users will find that the CPU is not the critical performer in the system and that bandwidth across the interconnect is the bottleneck. In that case, it may be useful to switch the ratio from 6:2:1 to 4:2:1 mode. Depending on the device speed grade, the frequency of the CPU clocks may be limited by the cpu_6x while in 6:2:1 mode and may be limited by the cpu_2x clock while in 4:2:1 mode. Therefore, it is suggested that for those applications that might exchange some CPU performance for interconnect performance, check the appropriate data sheet to determine the optimal frequencies.

25.3 System-wide Clock Frequency Examples

There are two clock configuration examples for 6:2:1 mode in Table 25-3. The first example is when the input PS_ CLK is at 33.33 MHz and the second example is when the input frequency is at 50 MHz. The PLL output frequency is determined by the frequency of the input clock PS_CLK multiplied by the PLL feedback divider value (M value). The example below assumes the ARM PLL feedback divider

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value is 40, which generates an ARM PLL output frequency of 33.33 * 40 = 1.33 GHz. For each of the clocks listed in the lower half of the table, the clock frequency equals the sourced PLL frequency divided by the divisor value. For some of the peripheral clocks, such as CAN, Ethernet, and the PL, there are two cascaded dividers. Table 25-3: Clock Frequency Setting Examples for 6:2:1 Mode Example 1 PS_CLK
PLL ARM PLL DDR PLL I/O PLL Clock cpu_6x4x cpu_3x2x cpu_2x cpu_1x ddr_3x ddr_2x DDR DCI SMC Quad SPI GigE SDIO UART SPI CAN PCAP Trace Port PLL FCLKs No. 1 1 1 1 1 1 1 1 1 2 2 1 2 2 1 1 4 PLL Source ARM PLL ARM PLL ARM PLL ARM PLL DDR PLL DDR PLL DDR PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL 2 3 7 10 5 8 10 40 5 10 5 10 20 2 PLL Feedback Divider Value 40 32 30 Divisor 0 Divisor 1 ~(1) ~ ~ ~ ~ ~ 15 ~ ~ 1 ~ ~ ~ 1 ~ ~ 1

Example 2 50 MHz
PLL Output Frequency 1333 1067 1000 Clock Frequency 667 333 222 111 533 356 10 100 200 125 100 25 200 100 200 100 50 2 3 7 12 6 8 10 40 8 12 6 15 20 2 PLL Feedback Divider value 20 16 20 Divisor 0 Divisor 1 ~ ~ ~ ~ ~ ~ 15 ~ ~ 1 ~ ~ ~ 1 ~ ~ 1 PLL Output Frequency 1000 800 1000 Clock Frequency 500 250 167 83 400 267 8 83 167 125 100 25 125 83 167 67 50

33.33 MHz

1. "~" in the table indicates that there is no second divider (not applicable).

25.4 Clock Generator Design

There are several different components to each clock generation circuit. This section describes a generic template that is used to explain the pieces used for all of the following I/O peripheral clocks. The most basic types include:

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2-to-1 multiplexers for selecting a clock source Programmable divider(s) Glitch-free clock activation gate

These features are shown in Figure 25-4.

X-Ref Target - Figure 25-4

Basic Clock Generator Design

DIVISOR_0

DIVISOR_1 Exists for some Clock Generators

Activate Bit

I/O PLL ARM PLL

GlitchFree GlitchFree

6-bit Programmable Divider 0

Glitch-Free

6-bit Programmable Divider 1

Glitch-Free

Clock Gate
Glitch-Free Not GlitchFree

<I/O Peripheral>_ REF_CLK

DDR PLL
Select Bit Select Bit

I/O Peripheral

Alternative Clock Signal (from MIO or PL)

Exists for some Clock Generators Select Bit
UG585_c25_04_021213

Figure 25-4:

Basic Clock Branch Design

PLL
The PLL uses a feedback divider to create an output clock that is equal to the input reference clock multiplied by the PLL_FDIV value supplied by the SLCR.

Glitch-Free Clock Multiplexers

When a dynamic selection is required between two clock sources, the glitch-free multiplexers (GFMs) change the clock selection on the low phase of the clock before starting the newly selected clock at the beginning of its low phase. The GFM operates properly only if both input clocks are active. Switching while either of the clocks is inactive causes the switching operation to fail.

Glitch-Free Divider
The glitch-free dividers take an input clock and divide it based on the divisor. When the divisor is changed, the output smoothly transitions to the new clock frequency without any glitches.

Glitch-Free Clock Gate

The glitch-free clock gate is used when a dynamic gating is required to enable and disable a clock source. The gate ensures that the clock is terminated and re-enabled cleanly on its low phase.

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Clock Select Multiplexers

The clock source multiplexers select between the local clock generated by a clock generator and another source that is external to the clock generator. The clock source multiplexer is not glitch free.

25.5 DDR Clocks

There are two independent DDR clock domains: DDR_2x and DDR_3x. The DDR AXI interface, core, and PHY are all clocked by DDR_3x (see Figure 25-5). The AXI_HP ports and the AXI_HP interconnect paths from the AXI_HP to the DDR Interconnect module are clocked by DDR_2x. These clocks are asynchronous to each other and can have a wide range of frequency ratios between them. The DIVISOR (DDR_CLK_CTRL[25:20]) for the DDR_3XCLK must be an even value. The DIVISOR for DDR_2X can be any value.
X-Ref Target - Figure 25-5

DDR_CLK_ CTRL [31:26]

DDR_CLK_CTRL [1] en
Glitch-Free Output

6-bit Programmable Divider

Glitch-Free

Clock Gate
Glitch-Free

Glitch-Free Output

DDR_2x

DDR PLL
DDR_CLK_ CTRL [25:20] DDR_CLK_CTRL [0] en
Glitch-Free Output

Note: The DDR_2x and DDR_3x clocks are independent and asynchronous to each other.

6-bit Programmable Divider

Glitch-Free

Clock Gate
Glitch-Free

Glitch-Free Output

DDR_3x

UG585_c25_05_022912

Figure 25-5:

DDR Clock Generation

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25.6 IOP Clock Generator

I/O peripheral (IOP) clocks: USB Ethernet SDIO SMC SPI Quad-SPI UART CAN GPIO I2C

25.6.1 USB Clocks

The ULPI clock comes from a USB MIO pin. The ULPI clock is gated with an enable as shown in Figure 25-6. USB clocks are described in Chapter 15, USB Host, Device, and OTG Controllers.
X-Ref Target - Figure 25-6

USB{1, 0}_ULPI_IN (from MIO)

Clock Gate

USB{1, 0}_ULPI_OUT

USB{1, 0}_CLK_CTRL[0]
UG585_c25_06_022712

Figure 25-6:

USB Clocks

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25.6.2 Ethernet Clocks

The Ethernet Clocks generation network is shown in Figure 25-7.
X-Ref Target - Figure 25-7

GEM{0,1}_RCLK_CTRL
[4]
Not Glitch-Free

[0] NET_CTRL [LOOPBACK_LOCAL, 1]

MIO_ENET{0,1}_RX_CLK

0 0 1 1

Not Glitch-Free

EMIO_ENET{0,1}_RX_CLK

Clock Gate
Glitch-Free

Ethernet Controller (Rx)

ENET{0,1}_RX_CLK

I/O PLL 0 ARM PLL 0 1 DDR PLL 1 [5]

GlitchFree GlitchFree

6-bit Programmable Divider 0

Glitch-Free

6-bit Programmable Divider 1

Glitch-Free

ENET{0,1}_REF_CLK

[13:8] [4]

[25:20] 0

GEM{0,1}_CLK_CTRL
EMIO_ENET{0,1}_TX_CLK (signal from PL)

Clock Gate
Glitch-Free Not Glitch-Free

Ethernet Controller (Tx)

ENET{0,1}_TX_CLK

[0]

[6]

GEM{0,1}_CLK_CTRL
UG585_C25_07_022912

Figure 25-7:

Ethernet Clock Generation

Ethernet Receiver Clocks

There are two Ethernet receiver clocks. In normal functional mode, these are either sourced from an external Ethernet PHY via the MIO or an extended MIO (EMIO). For MAC internal loopback mode, these clocks are sourced from the internal Ethernet reference clocks. They are also gated with an enable that can be used for power saving control. These are used to clock the receiver side of the Gigabit Ethernet MAC IP. The source selection multiplexer and the loopback selection multiplexer are not glitch free because the source clocks might not be present. It is recommended that the clock be disabled before the multiplexers are changed. To support loopback mode, enet0_rx_clk and enet1_rx_clk are supplied with enet0_ref_clk and enet1_ref_clk.

Ethernet Transmit Clocks

Two Ethernet clocks are required to be generated: enet0_tx_clk and enet1_tx_clk. These are used to clock the transmit side of the Ethernet MACs and as a source synchronous output clock for the RGMII

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interface. They are also used to provide a stable reference clock to the Ethernet receive paths when internal loopback mode is selected. These clocks can also be sourced from the EMIO. In this case, the associated RGMII interface is disabled and the MAC connects to the PL through an MII or GMII interface. In this case, the Ethernet reference clock must be provided by the PL. This is regardless of MII or GMII, where normally tx_clk is an input in MII and an output in GMII. When operating in MII or GMII mode, its reference clock is provided by the PL through the eth*_emio_tx_clk. The EMIO source multiplexer is not glitch free because the EMIO source clock cannot be relied upon to be present. It is anticipated that this source selection is a static configuration or that the generated clock be gated before changing to the EMIO source. To support loopback mode, gem0_rx_clk and gem1_rx_clk are supplied with gem0_ref_clk and gem1_ref_clk.

25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks

The SDIO, SMC, Quad SPI, and UART peripheral clocks all have the same programming model (see Figure 25-8. The PLL source and divider values are shared for each I/O peripheral controller. The clocks for each SDIO, SPI and the UART controller can be individually enabled/disabled. There is a single clock, each, for the SMC and Quad SPI controllers.
X-Ref Target - Figure 25-8

SDIO SMC SPI Quad SPI UART

I/O PLL ARM PLL DDR PLL

0

6-bit Programmable Divider

GlitchFree Glitch-Free

Clock Gate
Glitch-Free

1 GlitchFree

I/O Peripheral
DevC SDIO 0 SDIO 1 SMC SPI 0 SPI 1 Quad-SPI UART 0 UART 1

Control Register

Mux Ctrl Field

Mux Ctrl Field

Divider Ctrl Field

Clock Enable Field

I/O Peripheral Reference Clocks

SDIO0_REF_CLK SDIO1_REF_CLK SMC_REF_CLK SPI0_REF_CLK SPI1_REF_CLK QSPI_REF_CLK UART0_REF_CLK UART1_REF_CLK
UG585_c25_08_0725712

SDIO_CLK_CTRL SMC_CLK_CTRL SPI_CLK_CTRL LQSPI_CLK_CTRL UART_CLK_CTRL

SRCSEL, 4 SRCSEL, 4 SRCSEL, 4 SRCSEL, 4 SRCSEL, 4

SRCSEL, 5 SRCSEL, 5 SRCSEL, 5 SRCSEL, 5 SRCSEL, 5

DIVISOR, 13:8 DIVISOR, 13:8 DIVISOR, 13:8 DIVISOR, 13:8 DIVISOR, 13:8

CLKACT0, 0 CLKACT1, 1 CLKACT, 0 CLKACT0, 0 CLKACT1, 1 CLKACT, 0 CLKACT0, 0 CLKACT1, 1

Figure 25-8:

SDIO, SMC, SPI, Quad SPI and UART Reference Clocks

25.6.4 CAN Clocks

There are two controller area network (CAN) reference clocks: CAN0_REF_CLK and CAN1_REF_CLK. Both clocks share the same PLL source selection and dividers as shown in Figure 25-9. Each clock has independent alternate source selection (MIO pin or the clock generator), and independent clock gates. These clocks are used for the I/O interface side of the CAN peripherals.

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X-Ref Target - Figure 25-9

CAN_CLK_CTRL
[13:8] [25:20] [0], [1]

I/O PLL ARM PLL DDR PLL

0 GlitchFree 1

0 GlitchFree 1

6-bit Programmable Divisor 0

Glitch-Free

6-bit Programmable Divisor 1

Glitch-Free

CAN_MIOCLK_CTRL Clock Gate

Glitch-Free 0

[6], [22]

[4]

[5]

CAN_CLK_CTRL

CAN Reference Clock from MIO pin

Not GlitchFree 1

CAN Controller

53

CAN{0, 1}_REF_CLK

[5:0], [21:16]

CAN_MIOCLK_CTRL
UG585_c25_09_022912

Figure 25-9:

CAN Clock Generation

25.6.5 GPIO and I2C Clocks

The GPIO and I2C peripherals are clocked by the CPU_1x APB bus interface clock provided by the interconnect (refer to section 25.2 CPU Clock).

25.7 PL Clocks
The PL has its own clock management generation and distribution features and also receives four clock signals from the clock generator in the PS (see Figure 25-9). For the details of the PL clocking structures, see the 7 series FPGAs clocking documentation. The four clocks that are generated by the PS are completely asynchronous to each other with no relationship to other PL clocks. The four clocks are derived from individually selected PLLs in the PS. Each of the PL clocks are independent output signals that produce suitable clock waveforms for PL use.

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X-Ref Target - Figure 25-10

IO PLL ARM PLL DDR PLL

0 GlitchFree 1

0 GlitchFree 1

6-bit Programmable Divisor 0

Glitch-Free

6-bit Programmable Divisor 1

Glitch-Free

PL FCLK Clock

Control Register

Mux Ctrl Field

Mux Ctrl Field

Divider 0 Ctrl Field

Divider 1 Ctrl Field

Four Independent PL Clocks

FCLKCLK0 FCLKCLK1 FCLKCLK2 FCLKCLK3
UG585_c25_10_041612

PL FCLK 0 PL FCLK 1 PL FCLK 2 PL FCLK 3

FPGA0_CLK_CTRL FPGA1_CLK_CTRL FPGA2_CLK_CTRL FPGA3_CLK_CTRL

SRCSEL, 4 SRCSEL, 4 SRCSEL, 4 SRCSEL, 4

SRCSEL, 5 SRCSEL, 5 SRCSEL, 5 SRCSEL, 5

DIVISOR 0, 13:8 DIVISOR 0, 13:8 DIVISOR 0, 13:8 DIVISOR 0, 13:8

DIVISOR 1, 25:20 DIVISOR 1, 25:20 DIVISOR 1, 25:20 DIVISOR 1, 25:20

Figure 25-10:

PL Clock Generation

25.7.1 Clock Throttle

Each of the four PL clocks includes logic to start and stop the clock and to assist with PL design debug and co-simulation. The clock throttle behavior is controlled by software and the trigger input signal from the PL. The clock throttle functions include: Start/stop clock under software control Run clock for a pre-programmed number of pulses Run clock and use PL logic to pause the clock pulses

Each clock throttle has a 16-bit counter that is programmed for the number of clock pulses to generate. For a continuous clock output, write a 0 to the counter, which is the default value. The current count can be read by software. The counting and clock pulses can be paused by the PL logic using the FCLKCLKTRIGxN input signal from the PL. The software can re-start the clocking by writing to the PL clock control register. Table 25-4: PL Clock Throttle Input Signal I/O
I

Signal Name
FCLKCLKTRIGxN

Description
The PL clock trigger signal is an input from the PL logic and is used to halt (pause) the PL clock when counting a programmed number of clock pulses. The halt mode is entered by the rising edge (logic 0 to logic 1) of the FCLKCLKTRIGxN signal. This signal can be asserted asynchronously to the FCLK and all other signals. This pin has no affect when the clock is running continuously, [LAST_CNT] = 0 .

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Clock Controller States

The clock controller states are illustrated in Figure 25-11.
X-Ref Target - Figure 25-11

Software: Rising edge of [CPU_START]

Software

RUN
decrement Hardware: [CURR_VAL] =0
[CURR_VAL]

PL signal driven 0 to 1: FCLKCLKTRIGxN

Software: Rising edge of CPU_[START]

HALT
Clock stopped & halt [CURR_VAL]

UG585_c25_11_102912

Figure 25-11:

PL Clock Throttle States

25.7.2 Clock Throttle Programming

Example: Stop/Start Clock
This example illustrates a simple method to stop and start a PL clock (FCLKCLKx) using writes to the last count field in the throttle count register, slcr.FPGAx_THR_CNT [LAST_CNT]. The example assumes the slcr.FPGAx_THR_CTRL register is kept in its default state of 0x0000_0000 . 1. Stop Clock : Write 0x0000_0001 to slcr.FPGAx_THR_CTRL to immediately stop the clock.

[LAST_CNT] = 1 [Reserved] = 0 [LAST_CNT] = 0 [Reserved] = 0

2.

Start Clock : Write 0x0000_0000 to slcr.FPGAx_THR_CTRL to resume a continuous clock.

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Example: Run the PL Clock for 592 Pulses and Stop

In this example, there will be 592 clock pulses and stops. The slcr.FPGAx_THR_CTRL [CPU_START] bit is positive edge triggered to start the clock. 1. Prime the Start Clock bit: write 0x0000_0004 to the control register, slcr.FPGAx_THR_CTRL.

[CPU_START] = 0 [CNT_RST] = 0 [Reserved] = 0x001 [LAST_CNT] = 0x0250 [Reserved] = 0 [CPU_START] = 1 [CNT_RST] = 0 [Reserved] = 0x001

2.

Program a count of 592: write 0x0000_0250 to the count register, slcr.FPGAx_THR_CNT.

3.

Assert the Start Clock bit: write 0x0000_0005 to the control register, slcr.FPGAx_THR_CTRL.

Example: Program 592 Pulses and Interact with the PL Trigger Input
In this example, there will be 592 clock pulses that are paused by the clock trigger signal (FCLKCLKTRIGxN) and re-started by software. The slcr.FPGAx_THR_CTRL [CPU_START] bit is positive edge triggered to start the clock. 1. 2. 3. 4. 5. Prime the Start Clock bit: See previous example. Program a count of 592 : See previous example. Assert the Start Clock bit : See previous example. PL Logic Pauses the Clock (HALT state): the logic asserts FCLKCLKTRIGxN input to stop the clock. Prime the Start Clock bit: See previous example.

Assert the Start Clock bit : See previous example.

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25.8 Trace Port Clock

The trace port clock, is used to clock the top-level trace port and trace buffer within the SoC debug. This generated clock must be twice the frequency of the desired trace port clock. The frequency of trace_clk must be chosen to be fast enough to allow the trace port to keep up with the amount of data being traced, but slow enough to meet the dynamic characteristics of the output buffer. To allow some flexibility, TRACE_CLK is internally generated from a divided PLL output (see Figure 25-12).
X-Ref Target - Figure 25-12

EMIOTRACECLK
1 Not GlitchFree 0

IO PLL ARM PLL DDR PLL

0 GlitchFree 1

0 GlitchFree 1

6-bit Programmable Divider

Glitch-Free

Clock Gate
Glitch-Free

Debug Subsystem

[6]

[5]

[13:8]

[6]

[0]
UG585_c25_11_072512

DBG_CLK_CTRL Register Bit Fields

Figure 25-12:

Trace Port Clock Generation

25.9 Register Overview

An overview of the PS clock subsystem registers is shown in Table 25-5. Table 25-5: Clock Generation Register Overview Register
PLL_STATUS ARM_PLL_CTRL ARM_PLL_CFG DDR_PLL_CTRL DDR_PLL_CFG IO_PLL_CTRL IO_PLL_CFG ARM_CKL_CTRL CLK_621_TRUE PLL status CPU PLL control CPU PLL configuration DDR PLL control DDR PLL configuration I/O PLL control I/O PLL configuration CPU, DDR and Interconnect CPU clock control Select CPU clock frequency ratio 6:2:1 or 4:2:1 Control registers include: Reset, power-down, bypass Divisor(s) Configuration registers include: PLL control parameters (see Table 25-6)

Description
PLL

Comments

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Table 25-5:

Clock Generation Register Overview (Contd) Register Description

DDR clock control AMBA peripheral clock control Top-level switch clock control PL Clocks PS to PL output clock control PS to PL output clock throttle control, count and status I/O Peripheral Clocks USB ULPI clock control Gigabit Ethernet Rx clock control Gigabit Ethernet ref clock control SMC ref clock control Quad-SPI ref clock control SDIO ref clock control UART ref clock control SPI ref clock control CAN ref clock control CAN com port clock control System Debug Clocks CoreSight SoC trace clk control PCAP clock control DIVISOR bit field (one or two parameters, depending on the peripheral) Clock enable active control

Comments

DDR_CLK_CTRL APER_CLK_CTRL TOPSW_CLK_CTRL FPGA{3:0}_CLK_CTRL FPGA{3:0}_THR_{CTRL, CNT, STA}

USB{1, 0}_CLK_CTRL GEM{1, 0}_CLK_CTRL GEM{1, 0}_CLK_CTRL SMC_CLK_CTRL LQSPI_CLK_CTRL SDIO_CLK_CTRL UART_CLK_CTRL SPI_CLK_CTRL CAN_CLK_CTRL CAN_MIOCLK_CTRL DBG_CLK_CTRL PCAP_CLK_CTRL

25.10 Programming Model

25.10.1 Branch Clock Generator
Each clock generator has a clock control register <module>_CLK_CTRL. Within the clock control register, the SRCSEL field selects a clock source and the DIVISOR field is the amount the source clock is divided down to produce the desired clock frequency. Some clock generators have two cascaded dividers. To prevent the clock generator from exceeding the maximum frequency of the attached subsystem, program the SRCSEL and the DIVISOR values in three separate steps: 1. 2. Increase the value of the DIVISOR, as needed, so that the two PLL clock sources will not cause the clock generator to exceed the maximum clock frequency of the subsystem. Set the SRCSEL to the desired source.

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3.

Update the DIVISOR to the desired value.

6-bit Programmable Divider

The 6-bit divider provides a divide range of 1 to 63, supports both even and odd divide values while producing a close to 50% duty cycle, and is glitchless (divide values can be modified dynamically). The only two exceptions to this rule are that the DDR_3X divider can only be programmed to divide by an even divisor and the ARM_CLK_CTRL[DIVISOR] can not be programmed with a 1 or 3 when the PLL is being used. Some reference clocks have one divider and some have two dividers.

25.10.2 DDR Clocks

It is a requirement that the DDR_3x clock must always be programmed to an even divisor. Note that changing the divider frequency does not produce glitches on the clock, however the DDR controller will not necessarily operate correctly if the frequency is changed without modifying its timing parameters. Therefore, it is suggested to first idle the DDR controller when the DDR clock is to be reprogrammed.

25.10.3 Digitally Controlled Impedance (DCI) Clock

The digitally controlled impedance (DCI) clock is required by the DDR PHY for calibration. The DCI clock is a low frequency clock, normally set to 10 MHz.

25.10.4 PLLs
The three PLLs share the clock input signal, PS_ CLK. Each PLL can be bypassed individually under software control. As part of the power-on reset sequence, all PLLs can be bypassed using the pll_bypass boot mode pin straps. (Refer to the boot mode section of Chapter 6, Boot and Configuration.) The PLL configuration and control registers are in the SLCR. The PLL frequency control registers include the M (feedback divide ratio also known as PLL_FDIV), LOCK_CNT, PLL_CP, and PLL_RES control fields. For each divide ratio M, the PLL_CP, PLL_RES, and LOCK_CNT fields must also be updated to the values shown in Table 25-6. The worst case lock time for the PLLs is 60 us.

Enable PLL Mode when PLL Bypass Mode Pin is Tied High
After the system boots in bypass mode, the following sequence can be used to enable a PLL. Each PLL can be individually enabled. This example shows how to enable the ARM PLL: 1. 2. Program the ARM_PLL CTRL[PLL_FDIV] value and the PLL configuration register, ARM_PLL_CFG[LOCK_CNT, PLL_CP, PLL_RES], to their required values. Force the PLL into bypass mode by writing a 1 to ARM_PLL_CTRL [PLL_BYPASS_FORCE, 4] and setting the ARM_PLL_CTRL [PLL_BYPASS_QUAL, 3] bit to a 0 . This de-asserts the reset to the ARM PLL. Assert and de-assert the PLL reset by writing a 1 and then a 0 to ARM_PLL_CTRL [PLL_RESET, 0].

3.

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4. 5.

Verify that the PLL is locked by reading PLL_STATUS [ARM_PLL_LOCK, 3]. Disable the PLL bypass mode by writing a 0 to ARM_PLL_CTRL [4].

The DDR and I/O PLLs are programmed in a similar fashion.

Software-Controlled PLL Update

The following steps are required for software to update the PLL clock frequency. This example is for the I/O PLL. Table 25-6 shows the possible multiplier values and the required settings for each of those multiplier values. 1. 2. 3. 4. 5. Program the IO_PLL_CTRL[PLL_FDIV] value and the PLL configuration register, IO_PLL_CFG [LOCK_CNT, PLL_CP, PLL_RES]. Force the PLL into bypass mode by writing a 1 to IO_PLL_CTRL [PLL_BYPASS_FORCE, 4]. Assert and de-assert the PLL reset by writing 1 and then a 0 to IO_PLL_CTRL [PLL_RESET, 0]. Verify that the PLL is locked by reading PLL_STATUS [IO_PLL_LOCK, 2]. Disable the PLL bypass mode by writing a 0 to IO_PLL_CTRL [4]. PLL Frequency Control Settings Required PLL Control and Configuration Bit Fields PLL_FDIV
13 14 15 16 17 18 19 20 21 22 23 24 ~ 25 26 27 ~ 28 29 ~ 30 31 ~ 33 34 ~ 36 37 ~ 40 41 ~ 47 48 ~ 66

Table 25-6:

Desired PLL Multiplier

13 14 15 16 17 18 19 20 21 22 23 24 ~ 25 26 27 ~ 28 29 ~ 30 31 ~ 33 34 ~ 36 37 ~ 40 41 ~ 47 48 ~ 66

PLL CP
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2

PLL RES
6 6 6 10 10 10 10 12 12 12 12 12 12 12 12 2 2 2 12 4

LOCK CNT
750 700 650 625 575 550 525 500 475 450 425 400 375 350 325 300 275 250 250 250

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Chapter 26

Reset System
26.1 Introduction
The reset system includes resets generated by hardware, watchdog timers, the JTAG controller, and software. Every module and system in Zynq-7000 AP SoC devices includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B). There are three watchdog timers in the PS that can generate resets. The JTAG controller can generate a reset that only resets the debug portion of the PS and a system-level reset. Software can generate individual sub-module resets or a system-level reset. Resets are caused by many different sources and go to many different destinations. This chapter identifies all of the resets and either explains their functionality or provides a pointer to another chapter or another document.

26.1.1 Features
The key features of the reset system: Collects resets from hardware, watchdog timers, the JTAG controller and software Drives the reset of every module and subsystem Is an integral part of the device security system Executes a three-stage sequence: power-on, memory clear, and system enabling

26.1.2 Block Diagram

Figure 26-1 illustrates the logical dependencies of the main types of generated resets upon these reset triggers. This block diagram is intended to highlight dependencies, and does not accurately depict implementation detail or sequence timing.

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X-Ref Target - Figure 26-1

MODE_PINS

MIO Pin

Boot Mode Register PS_POR_B

Dedicated Pin

POR Reset Signal Filter

Clear

PS Clock Generator Detect & Hold Reset

Bypass PLL Locked

Security Lockdown Reset

Reset Reason and Persistent Registers

Reset Deassertion Delay

Debug Reset CPU Processors Watchdog Timer

SoC Debug Domain

Internal Registers

System Watchdog Timer PS_SRST_B

Dedicated Pin

SLCR & Dev Config Registers

Resets

Peripheral Resets

SLCR Soft Reset Debug System Reset Peripheral Reset Control Registers
UG585_c26_01_101812

Figure 26-1:

Resets Block Diagram

26.1.3 Reset Hierarchy

There are many different types of resets within the PS, from power-on reset that resets the entire system, to a peripheral reset which resets a single subsystem under software control. Figure 26-2 shows the relationships between all major reset signals within the PS. Reset signals flow from the top downwards. The rectangles at the end of the diagram represent the blocks that will be reset. For example, power-on reset (POR) resets all logic within the PS, but system reset only resets the functions indicated in the diagram. This diagram presents the reset hierarchy of operation rather than the reset signal routing shown in Figure 26-1.

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X-Ref Target - Figure 26-2

Power-on Reset

Legend Control

Logic

Debug Reset

Security Lock Down

External System Reset System Software Reset Watchdog Timer Resets Debug System Reset

SCU SoC Debug L-2 Cache CPU 0 Software Reset AWDT 0 Reset CPU 1 Software Reset AWDT 1 Reset IOP Software Resets PL Software Resets

SLCR

Interconnect CPU 0 w/ NEON CPU 1 w/ NEON Programmable Logic

UG585_c26_02_101812

I/O Peripherals

Figure 26-2:

Reset Hierarchy Diagram

26.1.4 Boot Flow

The complete reset sequence is shown as in Figure 26-3. The first two steps are controlled by the external system and PS logic only starts to respond when power on reset (POR) is de-asserted. When the PS is operational, any type of reset can occur after POR. Those resets would insert into the flow chart, at their respective locations. The POR signal can be asserted or de-asserted asynchronously. When the POR signal is de-asserted, it is conditioned to allow it to propagate cleanly to the clock module input logic and, if enabled, to the PLL clock circuits. There is a BOOT_MODE strapping pin to select between all PLLs enabled and all PLLs disabled (bypassed). When the PLL is bypassed, the boot process will take longer. After POR_N is released, the eFUSE controller comes out of reset. It automatically applies some data to the PLL and provides redundancy information to some of the RAMs in the PS. This activity is not visible to the user and cannot be affected by the user. This activity requires from 50 us to 100 us of time to complete. If the PLLs are enabled, then the POR signal is delayed at this point until the PLL clocks have locked. The PLL clocks take up to 60 uS to lock. If PLL bypass mode is selected, the POR signal is not delayed. Before the BootROM starts executing, the internal RAMs are cleared by hardware writing zeros into all addresses. For a listing of the times it takes to go through these steps, see section 6.3.3 Boot Performance in Chapter 6, Boot and Configuration.

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X-Ref Target - Figure 26-3

Stable Voltage Stable PS_CLK clock Release PS_POR_B Sample Bootstrap Pins Apply eFUSE bits

User Visible

User Visible User Visible User Config

PLL BYPASS?
(BOOT_MODE) No

Yes

Wait for PLLs to Lock

Power-on Reset Sequence

De-assert DBGRESET System Resets

Software SRST_B Watchdog Timers Security Reset

RAM Memory Clear De-assert all Resets for CPUs and peripherals

BootROM starts to execute

Process BootROM Header

User Code
UG585_c26_03_021213

Figure 26-3:

Power-On Reset Flow Diagram

26.2 Reset Sources

26.2.1 Power-on Reset (PS_POR_B)
The PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The PS_POR_B reset pin is held Low until all PS power supplies are at their required voltage levels and PS_CLK is active. It can be asynchronously asserted and is internally synchronized and filtered. The filter prevents High-going glitches from entering the PS while the signal is intended to be held Low. It does not filter Low-going glitches when the signal is intended to be held high. Any Low-going glitch that is detected causes an immediate reset of the device.

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The PS_POR_B signal is often connected to the power-good signal from the power supply. When PS_POR_B is de-asserted, the system samples the boot strap mode pins and begins its internal initialization process.

26.2.2 External System Reset (PS_SRST_B)

Power-on reset erases all debug configurations. The external system reset allows the user to reset all of the functional logic within the device without disturbing the debug environment. For example, the previous break points set by the user remain valid after the external system reset. Due to security concerns, system reset erases all memory content within the PS, including the OCM. The PL is also reset in system reset. System reset does not re-sample the boot mode strapping pins. If this pin is not used in the system, it should be tied high.

26.2.3 System Software Reset

The user can reset the entire system by asserting a software reset. By asserting, PSS_RST_CTRL[SOFT_RST], the entire system is reset with the same end result as the user pressing the PS_SRST_B pin (other than the RESET_REASON register value being different). Just like the other system resets, all of the RAMs are cleared and the PL is reset as well.

26.2.4 Watchdog Timer Resets

The watchdog timer resets are internally generated by the watchdog timers when they are enabled and the timer expires. There are three different watchdog timers in the PS: one system-level timer (SWDT) and one private timer in each of the two ARM cores (AWDT0 and AWDT1). The system-level timer reset signal always resets the entire system, while the private watchdog timers can either reset just the ARM core that housed it, or the entire system.

26.2.5 Secure Violation Lock Down

When a security violation is detected, the entire PS is reset and locked down. After a security lock down occurs, the PS only becomes active again by asserting and de-asserting the PS_POR_B reset pin. Refer to Chapter 32, Device Secure Boot for details of how and when this signal is asserted.

26.2.6 Debug Resets

There are two types of debug resets that originate from the debug access port (DAP) controller; debug system reset and debug reset. Debug system reset is a command from the ARM DAP which is controlled by JTAG. This causes the system to reset, just like the external system reset. Debug reset resets certain portions of the SoC debug block including the JTAG logic.

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The PS does not support the external TRST, although it does support assertion of a reset sequence using TMS. The JTAG logic is only reset at power-on reset or assertion of CDBGRSTREQ from the ARM debug access port (DAP) Controller (JTAG). All of the logic in the JTAG TCK clock domain is reset by this signal.

26.3 Reset Effects

The effects of various resets are described in Table 26-1. Table 26-1: Reset Effects Reset Name
Power-On Reset (PS_POR_B) Security Lock Down (requires a power-on reset to recover) External System Reset (PS_SRST_B) System Software System Debug Reset System Watchdog Timer CPU Watchdog Timers (when slcr.RS_AWDT_CTRL{1,0} = 0) CPU Watchdog Timers (when slcr.RS_AWDT_CTRL{1,0} = 1) Debug Reset Peripherals

Source
Device pin DevC Device pin SLCR JTAG SWDT AWDT AWDT JTAG SLCR

Portion of System that is Reset

Entire chip, including debug. (All) The PL must be re-programmed.

RAMs Cleared
All All All

All except debug and persistent registers. The PL must be re-programmed.

All All All All

CPU (s) only. Debug logic. Selected peripherals or CPUs.

None None None

26.3.1 Peripherals
All PS peripherals will be reset when the PS is reset. In addition, individual peripheral resets may also be asserted under software control, through programmable bits within the SLCR. Most peripherals have the ability to reset each of the clock domains within that peripheral. For instance, the Ethernet controller can reset the RX side, TX side, or the interconnect side. Each clock domain can be reset separately. Please note, that individual peripherals may have their own resets defined within those blocks. Peripheral resets will not result in the RAM memory clear logic being activated to clear all memories within the design.

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26.4 PL Resets
26.4.1 PL General Purpose User Resets
There are four separate reset signals, FCLKRESETN[3:0], routed to the PL which could be used as general purpose reset signals for PL logic. These reset signals are not removed until the PS is out of its boot sequence and user code de-asserts them. They are controllable by the SLCR. SLCR.FPGA_RST_CTRL. PL logic connecting to the PS must not be reset when active transactions exist, since uncompleted transactions could be left pending in the PS. It should be noted, that the reset signal is loosely associated with the FCLK of the same number, however, the timing is such that it must be considered an asynchronous reset to the PL. If the user requires a synchronized reset, they must synchronize it themselves in the PL. (The FCLK needs to be toggling for the reset to propagate out of the PS.)

26.5 Register Overviews

The following sections provide an overview of the reset control registers.

26.5.1 Reset Subsystem Control and Status

The Reset Subsystem Control and Status registers are identified in Table 26-2. Table 26-2:
Reason Reason Clear Reboot Status

Reset Subsystem Control and Status Description

Remains persistent except by PS_POR_B Clears the Reason register Remains persistent except by PS_POR_B

Name

HW Register Name
slcr.RST_REASON slcr.RST_REASON_CLR slcr.REBOOT_STATUS

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Table 26-2:
Persistent

Reset Subsystem Control and Status Description

Remains persistent except by PS_POR_B

Name

HW Register Name
devcfg.LOCK, devcfg.MULTIBOOT_ADDR, devcfg.STATUS, devcfg.UNLOCK, slcr.SLCR.REBOOT_STATUS, slcr.RESET_REASON, devcfg.CTRL.MULTIBOOT_EN, devcfg.CTRL.PCFG_AES_FUSE, devcfg.CTRL.PCFG_AES_EN, devcfg.CTRL.SEU_EN, devcfg.CTRL.SEC_EN, devcfg.LOCK, devcfg.STATUS.SECURE_RST, slcr.ARM_CLK_CTRL.SRCSEL, slcr.APU_CTRL.CFGSDISABLE, slcr.APU_CTRL.CP15SDISABLE, scu.Watchdog_Reset_Status_Register See Chapter 28, System Test and Debug

Debug

The persistent registers are registers that are not cleared during any reset other than the POR reset. Two types of persistent registers are used; one stores the state for user identification, and the other is used for security reasons. For information on the security registers, please see Appendix B, Register Details, or Chapter 32, Device Secure Boot. The first group includes the RST_REASON and the REBOOT_STATUS registers. The RST_REASON register indicates the cause of the last reset. User code should read this register, act on it, then clear it out using the slcr.RST_REASON_CLR register so it is primed for the next event. This register is written to by hardware. REBOOT_STATUS is written to by the BootROM. The details of values in the REBOOT_STATUS register can be found in Chapter 6, Boot and Configuration.

26.5.2 System Reset Control

System Reset registers are identified in Table 26-3. Table 26-3: System Reset Control Name
System Software Reset

Systems Affected
All

HW Register Name
slcr.PSS_RST_CTRL

26.5.3 Peripheral Reset Control

Peripheral Reset registers are identified in Table 26-4. Table 26-4: Peripheral Reset Control Registers Overview Description
Top level interconnect domain CPUs, L1/MMU, SCU, WDT, Timer

Peripheral Name
AXI Interconnect CPU and Peripherals

HW Register
slcr.TOPSW_RST_CTRL slcr.A9_CPU_RST_CTRL

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Table 26-4:
OCM CAN DDR DMA DevC Ethernet PSPL GPIO I2C Quad-SPI SDIO SPI SMC UART USB

Peripheral Reset Control Registers Overview (Contd) Description

On chip memory CPU 1x DDR PHY/controller/control registers DMA interface Subsystem, PCAP 2x and CPU 1x Ref, Rx and CPU 1x DMA controller resets to PL and general purpose PL resets CPU 1x CPU 1x Ref and CPU 1x Ref and CPU 1x Ref and CPU 1x Ref and CPU 1x Ref and CPU 1x ULPI and CPU 1x

Peripheral Name

HW Register
slcr.OCM_RST_CTRL slcr.CAN_RST_CTRL slcr.DDR_RST_CTRL slcr.DMAC_RST_CTRL slcr.DEVCI_RST_CTRL slcr.GEM_RST_CTRL slcr.FPGA_RST_CTRL slcr.GPIO_RST_CTRL slcr.I2C_RST_CTRL slcr.LQSPI_RST_CTRL slcr.SDIO_RST_CTRL slcr.SPI_RST_CTRL slcr.SMC_RST_CTRL slcr.UART_RST_CTRL slcr.USB_RST_CTRL

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Chapter 27

JTAG and DAP Subsystem

27.1 Introduction
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. Internally, the AP SoC device implements both an ARM debug access port (DAP) inside the Processing System (PS) as well as a standard JTAG test access port (TAP) controller inside the Programmable Logic (PL). The ARM DAP as part of ARM CoreSight debug architecture allows the user to leverage industry standard third-party debug tools. In addition to the standard JTAG functionality, the Xilinx TAP controller supports a number of PL features including PL Debug, eFuse/BBRAM programming, on-chip XADC access, etc. Most importantly, it also allows debugging of ARM software through the DAP and PL hardware by using the TAP simultaneously with a trace buffer and cross triggering interface between the PS and PL. Another important debug feature the Zynq-7000 AP SoC includes is debug trace support. This feature allows the user to capture both the PS and PL trace into a common trace buffer that is either read out through JTAG, described below, or sent out through the trace port interface unit (TPIU), described in Chapter 28, System Test and Debug.

27.1.1 Block Diagram

Figure 27-1 shows the top level DAP/TAP architecture. As soon as the BootROM passes control to user software, the JTAG chain is enabled automatically, assuming a non-secure boot process. This allows debugging from the user software entry point. JTAG supports two different modes: cascaded JTAG mode (also referred to as single chain mode) and independent JTAG mode (also referred to as split chain mode). The mode is determined through the mode input when the system comes out of reset. In cascaded JTAG chain mode, both the TAP and DAP are visible from external JTAG debug tools or a JTAG tester. With dedicated PL_TDO/TMS/TCK/TDI I/O at the PL side, only one JTAG cable can be connected, though it has access both to PS and PL features concurrently. To debug ARM software and the PL design simultaneously with separate cables, the user must switch to independent JTAG mode. In this mode, JTAG cables only see the Xilinx TAP controller from the dedicated PL_TDO/TMS/TCK/TDI pins. To debug ARM software, the user can route the ARM DAP signals (PJTAG) through the MIO or through the EMIO and to PL SelectIO pins. It is important to note that both the PS and PL must be powered on to use JTAG debug. Due to security reasons, the JTAG chain is protected with triple redundancy gating logic to prevent

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accidental debug enablement under the security environment due to a single event upset (SEU). Zynq-7000 AP SoC devices also provide JTAG disable lock-down to prevent debug enablement due to software errors. The Zynq-7000 AP SoC provides for permanently disabling JTAG, by using one eFuse bit to record. Care should be used when selecting this option because the eFuse JTAG disable is not reversible. Figure 27-2 shows the debug trace architecture. The user can enable debug trace source, PTM, ITM, and FTM using either the JTAG/DAP interface or software through the debug APB bus.
X-Ref Target - Figure 27-1

PS Domain
Hard Logic

PL Domain
Hard Logic

ARM DAP (Debug Access Port)

* 4-bit instructions * ARM CPU Debug * PS AXI Master

Xilinx PL TAP
* 6-bit instructions * ICAP

Dedicated Pins in PL Domain

TDO TDI, TCK, TMS TDI, TCK, TMS TDO

PL JTAG
Xilinx Platform Cable

Programmable Logic Configurable MIO Pins MIO PJTAG

TDO TDI, TCK, TMS

PL SelectIO Pins Passthrough EMIO PJTAG

ARM ICE
UG585_c27_01_011713

Figure 27-1:

JTAG System Block Diagram

This section focuses on the trace port interface unit, which is one of the trace sink modules used to dump real-time trace to an external trace capture module. Both TPIU and ETB receive exact same copies of aggregated trace from multiple trace sources. Although ETB is able to support high trace bandwidth, the 4 KB limit only allows capturing the trace in a small time window. To monitor trace information over a longer period of time, the user must enable the TPIU to dump either through MIO or EMIO so the trace is captured by external trace capture equipment such as an HP logic analyzer, Lauterbach Trace32, ARM DStream, etc.

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X-Ref Target - Figure 27-2

PTM

ITM

FTM

Debug APB

Trace ATB Funnel

(CSTF)

PS

TPIU

4K ETB EMIO Soft IP Trace Port

MIO

Trace Port
UG585_c27_02_050212

Figure 27-2:

Debug Trace Port

27.1.2 Features
Key features of the JTAG debug interface are: JTAG 1149.1 boundary scan support Two 1149.1 compliance TAP controllers: One JTAG TAP controller and one ARM DAP Single unique IDCODE from the Xilinx TAP for each of the Zynq 7000 family of devices IEEE 1532 programming in-system-configurable (ISC) devices support

eFuse programming BBRAM programming XADC access

On-board flash programming Xilinx chipscope debug support ARM CoreSight debug center control using ARM DAP Indirect PS address space access through DAP-AP port External trace capture using MIO in PS, or EMIO in PL

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27.2 Functional Description

Figure 27-3 shows the ARM DAP and JTAG TAP controllers connected in daisy-chain order with the ARM DAP at the front of chain. The two JTAG controllers belong to two different power domains. The ARM DAP is in the PS power domain while the TAP is in the PL power domain. JTAG I/O pads are located in the PL power domain to take advantage of existing JTAG I/O pads in the PL. Although the PS supports PL power down mode, both power domains must be powered on to support all JTAG related features. The ARM DAP controller has a 4-bit IR length and the TAP controller has a 6-bit IR length. The two controllers operate completely independently. The user can access the TAP and ARM DAP controller simultaneously in independent mode. Due to security reasons, the ARM DAP controller is bypassed when the PS is out of reset. The Xilinx TAP controller within the PL can be disabled through the eFuse or the control register within the PL configuration logic. All debug components within the PS are under direct control of the debug tools, such as ARM RVDS or Xilinx XDK, through ARM DAP. All debug components (including DAP) within the PS are designed and integrated following ARM CoreSight architecture. Although there is no CoreSight component within the PL, FTM components within the PS allows a PL trace to be dumped into the ETB. CTI/CTM supports cross triggering between the PS and PL. As shown in Figure 27-3, all PS debug components are tied to the debug APB bus with the DAP as the only bus master. External debug tools connected to the ARM DAP through JTAG uses the debug APB bus to configure all debug components including CPU, CTI/CTM, PTM, ITM, and FTM. Debug APB is also used to extract trace data from the ETB. It is a complicated process to configure all of the debug components properly to support user debug needs. Fortunately, most of the work is automatically handled by the debug tools. However, understanding Zynq debug architecture is necessary to better utilize the full system debug capability. Other than debug control, the ARM DAP also acts as master device within the system interconnect. In previous debug systems, it was required to halt the CPU in order to probe system address space. This new arrangement allows the user to access system address space without halting the CPU. (See Chapter 28, System Test and Debug for more information).

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The PL Xilinx TAP controller serves four key purposes: boundary scan test, eFuse programming, BBRAM programming, and PL debug chipscope.
X-Ref Target - Figure 27-3

AHB-AP

AHBAXI Time Stamp

Top Switch

PL

APB-AP

ARM DAP ROM JTAG-DP TDI TDO

CPU Debug

CTM

CTM

CTI

CTI

CTI CTI FTM Cross Trig(8) Trace Debug JTAG Interface (Chipscope)

PTM

CPU

PTM

CPU

ITM Debug APB

PL Logic

Trace ATB Funnel

(CSTF)

PS
PS_Pad

PL_Pad

TPIU

4K ETB

TDI TDO TDO TDI

XILINX TAP

Trace Port

eFuse BBRAM

Xilinx Custom Design

Trace Bus(ATB) Debug APB

Time Stamp Cross Triggering

UG585_c27_03_021313

Figure 27-3:

Debug System Architecture

The TPIU provides the mechanism to capture trace over long periods of time. There is no internal time limit to how long a trace can be dumped so the only practical limit is the Zynq-7000 bandwidth. If doing a trace dump using PS I/O through MIO, the maximum trace bandwidth depends on how many MIO trace I/Os could be allocated. Another alternative is trace dump through EMIO. PL soft logic connects the EMIO trace signal to the PL SelectIO. There are other potential innovative ways to handle EMIO trace. For example, users could loopback EMIO trace data back to the PS and store it in DDR memory or export trace via gigabit Ethernet to enable remote debug or monitor. In typical debug flow, the user enables minimum trace source dumping capability to fit trace data into allocated TPIU throughput. After a small time window when debug occurs as determined through trace monitoring, the user could enable full trace dumping capability if required, and store short periods of data into the ETB for the next level of debug. Other than debugging, trace port also brings significant value for software profiling. Soft profiling helps the user to identify those software routines that consume the

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most CPU power. Based on that, the user could decide to either perform software optimization or offload the process to the PL.

27.3 I/O Signals

In cascaded JTAG mode, only PL_TDO/TMS/TCK/TDI at the PL side are meaningful to users. Through them, users can access both the ARM DAP and Xilinx TAP. In independent JTAG mode, users can only access the Xilinx TAP, through PL_TDO/TMS/TCK/TDI. To access the ARM DAP, users must use PJTAG signals, as shown in Table 27-1. There are two choices to route PJTAG signals to chip pinouts: via EMIO to the PL SelectIO, or via MIO. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 27-1: Signal Name
TCK TMS TDI TDO TDO 3-state

PJTAG Signals via EMIO Signal

EMIOPJTAGTCK EMIOPJTAGTMS EMIOPJTAGTDI EMIOPJTAGTDO EMIOPJTAGTDTN

via MIO I/O

I I I O O

Pin
MIO 12, 24, 36 or 48 MIO 13, 25, 37 or 49 MIO 10, 22, 34 or 46 MIO 11, 23, 35 or 47

I/O
I I I O

Then TPIU output, as shown in Figure 27-3, can be routed to either EMIO or MIO (but not both). Table 27-2 shows the signal routing. Note that EMIO supports the full 32 bits of TRACE_DATA (bits [31:16] are not shown in the table), while MIO supports only 16 bits of TRACE_DATA. Table 27-2 shows the ARM DAP/Xilinx TPIU signal routing. Table 27-2: Signal Name
TRACE_CLK TRACE_CTL TRACE_DATA TRACE_DATA TRACE_DATA TRACE_DATA Notes:
With EMIO, the boundary for the I/O reference is the PS/PL boundary. With PJTAG, the boundary is the device package pins.

TPIU Signals EMIO Signal

EMIOTRACECLK EMIOTRACECTL [1:0] [3:2] [7:4] [15:8]

MIO I/O
I O

Pin
MIO12 or MIO24 MIO 13 or MIO25 MIO[15:14] or [27:26] MIO[23:22] MIO[19:16] MIO[9:2]

I/O
O O

EMIOTRACEDATA

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27.4 Programming Model

27.4.1 Use Case I: Software Debug with Trace Port Enabled
This is the normal debug case for most applications. Figure 27-4 shows ARM tool chain solution. It is also possible to replace ARM Real View ICE with a Xilinx or Lauterbach debug tool. In this case, there is no PL programming required and the user is able to start on software debug as soon as chip power is on. In this use case, the DAP is active to support software debug needs but the TAP is put into bypass mode. Trace port is also enabled through the MIO pin. Although bandwidth might be limited due to limited MIO availability in some cases, the user could enable a trace dump without depending on PL configuration in this configuration. The major challenge for most users is to allocate MIO pins for the Trace port.
X-Ref Target - Figure 27-4

PS

PL

JTAG

SS

DAP

TAP

ARM Real View ICE

TPIU
SRST

SS

ARM DStream
UG585_c27_04_031812

Figure 27-4:

User Case I: Software Debug with Trace Port Enabled

27.4.2 Use Case II: PS and PL Debug with Trace Port Enabled
The second use case shows how to enable PS software and PL hardware at the same time with two separate debug tools. The tool connected to the Xilinx TAP is typically a Xilinx debug tool. The tools connected to the PS DAP could be Xilinx or any third-party debug tools from ARM or Lauterbach. To support this mode, PL configuration is required to bring the DAP JTAG signals to the PL SelectIOs. Figure 27-5 shows trace port access through the PL SelectIO, but the user could use the MIO trace port as in the previous use case if there is way to manage to fit the trace port into the limited MIO pin multiplexing. Trace port access through SelectIO could support up to 32-bit trace data and gives users enough trace port throughput to address most debug need. As with the JTAG DAP access, the

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PL must be configured to route the trace signal from the EMIO at the PS/PL boundary to the PL SelectIO.
X-Ref Target - Figure 27-5

PS

PL
Xilinx Platform Cable

JTAG

SS

DAP

TAP

Soft Core
JTAG

SS

ARM Review ICE

TPIU

Soft Core

SS

ARM DStream

SRST

UG585_c27_05_031812

Figure 27-5:

User Case II: PS and PL Debug with Trace Port Enabled

27.5 ARM DAP Controller

The debug access port (DAP) is an implementation of an ARM debug interface standard comprising a number of components supplied in a single configuration. All of the supplied components fit into the various architectural components for debug ports (DPs) which are used to access the DAP from an external debugger, and access ports (APs) to access on-chip system resources. With the JTAG-DP, IEEE 1149.1 scan chains are used to read or write register information. A pair of scan chain registers is used to access the main control and access registers within the debug port: DPACC used for debug port (DP) accesses APACC used for access port (AP) accesses

An APACC might access a register of a debug component of the system to which the interface is connected. The scan chain model implemented by a JTAG-DP has the concepts of capturing the current value of APACC or DPACC, and of updating APACC or DPACC with a new value. An update might cause a read or write access to a DAP register that might then cause a read or write access to a debug register of a connected debug component. Table 27-3 shows four Tap ARM DAP IR Instructions. All other IR Instructions are implemented as BYPASS.

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Table 27-3:
ABORT DPACC APACC

ARM DAP IR Instruction Binary Code[3:0]

1000 1010 1011 1110 1111

IR Instruction

DR Width
35 35 35 32 1

Description
JTAG-DP abort register JTAG DP access register JTAG-AP access Register IDCODE for ARM DAP IP

ARM_IDCODE BYPASS

The ARM DAP is composed of one debug port (DP) and up to three access ports (APs). Among the three APs, Zynq-7000 devices only implement APB-AP as the bus master to access all debug components and AHB-AP to access system memory space directly. Table 27-4 lists all registers within the DP. Table 27-4:
CTRL/STAT SELECT

DP Registers Summary Access

IR=DPACC/ADDRESS = 0x4 IR=DPACC/ADDRESS = 0x8

DP Register

Description
DP Control and Status register Its main purpose is to select the current access port and the active four-word register window in that access port

Table 27-5 shows AHB-AP and APB-AP registers in the DAP. For each AP, there is a unique set of registers associated with each AP port. Although the DAP allows JTAG-AP, Zynq devices do not support this feature. Table 27-5:
CSW TAR DRW BD0-3

AP Registers Summary Access

IR=APACC/ADDRESS = 0x0 IR=APACC/ADDRESS = 0x4 IR=APACC/ADDRESS = 0xC IR=APACC/ADDRESS = 0x10 to 0x1C

AP Register

Description
Control and status word Transfer address, TAR Data read/write Band data 0 to 3

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27.6 Trace Port Interface Unit (TPIU)

Table 27-6 shows all registers within the TPIU. Table 27-6: TPIU Registers Summary Offset
0x0 0x4 0x100 0x104 0x108 0x200-0x208 0x300-0x308

TPIU Register
SUPPORT_PORT_SIZE CURRENT_PORT_SIZE TRIG_MODE TRG_COUNT TRIG_MULT TEST_PATTERN FORMAT_SYNC

Description
32-bit register with each bit indicating whether a single port size is allowed Indicates current trace port size with only 1 of 32-bits that could be set Indicates trigger mode support 8-bit register to enable delaying the indication of triggers to the external trace capture device Trigger counter multiplier Configures a test pattern to generate a known bit sequence that could be capture by external capture device Control generation of stop, trigger, and flush events

27.7 Xilinx TAP Controller

The Xilinx TAP contains four mandatory dedicated pins as specified by the protocol and typical JTAG architecture. Table 27-7 shows Xilinx TAP IR commands. Refer to UG470, 7 Series FPGAs Configuration User Guide for more details about the IR commands. Table 27-7:
EXTEST SAMPLE USER1 USER2 USER3 USER4 CFG_OUT CFG_IN USERCODE IDCODE ISC_ENABLE

JTAG Commands Binary Code[5:0]

000000 000001 000010 000011 100010 100011 000100 000101 001000 001001 010000

Boundary Scan Command

Description
Enables boundary-scan EXTEST operation Enables boundary-scan SAMPLE operation Access user-defined register 1 Access user-defined register 2 Access user-defined register 3 Access user-defined register 4 Access the configuration bus for readback Access the configuration bus for configuration Enables shifting out user code Enables shifting out of ID code Marks the beginning of ISC configuration; full shutdown is executed

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Table 27-7:

JTAG Commands (Contd) Binary Code[5:0]

010001 010010 010100 101011 010111 111111

Boundary Scan Command

ISC_PROGRAM ISC_PROGRAM_SECURITY ISC_NOOP ISC_READ ISC_DISABLE BYPASS

Description
Enables in-system programming Change security status from secure to non-secure mode and vice versa No operation Used to read back BBR Completes ISC configuration. Startup sequence is executed Enables bypass

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System Test and Debug

28.1 Introduction
The test and debug capability of Zynq-7000 AP SoC devices enables users to debug the PS and PL using intrusive and non-intrusive debug. Users can debug a complete system, including the PS and PL together. In addition to debugging software, users are also able to debug key hardware points in the PS and user-selected key hardware points in the PL. The test and debug capability is based on the ARM CoreSight v1.0 Architecture Specification and consists mostly of ARM-supplied components, but also includes one Xilinx-supplied component. ARM CoreSight architecture defines four classes of CoreSight components: access and control, trace source, trace link, and trace sink. Components of the access and control class provide a user interface to access the debug infrastructure through JTAG or memory-mapped locations. This class of components also coordinates the operation of separate CoreSight components with a trigger signal distribution network. Components of the trace source class capture debug information, like instruction addresses, bus transaction addresses, and generate trace packets. These trace packets are routed to components of the trace link class where trace packets can be combined or replicated. Components of the trace sink class receive trace packets and dump them into an on-chip trace buffer, or output them to chip pinouts (via the MIO) or to the PL (via the EMIO). CoreSight components are connected together via three major types of buses/signals; programming, trigger, and trace. The programming bus is the path for the access and control class to convey programming information from the JTAG or from processors to other CoreSight components. The trigger signals are used by all classes of components to receive and send triggers from/to each other to coordinate their operation. The trace bus is the main pathway for trace packets to flow, connecting trace source, trace links, and trace sinks.

28.1.1 Features
The CoreSight components provide the following capabilities for the system-wide trace: Debug and trace visibility of whole systems with a single debugger connection Cross triggering support between SoC subsystems Multi-source trace in a single stream Higher data compression than previous solutions Standard programmer's models for standard tools support

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Automatic discovery of topology Open interfaces for third party soft cores Low pin count options

28.1.2 Notices
7z010 CLG225 Device
This device supports 32 MIO pins as shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. The width of the TPIU in the 7x010 CLG225 device is restricted to 1, 2 or 4-bits via the MIO pins. All 32 data signals are available on the EMIO interface. All of the 7z010 CLKG225 device restrictions are listed in section 1.1.3 Notices.

28.2 Functional Description

The block diagram for the CoreSight system is shown in Figure 28-1.
X-Ref Target - Figure 28-1

Instrumentation Trace Macrocell (ITM) Trigger Register ITM Trigger Write Packet Registers

Fabric Trace Monitor (FTM) Embedded Cross Trigger (ECT)

FTM Trigger Packetizer Detector PL Fabric

Embedded Trace Buffer (ETB)

Read Packet Registers

Trace/Packet Output (TPIU) Replicator Funnel

MIO/ EMIO

CPUs

PTM Triggers (x2)

Program Trace Macrocell (PTM) CPU 0 CPU 1

Detector Packetizer

UG585_c28_01_022612

Figure 28-1:

CoreSight System Block Diagram

Figure 28-1 shows the four classes of CoreSight components:

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Access and control: DAP, ECT Trace source: PTM, FTM, ITM Trace link: Funnel, Replicator Trace sink: ETB, TPIU

The components are connected by three types of buses/signals: Programming Trigger Trace

The CoreSight system interacts with: CPUs CPUs PL CPUs EMIO/MIO CPUs/JTAG through PTM for debug and trace through ITM for trace through FTM for debug and trace through ETB for dumping trace through TPIU for dumping trace through DAP for programming CoreSight components

28.2.1 Debug Access Port (DAP)

The DAP is the front-end for user access to the Zynq-7000s AP SoC system test and debug functionalities. It is a CoreSight component of the access and control class, and connects to other components using the programming bus. DAP provides the user, with two interfaces to access the CoreSight infrastructure: External: JTAG, from chip pinout Internal: APB slave, from the slave interconnect

A debugger can use JTAG to communicate with the CoreSight infrastructure, while software running on a CPU uses APB through memory-mapped addresses assigned to the CoreSight infrastructure. The DAP forwards access requests arriving via either interface to the requested CoreSight component. In addition, the DAP also has another interface to access subsystems other than CoreSight, on the PS: Internal: AHB master, to the master interconnect

With AHB, the DAP can forward access requests from JTAG to other subsystems in the PS, subject to authentication requirements. For example, a debugger can query the value of a location in DDR or the value of a coprocessor register. The DAP follows the access model described in ARM Debug Interface v5 Architecture Specification and ARM Debug Interface v5.1 Architecture Supplement , where JTAG indirectly accesses debug components and resources by way of registers in the DAP. The DAP block is an ARM-supplied IP with the following configuration:

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JTAG is the only external interface on chip pinout. Serial wire interface (SW-DP) is not present. APB slave and AHB master are the two internal interfaces. JTAG at the DAP's internal side (JTAG-AP) is present, but only the nSRSTOUT[0] output is connected to the system reset controller. Power-down is not supported.

28.2.2 Embedded Cross Trigger (ECT)

ECT is the cross-triggering mechanism. Through ECT, a CoreSight component can interact with other components by sending and receiving triggers. ECT is implemented with two components: CTM: Cross Trigger Matrix CTI: Cross Trigger Interface

One or more CTMs form an event broadcasting network with multiple channels. A CTI listens to one or more channels for an event, maps a received event into a trigger, and sends the trigger to one or more CoreSight components connected to the CTI. A CTI also combines and maps the triggers from the connected CoreSight components and broadcasts them as events on one or more channels. Both CTM and CTI are CoreSight components of the control and access class. ECT is configured with: Four broadcast channels Four CTIs Power-down is not supported.

Table 28-1 lists the connections of trigger inputs and outputs of the CTIs. Table 28-1: CTI Trigger Inputs and Outputs
Signal
ETB full ETB acquisition complete ITM trigger ETB flush ETB trigger TPIU flush TPIU trigger

CTI Trigger Port CTI (connected to ETB, TPIU)

Trigger input 2 Trigger input 3 Trigger input 4 Trigger output 0 Trigger output 1 Trigger output 2 Trigger output 3

CTI (connected to FTM)

Trigger input 0 Trigger input 1 Trigger input 2 Trigger input 3 Trigger output 0 FTM trigger FTM trigger FTM trigger FTM trigger FTM trigger

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Table 28-1:

CTI Trigger Inputs and Outputs (Contd)

Signal
FTM trigger FTM trigger FTM trigger

CTI Trigger Port

Trigger output 1 Trigger output 2 Trigger output 3

CTI (connected to CPU0)

Trigger input 0 Trigger input 1 Trigger input 2 Trigger input 3 Trigger input 4 Trigger input 5 Trigger input 6 Trigger output 0 Trigger output 1 Trigger output 2 Trigger output 3 Trigger output 4 Trigger output 7 CPU0 DBGACK CPU0 PMU IRQ PTM0 EXT PTM0 EXT CPU0 COMMTX CPU0 COMMRX PTM0 TRIGGER CPU0 debug request PTM0 EXT PTM0 EXT PTM0 EXT PTM0 EXT CPU0 restart request

CTI (connected to CPU1)

Trigger input 0 Trigger input 1 Trigger input 2 Trigger input 3 Trigger input 4 Trigger input 5 Trigger input 6 Trigger output 0 Trigger output 1 Trigger output 2 Trigger output 3 Trigger output 4 Trigger output 7 CPU1 DBGACK CPU1 PMU IRQ PTM1 EXT PTM1 EXT CPU1 COMMTX CPU1 COMMRX PTM1 TRIGGER CPU1 debug request PTM1 EXT PTM1 EXT PTM1 EXT PTM1 EXT CPU1 restart request

Note: For details on the two CTIs connected to CPU0 and CPU1, refer to the CoreSight PTM-A9
Technical Reference Manual, r1p0, DDI0401C, section 1.3.6.

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28.2.3 Program Trace Macrocell (PTM)

The PTM is the block for tracing processor execution flow. It is based on the ARM program flow trace (PFT) architecture, and is a CoreSight component of the trace source class. The PTM generates information that trace tools use to reconstruct the execution of a program, by tracing only certain points in program execution called waypoints. This reduces the amount of trace data. Timestamps are supported for correlating multiple trace streams and coarse grain code profiling. The PTM provides some general resources, such as address/ID comparators, counter, sequencers, for setting up user-defined event triggering conditions. This enhances the base functions of tracing program execution. The PTM block in Zynq-7000 AP SoC devices is the standard ARM-supplied IP, with the no custom configuration.

28.2.4 Instrumentation Trace Macrocell (ITM)

The ITM is the block for software to generate a trace. It is a CoreSight component of the trace source class. Triggering and coarse-grained time stamping are also supported. The main uses include: printf style debugging Trace OS and application events Emit diagnostic system information

The ITM block in Zynq-7000 AP SoC devices is the standard ARM-supplied IP, with the no custom configuration.

28.2.5 Funnel
The funnel is the block for merging trace data from multiple sources into a single stream. It is a CoreSight component of the trace link class. Users select the sources to be merged and assign priorities to them. The funnel in Zynq-7000 AP SoC devices is the standard ARM-supplied IP, with the no custom configuration. Table 28-2 lists the connections of the input ports of the Funnel.
[

Table 28-2:
0 1 2 3 4-7

Funnel Input Port List

Trace Source
PTM0 PTM1 FTM ITM unused

Port

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28.2.6 Embedded Trace Buffer (ETB)

The ETB is the on-chip storage of trace data. It is a CoreSight component of the trace sink class. The ETB provides real-time full-speed storing capability, but is limited in size. Triggering is supported for events such as buffer full and acquisition complete. The ETB block in Zynq-7000 AP SoC devices is an ARM-supplied IP, with the following configuration: RAM size: 4 KB

28.2.7 Trace Packet Output (TPIU)

The TPIU is the block for outputting trace data to the PL or to chip pinout. It is a CoreSight component of the trace sink class. The TPIU provides unlimited trace data output, but is limited in bandwidth. Triggering and flushing are both supported. The TPIU block in Zynq-7000 AP SoC devices is an ARM-supplied IP, with the following configuration: Max data width: 32

Table 28-3 shows the two operating modes of TPIU. Table 28-3: Operating Modes of TPIU Values 1
Active interface Clock source to operate the TPIU Output clock present? Clock edge(s) to sample trace data and control Supported data widths Application Note EMIO EMIOTRACECLK No Rising 1, 2, 4, 8, 16, 32 Since PL supplies the clock to TPIU, PL can use the same clock to sample. MIO PS clock controller Yes Rising and falling 1, 2, 4, 8, 16 External device should delay the trace clock output by approximately half clock period, and use the delayed clock to sample.

SLCR[DBG_CLK_CTRL[6]]

Figure 28-2 shows the waveforms of TPIU I/O signals in the two modes. In EMIO mode, the PL supplies the trace clock signal to TPIU; PL can use the same clock to sample the trace data and control signals from PS. In MIO mode, all signals, including data, control, and clock, are aligned at the selected MIO pins; therefore, the external device should delay the trace clock output by approximately half the clock period to successfully sample the trace data and control signals.

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X-Ref Target - Figure 28-2

EMIOTRACEDATA EMIOTRACECTL EMIOTRACECLK

TPIU Signals on EMIO

trace data, control output on selected MIO pins trace clock output on selected MIO pins trace clock delayed by approximately half period TPIU Signals on MIO
UG585_c28_02_022612

Figure 28-2:

TPIU Operating Mode Waveforms

28.3 I/O Signals

Table 28-4 identifies the system test and debug I/O signals. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Table 28-4: Signals List Default Input Value Number
0 ~ ~ ~ 12 or 24 13 or 25 1-bit 2-bit Trace data ~ 4-bit 8-bit 16-bit 14 or 26 15, 14 or 27, 26 11, 10, 15, 14 or 23, 22, 27, 26 19-16, 11, 10, 15, 14 9-2,19-16,11,10,15,14 O TRACE_DATA[15:0] EMIOTRACEDATA[31:0] O

MIO Pins I/O Pin Name

~ O O ~ TRACE_CTL[0] TRACE_CTL[1]

EMIO Signals
Signal Name
EMIOTRACECLK ~ EMIOTRACECTL

TPIU Signal
Trace clock input Trace clock output Trace control

I/O
I ~ O

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28.4 Register Overview

28.4.1 Memory Map
Per the CoreSight specification, each CoreSight component has 4 kB address space. Table 28-5 lists the base address of each CoreSight component. Table 28-5:
Component
DAP ROM ETB CTI (connected to ETB, TPIU) TPIU Funnel ITM CTI (connected to FTM) FTM Cortex-A9 ROM CPU0 debug logic CPU0 PMU CPU1 debug logic CPU1 PMU CTI (connected to CPU0, PTM0) CTI (connected to CPU1, PTM1) PTM0 (for CPU0) PTM1 (for CPU1)

Memory Map Base Address

0xF880_0000 0xF880_1000 0xF880_2000 0xF880_3000 0xF880_4000 0xF880_5000 0xF880_9000 0xF880_B000 0xF888_0000 0xF889_0000 0xF889_1000 0xF889_2000 0xF889_3000 0xF889_8000 0xF889_9000 0xF889_C000 0xF889_D000

Note: CPU0 debug logic and CPU1 debug logic can also be accessed through CP14 coprocessor
instructions. See the Cortex-A9 Technical Reference Manual for details.

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28.4.2 Functionality
Table 28-6 summarizes the registers in each CoreSight component. Table 28-6: CoreSight Component Register Summary Name
Entry0-9 Peripheral ID0-7 Component ID0-3

Function
DAP ROM
Pointers CoreSight management

Overview
Pointers to other CoreSight components These registers provide identification information

ETB
Control Status RAM depth RAM read RAM write Trigger counter Formatter and flush CoreSight management CTL STS RDP RRD, RRP RWD, RWP TRG FFCR, FFSR Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test Enable/disable capture Status on pipeline, acquisition, trigger, full/empty Depth of RAM in words Read pointer and data Write pointer and data Sets the number of words to be stored after a trigger event Stop events, trigger mark, flush start, formatting control These registers provide: Identification information Authentication and access control Integration test

CTI
Control Acknowledge Channel event generation Channel event gating Forwarding control Trigger/Channel interface status CoreSight management CONTROL INTACK APPSET, APPCLR, APPPULSE GATE INEN, OUTEN TRIGINSTATUS, TRIGOUTSTATUS, CHINSTATUS, CHOUTSTATUS Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test Enable/disable CTI Provide for SW to acknowledge TRIGOUT when no hardware acknowledge is supplied Raise/clear/pulse channel events, used with GATE register to create local events Prevent the channel events from propagating to other CTI's in the system Enable the forwarding of events between the trigger interface and the channel interface Provide the current status of the trigger and channel interfaces These registers provide: Identification information Authentication and access control Integration test

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Table 28-6:

CoreSight Component Register Summary (Contd) Name Overview

Show maximum and current values of supported port size, test patterns, etc. Set Trigger counter, multiplier Set test pattern, modes and repeat count Control and status of formatter and flush Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test These registers provide: Identification information Authentication and access control Integration test

Function
TPIU
Supported feature Trigger Testing Format and finish CoreSight management

Funnel
Control CoreSight management Control, Priority Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test Enable slave ports, set hold time, and priority These registers provide: Identification information Authentication and access control Integration test

ITM
Control Stimulus Trace CoreSight management CR, SCR SPR TER, TTR Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test Enable ITM, configure features like timestamp, sync packets, sync count, etc. Cause the write data to be inserted into the FIFO for packets Enable trace and trigger These registers provide: Identification information Authentication and access control Integration test

FTM Cortex-A9 Integration ROM

Pointers CoreSight management Entry Peripheral ID Component ID Pointers to other CoreSight components for A9 These registers provide identification information

CPU debug
Control Breakpoints DBGDSCCR BVR BCR WVR WCR Controls cache behavior while the CPU is in debug state Set breakpoint values, and control breakpoints. A breakpoint can be set on an Instruction Virtual Address (IVA) or/and a Context ID Set watchpoint values, and control watchpoints. A watchpoint can be set on a Data Virtual Address (DVA) or with a Context ID

Watchpoints

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Table 28-6:

CoreSight Component Register Summary (Contd) Name

Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test

Function
CoreSight management

Overview
These registers provide: Identification information Authentication and access control Integration test

CPU PMU
Control Status Counter PMCR PMOVSR PMCNTENSET PMCNTENCLR PMSELR PMCCNTR PMXEVTYPER PMXEVCNTR PMUSERENR PMINTENSET PMINTENCLR Performance monitor control Overflow flag status Counter enable set/clear, software increment, cycle count

Event counters User enable Interrupt Enable

Counters to gather statistics on the operation of the processor and memory system User enable Interrupt enable set/clear

PTM
Configuration ETMCR, ETMCCR, ETMTRIGGER, ETMSR, ETMSCR ETMSSSCR, ETMTEEVR, ETMTECR1 ETMACVR, ETMACTR ETMCNTRLDVR, ETMCNTENR, ETMCNTVR ETMSQMNEVR, ETMSQR ETMEXTOUTEVER ETMCIDCVR1, ETMCIDCMR ETMSYNCFR, ETMIDR ETMCCER, ETMEXTINSELR, ETMTSEVR, ETMAUXCR, ETMTRACEIDR, ETMOSLSR Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test Main control registers, configuration, set trigger events, and status Trace enable start/stop, Trace enable event, Trace enable control Address comparator values, types Counter reload values, enable events, reload events, current values Sequencer state transition events, sequencer current state Set events that control the corresponding external output Context ID comparator value, mask Sync frequency, ID Sync frequency, ID Configuration code, external input selection, timestamp, auxiliary control, CoreSight trace ID, OS lock, power-down These registers provide: Identification information Authentication and access control Integration test

Trace Enable control Address comparators Counters

Sequencers External output event Context ID comparators General control Misc.

CoreSight management

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28.5 Programming Model

28.5.1 Authentication Requirements
ARM CoreSight infrastructure uses four signals to control authentication: DBGEN NIDEN SPIDEN SPNIDEN Invasive debug enable Non-invasive debug enable Secure invasive debug enable Secure non-invasive debug enable

Table 28-7 lists the Zynq-7000 AP SoC device authentication requirements for the CoreSight components. Table 28-7:
Requirement DAP AHB master
Non-secure access Secure access 1 1 x x 0 1 x x

CoreSight Authentication Requirements by Component DBGEN NIDEN SPIDEN SPNIDEN

CTI (connected to ETB, TPIU) CTI (connected to FTM)

Enable all trigger inputs Enable all trigger outputs x x x x x x x x

CTI (connected to CPU0) CTI (connected to CPU1)

Enable trigger input 0 Enable trigger input 1 Enable trigger input 2 Enable trigger input 3 Enable trigger input 4 Enable trigger input 5 Enable trigger input 6 Trigger output 0 Trigger output 1 Trigger output 2 Trigger output 3 Trigger output 4 Trigger output 6 Trigger output 7 x x x x x x x 1 x x x x 1 x 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

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Table 28-7:
Requirement Funnel TPIU ETB

CoreSight Authentication Requirements by Component (Contd) DBGEN NIDEN SPIDEN SPNIDEN

(no authentication is required)

ITM
Disable stimulus registers 0-15 Disable stimulus registers 16-31 0 x 0 x 0 0 0 0

CPU debug CPU PMU

Non-secure invasive debug Non-secure non-invasive debug Secure invasive debug Secure non-invasive debug 1 1 0 1 1 1 x x x x 1 x x x 1 1 x x x 1 1 x 1 x x x x x x 1 x 1

PTM
Prohibited regions of trace Use the following to determine: if (~NIDEN & ~DBGEN) Prohibited = 1 else if (security level == non-secure) Prohibited = 0 else if ((privilege level == user) & (SUNIDEN)) Prohibited = 0 else if (SPIDEN || SPNIDEN) Prohibited = 0 else Prohibited = 1

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On-Chip Memory (OCM)

29.1 Introduction
The on-chip memory (OCM) module contains 256 KB of RAM and 128 KB of ROM (BootROM). It supports two 64-bit AXI slave interface ports, one dedicated for CPU/ACP access via the APU snoop control unit (SCU), and the other shared by all other bus masters within the processing system (PS) and programmable logic (PL). The BootROM space is used exclusively by the boot process and is not visible to the user. OCM supports high AXI read and write throughput for RAM access by implementing the RAM as a double-wide memory (128 bits). To take advantage of the high RAM access throughput, the user application must use even AXI burst sizes and 128-bit aligned addresses. The TrustZone feature is supported at 4 KB memory granularity. The entire 256K RAM can be divided into 64 4 KB blocks, and assigned security attributes independently. As shown in Figure 29-1, there are 10 AXI channels associated with the OCM, 5 for the CPU/ACP (SCU) port and 5 for the other PS/PL masters (OCM switch port). Arbitration between the read and write channels of the SCU and OCM switch ports is performed within the OCM module. Parity generation and checking is performed on RAM accesses only. Other main interfaces are an interrupt signal (Irq) as well as a register access APB port.

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29.1.1 Block Diagram

X-Ref Target - Figure 29-1

4-port Mem Controller

SCU AXI64 RdCmd SCU AXI64 RdData

SCU AXI64 WrCmd

256 KB RAM

SCU AXI64 Bresp

SCU AXI64 WrData

OCM Switch AXI64 RdCmd

Parity Generation & Checking

OCM Switch AXI64 RdData

OCM Switch AXI64 WrCmd

OCM Switch AXI64 WrData

OCM Switch AXI64 Bresp

Arbiter
APB I/F

Registers

IRQ

UG585_c29_01_042512

Figure 29-1:

OCM Block Diagram

29.1.2 Features
Key features of the OCM include: On-chip 256 KB RAM On-chip 128 KB BootROM (not user visible) Two AXI 3.0, 64-bit slave interfaces Low latency path for CPU/ACP reads to OCM (CPU at 667 MHz minimum 23 cycles) Round-robin pre-arbitration between read and write AXI channels on OCM-interconnect port (non-CPU port) Fixed priority arbitration between the CPU/ACP (via SCU) and OCM-interconnect AXI ports Supports full AXI 64-bit bandwidth of simultaneous read and write commands (with optimal alignment restrictions) on the OCM interconnect port Random access supported to RAM from AXI masters

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TrustZone support for on-chip RAM with 4 KB page granularity Flexible address mapping capability RAM byte-wise parity generation, checking, and interrupt support Support for the following non-AXI features on the CPU (SCU) port:

Zero line fill Pre-fetch hint Early BRESP Speculative line pre-fetch

29.1.3 System Viewpoint

A system viewpoint of the OCM is illustrated in Figure 29-2.
X-Ref Target - Figure 29-2

All other Masters CPUs AXI_ACP AXI_HP

Via Central Interconnect

S0

S1

S0

S1

Snoop Control Unit

M0 M1

OCM Interconnect
M

DDR
S0 S1

On-chip RAM
256 kB
UG585_c29_02_022212

Figure 29-2:

OCM System Viewpoint

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29.2 Functional Description

29.2.1 Overview
The OCM module is mainly composed of a RAM memory block. The OCM module also contains arbitration, framing, parity, and interrupt logic in addition to the RAM array.

29.2.2 Optimal Transfer Alignment

The RAM is implemented as a single-ported, double-width (128-bit) module that can emulate a dual-ported memory under specific conditions. This emulation of dual-ported operation occurs automatically when 128-bit aligned, even burst multiples of AXI commands are used to access the 64-bit wide OCM AXI interfaces. Optimized bursts are theoretically able to achieve 100% throughput of the RAM. If bursts are not aligned to 128 bits or burst lengths are odd multiples of 64-bits, the control logic automatically realigns transfers inside the module start and end addresses can be presented to the RAM as 64-bit operations instead of more optimal 128-bit operations. Configuring OCM memory as device memory in the MMU or using narrow, non-modifiable accesses through the ACP port is not recommended. In this mode, pipelined 32-bit accesses are generated on the SCU port. This type of traffic pattern does not take advantage the double-width memory and effectively reduces OCM efficiency to 25%.

29.2.3 Clocking
The OCM module is clocked by the CPU_6x4x clock. However, the RAM array itself is an exception, and is clocked by CPU_2x, though its 128-bit width is double that of any of the incoming 64-bit wide AXI channels. The OCM switch feeding the OCM module is clocked by CPU_2x, and the SCU is clocked by CPU_6x4x.

29.2.4 Arbitration Scheme

Apart from the CPUs and ACP, all other AXI bus masters are assumed to not have a strong latency requirement. Therefore, the OCM uses a fixed arbitration scheme (on a data beat basis) between the two AXI slave interfaces. The default order of decreasing priorities is: 1. 2. 3. SCU-Rd SCU-Wr OCM-Switch

Using the ocm.OCM_CONTROL.ScuWrPriorityLo register setting (see Appendix B, Register Details), the decreasing priority arbitration can be modified to: 1. 2. 3. SCU-Rd OCM-Switch SCU-Wr

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Arbitration is implemented as shown in Figure 29-3.

X-Ref Target - Figure 29-3

SCU AXI64 RdCmd

Break Burst Into Individual Addresses Or Address Pairs (128-bit aligned)

Addr/Cmd

Req

Hi Priority

SCU AXI64 WrCmd SCU AXI64 WrData

Break Burst Into Individual Addresses Or Address Pairs (128-bit aligned)

Addr/Cmd/Data

Req

Med Priority

Fixed Priority Arbiter

Addr/Cmd

128

256 KB RAM

OCM Switch AXI64 RdCmd

Break Burst Into Individual Addresses Or Address Pairs (128-bit aligned)

Req

OCM Switch AXI64 WrCmd OCM Switch AXI64 WrData

Break Burst Into Individual Addresses Or Address Pairs (128-bit aligned)

Req

OCM Switch RoundRobin Arbiter

Req

Low Priority
Addr/Cmd/Data

Gnt[1:0]

Gnt[2:0]
UG585_c29_03_042512

Figure 29-3:

Default (ScuWrPriorityLo=0 ) OCM Arbitration

There is an additional round-robin pre-arbitration process that selects between a read or write transaction on a per data-beat basis for the OCM-switch port traffic.

Note: Arbitration is performed on a transfer (data beat or clock cycle) basis, not on an AXI command
basis. The in-coming AXI read and write commands are split into individual addresses (or 128-bit address pairs for aligned bursts) before arbitration.

Note: Each individual write address beat will not request access to the memory array until the write data associated with it is available inside the OCM module this prevents the scenario of a write request being stalled due to write data not being available.

Starvation Scenarios
System constraints on the OCM are: The RAM array and OCM Switch port are clocked with CPU_2x which runs at one third or one half the CPU clock. The SCU (CPU/ACP) port is clocked at full the CPU clock rate. Each of the four incoming AXI data channels are 64-bits wide.

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The RAM array is 128-bits wide. The OCM switch port has separate read and write channels that can be simultaneously active. The SCU (CPU/ACP) port has separate read and write channels that can be simultaneously active. The SCU (CPU/ACP) port channels have a fixed arbitration priority higher than the OCM switch port by default.

The address range assigned to the OCM can be modified to exist in the first or last 256 KB of the address map, to flexibly handle the ARM low or high exception vector modes. In addition, the CPU and ACP AXI interfaces can have their lowest 1 MB address range accesses diverted to DDR, using the SCU address filtering feature. This section describes these features through a series of example address configurations.

Mapping Summary
(See Appendix B, Register Details for detailed register information.) When addressing the OCM the following details should be considered: The 256 KB RAM array can be mapped to either a low address range (0x0000_0000 to 0x0003_FFFF ) or a high address range (0xFFFC_0000 to 0xFFFF_FFFF ) in a granularity of four independent 64 KB sections via the 4-bit slcr.OCM_CFG[RAM_HI]. The SCU address filtering (mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable]) field is set by hardware on any form of reset and should not be disabled by the user. Address filtering on non-OCM addresses is necessary to correctly route transactions between the two downstream SCU ports.The address filtering range has a 1 MB granularity. The SCU address filtering feature is able to redirect accesses from its CPU and ACP masters targeting the range ( 0x0000_0000 to 0x000F_FFFF ) which includes the OCM's low address range, to the PS DDR DRAM, independent of the RAM address settings. For each 64 KB section mapped to the high OCM address range via slcr.OCM_CFG[RAM_HI] which is not also part of the SCU address filtering range will be aliased for CPU and ACP masters at a range of 0x000C_0000-0x000F_FFFF. All other masters that do not pass through the SCU are always unable to access the lower 512 KB of DDR in the OCM's low address range ( 0x0000_0000 to 0x0007_FFFF ). Accesses to addresses which the RAM array is not currently mapped to are given an error response.

Initial View
Upon entering user mode, the BootROM is no longer accessible, and the RAM space is split. Note that one 64 KB range resides at the high OCM address, and the other 192 KB resides at the lower address range. Table 29-1 and Table 29-2 identify the initial OCM/DDR address map and register settings, respectively. Attempted accesses to reserved areas return all zeroes along with a SLVERR bus response.

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Table 29-1:

Initial OCM/DDR Address Map Size

64 KB 64 KB 64 KB 64 KB 256 KB 256 KB 64 KB 64 KB 64 KB 64 KB 1,023 MB 64 KB 64 KB 64 KB 64 KB

Address Range (Hex)

0000_0000 - 0000_FFFF 0001_0000 - 0001_FFFF 0002_0000 - 0002_FFFF 0003_0000 - 0003_FFFF 0004_0000 - 0007_FFFF 0008_0000 - 000B_FFFF 000C_0000 - 000C_FFFF 000D_0000 - 000D_FFFF 000E_0000 - 000E_FFFF 000F_0000 - 000F_FFFF 0010_0000 - 3FFF_FFFF FFFC_0000 - FFFC_FFFF FFFD_0000 - FFFD_FFFF FFFE_0000 - FFFE_FFFF FFFF_0000 - FFFF_FFFF

CPUs/ACP
OCM OCM OCM Reserved Reserved Reserved Reserved Reserved Reserved OCM3 (alias) DDR Reserved Reserved Reserved OCM3

Other Masters
OCM OCM OCM Reserved Reserved DDR DDR DDR DDR DDR DDR Reserved Reserved Reserved OCM3

Table 29-2:

Initial Register Settings Register Value

1000 1 0x0010_0000 0xFFE0_0000

slcr.OCM_CFG[RAM_HI] mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable] mpcore.Filtering_Start_Address_Register mpcore.Filtering_End_Address_Register

OCM Relocation
For a contiguous RAM address range, RAM located at address 0x0000_0000 to 0x0002_FFFF can be relocated to base address 0xFFFF_C0000 by programming the SLCR registers. Each bit of slcr.OCM_CFG[RAM_HI] corresponds to a 64 KB range, with the MSB corresponding to the highest address offset range. For more register programming details, refer to the SLCR information in the system level control registers section of Appendix B, Register Details. Table 29-3 and Table 29-4 identify an example OCM relocation address map and OCM relocation register settings, respectively. Table 29-3: Example OCM Relocation Address Map Size
64 KB 64 KB

Address Range (Hex)

0000_0000 - 0000_FFFF 0001_0000 - 0001_FFFF

CPUs/ACP
Reserved Reserved

Other Masters
Reserved Reserved

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Table 29-3:

Example OCM Relocation Address Map Size

64 KB 64 KB 256 KB 64 KB 64 KB 64 KB 64 KB 1,023 MB 64 KB 64 KB 64 KB 64 KB

Address Range (Hex)

0002_0000 - 0002_FFFF 0003_0000 - 0003_FFFF 0004_0000 - 0007_FFFF 000C_0000 - 000C_FFFF 000D_0000 - 000D_FFFF 000E_0000 - 000E_FFFF 000F_0000 - 000F_FFFF 0010_0000 - 3FFF_FFFF FFFC_0000 - FFFC_FFFF FFFD_0000 - FFFD_FFFF FFFE_0000 - FFFE_FFFF FFFF_0000 - FFFF_FFFF

CPUs/ACP
Reserved Reserved Reserved OCM0 (alias) OCM1 (alias) OCM2 (alias) OCM3 (alias) DDR OCM0 OCM1 OCM2 OCM3

Other Masters
Reserved Reserved Reserved DDR DDR DDR DDR DDR OCM0 OCM1 OCM2 OCM3

Table 29-4:

Example OCM Relocation Register Settings Register Value

1111 1 0x0010_0000 0xFFE0_0000

slcr.OCM_CFG[RAM_HI] mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable] mpcore.Filtering_Start_Address_Register mpcore.Filtering_End_Address_Register

SCU Address Filtering

The view of the OCM as seen by the CPUs and ACP via the SCU port relative to other masters via the OCM switch is potentially different. The SCU uses its own dedicated address filtering mechanism to address slaves other than the OCM while the other bus masters in the system are routed via a fixed address decode scheme built into the system interconnects. These other bus masters always see the OCM with accesses (from address 0x0000_0000 to 0x0007_FFFF and address 0xFFFF_C000 to 0xFFFF_FFFF) going to OCM space. Depending on how the SLCR OCM registers are configured, these accesses either terminate at the RAM array or to a default reserved address, resulting in an AXI SLVERR error. These other masters potentially see gaps in the RAM address maps. The CPU/ACP view, however, can be different using the SCU address filtering. For example, if the CPU wants DDR DRAM to be located at address 0x0000_0000 , it can configure the address filtering and SLCR OCM registers so that the address map shown in Table 29-5 is seen. In Table 29-5, note that the CPU/ACP masters are able to address the entire DDR address range, while all other masters cannot address the lower 512 KB of DDR. Table 29-6 identifies example of OCM relocation register settings.

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Table 29-5:

Example SCU Address Filtering Address Map Size

512 KB 512 KB 1,023 MB 64 KB 64 KB 64 KB 64 KB

Address Range (Hex)

0000_0000 - 0007_FFFF 0008_0000 - 000F_FFFF 0010_0000 - 3FFF_FFFF FFFC_0000 - FFFC_FFFF FFFD_0000 - FFFD_FFFF FFFE_0000 - FFFE_FFFF FFFF_0000 - FFFF_FFFF

CPUs/ACP
DDR DDR DDR OCM0 OCM1 OCM2 OCM3

Other Masters
Reserved DDR DDR OCM0 OCM1 OCM2 OCM3

Table 29-6:

Example OCM Relocation Register Settings Register Value

1111 1 0x0000_0000 0xFFE0_0000

slcr.OCM_CFG[RAM_HI] mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable] mpcore.Filtering_Start_Address_Register mpcore.Filtering_End_Address_Register

29.2.5 Interrupts
The OCM module is able to assert an interrupt signal to the APU under the following circumstances: Single-bit Parity Error Multiple-bit Parity Error Unsupported LOCK Request

All interrupts are enabled via the OCM.OCM_PARITY_CTRL register. Individual interrupt status is accessed via the OCM.OCM_IRQ_STS register, and cleared with a write of 1 to each bit location. Parity on the RAM array is performed when the OCM.OCM_PARITY_CTRL[ParityCheckDis] is not asserted. When parity checking is enabled, a single- or multi-bit parity error sets the appropriate interrupt status, and triggers an external interrupt if the associated enable bit is set. The address offset of the first parity error is stored in the OCM.OCM_PARITY_ERRADDRESS register. For reads, a SLVERR response can also be issued to the requesting master for devices that are unable to or prefer not to handle interrupts.

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29.3 Register Overview

A partial list of registers related to the OCM is listed in Table 29-7. (See Appendix B, Register Details for the complete list.) Table 29-7: Module
OCM

On-Chip Memory Register Overview Register Name

OCM_PARITY_ERRADDRESS OCM_PARITY_CTRL OCM_IRQ_STS OCM_CONTROL

Overview
Returns RAM parity error address Set interrupt enables, AXI read response error enable, parity enable, odd parity generation Read raw interrupt status, clear interrupts Change pre-arbitration priority SLCR register write disable SLCR register write enable OCM subsystem reset OCM TrustZone Configures RAM address mapping SCU address filtering enable SCU address filtering base address SCU address filtering end address

slcr

SLCR_LOCK SLCR_UNLOCK OCM_RST_CTRL TZ_OCM_RAM0/1 OCM_CFG

mpcore

SCU_CONTROL_REGISTER Filtering_Start_Address_Register Filtering_End_Address_Register

29.4 Programming Model

29.4.1 Changing Address Mapping
A method for reorganizing the OCM address space and performing DDR remapping is as follows: 1. 2. Complete all outstanding transactions by issuing data (DSB) and instruction (ISB) synchronization barrier commands. Since the changing the address map may prevent the fetching of the nearby instructions, enable L1 instruction cache, and prefetch cache lines for the remainder of the function, typically with PLI instructions. To facilitate prefetching, consider aligning the instructions to be prefetched to start at a cacheline boundary. Ensure that the instruction prefetching has completed by issuing an ISB instruction. Unlock the SLCR by writing the unlock key value to the slcr.SLCR_unlock register. Modify the slcr.OCM_CFG register to change the address ranges that the RAM responds to. Re-lock the SLCR by writing the lock key value to the slcr.SLCR_lock register, if desired.

3. 4. 5. 6. 7.

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8.

Modify the mpcore.Filtering_Start_Address_Register to the desired start address of transactions that should be filtered away from the OCM for SCU masters. Typical settings are 0x0010_0000 (default, do not redirect lower 1 MB), and 0x0000_0000 (start redirect at lowest address to DDR RAM). Modify the mpcore.Filtering_End_Address_Register to the desired end address of transactions that should be filtered away from the OCM for SCU masters. A typical setting is 0xFFE0_0000 .

9.

10. Set mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable] to enable address filtering. 11. Ensure that the access has completed to the SLCR by issuing a data memory barrier (DMB) instruction. This allows subsequent accesses to rely on the new address mapping.

29.4.2 AXI Responses

The OCM module produces the following AXI responses: OKAY Generated for exclusive access transactions, indicating exclusive access failure. (OCM does not support exclusive access transactions). Also generated for all other successful transactions. Generated for TrustZone (TZ) violations when accessing RAM/BootROM. A TZ violation occurs when a non-secure AXI access (AxPROT[1] = 1 ) is attempted to a secure 4 KB region of RAM/BootROM (TZ operations occur at a 4 KB page granularity). Generated for attempted access to reserved locations. SLVERR also generated for parity errors detected on RAM read access, if enabled.

DECERR

SLVERR

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Chapter 30

XADC Interface
30.1 Introduction
The Xilinx analog mixed signal module, referred to as the XADC, is a hard macro. It has JTAG and DRP interfaces for accessing the XADCs status and control registers in the 7-series FPGAs. Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to control the XADC. The Zynq-7000 AP SoC devices combine a flexible analog-to-digital converter with programmable logic to address a broad range of analog data acquisition and monitoring requirements. The XADC is part of a larger analog mixed signal (AMS) topic that is a combination of analog and digital circuits. The XADC has two 12 - bit 1 mega samples per second (MSPS) ADCs with separate track and hold amplifiers, an analog multiplexer (up to 17 external analog input channels), and on-chip thermal and on-chip voltage sensors. The two ADCs can be configured to simultaneously sample two external-input analog channels. The track and hold amplifiers support a range of analog input signal types, including unipolar, bipolar, and differential . The analog inputs can support signal bandwidth of 50 0 KHz at sample rate of 1 MSPS. It is possible to support higher analog bandwidths using external analog multiplexer mode with the dedicated analog input. The XADC optionally uses an on-chip reference circuit, thereby eliminating the need for external active components for basic on-chip monitoring of temperature and power supply rails. To achieve the full 12-bit performance of the ADCs , an external 1.25V reference IC is recommended. The most recent measurement results (together with maximum and minimum readings) are stored in dedicated registers. User-defined alarm thresholds can automatically indicate over-temperature events and unacceptable power supply variation . A user-specified limit (for example , 100C) can be used to initiate a software-controlled system power- down.

Control Interfaces
Software running in the PS can communicate with the XADC in one of two ways: PS-XADC Interface: a 32-bit APB slave interface on the PS interconnect that is FIFOd and serialized. PS to PL AXI master could also be used to control the XADC via the AXI XADC core logic.

Development tools can connect to the PL-JTAG pins and control many parts of the AP SoC including the XADC. The interface is described in Chapter 27, JTAG and DAP Subsystem. The PL-JTAG interface and the internal PS-XADC interface cannot be used at the same time. The selection between the

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these interfaces is controlled by the devcfg.XADCIF_CFG[ENABLE] bit. However, the XADC arbitrates between the selected interface (PL-JTAG or PS-XADC) and the DRP interface.

System Considerations
For high-performance ADC applications managed by the PS, use the IP core Core Logic connected to an M_AXI_GP interface. This is a parallel data path. When using the PS-XADC interface, FIFOs are used for commands and read data to allow software to quickly queue-up commands without having to wait for serialization, but on the back end the data is serialized to the XADC much like the PL-JTAG interface. This is the serial datapath and is much slower.

30.1.1 Features
Analog-to-Digital Converters
Dual 12-bit 1 MSPS analog-to-digital converters (ADCs) Up to 17 flexible and user-configurable analog inputs On-chip or external reference option On-chip temperature and power supply sensors JTAG access to ADC measurements

PS-XADC Interface
Read and write XADC registers Serial data transfers to/from XADC Buffered read-write data operations 15-word by 32-bit command FIFO 15-word by 32-bit Read Data FIFO Programmable FIFO-level interrupts Programmable alarm interrupts Configured interface operations (using devcfg registers)

DRP Parallel Interface

Highest interface bandwidth 16-bit sample data

PL-JTAG Interface
Access the XADC when the PL is not programmed but is powered-up Uses the JTAG TAP controller to access the XADC registers

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Enables JTAG access to all XADC registers including ADC measurements

30.1.2 System Viewpoint

The XADC is a implemented in hard logic and resides in the PL power domain. The PS-XADC interface is part of the PS and can be accessed by the PS APU without the PL being programmed. The PL must be powered up to configure the PS-XADC interface, use the PL-JTAG or DRP interfaces, and to operate the XADC. A system level block diagram is shown in Figure 30-1.
X-Ref Target - Figure 30-1

JTAG

Dedicated pins in PL devcfg.XADCIF_CFG [31]

Zynq-7000 AP SoC Device

PL
PL-JTAG Interface

Serial Serial 32-bit APB Slave

(from Master Interconnect)

PS-XADC DevC (devcfg)

Interrupt Status

DRP
16-bit data

Arbitor

Internal Temperature Internal Voltages XADC

Security

32-bit AXI (M_AXI_GP)

PCAP

PS
LogiCORE IP AXI XADC Core Logic
Refer to the PG019 Product Specification

Alarm and OT Signals

External Voltages
Dual purpose PL pins.

Misc. Signals

Configured by Bitstream or via DRP commands.

UG585_c30_10_021913

Figure 30-1: interface.

XADC Module System Viewpoint

Note: The XADC arbitrates between the DRP interface and either the PS-XADC or the PL- JTAG

PS-XADC Interface
The PS-XADC interface description consumes the majority of this chapter. Software running in the PS configures the interface using the devcfg registers. Software writes commands to the interface that are pushed into the Command FIFO. These 32-bit writes, consisting of DRP command, address and data, are serialized and sent to the XADC in a loopback path that fills the returning Read Data FIFO that is read by the software. The interface is configured by the devcfg registers, refer to Appendix B, Register Details.

DRP Interface
The DRP interface is a parallel 16-bit bidirectional interface that can connect to a PL bus master via the LogiCORE IP AXI XADC PL logic using an AXI4-Lite interface to enable the PS or a MicroBlaze processor to control the XADC. The IP core receives 16 bits of data with each AXI4-Lite read/write transaction. The interface is described in DS790, Product Specification.

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The PL-AXI interface provides the highest performance. This interface uses the PL-AXI interface protocol and provides flexibility of integrating additional signal processing IPs in the data path of XADCs samples. For example, a FIR filter can be instantiated in the PL-AXI data path between the XADC and the M_AXI_GP interface of PS (or other logic in the PL).

PL JTAG Interface
The JTAG interface features and functions are described in UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide . This interface connects to the development tools. The Chipscope application can use the PL JTAG interface to read and write to the XADC status and control registers respectively. Note: The PL-JTAG interface is disabled, including control by Chipscope, when the PS-XADC interface is selected.

Alarms
The seven alarm and over temperature signals are routed to the PS-XADC interface and made available to the PL. For the PS-XADC interface, these are described in section 30.3 PS-XADC Interface Description. Their use by the LogiCORE IP is described in PG091, LogiCORE IP XADC Wizard Product Guide .

30.1.3 PS-XADC Interface Block Diagram

The block diagram for the PS-XADC interface is shown in Figure 30-2. The PS-XADC interface is normally controlled by software executing in the APU. The software writes 32-bit commands and nops to the command FIFO. The command FIFO output is serialized by the Serial Communications Channel in 32-bit packets for the XADC. There is a programmable idle gap time between packets to allow time for the XADC to load read data in response to the previous packet. For every word shift out from the command FIFO, a corresponding word is shifted in to the Read Data FIFO. In the case of a DRP read command, as it is shifted out of the command FIFO, the old content of XADC_DRPs DR register is shifted out. After IGAP time, the result of the current DRP read is available in XADC DRPs DR register. When the next command from TXFIFO is shifted out, the result of the current read which is in the DR register, is shifted into the RDFIFO.

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X-Ref Target - Figure 30-2

PS Interconnect

APB 3.0 Interface

32 32 32

15-deep Command FIFO

Configuration, Control, and Status Registers

15-deep Read Data FIFO

32

32

Parallel-to-serial Converter
1 XADC_PS_TCK XADC_PS_RESET XADC_PS_EN XADC_PS_ALARM[6:0] XADC_PS_OT

Serial-to-parallel Converter
1 XADC_PS_TDO
UG585_c31_01_021913

XADC_PS_TDI

Word in XADC

Figure 30-2:

XADC PS-XADC Interface Block Diagram

30.1.4 Programming Guide

PS-XADC Interface
The programming model for the PS-XADC interface is described in 30.3 PS-XADC Interface Description.

DRP Interface
The programming model for the DRP interface is described in UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide . This interface can connect to the LogiCORE IP AXI XADC interface to provide an AXI4-lite interface as described in the AXI XADC Interface product specification.

PL-JTAG Interface
The programming model for the PL-JTAG interface is described in the UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.

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Notices
7z010 CLG225 Device
This device provides four external ADC signal pairs (differential inputs). All other Zynq-7000 devices provide 12 external ADC signal pairs. The hardware pin information is provided in UG865, Zynq-7000 All Programmable SoC Packaging and Pinout product Specification.

30.2 Functional Description

The system level block diagram is shown in Figure 30-2, page 686. A block diagram of the XADC is provided in UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide . This section includes functionally that is common to more than one of the interfaces that can control the XADC. This content is not necessarily available in other documents: 30.2.1 Interface Arbiter (PL-JTAG and PS-XADC) 30.2.2 Serial Communication Channel (PL-JTAG and PS-XADC) 30.2.3 Analog-to-Digital Converter (All) 30.2.4 Sensor Alarms (PS-XADC and DRP)

30.2.1 Interface Arbiter (PL-JTAG and PS-XADC)

The XADC actively arbitrates requests between two of the three XADC interfaces. One of the interfaces is always the DRP interface that is optionally connected to the LogiCORE XADC bridge. The interfaces that are arbitrated depend on the setting of the devcfg.XADCIF_CFG [ENABLE] bit. [ENABLE] = 0 : DRP and PL-JTAG (reset default) [ENABLE] = 1: DRP and PS-XADC

If a JTAG transaction is in progress when a DRP request occurs, the LogiCORE XADC bridge can buffer the request until the JTAG transaction is complete. The XADC asserts the JTAGBUSY signal to indicate an ongoing JTAG transaction. A JTAG transaction cannot be started if a DRP read/write operation is in progress. For more details on the arbitration, please refer to UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide .

30.2.2 Serial Communication Channel (PL-JTAG and PS-XADC)

The serial communication channel connects the XADC to the PS-XADC or PL-JTAG interface, depending on the devcfg.XADCIF_CFG [ENABLE] bit setting.

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The channel is a full duplex synchronous bit-serial link with dedicated control signals using a JTAG protocol. By default, after reset, the connection between the PS and XADC (PS-XADC interface) is disabled. PS software can write a 1 to the devcfg.XADCIF_CFG [ENABLE] bit to control the source and switch the communication channel from the PL-JTAG interface to the PS-XADC interface. When the PS-XADC interface is enabled to control the XADC, the XADC is no longer accessible by the PL - JTAG interface. The inverse is true, when XADC is accessible by PL-JTAG, it can not be accessed by the PS-XADC. The PS-XADC interface interacts with the PS via an APB 3.0 interface on the PS interconnect. This interface is part of the DevC module and is described in section 6.4 Device Configuration Interface .

30.2.3 Analog-to-Digital Converter (All)

The functions and features of the XADC are described in UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.

30.2.4 Sensor Alarms (PS-XADC and DRP)

The XADC can generate an alarm signal when an internal sensor measurement exceeds the value programmed into the XADC threshold register. The alarm thresholds are stored in the XADC Control registers, refer to UG480 for their descriptions.

PS-XADC Interface
The alarm signals are routed directly from the XADC block into the PS_XADC interface block, thus allowing alarm status to be reflected directly in the PS XADCs interface registers and enabling alarms to trigger interrupts. Individual alarm interrupts can be disabled using the devcfg.XADCIF_INT_MASK register. The alarm signals are sent to the PS-XADC Interface Status register. This register is masked and the masked interrupts are ORd together to generate the IRQ ID #39 interrupt to the PS interrupt controller. When an alarm goes active, it triggers a maskable interrupt. The alarm signals get latched in the PS-XADC interface devcfg.XADCIF_INT_STS register and it can be used to determine which alarm was activated. Writing a 1 to the active alarm bit in the devcfg.XADCIF_INT_STS register clears the interrupt. The unmasked status of the alarm signals can be read using the devcfg.XADCIF_MSTS register.

DRP Interface
The alarms and OT signals are available on the DRP interface. They are actively connected to and used by the LogiCORE AXI_XADC bridge, refer PG019, LogiCORE IP AXI XADC Product Guide .

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Functional Description
When the measured value on a voltage sensor is greater than the maximum thresholds or less than the minimum threshold values, then the output alarm signal goes active. The alarm is reset (inactive) when a subsequent measurement value falls between the upper and lower threshold values . This operation differs for the temperature sensor alarm, The temperature alarm goes active when the measured temperature exceeds the high threshold. The temperature alarm is reset (inactive) when the temperature falls below the lower threshold value. The alarm signals are summarized in Table 30-1. Table 30-1: Alarm
ALM[0] ALM[1] ALM[2] ALM[3] ALM[4] ALM[5] ALM[6] OT

XADC Alarm Signals Description

Programmable Temperature sensor alarm VCCINT sensor alarm (PL internal voltage) VCCAUX sensor alarm (PL auxiliary voltage) VCCBRAM sensor alarm (PL BRAM voltage) VCCPINT sensor alarm (PS internal voltage) VCCPAUX sensor alarm (PS auxiliary voltage) VCCO_DDR sensor alarm (PS DDR I/O voltage) Over-temperature Alarm Refer to the LogiCORE User Guide sections: Maximum and Minimum Status Registers Automatic Alarms

Upper/Lower Threshold Control and Maximum/Minimum Status Registers

30.3 PS-XADC Interface Description

The main function of the PS-XADC interface is to serialize commands written by software before sending them to the XADC, and to perform a serial-to -parallel conversion when serial data is received from the XADC for the software to read.

30.3.1 Serial Channel Clock Frequency

The serial communications channel between the PS-XADC interface and the XADC should not be clocked faster than 50 MHz. The serial clock is derived from the PCAP clock generated by the PS clock subsystem (refer to Chapter 25, Clocks). This clock has a nominal frequency of 200 MHz. A configurable clock divider is controlled by the devcfg.XADCIF_CFG [TCLK_RATE] bit field to reduce the PCAP clock frequency to no more than 50 MHz. XADC serial clock = PCAP clock / [TCLK_RATE] The XADC serial clock drives the DCLK that is described in the LogiCORE User Guide.

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30.3.2 Command and Data Packets

The PS-XADC interface buffers the 32-bit reads and writes to minimize the effects of the slow serial transfer process on PS system throughput. The PS-XADC interface buffers up to 15 commands. Each command is serialized and communicated to the XADC. For every command that is written to the PS-XADC interface, a data word is received in the Read Data FIFO. The Read Data FIFO can store 15 data words . Up to 15 commands at a time to be written and up to 15 read data words can be in FIFOs. After a read command has been written, the corresponding read data is available after the next command is serialized to the XADC. Therefore, if the last command in CMD FIFO is a read command, one additional nop command is always needed to push out the last read data . The XADC commands are listed in the LogiCORE user guide . All control commands, read requests, write requests, and NOPs shift data into the Read Data FIFO that can be read using the devcfg.XADCIF_RDFIFO register. The software controlling the PS-XADC interface should account for this and should read and discard data not generated by a read command. XADC read data is 32-bits but only the 16 LSBs of the 32-bit word contain ADC data.

PS-XADC Event Timing

Command register write Serialized to XADC (control and data) Programmable idle gap width, devcfg.XADCIF_CFG [IGAP]

X-Ref Target - Figure 30-3

Write Sequence to the Command FIFO

First Command Second Command Dummy Data

n
32-bit

n+1

n+2

Idle Gap Time

PS_TDO Signal (commands)

32 bits

Command is processed by the XADC. PS_TDI Signal (results)

Command is processed by the XADC.

32-bit

Reads from Data Read FIFO

n-1
Dummy Data or Previous Command Result

n
Result from First Command

n +1
Result from Second Command
UG585_c30_11_022513

Figure 30-3:

XADC PS-XADC Interface Event Timing Diagram

The status of the command and Read Data FIFOs can be monitored using the devcfg.XADCIF_MSTS Interface Miscellaneous Status register. Software can also setup interrupts using the devcfg.XADCIF_INT_STS iNterrupt Status register.

Note: Reading from an empty Read Data FIFO causes an APB slave bus error.

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One packet remains in the XADC when the Command FIFO is emptied. To retrieve the packet, write a dummy command.

30.3.3 Command Format

Figure 30-4 shows the data format of the PS-XADC interface commands. The first 16 LSBs of the XADCIF_CMD_FIFO contain the DRP register data . For both read and write operations, the address bits , XADCIF_CMD_FIFO [25:16], hold the DRP target register address . The command bits, XADCIF_CMD_FIFO [29:26], specify a read , write , or no operation (see Table 30-2) .
X-Ref Target - Figure 30-4

31 30 29

26 25

16 15

X X CMD [3:0] DRP Address [9:0]

Figure 30-4: Table 30-2:
0 0 0 0 0 0

DRP Data [15:0]

UG585_c30_12_021913

PS-XADC Interface Command Register

PS-XADC Interface DRP Command Format Operation

0 1 0 No operation DRP read DRP Write Not defined 0 0 1

CMD [3:0]

Others

DPR Address and DRP Data

The full list of XADC DRP registers and instructions on how to configure them can be found in the UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide .

30.3.4 Read Data Format

The XADC data is returned in the lower 16 bits of the devcfg.XADCIF_RDFIFO register read. The interpretation of the DRP data can be found in the UG480 LogiCORE User Guide.
X-Ref Target - Figure 30-5

31

16 15

0
Figure 30-5:

DRP Data [15:0]

UG585_c30_13_021913

PS-XADC Interface Read Data Format

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30.3.5 Min/Max Voltage Thresholds

The XADC tracks the minimum and maximum values recorded for the internal supply sensors since the last power-up or the last reset of the XADC control logic. The maximum and minimum values recorded are stored in the DRP Status registers. On power-up or after reset, all Minimum registers are set to FFFFh and all Maximum registers are set to 0000h . Each new measurement generated for an on-chip sensor is compared to the contents of its Maximum and Minimum register. If the measured value is greater than the contents of it Maximum register, the measured value is written to the Maximum register. Similarly, for the Minimum register, if the measured value is less than the contents of its Minimum register, the measured value is written to the Minimum register. This check is carried out each time a measurement result is written to the Status register.

30.3.6 Critical Over-temperature Alarm

Note: This feature sends an interrupt status to the PS and causes an automatic shutdown feature for
the PL side of the Zynq-7000 device if enabled. The FPGA function is enabled via the bitstream. The on-chip temperature measurement is used for critical temperature warnings. The default over temperature threshold is 125C. This threshold is used when the contents of the OT Upper Alarm register (listed in UG480) have not been configured. When the die temperature exceeds the threshold set in the XADCs Control register, the over-temperature alarm (OT) becomes active. The OT signal resets when the die temperature has fallen below set threshold. The OT alarm can also be used to automatically power down the PL upon activation. The OT alarm can be disabled by writing a 1 to the OT bit in the XADCs Configuration register. Note: these registers are in the XADC and are accessible using the DRP. The XADC OT alarm signal is sent to the PS via the dedicated PS-XADC interface. When the OT alarm goes active it triggers a maskable interrupt . The OT bit of the XADCIF_INT_STS register needs to be cleared by writing a 1 to the bit location . The real time value of the OT alarm signal can be found on the XADCIF_MSTS register.

30.4 Programming Guide for the PS-XADC Interface

The following sequence describes how to configure and interact with the PS-XADC interface to read an internal VCC auxiliary PS voltage (VCCPAUX) and raise an Alarm interrupt when VCCPAUX value does not fall between higher and lower thresholds. The PS-XADC interface specifies commands to be sent in a specific format as described in section 30.3.3 Command Format. Refer to detailed examples in section 30.4.3 Command Preparation.

Example: Initialization of XADC via the PS-XADC Interface

This example resets the communications channel and the XADC. It also flushes the FIFOs; leaving a NOOP (dummy) word in the XADC.

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1. 2. 3.

Reset the serial communication channel. Write a 1 and then a 0 to devcfg.XADCIF_MCTRL [RESET]. Reset the XADC. Write any 16-bit value to DRP address 0x03 (reset register). Write 08030000h to the devcfg.XADCIF_CMDFIFO register. Flush the FIFOs. There is no reset signal, instead flush the FIFOs: a. Wait for the Command FIFO to empty. The last command should be a NOOP (dummy write). b. Read the Read Data FIFO until empty.

Example: Start-up Sequence via the PS-XADC Interface

This example sets various interface parameters and includes steps for interrupts and data transfers. It assumes the interface and the XADC are already initialized. 1. Configure the PS-XADC interface : Program the configuration register. Write 80001114h into the devcfg.XADCIF_CFG register: a. c. e. f. 2. 3. Use default Minimum idle gap, [IGAP] = 14h (20 clocks). Use default FIFO serial read capture edge (rising), [REDGE] = 1 . Use default Read Data FIFO threshold level, [DFIFOTH] = 0x0 . Use default Command FIFO threshold level, [CFIFOTH] = 0 . b. Use default XADC clock frequency to 1/4 of PCAP clock frequency, [TCKRATE] = 01 . d. Use default FIFO serial write launch edge (falling), [WEDGE] = 0 .

g. Enable the PS access of XADC. Write 0x1 to devcfg.XADCIF_CFG [ENABLE]. Configure the interrupts : Interrupts are used to manage the alarms from the XADC and Command/Read Data FIFOs. Refer to the program example in section 30.5.3 Interrupts. Data transfers to the XADC : Refer to section 30.5.2 Read and Write FIFOs.

30.4.1 Read and Write to the FIFOs

This example configures the devcfg.XADCIF_CFG register for the FIFOs and communications channel. This register controls the command and Read Data FIFO thresholds, the clock rate of the XADC, the clocking edges for the serial bus and the idle gap between serial packets. After power on Command and Read Data FIFOs of the PS-XADC interface are empty, but must be flushed after an XADC interface reset. Commands for writing to or reading from XADC registers are sent to the XADC using the Command FIFO, and data returned from the XADC is collected in the Read Data FIFO.

Example: Write Command to the XADC

This example writes to the XADC VCCPAUX Alarm Upper threshold register. 1. 2. Prepare command. Prepare the command as described in section 30.4.3 Command Preparation for writing to the XADC VCCPAUX Alarm Upper threshold register ( 0x5A ) with required threshold. Fill the Command FIFO with data . Write the data formatted in step 1 to the devcfg.XADCIF_CMDFIFO register.

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3.

Wait until the Command FIFO becomes empty. Wait until devcfg.XADCIF_MSTS [CFIFOE] = 1.

Note: For every write to the devcfg.XADCIF_CMDFIFO register, data is shifted into the
devcfg.XADCIF_RDFIFO register (Read Data FIFO).

Example: Read the VCCPAUX value from the XADC

This example reads the current VCCPAUX value from the XADC VCCPAUX status register. 1. 2. 3. 4. 5. 6. 7. Prepare command . Prepare the command as described in section 30.4.3 Command Preparation for reading the XADC VCCPAUX Status register ( 0x0E ). Write data to Command FIFO. Write data formatted in step 1 to the devcfg.XADCIF_CMDFIFO register. Wait until the Command FIFO becomes empty. Wait until devcfg.XADCIF_MSTS [CFIFOE] = 1. Read dummy data from the Read Data FIFO. Read the devcfg.XADCIF_RDFIFO register. Format data. Prepare Command for No operation as described in 30.4.3 Command Preparation. Write data to the Command FIFO. Write the formatted data in step 5 to the devcfg.XADCIF_CMDFIFO register. Read the Read Data FIFO. Read the devcfg.XADCIF_RDFIFO register.

Note: After a read command has been sent to the XADC, the corresponding read data will be

available during the next shift period. Therefore, one dummy command write (as shown in step 5) is always needed to push out the last read data.

30.4.2 Interrupts
Example: Configure and Manage Alarm 5 (VCCPAUX)
This example configures the XADC registers to set alarm thresholds, operating mode, and enables the Alarm 5 (VCCPAUX) interrupt in the PS-XADC interface. The XADC hard macro has to be operated in Independent mode because alarms are not enabled in Default mode (refer to the XADC Operating Modes section of UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. 1. Prepare commands. Prepare commands as described in section 30.4.3 Command Preparation for writing to the XADC hard macro alarm threshold registers (VCCPAUX Upper- 0x5A and VCCPAUX Lower- 0x5E ) with the required thresholds and XADC Config_Reg1 (0x41 ) to set the XADC in Independent mode. Write commands to the Command FIFO. Write the commands prepared in step 1 to the devcfg.XADCIF_CMDFIFO register. Enable the Alarm 5 interrupt in the PS-XADC interface. Write devcfg.XADCIF_INT_MASK [M_ALM] = 7Eh . Check if Alarm 5 is triggered. Poll for devcfg.XADCIF_INT_STS [M_ALM] = 1 . Clear the Alarm 5 interrupt. Write devcfg.XADCIF_INT_STS [M_ALM] = 1 . Disable the Alarm 0 interrupt. Write devcfg.XADCIF_INT_MASK [M_ALM] = 7Fh

2. 3. 4. 5. 6.

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30.4.3 Command Preparation

Example: Prepare Data for Writing to the XADC Register
This example formats data for writing to XADC Configuration Register 1 to set the XADC in Independent mode. Refer toTable 30-2, page 691. 1. 2. 3. DRP data. Data to set the XADC in independent mode is 8000h . Refer to the XADC Register Interface section of UG480. DRP address. The address of the XADC Configuration Register 1 is 0x41 . Write command . The command for a write operation is 0010b . The command to write 8000h in XADC Configuration Register 1 ( 0x41 ) is 08418000h .

Example: Prepare Data for Reading from the XADC Register

This example formats data for reading the XADC VCCPAUX Status register, 0x0E . 1. 2. 3. DRP data. Data can be any arbitrary data for the read operation (0 ). DRP address. The address of the XADC VCCPAUX Status register is 0x0E . Write command . The command for a read operation is 0001b . The command to read the XADC VCCPAUX Status register, 0x0E , is 040E0000h .

30.4.4 Register Overview

An overview of the PS-XADC Interface control registers is shown in Table 30-3. Register bit details are provided in Appendix B, Register Details. Refer to the XADC Register Interface section of UG480 LogiCORE User Guide for register details of the XADC.

Note: After power-up (refer to the Zynq-7000 AP SoC data sheet for the proper voltage sequencing),
PS-to-PL voltage shifters are automatically enabled. The PL must be powered-up to access the PS-XADC interface registers, but the PL does not need to be configured to access the registers. Table 30-3 shows an overview of XADC Interface registers. Table 30-3: Register Overview Mnemonic
devcfg.XADCIF_CFG Configuration devcfg.XADCIF_MCTL Interrupts devcfg.XADCIF_INT_STS devcfg.XADCIF_INT_MASK devcfg.XADCIF_MSTS

Function

Description
Configuration: Enable, FIFO threshold, frequency ratio, and launch edge. XADC Interface Misc. Control register XADC Interface Interrupt Status register XADC Interface Interrupt Mask register XADC Interface Misc. Status register

Type
Read/Write Read/Write Read, Write 1 to clear Read/Write Read

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Table 30-3:

Register Overview (Contd) Mnemonic

devcfg.XADCIF_CMDFIFO devcfg.XADCIF_RDFIFO

Function
Command and Read Data FIFOs

Description
XADC Interface Command FIFO XADC Interface Read Data FIFO

Type
Write Read

30.5 Programming Guide for the DRP Interface

The XADC can also be accessed by instantiating a LogiCORE AXI XADC bridge in the PL. This method provides more powerful features and easy access to all XADC registers and signals using a register read/write programming model for microprocessors.

30.6 Programming Guide for the PL-JTAG Interface

The PS-XADC interface commands are similar to the JTAG DRP commands. Refer to the JTAG DRP commands shown in UG480 .

Note: PL-JTAG cannot access the XADC if the PS-XADC interface is accessing the XADC (i.e.,
devcfg.XADCIF_CFG [ENABLE] = 1 ).

30.7 System Functions

30.7.1 Clocks
Clocking is determined by the interface choice.

PS-XADC Interface Clocks

1. 2. 3. The PS-XADC interface uses FIFOs to cross between the PS system clock and the XADCIF clock . PS system interface clock is the CPU_1x clock. The XADCIF clock frequency is the PCAP clock / [TCLKRATE]. a. c. The XADCIF clock maximum frequency is 50 MHz. The [TCLKRATE] bit: divide 2, 4 (default), 8, or 16. b. The PCAP clock frequency is nominally 200 MHz.

See Chapter 25, Clocks for more information about the PS clocks.

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DRP Interface Clocks

The PL-AXI interface is a soft core instantiated within the PL and uses a clock from one of the PLs PLLs.

PL-JTAG Interface Clocks

PL-JTAG uses the JTAG port to interface with the XADC and uses the JTAG clock, TCK.

30.7.2 Resets
There are several resets in the XADC module.

PS-XADC Interface Reset

The PS-XADC interface and its serial communication channel to the XADC are reset using devcfg.XADCIF_MCTRL [RESET].

Note: The PS-XADC FIFOs are not cleared by the interface reset.

XADC Reset
The XADC is reset by writing to the reset register using a DRP address of 03h . Write 0x08030000 to the devcfg.XADCIF_CMDFIFO register. The data that is included is ignored by the XADC.

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PCI Express
31.1 Introduction
The Zynq-7z030, Zynq-7z045, and Zynq-7z100 AP SoC devices include the Xilinx 7 series Integrated block for PCI Express core which is a reliable, high-bandwidth, third-generation I/O solution. The PCI Express solution for these Zynq AP SoC devices supports x1, x2, x4, and x8 lane Root Port and Endpoint configurations at both Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) speeds. Attention must be paid to system level bandwidth if full Gen 2 x8 throughput is needed. This might include either inline processing of the data in PL before storing it to the PS DDR memory or using a wider DDR3 memory interface in the PL. The Root Port configuration can be used to build a Root Complex solution. These configurations are compatible with the PCI Express Base Specification, Rev 2.1. The PCI Express module supports the AXI4-stream interface for the user interface at both 64-bit and 128-bit widths. For more detailed information regarding the 7 Series FPGAs Integrated block for PCI Express core, refer to these documents on the Xilinx website: DS821, LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express Data Sheet UG477, LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express User Guide

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31.2 Block Diagram

X-Ref Target - Figure 31-1

LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express Core

TX Block RAM RX Block RAM

User Logic

Transaction (AXI-ST)

Physical Layer Control and Status

Physical (PL)

7 Series FPGAs Integrated Block for PCI Express (PCIE_2_1)

PCI Express (PCI_EXP)

Transceivers

PCI Express Logic

Host Interface

Configuration (CFG)

Optional Debug

User Logic

User Logic

Optional Debug (DRP)

System (SYS)

Clock and Reset

UG585_c32_01_021313

Figure 31-1:

PCI Express Block Diagram

For additional information regarding the different interfaces to the Integrated block for PCI Express core, refer to Chapter 2: Core Overview of UG477, 7 Series FPGAs Integrated Block for PCI Express User Guide .

31.3 Features
The PCI Express core provides these key features: High-performance, highly flexible, scalable, and reliable, general-purpose I/O core

Compatible with the PCI Express Base Specification, rev. 2.1 Compatible with conventional PCI software model

Incorporates Xilinx Smart-IP technology to guarantee critical timing Uses GTXE2 transceivers for 7 Series FPGA families

2.5 Gb/s and 5.0 Gb/s line speed Supports 1-lane, 2-lane, 4-lane, and 8-lane operation Elastic buffers and clock compensation

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Automatic clock data recovery

Supports Endpoint and Root Port configurations 8B/10B encode and decode Supports lane reversal and lane polarity inversion per PCI Express specification requirements Standardized user interface

Supports AXI4-stream interface Easy-to-use packet-based protocol Full-duplex communication Back-to-back transactions enable greater link bandwidth utilization Supports flow control of data and discontinuation of an in-process transaction in transmit direction

Supports flow control of data in receive direction Compatible with PCI/PCI Express power management functions Supports a maximum transaction payload of up to 1,024 bytes Supports multi-vector MSI for up to 32 vectors and MSI-X Up-configure capability enables application-driven bandwidth scalability Compatible with PCI Express transaction ordering rules

31.4 Endpoint Use Case

For an example of a Zynq Endpoint use case, please refer to UG963, ZC706 PCIe Targeted Reference Design User Guide .

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Device Secure Boot

32.1 Introduction
Zynq-7000 AP SoC devices support the ability to perform a secure boot to load authenticated and encrypted PS images and PL bitstreams.

32.1.1 Block Diagram

Figure 32-1 is a block diagram showing the different systems involved in a secure boot.

32.1.2 Features
Zynq-7000 AP SoC devices provide the following secure boot features: Advanced Encryption Standard

AES-CBC with 256-bit key Encryption key stored on-chip in either eFuse or Battery-backed RAM (BBRAM) SHA-256 authentication engine (FIPS180-2) 2048-bit public key

Keyed-hashed message authentication code (HMAC)

RSA public key authentication

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X-Ref Target - Figure 32-1

bootstrap

Zynq-7000 AP SoC
ROM Step 1 On-Chip RAM NAND NOR QSPI IOP Step 3 Step 4 CPU0 CPU1

Processing System
DAP

AXI Top Switch

MDDR DDR Memory Controller

Configuration File 1 Secure FSBL

(AES Encrypted with SHA-256 HMAC)

Common Boot Path PS Boot Path PL Configuration Path

Secure Vault FIFO eFuse/BBRAM Security

AXI

FIFO PCAP

Device Configuration Block

Secure Boot Process

Step 1: Power applied, ROM begins execution Step 2: (Optional) RSA authentication performed on encrypted FSBL Step 3: FSBL decryption (AES) and authentication (HMAC) Step 4: Decrypted, authenticated FSBL stored in OCM Step 5: (Optional) PL configuration

Device Key AES HMAC JTAG

Step 5

PL

Programmable Logic
UG585_c33_01_022613

Figure 32-1:

Secure Boot Block Diagram

A device secure boot involves several systems contained within the AP SoC device. The secure boot process is always initiated by the boot ROM. If RSA authentication has been enabled the boot ROM will use the public key to authenticate the first stage boot loader (FSBL) before it is decrypted or executed. If the boot image header indicates a secure boot, the boot ROM enables the AES and HMAC engines which reside in the PL. The encrypted FSBL is then sent by the boot ROM to the AES and HMAC in the PL via the processor configuration access port (PCAP). The FSBL image is decrypted and sent back to the PS via the PCAP where it is loaded into the on-chip RAM (OCM) for execution. The PS is then able to securely configure the PL by sending an encrypted bitstream through the PCAP to the AES for decryption and distribution to the PL memory cells.

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32.2 Functional Description

32.2.1 Master Secure Boot
Master secure boot is the only secure boot mode supported in Zynq-7000 AP SoC devices. It uses the hardened AES decryption engine and the hardened HMAC authentication engine within the PL to decrypt PS images and PL bitstreams. If RSA authentication is enabled, the boot ROM authenticates the encrypted FSBL using the public key prior to decryption (see Table 32-3). The boot process for the master secure boot mode is shown in Figure 32-2.

Note: The master secure boot mode uses the AES decr yption and HMAC authentication engines

within the PL , therefore the PL must be powered on during the secure boot process. The boot ROM ensures that the PL is powered before reading the encr ypted image from the external boot device. It is the users responsibility to ensure that the PL is powered on before trying to decrypt any new configuration files .

Power on Reset
After the power-on and reset sequences have completed, the on-chip boot ROM begins to execute. An optional eFuse setting can be used to perform a full 128 KB CRC on the boot ROM for a small boot time penalty. After the integrity check the boot ROM reads the boot mode setting specified by the bootstrap pins . The boot ROM then reads the boot header from the specified external memory.

RSA Authentication Performed on FSBL

If RSA authentication is enabled the boot ROM loads the boot image header and the FSBL into the first 192 KB of the OCM. Next the public key is loaded from the boot image (see section 32.2.3 Secure Boot Image) and validated by calculating a SHA-256 signature and comparing it to the hash value stored in eFuse. If the values match, the boot ROM calculates the signature for the FSBL and authenticates it with the public key. If the public key signature does not match the hash value stored in eFuse or the authentication fails on the FSBL, the boot ROM performs a fallback and searches for a new FSBL if the boot device is NAND, NOR, or QSPI. If the fallback fails or the boot device is SD, the boot ROM enters either an error state and enables JTAG or enters a secure lockdown if the boot image was encrypted. If the authentication of the FSBL passes, the boot ROM continues the boot process. For more details see section 32.2.5 RSA Authentication.

Secure Boot
If a secure boot is specif ied in the boot image header, the boot ROM starts by checking the power-on status of the PL . Since the AES and HMAC engines reside within the PL, the PL must be powered up to perform a secure boot. The boot ROM waits until the PL is powered up before continuing the secure boot sequence. After the power-on status of the PL is conf irmed , the boot ROM begins to load the encrypted FSBL into the AES engine via the PCAP. The PL sends the decrypted FSBL back to the PS via the PCAP . The decrypted image is then loaded into the OCM . The boot ROM also monitors the HMAC authentication status of the FSBL and if an authentication error occurs, the boot ROM puts the PS into a secure lockdown state.

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Handoff to FSBL
Once the FSBL has been successfully loaded and authenticated, control is turned over to the decrypted FSBL which now resides in the OCM. Based on the user application, the FSBL could then start processing, configure the PL, load additional software, or wait for further instruction from an external source.
X-Ref Target - Figure 32-2

Power On Reset
(Debug access with JTAG disabled)

Internal memory hardware clean process (Optional ROM CRC) RSA enabled

RSA authentication performed on FSBL

Load boot image header

Secure boot

Non-secure boot

AES decryption of FSBL

(Decrypted FSBL loaded to internal RAM)

Disable and LOCK all security features (AES and HMAC)

HMAC authentication of FSBL

Load FSBL into internal RAM or external DDR memory

Disable ROM code

Disable ROM Code

Pass control to FSBL

Enable JTAG

Pass Control to FSBL

UG585_c33_02_022013

Figure 32-2:

PS Boot Flow

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32.2.2 External Boot Devices

Secure boot mode is restricted to NOR, NAND, SDIO, or Quad-SPI flash as the external boot device. A secure boot from JTAG or any other external interface is not allowed.

32.2.3 Secure Boot Image

The secure boot image format is shown in Figure 32-3 The secure boot image consists of a boot image header (required), a FSBL partition (required), a FSBL RSA authentication certificate (optional), and any number, including zero, of succeeding partitions.

Boot Image Header

The boot image header identifies the image as secure or non-secure at offset 0x028 . The value stored in the boot header at offset 0x028 determines the AES key source (see Table 32-1). More information regarding the boot image header can be found in Chapter 6, Boot and Configuration. Table 32-1: Boot ROM Header Summary Description
Encrypted image using eFuse key Encrypted image using BBRAM key Non-encrypted image

Boot ROM Header Value at 0x028

0xA5C3C5A3 0x3A5C3C5A All others

The boot image header is not encrypted.

Partition Data
Partition data is signed and encrypted. The partition data is decrypted and authenticated by the AES and HMAC engines within the PL.

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X-Ref Target - Figure 32-3

Boot Image Header

AES Encrypted Image HMAC Authenticated Image

Encrypted FSBL (AES & HMAC)

FSBL

HMAC Signature FSBL RSA authentication certificate (optional)

Partition

Partition RSA authentication certificate (optional)

AES Encrypted Image HMAC Authenticated Image

Partition

PS Image or PL Bitstream

HMAC Signature Partition RSA authentication certificate (optional) Partition Partition RSA authentication certificate (optional)

Expansion Space

. . .
Figure 32-3: Secure Boot Image Format

UG585_c33_03_022513

RSA Authentication Certificate Format

The RSA authentication certificate consists of three major components; the authentication header, the PPK and SPK, and the SPK and FSBL signatures (see Figure 32-4). The authentication header is 32-bits with the following value 0x00000101 , padded to a 512-bit boundary. Each public key consists of three parts, a 2,048-bit modulus, a 2,048-bit modulus extension to speed up calculations, and a 32-bit public exponent which gets padded to 512 bits. The other component is the 2,048-bit SPK and FSBL signatures. Since SHA-256 is used as the secure hash algorithm, the FSBL, partition, and authentication certificates must be padded to a 512-bit boundary.

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X-Ref Target - Figure 32-4

Authentication Header Authentication Header Padding Modulus (n) PPK

32 bits Padding to 512-bit boundary 2,048 bits

Modulus Extension Public Exponent Modulus (n)

2,048 bits 32 bits, padded to 512-bit boundary 2,048 bits

SPK Modulus Extension Public Exponent SPK Signature 2,048 bits 32 bits, padded to 512-bit boundary 2,048 bits

FSBL Signature

2,048 bits
UG585_c33_04_022513

Figure 32-4:

RSA Authentication Certificate Format

32.2.4 eFuse Settings

PL eFUSE Settings
The secure boot features can also be controlled via three PL eFuse bits that are described in Table 32-2. (See UG470, 7 Series FPGAs Configuration User Guide for more information regarding eFuse.) Table 32-2: PL eFuse Settings Summary eFuse
eFuse Secure Boot

Description
The AP SoC device must boot securely and use the eFuse key as the AES key source. Non-secure boot of the device is not allowed. If the boot image header does not match this setting, a security lockdown occurs. If the AP SoC device is booted in secure mode, then the eFuse key must be selected. Non-secure boot of the device is allowed. If the boot image header does not match this setting, a security lockdown occurs. The ARM DAP and PL TAP are permanently disabled. Any attempt to active the ARM DAP or the PL TAP controllers causes a security lockdown.

BBRAM Key Disable

JTAG Chain Disable

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PS eFUSE Settings
The PS also has an eFuse array. The primary purpose is to store the memory built in self repair information and the RSA public key hash. The PS eFuse also has a number of fuses that can be used to control the security boot flow of the device. (see Table 32-3). Table 32-3: PS eFuse Setting Summary eFuse
eFuse Write Protection (2 fuses)

Description
Blow both of these fuses to permanently disable all writes to the PS eFuse array. Enables a full 128 KB CRC on the ROM prior to loading the FSBL. Enables RSA authentication for NAND, NOR, SD, or QSPI. The ARM DAP and PL TAP are disabled when the device is booted in DFT mode, any attempt to activate the ARM DAP or the PL TAP causes a security lockdown. The DFT boot mode is permanently disabled. Booting in DFT mode immediately triggers a security lockdown. SHA-256 signature for the RSA primary public key including extra ECC bits.

ROM 128KB CRC Enable RSA Authentication Enable DFT JTAG Disable

DFT Mode Disable RSA PPK Hash (310 fuses)

32.2.5 RSA Authentication

The boot ROM has the ability to authenticate a secure FSBL prior to decryption or a non-secure FSBL prior to execution using RSA public key authentication. This feature is enabled by blowing the RSA Authentication Enable fuse in the PS eFuse array. When RSA authentication is enabled, the boot ROM starts by loading the FSBL into the OCM. Then the Primary Public Key (PPK) is loaded and a SHA-256 signature is calculated. This calculated signature is compared to the PPK Hash value stored in the PS eFuse. If the PPK signature matches the PPK Hash value, then the boot continues. The boot ROM then loads the Secondary Public Key (SPK) from the boot image and the SPK signature. The SPK is authenticated using the PPK. Failure to authenticate the PPK or SPK triggers a fallback mode by the boot ROM. If a new FSBL is not found, the device enters a secure lockdown. Once the SPK has been authenticated, the boot ROM calculates the SHA-256 hash value for the FSBL stored in OCM. The FSBL is authenticated using the SPK. If the authentication passes, a secure FSBL is then decrypted using the AES or a non-secure FSBL will start execution.

32.2.6 Boot Image and Bitstream Encryption

Boot images are assembled and encrypted using software provided by Xilinx, bootgen. A FSBL and any additional PS images or PL bitstreams along with the encryption key and authentication signature must be supplied to bootgen. The correct headers are generated automatically when bootgen builds the boot image.

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32.2.7 Boot Image and Bitstream Decryption and Authentication

For PS image and PL bitstream decryption, Xilinx uses the advanced encryption standard (AES) in cipher block chaining (CBC) mode with a 256-bit key. PS images and PL bitstreams are authenticated with a keyed-hashed message authentication code (HMAC) using the SHA-256 hash algorithm (FIPS180-2). When the boot ROM detects that the FSBL image is encrypted, it enables the decryption and authentication engines within the PL. Both are enabled or disabled in tandem. Subsequent PS images do not have to be encrypted. Once an encrypted FSBL has been loaded, it is trusted and can then load a non-encrypted second stage boot loader or application. The path from the external memory to the OCM can bypass the decryption/authentication engines within the PL. Loading of non-encrypted PS images after a secure boot is not recommended and should only be done after fully evaluating the system-level security.

32.2.8 HMAC Signature

The HMAC authentication requires a signature that must also be supplied to the bootgen software. This signature is not stored on the device like the AES key. It is contained and protected by the encrypted PS image or the encrypted bitstream. During the on-chip decryption process, this HMAC signature is extracted from the image or bitstream and used by the authentication algorithm. No on-chip storage for the HMAC signature is required.

32.2.9 AES Key Management

The AES encryption key is stored on-chip within the PL. It can be loaded into either volatile battery-backed RAM (BBRAM) or in non-volatile eFuse storage. The keys are loaded into the PL via the JTAG interface using the iMPACT software. (See UG470, 7 Series FPGAs Configuration User Guide for more information)

32.3 Secure Boot Features

32.3.1 Non-Secure Boot State
The non-secure state is entered when the boot ROM detects that the FSBL is not encrypted. In this state the decryption and authentication engines are disabled and locked requiring a power-on reset (POR) to re-enable. All subsequent PS images, PL configuration bitstreams, and PL partial re-configuration bitstreams must be non-encrypted. There is no mechanism to move from the non-secure state to the secure state, aside from power-on reset. Any attempt to load encrypted data after non-encrypted data results in a security violation and security lockdown.

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32.3.2 Secure Boot State

The Zynq AP SoC always powers up in the secure state, only switching to the non-secure state when the ROM detects that the FSBL is not encrypted. In the secure state the encrypted FSBL is loaded into the PS. The first configuration bitstream loaded into the PL must also be encrypted. Since the encrypted FSBL loaded in a secure boot is trusted, it is possible to load additional non-encrypted PS images. PL partial re-configuration bitstreams can be loaded via the PCAP or ICAP interfaces as encrypted or non-encrypted. Subsequent PS images or PL bitstreams must use the same key source as the FSBL, key switching is not allowed. Loading of non-encrypted images or bitstreams after a secure boot is not recommended.

32.3.3 Security Lockdown

The PS's device configuration interface contains a security policy block that is used to monitor the system security. When conflicting status is detected either from the PS or the PL that could indicate inconsistent system configuration or tampering, a security lockdown is triggered. In a security lockdown the on-chip RAM is cleared along with all the system caches. The PL is reset and the PS enters a lockdown mode that can only be cleared by issuing a power-on reset. The following conditions cause a security lockdown: Non-secure boot specified in the boot image header and secure boot only eFuse is set Enabling the JTAG chain or the ARM DAP with the JTAG chain disable eFuse set SEU error tracking has been enabled in the PS and the PL reports an SEU error A discrepancy in the redundant AES enable logic Software sets the FORCE_RST bit of the Device Configuration Control register

32.3.4 Golden Image Search

The boot ROM supports the capability to fall-back and reload to a golden image if there is a problem loading the FSBL. If RSA authentication is used, the fallback image must also be signed. If the FSBL is secure, the subsequent golden images must also be secure. Loading an encrypted golden image after loading a non-encrypted FSBL is not supported. Likewise, if the FSBL is encrypted, the golden image must also be encrypted with the same key as the FSBL. Loading a non-encrypted golden image after loading an encrypted FSBL is not supported.

32.3.5 JTAG and Debug Considerations

Whenever the boot ROM is running, the PS DAP and the PL TAP controllers are disabled, eliminating any JTAG access to the AP SoC device. In non-secure boot modes JTAG access is restored once the boot ROM has completed execution. In secure boot modes JTAG access can be restored by the FSBL or subsequent PS images as these applications are considered trusted . Access to the DAP enable registers can be locked out using the Device Configuration Interface LOCK register.

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The PS DAP and PL TAP controllers can be permanently disabled using the JTAG CHAIN DISABLE eFuse. The JTAG access to the PL can also be disabled by setting the DISABLE_JTAG configuration option when creating the PL bitstream. (see UG628, Command Line Tools User Guide for more information.

32.3.6 Readback
Whenever an encrypted bitstream is loaded into the PL, readback of the internal configuration memory cannot be performed by any of the external interfaces, including JTAG. The only readback access to the configuration memory after an encrypted bitstream load is via PCAP or ICAP. The PCAP and ICAP interfaces are trusted channels since access to these interfaces are from an authenticated PS image or an authenticated PL bitstream.

32.3.7 Secure Boot Modes of Operation

Zynq RSA authentication and AES encryption features can be used in a number of combinations to deliver a flexible secure boot solution. Table 32-4 through Table 32-7 show the possible authentication and encryption options available for a Zynq secure boot. The following two points must be taken into consideration when using secure boot: 1. 2. The FSBL must be encrypted if any other PS images or PL bitstreams are required to be encrypted. The boot ROM only provides authentication for the FSBL. If any other PS images or PL bitstreams require authentication, the RSA algorithm must be provided as user software. Non-secure Boot Options Boot ROM RSA
FSBL PL Bitstream u-Boot Linux Applications No Not allowed Not allowed Not allowed Not allowed

Table 32-4:

User SW RSA
Not allowed No No No No

AES / HMAC
No Not allowed Not allowed Not allowed Not allowed

Table 32-5:
FSBL PL Bitstream u-Boot Linux Applications

RSA Authenticated Options Boot ROM RSA

Yes Not allowed Not allowed Not allowed Not allowed

User SW RSA
Not allowed Allowed Allowed Allowed Allowed

AES / HMAC
No Not allowed Not allowed Not allowed Not allowed

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Table 32-6:
FSBL PL Bitstream u-Boot Linux Applications

Secure Boot Options Boot ROM RSA

No Not allowed Not allowed Not allowed Not allowed

User SW RSA
Not allowed Allowed Allowed Allowed Allowed

AES / HMAC
Yes Allowed Allowed Allowed Allowed

Table 32-7:
FSBL PL Bitstream u-Boot Linux Applications

Authenticated Secure Boot Options Boot ROM RSA

Yes Not allowed Not allowed Not allowed Not allowed

User SW RSA
Not allowed Allowed Allowed Allowed Allowed

AES / HMAC
Yes Allowed Allowed Allowed Allowed

32.4 Programming Considerations

Although most of the secure boot process is handled by the boot ROM, it is possible to decrypt PS images or PL bitstreams after the initial boot. To decrypt secure images the PL must be powered on. The PL is powered on and ready to accept new encrypted data if the PCFG_INIT bit of the Device Configuration Interface (DevC) Status register is set. To send encrypted data to the PL for decryption, the PCAP_MODE and PCAP_PR bits of the DevC Control register must be set to 1 . Because the AES engine decrypts data one byte at a time, the QUARTER_PCAP_RATE_EN bit on the DevC Control register must also be set to 1 . To disable the AES and HMAC engines, the three PCFG_AES_EN bits of the DevC Control register must be set to 0 . All three bits must be set with the same register write or a security violation occurs, resulting in a security lockdown of the device. Once the AES and HMAC engines have been disabled, they cannot be enabled again without a power-on-reset.

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Appendix A

Additional Resources
A.1 Xilinx Resources
Product Support and Documentation
www.xilinx.com/support

Xilinx Glossary
www.xilinx.com/company/terms.htm

Device User Guides

http://www.xilinx.com/support/documentation/zynq-7000_user_guides.htm http://www.xilinx.com/support/documentation/7_series_user_guides.htm

Xilinx Design Tools: Installation and Licensing Guide (UG798)

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/iil.pdf

Xilinx Design Tools: Release Notes Guide (UG631)

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/irn.pdf

Xilinx Forums and Wiki Links

http://forums.xilinx.com http://wiki.xilinx.com http://wiki.xilinx.com/zynq-linux http://wiki.xilinx.com/zynq-uboot

Xilinx git Websites

http://git.xilinx.com

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Appendix A: Additional Resources

A.2 Solution Centers

See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.

A.3 References
A.3.1 Zynq-7000 AP SoC Documents
Refer to the following Zynq-7000 AP SoC documents for further reference:

DS190, Zynq-7000 AP SoC Product Overview DS187, Zynq-7000 AP SoC (7z010 and 7z020): AC and DC Switching Characteristics Data Sheet DS191, Zynq-7000 AP SoC (7z030, 7z045, and 7z100): AC and DC Switching Characteristics Data Sheet UG865, Zynq-7000 AP SoC Packaging and Pinout Specifications UG821, Zynq-7000 AP SoC Software Developers Guide UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide EN191, Zynq-7000 AP SoC Errata Sheet

A.3.2 PL Documents Device and Boards

To learn more about the PL resources, refer to the following 7 Series FPGA User Guides:

DS821, Xilinx LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express Product Specification UG471, Xilinx 7 Series FPGAs SelectIO Resources User Guide UG472, Xilinx 7 Series FPGAs Clocking Resources User Guide UG473, Xilinx 7 Series FPGAs Memory Resources User Guide UG474, Xilinx 7 Series FPGAs Configurable Logic Block User Guide UG476, Xilinx 7 Series FPGAs GTX Transceiver User Guide UG477, Xilinx 7 Series FPGAs Integrated Block v1.3 for PCI Express User Guide UG479, Xilinx 7 Series FPGAs DSP48E1 User Guide UG480, Xilinx 7 Series FPGAs XADC User Guide UG483, Xilinx 7-Series FPGAs PCB and Pin Planning Guide

These user guides and additional relevant information can be found in the 7 Series overall set of documentation on the 7 Series FPGAs, which is available on the Xilinx website: http://www.xilinx.com/support/documentation/7_series.htm Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.5) March 7, 2013 www.xilinx.com 714

Appendix A: Additional Resources

A.3.3 Advanced eXtensible Interface (AXI) Documents

Refer to UG761, AXI Reference Guide for further reference on the AXI protocol.

A.3.4 Software Documents

Zynq-7000 AP SoC Software Developers Guide (UG821)
http://www.xilinx.com/support/documentation/zynq-7000_user_guides.htm

Zynq EDK Concepts, Tools, and Techniques Guide (UG873)

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug873-zynq-ctt.pdf The source drivers for stand alone and FSBL are provided as part of the Xilinx IDE Design Suite Embedded Edition. The Linux drivers are provided via the Xilinx Open Source Wiki at: http://wiki.xilinx.com Xilinx Alliance Program partners provide system software solutions for IP, middleware, operation sys tems, etc. For the latest information refer to the Zynq-7000 landing page at: http://www.xilinx.com/products/silicon-devices/soc/zynq-7000

A.3.5 git Information

http://git-scm.com http://git-scm.com/documentation http://git-scm.com/download

A.3.6 Design Tool Documents

Xilinx Command Line Tools User Guide (UG628) Xilinx ISE Manuals
http://www.xilinx.com/support/documentation/dt_ise.htm

Xilinx XPS/EDK Supported IP Website

http://www.xilinx.com/ise/embedded/edk_ip.htm

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Appendix A: Additional Resources

ChipScope Pro Software and Cores User Guide (UG029) PlanAhead Tutorial: Debugging with ChipScope (UG677) Xilinx Problem Solvers
http://www.xilinx.com/support/troubleshoot.htm

A.3.7 EDK Documentation

The entire EDK documentation set can be accessed at: http://www.xilinx.com/support/documentation/dt_edk_edk14-1.htm

Embedded System Tools Reference Manual (UG111): http://www.xilinx.com/support/documentation/xilinx14_1/est_rm.pdf

OS and Libraries Document Collection (UG643): http://www.xilinx.com/support/documentation/xilinx14_1/oslib_rm.pdf

Platform Specification Format Reference Manual (UG642): http://www.xilinx.com/support/documentation/xilinx14_1/psf_rm.pdf

EDK Tutorials Website

http://www.xilinx.com/support/documentation/dt_edk_edk14-1_tutorials.htm

Platform Studio and EDK Website

http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm

XPS/EDK Supported IP Website

http://www.xilinx.com/ise/embedded/edk_ip.htm

A.3.8 Third-Party IP and Standards Documents

To learn about functional details related to vendor IP cores contained in Zynq-7000 devices or related international interface standards, refer the following documents:

Note: ARM documents can be found at: http://infocenter.arm.com/help/index.jsp

ARM AMBA Level 2 Cache Controller (L2C-310) TRM (also called PL310) ARM AMBA Specification Revision 2.0, 1999 (IHI 0011A) ARM Architecture Reference Manual (Need to register with ARM) ARM Cortex-A Series Programmer's Guide

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Appendix A: Additional Resources

ARM Cortex-A9 Technical Reference Manual, Revision r3p0 ARM Cortex-A9 MPCore Technical Reference Manual, Revision r3p0 (DDI0407F) includes descriptions for accelerator coherency port (ACP), CPU private timers and watchdog timers (AWDT), event bus, general interrupt controller (GIC), and snoop control unit (SCU) ARM Cortex-A9 NEON Media Processing Engine Technical Reference Manual, Revision r3p0 ARM Cortex-A9 Floating-Point Unit Technical Reference Manual, Revision r3p0 ARM CoreSight v1.0 Architecture Specification includes descriptions for ATB Bus, and Authentication ARM CoreSight Program Flow Trace Architecture Specification ARM Debug Interface v5.1Architecture Specification ARM Debug Interface v5.1 Architecture Specification Supplement ARM CoreSight Components TRM includes descriptions for embedded cross trigger (ECT), embedded trace buffer (ETB), instrumentation trace macrocell (ITM), debug access port (DAP), and trace port interface unit (TPIU) ARM CoreSight PTM-A9 TRM ARM CoreSight Trace Memory Controller Technical Reference Manual ARM Generic Interrupt Controller v1.0 Architecture Specification (IHI 0048B) ARM Generic Interrupt Controller PL390 Technical Reference Manual (DDI0416B) ARM PrimeCell DMA Controller (PL330) Technical Reference Manual ARM Application Note 239: Example programs for CoreLink DMA Controller DMA-330 ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual, Revision r2p1, 12 October 2007 (ARM DDI 0380G)

BOSCH, CAN Specification Version 2.0 PART A and PART B, 1991 Cadence, Watchdog Timer (SWDT) Specification IEEE 802.3-2008 - IEEE Standard for Information technology-Specific requirements - Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, 2008 Universal Serial Bus (USB) Specification, Revision 2.0 UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0 SD Association, Part A2 SD Host Controller Standard Specification Ver2.00 Final 070130 SD Association, Part E1 SDIO Specification Ver2.00 Final 070130 SD Group, Part 1 Physical Layer Specification Ver2.00 Final 060509

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Appendix B

Register Details
B.1 Overview
This appendix provides details of all the memory-mapped registers in the Zynq-7000 AP SoC. Throughout this manual, the names of registers and register bit fields used match those given in the hardware. They are called the hardware names. C header files are delivered with this product which define register and bit field names for easy use in software code. In some cases, the software names are different from the hardware names. This appendix includes software names where they differ from hardware names: Software Module Name: This is included in the module introduction section and is named Software Name . Software Register Name: This is included in the detailed register description and is also named Software Name . Software Bit field Name: These are included in the register bit field tables in the Field Name column. These names follow the hardware field name and are contained in parentheses.

Note: If a software name does not exist in the C header files or if it exists but is the same as the
hardware name, it is not included in this appendix and the above fields are not present. The software register name will be: <software module name>_<software register name>_<optional suffix> . One common suffix used for register names is OFFSET, which would give the OFFSET address of that register from the base address for the module. The software bit field name will be: <software module name>_<software register name>_<software bit field name>_<optional suffix> . One common suffix used for bit field names is MASK, which would be useful when extracting the bit field of interest from the full register.

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Appendix B: Register Details

B.2 Acronyms
The following acronyms are used for many of the registers.
Access Type
clronrd clronwr nsnsro nsnsrw nsnswo nssraz raz ro rud rw rwso sro srw swo waz wo wtc z Readable, clears value on read Readable, clears value on write During non-secure access, if thread is non-secure, it is read only During non-secure access, if thread is non-secure, it is read write During non-secure access, if thread is non-secure, it is write only During non-secure access, if thread is secure, it is read as zero Read as zero Read-only Read undefined Normal read/write Read/write, set only During secure access, it is read only During secure access, it is read write During secure access, it is write only Write as zero Write-only Readable, write a one to clear Access (read or write) as zero

Description

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Appendix B: Register Details

B.3 Module Summary

Module Name axi_hp0 axi_hp1 axi_hp2 axi_hp3 can0 can1 ddrc debug_cpu_cti 0 debug_cpu_cti 1 debug_cpu_p mu0 debug_cpu_p mu1 debug_cpu_pt m0 debug_cpu_pt m1 debug_cti_etb _tpiu debug_cti_ftm debug_dap_ro m debug_etb debug_ftm debug_funnel Module Type axi_hp axi_hp axi_hp axi_hp can can ddrc cti cti cortexa9_pmu cortexa9_pmu ptm ptm cti cti dap etb ftm funnel Base Address 0xF8008000 0xF8009000 0xF800A000 0xF800B000 0xE0008000 0xE0009000 0xF8006000 0xF8898000 0xF8899000 0xF8891000 0xF8893000 0xF889C000 0xF889D000 0xF8802000 0xF8809000 0xF8800000 0xF8801000 0xF880B000 0xF8804000 Description AXI_HP Interface (AFI) AXI_HP 0 Interface AXI_HP Interface (AFI) AXI_HP 1 Interface AXI_HP Interface (AFI) AXI_HP 2 Interface AXI_HP Interface (AFI) AXI_HP 3 Interface Controller Area Network Instance no. 0. Controller Area Network Instance no. 1. DDR memory controller Cross Trigger Interface CoreSight Cross Trigger Interface for CPU 0. Cross Trigger Interface CoreSight Cross Trigger Interface for CPU 1. Cortex A9 Performance Monitoring Unit Cortex A9 Performance Monitoring Unit for CPU 0. Cortex A9 Performance Monitoring Unit Cortex A9 Performance Monitoring Unit for CPU 1. CoreSight PTM-A9 CoreSight Program Trace Macrocell for CPU 0. CoreSight PTM-A9 CoreSight Program Trace Macrocell for CPU 1. Cross Trigger Interface CoreSight Cross Trigger Interface for the ETB and TPIU. Cross Trigger Interface CoreSight Cross Trigger Interface for the FTM. Debug Access Port ROM Table Embedded Trace Buffer Fabric Trace Macrocell CoreSight Trace Funnel

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Appendix B: Register Details

Module Name debug_itm debug_tpiu devcfg dmac0_ns dmac0_s gem0 gem1 gpio gpv_qos301_c pu gpv_qos301_d mac

Module Type itm tpiu devcfg dmac dmac GEM GEM gpio qos301

Base Address 0xF8805000 0xF8803000 0xF8007000 0xF8004000 0xF8003000 0xE000B000 0xE000C000 0xE000A000 0xF8946000

Description Instrumentation Trace Macrocell Trace Port Interface Unit Device configuraion Interface Direct Memory Access Controller, PL330 Direct Memory Access Controller (Non-Secure Mode) Direct Memory Access Controller, PL330 Direct Memory Access Controller (Secure Mode) Gigabit Ethernet Controller Instance no. 0. Gigabit Ethernet Controller Instance no. 1. General Purpose Input / Output AMBA Network Interconnect Advanced Quality of Service (QoS-301) AMBA Quality of Service for CPU-to-DDR. AMBA Network Interconnect Advanced Quality of Service (QoS-301) AMBA Quality of Service for DMAC. AMBA Network Interconnect Advanced Quality of Service (QoS-301) AMBA Quality of Service for IOU. AMBA NIC301 TrustZone.

qos301

0xF8947000

gpv_qos301_io qos301 u gpv_trustzone

0xF8948000

nic301_addr_r 0xF8900000 egion_ctrl_regi sters IIC IIC L2Cpl310 mpcore ocm qspi sdio 0xE0004000 0xE0005000 0xF8F02000 0xF8F00000 0xF800C000 0xE000D000 0xE0100000

i2c0 i2c1 l2cache mpcore ocm qspi sd0

Inter Integrated Circuit (I2C) Instance no. 0. Inter Integrated Circuit (I2C) Instance no. 1. L2 cache PL310 Mpcore - SCU, Interrupt controller, Counters and Timers On-Chip Memory Registers LQSPI module Registers SD2.0/ SDIO2.0/ MMC3.31 AHB Host ControllerRegisters Instance no. 0. SD2.0/ SDIO2.0/ MMC3.31 AHB Host ControllerRegisters Instance no. 1. System Level Control Registers

sd1

sdio

0xE0101000

slcr

slcr

0xF8000000

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Appendix B: Register Details

Module Name smcc spi0 spi1 swdt ttc0 ttc1 uart0 uart1 usb0 usb1

Module Type pl353 SPI SPI swdt ttc ttc UART UART usb usb

Base Address 0xE000E000 0xE0006000 0xE0007000 0xF8005000 0xF8001000 0xF8002000 0xE0000000 0xE0001000 0xE0002000 0xE0003000

Description Shared memory controller Serial Peripheral Interface Instance no. 0. Serial Peripheral Interface Instance no. 1. System Watchdog Timer Registers Triple Timer Counter Instance no. 0. Triple Timer Counter Instance no. 1. Universal Asynchronous Receiver Transmitter Instance no. 0. Universal Asynchronous Receiver Transmitter Instance no. 1. USB controller registers Instance no. 0. USB controller registers Instance no. 1.

50 modules, 2038 registers.

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Appendix B: Register Details

B.4 AXI_HP Interface (AFI) (axi_hp)

Module Name Base Address AXI_HP Interface (AFI) (axi_hp) 0xF8008000 axi_hp0 0xF8009000 axi_hp1 0xF800A000 axi_hp2 0xF800B000 axi_hp3 Description Vendor Info AXI_HP Interface (AFI) Xilinx S_AXI_HP

Register Summary
Register Name AFI_RDCHAN_CTRL AFI_RDCHAN_ISSUI NGCAP AFI_RDQOS AFI_RDDATAFIFO_LE VEL AFI_RDDEBUG AFI_WRCHAN_CTRL AFI_WRCHAN_ISSUI NGCAP AFI_WRQOS AFI_WRDATAFIFO_L EVEL AFI_WRDEBUG Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 Width 32 32 32 32 32 32 32 32 32 32 Type mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed Reset Value 0x00000000 0x00000007 0x00000000 0x00000000 0x00000000 0x00000F00 0x00000007 0x00000000 0x00000000 0x00000000 Description Read Channel Control Register Read Issuing Capability Register QOS Read Channel Register Read Data FIFO Level Register Read Channel Debug Register Write Channel Control Register Write Issuing Capability Register QOS Write Channel Register Write Data FIFO Level Register Write Channel Debug Register

Register (axi_hp) AFI_RDCHAN_CTRL

Name Relative Address Absolute Address AFI_RDCHAN_CTRL 0x00000000 axi_hp0: 0xF8008000 axi_hp1: 0xF8009000 axi_hp2: 0xF800A000 axi_hp3: 0xF800B000 Width Access Type 32 bits mixed

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Appendix B: Register Details

Reset Value Description

0x00000000 Read Channel Control Register

Register AFI_RDCHAN_CTRL Details

Control fields for Read Channel operation
Field Name reserved QosHeadOfCmdQEn Bits 31:4 3 Type raz rw Reset Value 0x0 0x0 Description Return 0 when read When set, allows the priority of a transaction at the head of the RdCmdQ to be promoted if higher priority transactions are backed up behind it. The entire RdCmdQ will therefore be promoted when the fabric RdQos signal is promoted. When disabled, only the new read commands issued will receive the promotion. FabricOutCmdEn 2 rw 0x0 Enable control of outstanding read commands from the fabric 0: The maximum number of outstanding read commands is always taken from APB register field, rdIssueCap0 1: The maximum outstanding number of read commands is selected from the fabric input, axds_rdissuecap1_en, as follows: Max Outstanding Read Commands = axds_rdissuecap1_en ? rdIssueCap1 : rdIssueCap0 FabricQosEn 1 rw 0x0 Enable control of qos from the fabric 0: The qos bits are derived from APB register, AFI_RDQOS.staticQos 1: The qos bits are dynamically driven from the fabric input, axds_arqos[3:0] 32BitEn 0 rw 0x0 Configures the Read Channel as a 32-bit interface. 1: 32-bit enabled 0: 64-bit enabled

Register (axi_hp) AFI_RDCHAN_ISSUINGCAP

Name Relative Address Absolute Address AFI_RDCHAN_ISSUINGCAP 0x00000004 axi_hp0: 0xF8008004 axi_hp1: 0xF8009004 axi_hp2: 0xF800A004 axi_hp3: 0xF800B004 Width 32 bits

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Appendix B: Register Details

Access Type Reset Value Description

mixed 0x00000007 Read Issuing Capability Register

Register AFI_RDCHAN_ISSUINGCAP Details

Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AXI_HP to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.
Field Name reserved rdIssueCap1 Bits 31:7 6:4 Type raz rw Reset Value 0x0 0x0 Description Return 0 when read Max number of outstanding read commands (Read Issuing Capability) field 1: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands reserved rdIssueCap0 3 2:0 raz rw 0x0 0x7 Return 0 when read Max number of outstanding read commands (Read Issuing Capability) field 0: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands

Register (axi_hp) AFI_RDQOS

Name Relative Address Absolute Address AFI_RDQOS 0x00000008 axi_hp0: 0xF8008008 axi_hp1: 0xF8009008 axi_hp2: 0xF800A008 axi_hp3: 0xF800B008 Width Access Type Reset Value Description 32 bits mixed 0x00000000 QOS Read Channel Register

Register AFI_RDQOS Details

Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.

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Appendix B: Register Details

Field Name reserved staticQos

Bits 31:4 3:0

Type raz rw

Reset Value 0x0 0x0

Description Return 0 when read Sets the level of the Qos field to be used for the read channel 4'b0000: Lowest Priority' ' '4'b1111: Highest Priority

Register (axi_hp) AFI_RDDATAFIFO_LEVEL

Name Relative Address Absolute Address AFI_RDDATAFIFO_LEVEL 0x0000000C axi_hp0: 0xF800800C axi_hp1: 0xF800900C axi_hp2: 0xF800A00C axi_hp3: 0xF800B00C Width Access Type Reset Value Description 32 bits mixed 0x00000000 Read Data FIFO Level Register

Register AFI_RDDATAFIFO_LEVEL Details

Returns the Level of the Read Data FIFO in Qwords. Note that this register should only be read if a valid HP port clock is actively running. If no clock is running the APB access will hang.
Field Name reserved FifoLevel Bits 31:8 7:0 Type raz ro Reset Value 0x0 0x0 Description Return 0 when read Returns the level measured in Dwords (64-bits) of the Read Data FIFO 8'h00: 0 Entries 8'h01: 1 Entry' ' '8'h8F: 128 Entries

Register (axi_hp) AFI_RDDEBUG

Name Relative Address Absolute Address AFI_RDDEBUG 0x00000010 axi_hp0: 0xF8008010 axi_hp1: 0xF8009010 axi_hp2: 0xF800A010 axi_hp3: 0xF800B010 Width 32 bits

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Appendix B: Register Details

Access Type Reset Value Description

mixed 0x00000000 Read Channel Debug Register

Register AFI_RDDEBUG Details

Miscellaneous debug fields for the Read channel. Not to be used for functional purposes.
Field Name reserved OutRdCmds Bits 31:5 4:1 Type raz ro Reset Value 0x0 0x0 Description Return 0 when read Returns the number of read commands in flight between the AXI_HP and the SAM switch 4'h0: 0 4'h1: 1 etc RdDataFifoOverflow 0 ro 0x0 Bit is set if the RdDataFIFO overflows

Register (axi_hp) AFI_WRCHAN_CTRL

Name Relative Address Absolute Address AFI_WRCHAN_CTRL 0x00000014 axi_hp0: 0xF8008014 axi_hp1: 0xF8009014 axi_hp2: 0xF800A014 axi_hp3: 0xF800B014 Width Access Type Reset Value Description 32 bits mixed 0x00000F00 Write Channel Control Register

Register AFI_WRCHAN_CTRL Details

Control fields for Write Channel operation

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Appendix B: Register Details

Field Name reserved WrDataThreshold

Bits 31:12 11:8

Type raz rw

Reset Value 0x0 0xF

Description Return 0 when read Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field. 4'b0000: Send Write Command When 1 data beat is pushed into the Write Data FIFO 4'b0001: Send Write Command When 2 data beats are pushed into the Write Data FIFO' ' '4'b1111: Send Write Command When 16 data beats are pushed into the Write Data FIFO Note: If this field is programmed to be less than the actual burst length of the write command, the 'Wlast' will take priority. For example, if 'WrDataThreshold' is set to 4'b1111 (indicates 16 beats), and a Wlast is received after 8 beats, the write command is sent.

reserved WrCmdReleaseMode

7:6 5:4

raz rw

0x0 0x0

Return 0 when read Mode of Write Command Release. 2'b00: Release Wr Command on 'Wlast' enqueue into Write Data FIFO 2'b01: Release Wr Command on a particular threshold being reached on the enqueue into Write Data FIFO. The 'WrDataThreshold' field is used to program the actual threshold. 2'b10: Reserved 2'b11: Reserved

QosHeadOfCmdQEn

rw

0x0

When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher priority transactions are backed up behind it. The entire WrCmdQ will therefore be 'promoted' when the fabric 'WrQos' signal is promoted. When disabled, only the new write commands issued will receive the 'promotion'.

FabricOutCmdEn

rw

0x0

Enable control of outstanding write commands from the fabric 0: The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1: The maximum outstanding number of write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows: Max Outstanding Write Commands = axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0

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Appendix B: Register Details

Field Name FabricQosEn

Bits 1

Type rw

Reset Value 0x0

Description Enable control of qos from the fabric 0: The qos bits are derived from APB register, 'AFI_WRQOS.staticQos'1: The qos bits are dynamically driven from the fabric input, 'axds_awqos[3:0]'

32BitEn

rw

0x0

Configures the Write Channel as a 32-bit interface. 1: 32-bit enabled 0: 64-bit enabled

Register (axi_hp) AFI_WRCHAN_ISSUINGCAP

Name Relative Address Absolute Address AFI_WRCHAN_ISSUINGCAP 0x00000018 axi_hp0: 0xF8008018 axi_hp1: 0xF8009018 axi_hp2: 0xF800A018 axi_hp3: 0xF800B018 Width Access Type Reset Value Description 32 bits mixed 0x00000007 Write Issuing Capability Register

Register AFI_WRCHAN_ISSUINGCAP Details

Sets the maximum number of Outstanding Write Commands (Issuing Capability) allowed. Refers to the commands that can be outstanding from the AXI_HP to the SAM switch and back. Fields are selected by the 'axds_wrissuecap1_en' input.
Field Name reserved wrIssueCap1 Bits 31:7 6:4 Type raz rw Reset Value 0x0 0x0 Description Return 0 when read Max number of outstanding write commands (Write Issuing Capability) field 1: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands reserved wrIssueCap0 3 2:0 raz rw 0x0 0x7 Return 0 when read Max number of outstanding write commands (Write Issuing Capability) field 0: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands

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Appendix B: Register Details

Register (axi_hp) AFI_WRQOS

Name Relative Address Absolute Address AFI_WRQOS 0x0000001C axi_hp0: 0xF800801C axi_hp1: 0xF800901C axi_hp2: 0xF800A01C axi_hp3: 0xF800B01C Width Access Type Reset Value Description 32 bits mixed 0x00000000 QOS Write Channel Register

Register AFI_WRQOS Details

Sets the static Qos value to be used for the write channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all write commands enqueued into the WrCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored.
Field Name reserved staticQos Bits 31:4 3:0 Type raz rw Reset Value 0x0 0x0 Description Return 0 when read Sets the level of the Qos field to be used for the write channel 4'b0000: Lowest Priority' ' '4'b1111: Highest Priority

Register (axi_hp) AFI_WRDATAFIFO_LEVEL

Name Relative Address Absolute Address AFI_WRDATAFIFO_LEVEL 0x00000020 axi_hp0: 0xF8008020 axi_hp1: 0xF8009020 axi_hp2: 0xF800A020 axi_hp3: 0xF800B020 Width Access Type Reset Value Description 32 bits mixed 0x00000000 Write Data FIFO Level Register

Register AFI_WRDATAFIFO_LEVEL Details

Returns the Level of the Write Data FIFO in Dwords. Note that this register should only be read if a valid HP port clock is actively running. If no clock is present, the APB access will hang.

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Appendix B: Register Details

Field Name reserved FifoLevel

Bits 31:8 7:0

Type raz ro

Reset Value 0x0 0x0

Description Return 0 when read Returns the level measured in Dwords (64-bits) of the Write Data FIFO 8'h00: 0 Entries 8'h01: 1 Entry' ' '8'h8F: 128 Entries

Register (axi_hp) AFI_WRDEBUG

Name Relative Address Absolute Address AFI_WRDEBUG 0x00000024 axi_hp0: 0xF8008024 axi_hp1: 0xF8009024 axi_hp2: 0xF800A024 axi_hp3: 0xF800B024 Width Access Type Reset Value Description 32 bits mixed 0x00000000 Write Channel Debug Register

Register AFI_WRDEBUG Details

Field Name reserved OutWrCmds Bits 31:5 4:1 Type raz ro Reset Value 0x0 0x0 Description Return 0 when read Returns the number of write commands in flight between the AXI_HP and the SAM switch 4'h0: 0 4'h1: 1 etc WrDataFifoOverflow 0 ro 0x0 Bit is set if the WrDataFIFO overflows

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Appendix B: Register Details

B.5 CAN Controller (can)

Module Name Software Name Base Address Description Vendor Info CAN Controller (can) XCANPS 0xE0008000 can0 0xE0009000 can1 Controller Area Network Xilinx CAN

Register Summary
Register Name SRR MSR BRPR BTR ECR ESR SR ISR IER ICR TCR WIR TXFIFO_ID TXFIFO_DLC TXFIFO_DATA1 TXFIFO_DATA2 TXHPB_ID TXHPB_DLC Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000040 0x00000044 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type rw rw rw rw ro mixed mixed mixed rw mixed mixed rw wo rw rw rw wo rw Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00006000 0x00000000 0x00000000 0x00000000 0x00003F3F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description Software Reset Register Mode Select Register Baud Rate Prescaler Register Bit Timing Register Error Counter Register Error Status Register Status Register Interrupt Status Register Interrupt Enable Register Interrupt Clear Register Timestamp Control Register Watermark Interrupt Register transmit message fifo message identifier transmit message fifo data length code transmit message fifo data word 1 transmit message fifo data word 2 transmit high priority buffer message identifier transmit high priority buffer data length code

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Appendix B: Register Details

Register Name TXHPB_DATA1 TXHPB_DATA2 RXFIFO_ID RXFIFO_DLC RXFIFO_DATA1 RXFIFO_DATA2 AFR AFMR1 AFIR1 AFMR2 AFIR2 AFMR3 AFIR3 AFMR4 AFIR4

Address 0x00000048 0x0000004C 0x00000050 0x00000054 0x00000058 0x0000005C 0x00000060 0x00000064 0x00000068 0x0000006C 0x00000070 0x00000074 0x00000078 0x0000007C 0x00000080

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw ro rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000000 0x00000000 x x x x 0x00000000 x x x x x x x x

Description transmit high priority buffer data word 1 transmit high priority buffer data word 2 receive message fifo message identifier receive message fifo data length code receive message fifo data word 1 receive message fifo data word 2 Acceptance Filter Register Acceptance Filter Mask Register 1 Acceptance Filter ID Register 1 Acceptance Filter Mask Register 2 Acceptance Filter ID Register 2 Acceptance Filter Mask Register 3 Acceptance Filter ID Register 3 Acceptance Filter Mask Register 4 Acceptance Filter ID Register 4

Register (can) SRR

Name Relative Address Absolute Address Width Access Type Reset Value Description SRR 0x00000000 can0: 0xE0008000 can1: 0xE0009000 32 bits rw 0x00000000 Software Reset Register

Register SRR Details

Writing to the Software Reset Register (SRR) places the CAN controller in Configuration mode. Once in Configuration mode, the CAN controller drives recessive on the bus line and does not transmit or receive messages. During power-up, CEN and SRST bits are '0' and CONFIG bit in the Status Register (SR) is '1.'

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Appendix B: Register Details

The Transfer Layer Configuration Registers can be changed only when CEN bit in the SRR Register is '0.' If the CEN bit is changed during core operation, it is recommended to reset the core so that operations start afresh.
Field Name reserved CEN Bits 31:2 1 Type rw rw Reset Value 0x0 0x0 Reserved. Can Enable The Enable bit for the CAN controller. 1: The CAN controller is in Loop Back, Sleep or Normal mode depending on the LBACK and SLEEP bits in the MSR. 0: The CAN controller is in the Configuration mode. If the CEN bit is changed during core operation, it is recommended to reset the core so that operations start afresh. SRST 0 rw 0x0 Reset The Software reset bit for the CAN controller. 1: CAN controller is reset. If a 1 is written to this bit, all the CAN controller configuration registers (including the SRR) are reset. Reads to this bit always return a 0. Description

Register (can) MSR

Name Relative Address Absolute Address Width Access Type Reset Value Description MSR 0x00000004 can0: 0xE0008004 can1: 0xE0009004 32 bits rw 0x00000000 Mode Select Register

Register MSR Details

Writing to the Mode Select Register (MSR) enables the CAN controller to enter Snoop, Sleep, Loop Back, or Normal modes. In Normal mode, the CAN controller participates in normal bus communication. If the SLEEP bit is set to '1,' the CAN controller enters Sleep mode. If the LBACK bit is set to '1,' the CAN controller enters Loop Back mode. If the SNOOP mode is set to '1', the CAN controller enters Snoop mode and does not participate in bus communication but only receives messages. The LBACK and SLEEP bits should never be set to '1' at the same time. At any given point the CAN controller can be either in Loop Back mode or Sleep mode, but not both simultaneously. If both bits are set, then LBACK Mode takes priority. SNOOP Mode has least priority. In order for core to enter SNOOP mode LBACK and SLEEP modes should be set to '0'.

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Appendix B: Register Details

Field Name reserved SNOOP

Bits 31:3 2

Type rw rw

Reset Value 0x0 0x0 Reserved.

Description

Snoop Mode Select The Snoop Mode Select bit. 1: CAN controller is in Snoop mode. 0: CAN controller is in Normal, Loop Back, Configuration, or Sleep mode. This bit can be written to only when CEN bit in SRR is 0.

LBACK

rw

0x0

Loop Back Mode Select The Loop Back Mode Select bit. 1: CAN controller is in Loop Back mode. 0: CAN controller is in Normal, Snoop, Configuration, or Sleep mode. This bit can be written to only when CEN bit in SRR is 0.

SLEEP

rw

0x0

Sleep Mode Select The Sleep Mode select bit. 1: CAN controller is in Sleep mode. 0: CAN controller is in Normal, Snoop, Configuration or Loop Back mode. This bit is cleared when the CAN controller wakes up from the Sleep mode.

Register (can) BRPR

Name Relative Address Absolute Address Width Access Type Reset Value Description BRPR 0x00000008 can0: 0xE0008008 can1: 0xE0009008 32 bits rw 0x00000000 Baud Rate Prescaler Register

Register BRPR Details

The BRPR can be programmed to any value in the range 0-255. The actual value is 1 more than the value written into the register. Please refer to the CAN chapter for more details.

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Appendix B: Register Details

Field Name reserved BRP

Bits 31:8 7:0

Type rw rw

Reset Value 0x0 0x0 Reserved

Description

Baud Rate Prescaler These bits indicate the prescaler value. The actual value ranges from 1 to 256.

Register (can) BTR

Name Relative Address Absolute Address Width Access Type Reset Value Description BTR 0x0000000C can0: 0xE000800C can1: 0xE000900C 32 bits rw 0x00000000 Bit Timing Register

Register BTR Details

The Bit Timing Register (BTR) specifies the bits needed to configure bit time. Specifically, the Propagation Segment, Phase segment 1, Phase segment 2, and Synchronization Jump Width (as defined in CAN 2.0A, CAN 2.0B and ISO 11891-1) are written to the BTR. The actual value of each of these fields is one more than the value written to this register.
Field Name reserved SJW Bits 31:9 8:7 Type rw rw Reset Value 0x0 0x0 Reserved Synchronization Jump Width Indicates the Synchronization Jump Width as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register. TS2 6:4 rw 0x0 Time Segment 2 Indicates Phase Segment 2 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register. TS1 3:0 rw 0x0 Time Segment 1 Indicates the Sum of Propagation Segment and Phase Segment 1 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register. Description

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Register (can) ECR

Name Relative Address Absolute Address Width Access Type Reset Value Description ECR 0x00000010 can0: 0xE0008010 can1: 0xE0009010 32 bits ro 0x00000000 Error Counter Register

Register ECR Details

The ECR is a read-only register. Writes to the ECR have no effect. The value of the error counters in the register reflect the values of the transmit and receive error counters in the CAN Protocol Engine Module (see Figure 1). The following conditions reset the Transmit and Receive Error counters: * When '1' is written to the SRST bit in the SRR * When '0' is written to the CEN bit in the SRR * When the CAN controller enters Bus Off state * During Bus Off recovery when the CAN controller enters Error Active state after 128 occurrences of 11 consecutive recessive bits When in Bus Off recovery, the Receive Error counter is advanced by 1 when a sequence of 11 consecutive recessive bits is seen.
Field Name reserved REC TEC Bits 31:16 15:8 7:0 Type ro ro ro Reset Value 0x0 0x0 0x0 Reserved Receive Error Counter Indicates the Value of the Receive Error Counter. Transmit Error Counter Indicates the Value of the Transmit Error Counter. Description

Register (can) ESR

Name Relative Address Absolute Address Width Access Type ESR 0x00000014 can0: 0xE0008014 can1: 0xE0009014 32 bits mixed

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Reset Value Description

0x00000000 Error Status Register

Register ESR Details

The Error Status Register (ESR) indicates the type of error that has occurred on the bus. If more than one error occurs, all relevant error flag bits are set in this register. The ESR is a write-to-clear register. Writes to this register will not set any bits, but will clear the bits that are set.
Field Name reserved ACKER Bits 31:5 4 Type rw wtc Reset Value 0x0 0x0 Reserved ACK Error Indicates an acknowledgment error. 1: Indicates an acknowledgment error has occurred. 0: Indicates an acknowledgment error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. BERR 3 wtc 0x0 Bit Error Indicates the received bit is not the same as the transmitted bit during bus communication. 1: Indicates a bit error has occurred. 0: Indicates a bit error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. STER 2 wtc 0x0 Stuff Error Indicates an error if there is a stuffing violation. 1: Indicates a stuff error has occurred. 0: Indicates a stuff error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. Description

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Appendix B: Register Details

Field Name FMER

Bits 1

Type wtc

Reset Value 0x0 Form Error

Description

Indicates an error in one of the fixed form fields in the message frame. 1: Indicates a form error has occurred. 0: Indicates a form error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. CRCER 0 wtc 0x0 CRC Error Indicates a CRC error has occurred. 1: Indicates a CRC error has occurred. 0: Indicates a CRC error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.

Register (can) SR
Name Relative Address Absolute Address Width Access Type Reset Value Description SR 0x00000018 can0: 0xE0008018 can1: 0xE0009018 32 bits mixed 0x00000001 Status Register

Register SR Details
The CAN Status Register provides a status of all conditions of the Core. Specifically, FIFO status, Error State, Bus State and Configuration mode are reported.
Field Name reserved SNOOP Bits 31:13 12 Type rw ro Reset Value 0x0 0x0 Reserved Snoop Mode Indicates the CAN controller is in Snoop Mode. 1: Indicates the CAN controller is in Snoop Mode. 0: Indicates the CAN controller is not in Snoop mode. Description

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Appendix B: Register Details

Field Name ACFBSY

Bits 11

Type ro

Reset Value 0x0

Description Acceptance Filter Busy indicator. Indicates write-ablity of the Mask and ID registers, read-only: 0: writable 1: not writable. This bit reads 1 when a 0 is written to any of the valid UAF bits in an Acceptance Filter Register.

TXFLL

10

ro

0x0

Transmit FIFO Full Indicates that the TX FIFO is full. 1: Indicates the TX FIFO is full. 0: Indicates the TX FIFO is not full.

TXBFLL

ro

0x0

High Priority Transmit Buffer Full Indicates the High Priority Transmit Buffer is full. 1: Indicates the High Priority Transmit Buffer is full. 0: Indicates the High Priority Transmit Buffer is not full.

ESTAT

8:7

ro

0x0

Error Status Indicates the error status of the CAN controller. 00: Indicates Configuration Mode (CONFIG = 1). Error State is undefined. 01: Indicates Error Active State. 11: Indicates Error Passive State. 10: Indicates Bus Off State.

ERRWRN

ro

0x0

Error Warning Indicates that either the Transmit Error counter or the Receive Error counter has exceeded a value of 96. 1: One or more error counters have a value greater than or equal to 96. 0: Neither of the error counters has a value greater than or equal to 96.

BBSY

ro

0x0

Bus Busy Indicates the CAN bus status. 1: Indicates that the CAN controller is either receiving a message or transmitting a message. 0: Indicates that the CAN controller is either in Configuration mode or the bus is idle.

BIDLE

ro

0x0

Bus Idle Indicates the CAN bus status. 1: Indicates no bus communication is taking place. 0: Indicates the CAN controller is either in Configuration mode or the bus is busy.

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Appendix B: Register Details

Field Name NORMAL

Bits 3

Type ro

Reset Value 0x0 Normal Mode

Description

Indicates the CAN controller is in Normal Mode. 1: Indicates the CAN controller is in Normal Mode. 0: Indicates the CAN controller is not in Normal mode. SLEEP 2 ro 0x0 Sleep Mode Indicates the CAN controller is in Sleep mode. 1: Indicates the CAN controller is in Sleep mode. 0: Indicates the CAN controller is not in Sleep mode. LBACK 1 ro 0x0 Loop Back Mode Indicates the CAN controller is in Loop Back mode. 1: Indicates the CAN controller is in Loop Back mode. 0: Indicates the CAN controller is not in Loop Back mode. CONFIG 0 ro 0x1 Configuration Mode Indicator Indicates the CAN controller is in Configuration mode. 1: Indicates the CAN controller is in Configuration mode. 0: Indicates the CAN controller is not in Configuration mode.

Register (can) ISR

Name Relative Address Absolute Address Width Access Type Reset Value Description ISR 0x0000001C can0: 0xE000801C can1: 0xE000901C 32 bits mixed 0x00006000 Interrupt Status Register

Register ISR Details

The Interrupt Status Register (ISR) contains bits that are set when a particular interrupt condition occurs. If the corresponding mask bit in the Interrupt Enable Register is set, an interrupt is generated. Interrupt bits in the ISR can be cleared by writing to the Interrupt Clear Register. For all bits in the ISR, a set condition takes priority over the clear condition and the bit continues to remain '1.'

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Appendix B: Register Details

Field Name reserved TXFEMP (IXR_TXFEMP)

Bits 31:15 14

Type rw ro

Reset Value 0x0 0x1 reserved

Description

Transmit FIFO EmptyInterrupt A 1 indicates that the Transmit FIFO is empty. The interrupt continues to assert as long as the TX FIFO is empty. This bit can be cleared only by writing to the ICR.

TXFWMEMP (IXR_TXFWMEMP)

13

ro

0x1

Transmit FIFO Watermark Empty Interrupt A 1 indicates that the TX FIFO is empty based on watermark programming. The interrupt continues to assert as long as the number of empty spaces in the TX FIFO is greater than TX FIFO empty watermark. This bit can be cleared only by writing to the Interrupt Clear Register.

RXFWMFLL (IXR_RXFWMFLL)

12

ro

0x0

Receive FIFO Watermark Full Interrupt A 1 indicates that the RX FIFO is full based on watermark programming. The interrupt continues to assert as long as the RX FIFO count is above RX FIFO Full watermark. This bit can be cleared only by writing to the Interrupt Clear Register.

WKUP (IXR_WKUP)

11

ro

0x0

Wake up Interrupt A 1 indicates that the CAN controller entered Normal mode from Sleep Mode. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

SLP (IXR_SLP)

10

ro

0x0

Sleep Interrupt A 1 indicates that the CAN controller entered Sleep mode. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

BSOFF (IXR_BSOFF)

ro

0x0

Bus Off Interrupt A 1 indicates that the CAN controller entered the Bus Off state. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

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Field Name ERROR (IXR_ERROR)

Bits 8

Type ro

Reset Value 0x0 Error Interrupt

Description

A 1 indicates that an error occurred during message transmission or reception. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

RXNEMP (IXR_RXNEMP) RXOFLW (IXR_RXOFLW)

ro

0x0

Receive FIFO Not Empty Interrupt A 1 indicates that the Receive FIFO is not empty. This bit can be cleared only by writing to the ICR.

ro

0x0

RX FIFO Overflow Interrupt A 1 indicates that a message has been lost. This condition occurs when a new message is being received and the Receive FIFO is Full. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

RXUFLW (IXR_RXUFLW)

ro

0x0

RX FIFO Underflow Interrupt A 1 indicates that a read operation was attempted on an empty RX FIFO. This bit can be cleared only by writing to the ICR.

RXOK (IXR_RXOK)

ro

0x0

New Message Received Interrupt A 1 indicates that a message was received successfully and stored into the RX FIFO. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

TXBFLL (IXR_TXBFLL)

ro

0x0

High Priority Transmit Buffer Full Interrupt A 1 indicates that the High Priority Transmit Buffer is full. The status of the bit is unaffected if write transactions occur on the High Priority Transmit Buffer when it is already full. This bit can be cleared only by writing to the ICR.

TXFLL (IXR_TXFLL)

ro

0x0

Transmit FIFO Full Interrupt A 1 indicates that the TX FIFO is full. The status of the bit is unaffected if write transactions occur on the Transmit FIFO when it is already full. This bit can be cleared only by writing to the Interrupt Clear Register.

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Field Name TXOK (IXR_TXOK)

Bits 1

Type ro

Reset Value 0x0

Description Transmission Successful Interrupt A 1 indicates that a message was transmitted successfully. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. In Loop Back mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.

ARBLST (IXR_ARBLST)

ro

0x0

Arbitration Lost Interrupt A 1 indicates that arbitration was lost during message transmission. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR.

Register (can) IER

Name Relative Address Absolute Address Width Access Type Reset Value Description IER 0x00000020 can0: 0xE0008020 can1: 0xE0009020 32 bits rw 0x00000000 Interrupt Enable Register

Register IER Details

Field Name reserved ETXFEMP (IXR_TXFEMP) Bits 31:15 14 Type rw rw Reset Value 0x0 0x0 Reserved Enable TXFIFO Empty Interrupt Writes to this bit enable or disable interrupts when the TXFEMP bit in the ISR is set. 1: Enable interrupt generation if TXFEMP bit in ISR is set. 0: Disable interrupt generation if TXFEMP bit in ISR is set. Description

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Appendix B: Register Details

Field Name ETXFWMEMP (IXR_TXFWMEMP)

Bits 13

Type rw

Reset Value 0x0

Description Enable TXFIFO watermark Empty Interrupt Writes to this bit enable or disable interrupts when the TXFWMEMP bit in the ISR is set. 1: Enable interrupt generation if TXFWMEMP bit in ISR is set. 0: Disable interrupt generation if TXFWMEMP bit in ISR is set.

ERXFWMFLL (IXR_RXFWMFLL)

12

rw

0x0

Enable RXFIFO watermark Full Interrupt Writes to this bit enable or disable interrupts when the RXFLL bit in the ISR is set. 1: Enable interrupt generation if RXFWMFLL bit in ISR is set. 0: Disable interrupt generation if RXFWMFLL bit in ISR is set.

EWKUP (IXR_WKUP)

11

rw

0x0

Enable Wake up Interrupt Writes to this bit enable or disable interrupts when the WKUP bit in the ISR is set. 1: Enable interrupt generation if WKUP bit in ISR is set. 0: Disable interrupt generation if WKUP bit in ISR is set.

ESLP (IXR_SLP)

10

rw

0x0

Enable Sleep Interrupt Writes to this bit enable or disable interrupts when the SLP bit in the ISR is set. 1: Enable interrupt generation if SLP bit in ISR is set. 0: Disable interrupt generation if SLP bit in ISR is set.

EBSOFF (IXR_BSOFF)

rw

0x0

Enable Bus OFF Interrupt Writes to this bit enable or disable interrupts when the BSOFF bit in the ISR is set. 1: Enable interrupt generation if BSOFF bit in ISR is set. 0: Disable interrupt generation if BSOFF bit in ISR is set.

EERROR (IXR_ERROR)

rw

0x0

Enable Error Interrupt Writes to this bit enable or disable interrupts when the ERROR bit in the ISR is set. 1: Enable interrupt generation if ERROR bit in ISR is set. 0: Disable interrupt generation if ERROR bit in ISR is set.

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Appendix B: Register Details

Field Name ERXNEMP (IXR_RXNEMP)

Bits 7

Type rw

Reset Value 0x0

Description Enable Receive FIFO Not Empty Interrupt Writes to this bit enable or disable interrupts when the RXNEMP bit in the ISR is set. 1: Enable interrupt generation if RXNEMP bit in ISR is set. 0: Disable interrupt generation if RXNEMP bit in ISR is set.

ERXOFLW (IXR_RXOFLW)

rw

0x0

Enable RX FIFO Overflow Interrupt Writes to this bit enable or disable interrupts when the RXOFLW bit in the ISR is set. 1: Enable interrupt generation if RXOFLW bit in ISR is set. 0: Disable interrupt generation if RXOFLW bit in ISR is set.

ERXUFLW (IXR_RXUFLW)

rw

0x0

Enable RX FIFO Underflow Interrupt Writes to this bit enable or disable interrupts when the RXUFLW bit in the ISR is set. 1: Enable interrupt generation if RXUFLW bit in ISR is set. 0: Disable interrupt generation if RXUFLW bit in ISR is set.

ERXOK (IXR_RXOK)

rw

0x0

Enable New Message Received Interrupt Writes to this bit enable or disable interrupts when the RXOK bit in the ISR is set. 1: Enable interrupt generation if RXOK bit in ISR is set. 0: Disable interrupt generation if RXOK bit in ISR is set.

ETXBFLL (IXR_TXBFLL)

rw

0x0

Enable High Priority Transmit Buffer Full Interrupt Writes to this bit enable or disable interrupts when the TXBFLL bit in the ISR is set. 1: Enable interrupt generation if TXBFLL bit in ISR is set. 0: Disable interrupt generation if TXBFLL bit in ISR is set.

ETXFLL (IXR_TXFLL)

rw

0x0

Enable Transmit FIFO Full Interrupt Writes to this bit enable or disable interrupts when TXFLL bit in the ISR is set. 1: Enable interrupt generation if TXFLL bit in ISR is set. 0: Disable interrupt generation if TXFLL bit in ISR is set.

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Appendix B: Register Details

Field Name ETXOK (IXR_TXOK)

Bits 1

Type rw

Reset Value 0x0

Description Enable Transmission Successful Interrupt Writes to this bit enable or disable interrupts when the TXOK bit in the ISR is set. 1: Enable interrupt generation if TXOK bit in ISR is set. 0: Disable interrupt generation if TXOK bit in ISR is set.

EARBLST (IXR_ARBLST)

rw

0x0

Enable Arbitration Lost Interrupt Writes to this bit enable or disable interrupts when the ARBLST bit in the ISR is set. 1: Enable interrupt generation if ARBLST bit in ISR is set. 0: Disable interrupt generation if ARBLST bit in ISR is set.

Register (can) ICR

Name Relative Address Absolute Address Width Access Type Reset Value Description ICR 0x00000024 can0: 0xE0008024 can1: 0xE0009024 32 bits mixed 0x00000000 Interrupt Clear Register

Register ICR Details

Field Name reserved CTXFEMP (IXR_TXFEMP) CTXFWMEMP (IXR_TXFWMEMP) CRXFWMFLL (IXR_RXFWMFLL) 12 wo 0x0 13 wo 0x0 Bits 31:15 14 Type rw wo Reset Value 0x0 0x0 Reserved Clear TXFIFO Empty Interrupt Writing a 1 to this bit clears the TXFEMP bit in the ISR. Clear TXFIFO Watermark Empty Interrupt Writing a 1 to this bit clears the TXFWMEMP bit in the ISR. Clear RXFIFO Watermark Full Interrupt Writing a 1 to this bit clears the RXFWMFLL bit in the ISR. Description

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Field Name CWKUP (IXR_WKUP) CSLP (IXR_SLP) CBSOFF (IXR_BSOFF) CERROR (IXR_ERROR) CRXNEMP (IXR_RXNEMP) CRXOFLW (IXR_RXOFLW) CRXUFLW (IXR_RXUFLW) CRXOK (IXR_RXOK) CTXBFLL (IXR_TXBFLL) CTXFLL (IXR_TXFLL) CTXOK (IXR_TXOK) CARBLST (IXR_ARBLST)

Bits 11

Type wo

Reset Value 0x0

Description Clear Wake up Interrupt Writing a 1 to this bit clears the WKUP bit in the ISR.

10 9

wo wo

0x0 0x0

Clear Sleep Interrupt Writing a 1 to this bit clears the SLP bit in the ISR. Clear Bus Off Interrupt Writing a 1 to this bit clears the BSOFF bit in the ISR.

wo

0x0

Clear Error Interrupt Writing a 1 to this bit clears the ERROR bit in the ISR.

wo

0x0

Clear Receive FIFO Not Empty Interrupt Writing a 1 to this bit clears the RXNEMP bit in the ISR.

wo

0x0

Clear RX FIFO Overflow Interrupt Writing a 1 to this bit clears the RXOFLW bit in the ISR.

wo

0x0

Clear RX FIFO Underflow Interrupt Writing a 1 to this bit clears the RXUFLW bit in the ISR.

wo

0x0

Clear New Message Received Interrupt Writing a 1 to this bit clears the RXOK bit in the ISR.

wo

0x0

Clear High Priority Transmit Buffer Full Interrupt Writing a 1 to this bit clears the TXBFLL bit in the ISR.

wo

0x0

Clear Transmit FIFO Full Interrupt Writing a 1 to this bit clears the TXFLL bit in the ISR.

wo

0x0

Clear Transmission Successful Interrupt Writing a 1 to this bit clears the CTXOK bit in the ISR.

wo

0x0

Clear Arbitration Lost Interrupt Writing a 1 to this bit clears the ARBLST bit in the ISR.

Register (can) TCR

Name Relative Address TCR 0x00000028

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

can0: 0xE0008028 can1: 0xE0009028 32 bits mixed 0x00000000 Timestamp Control Register

Register TCR Details

Field Name reserved CTS Bits 31:1 0 Type rw wo Reset Value 0x0 0x0 reserved Clear Timestamp Internal free running counter is cleared to 0 when CTS=1. This bit only needs to be written once with a 1 to clear the counter. The bit will automatically return to 0. Description

Register (can) WIR

Name Relative Address Absolute Address Width Access Type Reset Value Description WIR 0x0000002C can0: 0xE000802C can1: 0xE000902C 32 bits rw 0x00003F3F Watermark Interrupt Register

Register WIR Details

The TXFIFO Empty watermark (EW) programmed in this register will be applied to TX FIFO only. The RXFIFO Full watermark (FW) programmed in this register will be applied to RX FIFO only. The watermark register is allowed to program only when CEN=0 in SRR register. The TXFIFO Watermark EMPTY interrupt (TXFWMEMP) will continue to assert as long as the number of empty spaces in the TX FIFO is greater than the TXFIFO Empty watermark (EW). The RXFLL interrupt will continue to assert as long as the RX FIFO count remains above the RXFIFO Full watermark (FW).

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Appendix B: Register Details

Field Name reserved EW

Bits 31:16 15:8

Type rw rw

Reset Value 0x0 0x3F reserved

Description

TXFIFO Empty watermark TXFIFO generates an EMPTY interrupt based on the value programmed in this field. The valid range is (1-63). No protection is given for illegal programming in this field. This field can be written to only when CEN bit in SRR is 0.

FW

7:0

rw

0x3F

RXFIFO Full watermark RXFIFO generates FULL interrupt based on the value programmed in this field. The valid range is (1-63). No protection is given for illegal programming in this field. This field can be written to only when CEN bit in SRR is 0.

Register (can) TXFIFO_ID

Name Relative Address Absolute Address Width Access Type Reset Value Description TXFIFO_ID 0x00000030 can0: 0xE0008030 can1: 0xE0009030 32 bits wo 0x00000000 transmit message fifo message identifier

Register TXFIFO_ID Details

Field Name IDH (IDR_ID1) Bits 31:21 Type wo Reset Value 0x0 Description Standard Message ID The Identifier portion for a Standard Frame is 11 bits. These bits indicate the Standard Frame ID. This field is valid for both Standard and Extended Frames. 20 wo 0x0 Substitute Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Standard Frames. For Extended frames this bit is 1. 1: Indicates that the message frame is a Remote Frame. 0: Indicates that the message frame is a Data Frame.

SRRRTR (IDR_SRR)

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Appendix B: Register Details

Field Name IDE (IDR_IDE)

Bits 19

Type wo

Reset Value 0x0

Description Identifier Extension This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1: Indicates the use of an Extended Message Identifier. 0: Indicates the use of a Standard Message Identifier.

IDL (IDR_ID2)

18:1

wo

0x0

Extended Message ID This field indicates the Extended Identifier. Valid only for Extended Frames. For Standard Frames, reads from this field return 0s. For Standard Frames, writes to this field should be 0s.

RTR (IDR_RTR)

wo

0x0

Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Extended Frames. 1: Indicates the message object is a Remote Frame 0: Indicates the message object is a Data Frame For Standard Frames, reads from this bit returns 0 For Standard Frames, writes to this bit should be 0

Register (can) TXFIFO_DLC

Name Relative Address Absolute Address Width Access Type Reset Value Description TXFIFO_DLC 0x00000034 can0: 0xE0008034 can1: 0xE0009034 32 bits rw 0x00000000 transmit message fifo data length code

Register TXFIFO_DLC Details

Field Name DLC (DLCR_DLC) Bits 31:28 Type rw Reset Value 0x0 Data Length Code This is the data length portion of the control field of the CAN frame. This indicates the number valid data bytes in Data Word 1 and Data Word 2 registers. 27:0 rw 0x0 reserved Description

reserved

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Appendix B: Register Details

Register (can) TXFIFO_DATA1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXFIFO_DATA1 TXFIFO_DW1 0x00000038 can0: 0xE0008038 can1: 0xE0009038 32 bits rw 0x00000000 transmit message fifo data word 1

Register TXFIFO_DATA1 Details

Field Name DB0 (DW1R_DB0) DB1 (DW1R_DB1) DB2 (DW1R_DB2) DB3 (DW1R_DB3) 7:0 rw 0x0 15:8 rw 0x0 23:16 rw 0x0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 0 Reads from this field return invalid data if the message has no data. Data Byte 1 Reads from this field return invalid data if the message has only 1 byte of data or fewer Data Byte 2 Reads from this field return invalid data if the message has only 2 byte of data or fewer Data Byte 3 Reads from this field return invalid data if the message has only 3 byte of data or fewer Description

Register (can) TXFIFO_DATA2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXFIFO_DATA2 TXFIFO_DW2 0x0000003C can0: 0xE000803C can1: 0xE000903C 32 bits rw 0x00000000 transmit message fifo data word 2

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Appendix B: Register Details

Register TXFIFO_DATA2 Details

Field Name DB0 (DW2R_DB4) DB1 (DW2R_DB5) DB2 (DW2R_DB6) DB3 (DW2R_DB7) 7:0 rw 0x0 15:8 rw 0x0 23:16 rw 0x0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 4 Reads from this field return invalid data if the message has only 4 byte of data or fewer Data Byte 5 Reads from this field return invalid data if the message has only 5 byte of data or fewer Data Byte 6 Reads from this field return invalid data if the message has only 6 byte of data or fewer Data Byte 7 Reads from this field return invalid data if the message has 7 byte of data or fewer Description

Register (can) TXHPB_ID

Name Relative Address Absolute Address Width Access Type Reset Value Description TXHPB_ID 0x00000040 can0: 0xE0008040 can1: 0xE0009040 32 bits wo 0x00000000 transmit high priority buffer message identifier

Register TXHPB_ID Details

Field Name IDH (IDR_ID1) Bits 31:21 Type wo Reset Value 0x0 Description Standard Message ID The Identifier portion for a Standard Frame is 11 bits. These bits indicate the Standard Frame ID. This field is valid for both Standard and Extended Frames. 20 wo 0x0 Substitute Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Standard Frames. For Extended frames this bit is 1. 1: Indicates that the message frame is a Remote Frame. 0: Indicates that the message frame is a Data Frame.

SRRRTR (IDR_SRR)

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Field Name IDE (IDR_IDE)

Bits 19

Type wo

Reset Value 0x0

Description Identifier Extension This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1: Indicates the use of an Extended Message Identifier. 0: Indicates the use of a Standard Message Identifier.

IDL (IDR_ID2)

18:1

wo

0x0

Extended Message ID This field indicates the Extended Identifier. Valid only for Extended Frames. For Standard Frames, reads from this field return 0s. For Standard Frames, writes to this field should be 0s.

RTR (IDR_RTR)

wo

0x0

Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Extended Frames. 1: Indicates the message object is a Remote Frame 0: Indicates the message object is a Data Frame For Standard Frames, reads from this bit returns 0 For Standard Frames, writes to this bit should be 0

Register (can) TXHPB_DLC

Name Relative Address Absolute Address Width Access Type Reset Value Description TXHPB_DLC 0x00000044 can0: 0xE0008044 can1: 0xE0009044 32 bits rw 0x00000000 transmit high priority buffer data length code

Register TXHPB_DLC Details

Field Name DLC (DLCR_DLC) Bits 31:28 Type rw Reset Value 0x0 Data Length Code This is the data length portion of the control field of the CAN frame. This indicates the number valid data bytes in Data Word 1 and Data Word 2 registers. 27:0 rw 0x0 reserved Description

reserved

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Register (can) TXHPB_DATA1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXHPB_DATA1 TXHPB_DW1 0x00000048 can0: 0xE0008048 can1: 0xE0009048 32 bits rw 0x00000000 transmit high priority buffer data word 1

Register TXHPB_DATA1 Details

Field Name DB0 (DW1R_DB0) DB1 (DW1R_DB1) DB2 (DW1R_DB2) DB3 (DW1R_DB3) 7:0 rw 0x0 15:8 rw 0x0 23:16 rw 0x0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 0 Reads from this field return invalid data if the message has no data. Data Byte 1 Reads from this field return invalid data if the message has only 1 byte of data or fewer Data Byte 2 Reads from this field return invalid data if the message has only 2 byte of data or fewer Data Byte 3 Reads from this field return invalid data if the message has only 3 byte of data or fewer Description

Register (can) TXHPB_DATA2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXHPB_DATA2 TXHPB_DW2 0x0000004C can0: 0xE000804C can1: 0xE000904C 32 bits rw 0x00000000 transmit high priority buffer data word 2

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Register TXHPB_DATA2 Details

Field Name DB0 (DW2R_DB4) DB1 (DW2R_DB5) DB2 (DW2R_DB6) DB3 (DW2R_DB7) 7:0 rw 0x0 15:8 rw 0x0 23:16 rw 0x0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 4 Reads from this field return invalid data if the message has only 4 byte of data or fewer Data Byte 5 Reads from this field return invalid data if the message has only 5 byte of data or fewer Data Byte 6 Reads from this field return invalid data if the message has only 6 byte of data or fewer Data Byte 7 Reads from this field return invalid data if the message has 7 byte of data or fewer Description

Register (can) RXFIFO_ID

Name Relative Address Absolute Address Width Access Type Reset Value Description RXFIFO_ID 0x00000050 can0: 0xE0008050 can1: 0xE0009050 32 bits ro x receive message fifo message identifier

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Appendix B: Register Details

Register RXFIFO_ID Details

Field Name IDH (IDR_ID1) Bits 31:21 Type ro Reset Value x Description Standard Message ID The Identifier portion for a Standard Frame is 11 bits. These bits indicate the Standard Frame ID. This field is valid for both Standard and Extended Frames. SRRRTR (IDR_SRR) 20 ro x Substitute Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Standard Frames. For Extended frames this bit is 1. 1: Indicates that the message frame is a Remote Frame. 0: Indicates that the message frame is a Data Frame. IDE (IDR_IDE) 19 ro x Identifier Extension This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1: Indicates the use of an Extended Message Identifier. 0: Indicates the use of a Standard Message Identifier. IDL (IDR_ID2) 18:1 ro x Extended Message ID This field indicates the Extended Identifier. Valid only for Extended Frames. For Standard Frames, reads from this field return 0s For Standard Frames, writes to this field should be 0s RTR (IDR_RTR) 0 ro x Remote Transmission Request This bit differentiates between data frames and remote frames. Valid only for Extended Frames. 1: Indicates the message object is a Remote Frame 0: Indicates the message object is a Data Frame For Standard Frames, reads from this bit returns 0 For Standard Frames, writes to this bit should be 0

Register (can) RXFIFO_DLC

Name RXFIFO_DLC

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000054 can0: 0xE0008054 can1: 0xE0009054 32 bits rw x receive message fifo data length code

Register RXFIFO_DLC Details

Field Name DLC (DLCR_DLC) Bits 31:28 Type rw Reset Value x Data Length Code This is the data length portion of the control field of the CAN frame. This indicates the number valid data bytes in Data Word 1 and Data Word 2 registers. 27:16 15:0 rw rw x x reserved RX Timestamp Description

reserved RXT

Register (can) RXFIFO_DATA1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description RXFIFO_DATA1 RXFIFO_DW1 0x00000058 can0: 0xE0008058 can1: 0xE0009058 32 bits rw x receive message fifo data word 1

Register RXFIFO_DATA1 Details

Field Name DB0 (DW1R_DB0) DB1 (DW1R_DB1) 23:16 rw x Bits 31:24 Type rw Reset Value x Data Byte 0 Reads from this field return invalid data if the message has no data. Data Byte 1 Reads from this field return invalid data if the message has only 1 byte of data or fewer Description

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Field Name DB2 (DW1R_DB2) DB3 (DW1R_DB3)

Bits 15:8

Type rw

Reset Value x Data Byte 2

Description

Reads from this field return invalid data if the message has only 2 byte of data or fewer 7:0 rw x Data Byte 3 Reads from this field return invalid data if the message has only 3 byte of data or fewer

Register (can) RXFIFO_DATA2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description RXFIFO_DATA2 RXFIFO_DW2 0x0000005C can0: 0xE000805C can1: 0xE000905C 32 bits rw x receive message fifo data word 2

Register RXFIFO_DATA2 Details

Field Name DB0 (DW2R_DB4) DB1 (DW2R_DB5) DB2 (DW2R_DB6) DB3 (DW2R_DB7) 7:0 rw x 15:8 rw x 23:16 rw x Bits 31:24 Type rw Reset Value x Data Byte 4 Reads from this field return invalid data if the message has only 4 byte of data or fewer Data Byte 5 Reads from this field return invalid data if the message has only 5 byte of data or fewer Data Byte 6 Reads from this field return invalid data if the message has only 6 byte of data or fewer Data Byte 7 Reads from this field return invalid data if the message has 7 byte of data or fewer Description

Register (can) AFR

Name Relative Address AFR 0x00000060

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

can0: 0xE0008060 can1: 0xE0009060 32 bits rw 0x00000000 Acceptance Filter Register

Register AFR Details

The Acceptance Filter Register (AFR) defines which acceptance filters to use. Each Acceptance Filter ID Register (AFIR) and Acceptance Filter Mask Register (AFMR) pair is associated with a UAF bit. When the UAF bit is '1,' the corresponding acceptance filter pair is used for acceptance filtering. When the UAF bit is '0,' the corresponding acceptance filter pair is not used for acceptance filtering. To modify an acceptance filter pair in Normal mode, the corresponding UAF bit in this register must be set to '0.'After the acceptance filter is modified, the corresponding UAF bit must be set to '1.'The following conditions govern the number of UAF bits that can exist in the. * If all UAF bits are set to '0,' then all received messages are stored in the RX FIFO * If the UAF bits are changed from a '1' to '0' during reception of a CAN message, the message may not be stored in the RX FIFO.
Field Name reserved UAF4 Bits 31:4 3 Type rw rw Reset Value 0x0 0x0 reserved Use Acceptance Filter Number 4 Enables the use of acceptance filter pair 4. 1: Indicates Acceptance Filter Mask Register 4 and Acceptance Filter ID Register 4 are used for acceptance filtering. 0: Indicates Acceptance Filter Mask Register 4 and Acceptance Filter ID Register 4 are not used for acceptance filtering. UAF3 2 rw 0x0 Use Acceptance Filter Number 3 Enables the use of acceptance filter pair 3. 1: Indicates Acceptance Filter Mask Register 3 and Acceptance Filter ID Register 3 are used for acceptance filtering. 0: Indicates Acceptance Filter Mask Register 3 and Acceptance Filter ID Register 3 are not used for acceptance filtering. Description

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Appendix B: Register Details

Field Name UAF2

Bits 1

Type rw

Reset Value 0x0

Description Use Acceptance Filter Number 2 Enables the use of acceptance filter pair 2. 1: Indicates Acceptance Filter Mask Register 2 and Acceptance Filter ID Register 2 are used for acceptance filtering. 0: Indicates Acceptance Filter Mask Register 2 and Acceptance Filter ID Register 2 are not used for acceptance filtering.

UAF1

rw

0x0

Use Acceptance Filter Number 1. Enables the use of acceptance filter pair 1. 1: Indicates Acceptance Filter Mask Register 1 and Acceptance Filter ID Register 1 are used for acceptance filtering. 0: Indicates Acceptance Filter Mask Register 1 and Acceptance Filter ID Register 1 are not used for acceptance filtering.

Register (can) AFMR1

Name Relative Address Absolute Address Width Access Type Reset Value Description AFMR1 0x00000064 can0: 0xE0008064 can1: 0xE0009064 32 bits rw x Acceptance Filter Mask Register 1

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Appendix B: Register Details

Register AFMR1 Details

Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMSRR 20 rw x Substitute Remote Transmission Request Mask This bit is used for masking the RTR bit in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMIDE 19 rw x Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 0, this mask is applicable to only Standard frames. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 1, this mask is applicable to only extended frames. If AMIDE = 0 this mask is applicable to Standard frame.

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Appendix B: Register Details

Field Name AMIDL

Bits 18:1

Type rw

Reset Value x

Description Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

AMRTR

rw

Remote Transmission Request Mask. This bit is used for masking the RTR bit in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

Register (can) AFIR1

Name Relative Address Absolute Address Width Access Type Reset Value Description AFIR1 0x00000068 can0: 0xE0008068 can1: 0xE0009068 32 bits rw x Acceptance Filter ID Register 1

Register AFIR1 Details

Field Name AIIDH AISRR Bits 31:21 20 Type rw rw Reset Value x x Description Standard Message ID Standard Identifier Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames

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Appendix B: Register Details

Field Name AIIDL AIRTR

Bits 18:1 0

Type rw rw

Reset Value x x

Description Extended Message ID Mask Extended Identifier Remote Transmission Request Mask RTR bit for Extended frames.

Register (can) AFMR2

Name Relative Address Absolute Address Width Access Type Reset Value Description AFMR2 0x0000006C can0: 0xE000806C can1: 0xE000906C 32 bits rw x Acceptance Filter Mask Register 2

Register AFMR2 Details

Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMSRR 20 rw x Substitute Remote Transmission Request Mask This bit is used for masking the RTR bit in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

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Appendix B: Register Details

Field Name AMIDE

Bits 19

Type rw

Reset Value x

Description Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 0, this mask is applicable to only Standard frames. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 1, this mask is applicable to only extended frames. If AMIDE = 0 this mask is applicable to Standard frame.

AMIDL

18:1

rw

Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

AMRTR

rw

Remote Transmission Request Mask. This bit is used for masking the RTR bit in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

Register (can) AFIR2

Name Relative Address Absolute Address Width Access Type Reset Value AFIR2 0x00000070 can0: 0xE0008070 can1: 0xE0009070 32 bits rw x

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Appendix B: Register Details

Description

Acceptance Filter ID Register 2

Register AFIR2 Details

Field Name AIIDH AISRR Bits 31:21 20 Type rw rw Reset Value x x Description Standard Message ID Standard Identifier Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames AIIDL AIRTR 18:1 0 rw rw x x Extended Message ID Mask Extended Identifier Remote Transmission Request Mask RTR bit for Extended frames.

Register (can) AFMR3

Name Relative Address Absolute Address Width Access Type Reset Value Description AFMR3 0x00000074 can0: 0xE0008074 can1: 0xE0009074 32 bits rw x Acceptance Filter Mask Register 3

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Register AFMR3 Details

Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMSRR 20 rw x Substitute Remote Transmission Request Mask This bit is used for masking the RTR bit in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMIDE 19 rw x Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 0, this mask is applicable to only Standard frames. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 1, this mask is applicable to only extended frames. If AMIDE = 0 this mask is applicable to Standard frame.

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Appendix B: Register Details

Field Name AMIDL

Bits 18:1

Type rw

Reset Value x

Description Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

AMRTR

rw

Remote Transmission Request Mask. This bit is used for masking the RTR bit in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

Register (can) AFIR3

Name Relative Address Absolute Address Width Access Type Reset Value Description AFIR3 0x00000078 can0: 0xE0008078 can1: 0xE0009078 32 bits rw x Acceptance Filter ID Register 3

Register AFIR3 Details

Field Name AIIDH AISRR Bits 31:21 20 Type rw rw Reset Value x x Description Standard Message ID Standard Identifier Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames

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Appendix B: Register Details

Field Name AIIDL AIRTR

Bits 18:1 0

Type rw rw

Reset Value x x

Description Extended Message ID Mask Extended Identifier Remote Transmission Request Mask RTR bit for Extended frames.

Register (can) AFMR4

Name Relative Address Absolute Address Width Access Type Reset Value Description AFMR4 0x0000007C can0: 0xE000807C can1: 0xE000907C 32 bits rw x Acceptance Filter Mask Register 4

Register AFMR4 Details

Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMSRR 20 rw x Substitute Remote Transmission Request Mask This bit is used for masking the RTR bit in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

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Field Name AMIDE

Bits 19

Type rw

Reset Value x

Description Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 0, this mask is applicable to only Standard frames. If AMIDE = 1 and the AIIDE bit in the corresponding Acceptance ID register is 1, this mask is applicable to only extended frames. If AMIDE = 0 this mask is applicable to Standard frame.

AMIDL

18:1

rw

Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

AMRTR

rw

Remote Transmission Request Mask. This bit is used for masking the RTR bit in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.

Register (can) AFIR4

Name Relative Address Absolute Address Width Access Type Reset Value AFIR4 0x00000080 can0: 0xE0008080 can1: 0xE0009080 32 bits rw x

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Appendix B: Register Details

Description

Acceptance Filter ID Register 4

Register AFIR4 Details

Field Name AIIDH AISRR Bits 31:21 20 Type rw rw Reset Value x x Description Standard Message ID Standard Identifier Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames AIIDL AIRTR 18:1 0 rw rw x x Extended Message ID Mask Extended Identifier Remote Transmission Request Mask RTR bit for Extended frames.

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Appendix B: Register Details

B.6 DDR Memory Controller (ddrc)

Module Name Base Address Description Vendor Info DDR Memory Controller (ddrc) 0xF8006000 ddrc DDR memory controller Virage Logic/Synopsys

Register Summary
Register Name ddrc_ctrl Two_rank_cfg HPR_reg LPR_reg WR_reg DRAM_param_reg0 DRAM_param_reg1 DRAM_param_reg2 DRAM_param_reg3 DRAM_param_reg4 DRAM_init_param DRAM_EMR_reg DRAM_EMR_MR_reg DRAM_burst8_rdwr DRAM_disable_DQ Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 Width 32 29 26 26 26 21 32 32 32 28 14 32 32 29 13 20 32 28 30 20 32 21 Type rw rw rw rw rw rw rw rw mixed mixed rw rw rw mixed mixed rw rw rw rw ro mixed ro Reset Value 0x00000200 0x000C1076 0x03C0780F 0x03C0780F 0x0007F80F 0x00041016 0x351B48D9 0x83015904 0x250882D0 0x0000003C 0x00002007 0x00000008 0x00000940 0x00020034 0x00000000 0x00000F77 0xFFF00000 0x0FF55555 0x00000249 0x00000000 0x00010200 0x00000000 Description DDRC Control Two Rank Configuration HPR Queue control LPR Queue control WR Queue control DRAM Parameters 0 DRAM Parameters 1 DRAM Parameters 2 DRAM Parameters 3 DRAM Parameters 4 DRAM Initialization Parameters DRAM EMR2, EMR3 access DRAM EMR, MR access DRAM Burst 8 read/write DRAM Disable DQ Row/Column address bits Column address bits Select DRAM row address bits DRAM ODT control PHY debug PHY command time out and read data capture FIFO Controller operation mode status

DRAM_addr_map_ban 0x0000003C k DRAM_addr_map_col DRAM_addr_map_ro w DRAM_ODT_reg phy_dbg_reg phy_cmd_timeout_rdd ata_cpt mode_sts_reg 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000050 0x00000054

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Appendix B: Register Details

Register Name DLL_calib ODT_delay_hold ctrl_reg1 ctrl_reg2 ctrl_reg3 ctrl_reg4 ctrl_reg5 ctrl_reg6 CHE_REFRESH_TIME R01 CHE_T_ZQ CHE_T_ZQ_Short_Inte rval_Reg deep_pwrdwn_reg reg_2c reg_2d dfi_timing CHE_ECC_CONTROL _REG_OFFSET CHE_CORR_ECC_LO G_REG_OFFSET CHE_CORR_ECC_AD DR_REG_OFFSET CHE_CORR_ECC_DA TA_31_0_REG_OFFSE T

Address 0x00000058 0x0000005C 0x00000060 0x00000064 0x00000068 0x0000006C 0x00000078 0x0000007C 0x000000A0 0x000000A4 0x000000A8 0x000000AC 0x000000B0 0x000000B4 0x000000B8 0x000000C4 0x000000C8 0x000000CC 0x000000D0

Width 17 16 13 18 26 16 32 32 24 32 28 9 29 11 25 2 8 31 32

Type rw rw mixed mixed rw rw mixed mixed rw rw rw rw mixed rw rw rw mixed ro ro

Reset Value 0x00000101 0x00000023 0x0000003E 0x00020000 0x00284027 0x00001610 0x00455111 0x00032222 0x00008000 0x10300802 0x0020003A 0x00000000 0x00000000 0x00000200 0x00200067 0x00000000 0x00000000 0x00000000 0x00000000

Description DLL calibration ODT delay and ODT hold Controller 1 Controller 2 Controller 3 Controller 4 Controller register 5 Controller register 6 CHE_REFRESH_TIMER01 ZQ parameters Misc parameters Deep powerdown (LPDDR2) Training control Misc Debug DFI timing ECC error clear ECC error correction ECC error correction address log ECC error correction data log low ECC error correction data log mid ECC error correction data log high ECC unrecoverable error status ECC unrecoverable error address ECC unrecoverable error data low

CHE_CORR_ECC_DA 0x000000D4 TA_63_32_REG_OFFSE T CHE_CORR_ECC_DA 0x000000D8 TA_71_64_REG_OFFSE T CHE_UNCORR_ECC_ LOG_REG_OFFSET CHE_UNCORR_ECC_ ADDR_REG_OFFSET CHE_UNCORR_ECC_ DATA_31_0_REG_OFF SET 0x000000DC 0x000000E0 0x000000E4

32

ro

0x00000000

ro

0x00000000

1 31 32

clron wr ro ro

0x00000000 0x00000000 0x00000000

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Appendix B: Register Details

Register Name CHE_UNCORR_ECC_ DATA_63_32_REG_OF FSET CHE_UNCORR_ECC_ DATA_71_64_REG_OF FSET CHE_ECC_STATS_RE G_OFFSET ECC_scrub CHE_ECC_CORR_BIT _MASK_31_0_REG_OF FSET CHE_ECC_CORR_BIT _MASK_63_32_REG_O FFSET phy_rcvr_enable PHY_Config0 PHY_Config1 PHY_Config2 PHY_Config3 phy_init_ratio0 phy_init_ratio1 phy_init_ratio2 phy_init_ratio3 phy_rd_dqs_cfg0 phy_rd_dqs_cfg1 phy_rd_dqs_cfg2 phy_rd_dqs_cfg3 phy_wr_dqs_cfg0

Address 0x000000E8

Width 32

Type ro

Reset Value 0x00000000

Description ECC unrecoverable error data middle ECC unrecoverable error data high ECC error count ECC mode/scrub ECC data mask low

0x000000EC

ro

0x00000000

0x000000F0 0x000000F4 0x000000F8

16 4 32

clron wr rw ro

0x00000000 0x00000008 0x00000000

0x000000FC

32

ro

0x00000000

ECC data mask high

0x00000114 0x00000118 0x0000011C 0x00000120 0x00000124 0x0000012C 0x00000130 0x00000134 0x00000138 0x00000140 0x00000144 0x00000148 0x0000014C 0x00000154

8 31 31 31 31 20 20 20 20 20 20 20 20 20

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

0x00000000 0x40000001 0x40000001 0x40000001 0x40000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000040 0x00000040 0x00000040 0x00000040 0x00000000

Phy receiver enable register PHY configuration register for data slice 0. PHY configuration register for data slice 1. PHY configuration register for data slice 2. PHY configuration register for data slice 3. PHY init ratio register for data slice 0. PHY init ratio register for data slice 1. PHY init ratio register for data slice 2. PHY init ratio register for data slice 3. PHY read DQS configuration register for data slice 0. PHY read DQS configuration register for data slice 1. PHY read DQS configuration register for data slice 2. PHY read DQS configuration register for data slice 3. PHY write DQS configuration register for data slice 0.

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Appendix B: Register Details

Register Name phy_wr_dqs_cfg1 phy_wr_dqs_cfg2 phy_wr_dqs_cfg3 phy_we_cfg0 phy_we_cfg1 phy_we_cfg2 phy_we_cfg3 wr_data_slv0 wr_data_slv1 wr_data_slv2 wr_data_slv3 reg_64 reg_65 reg69_6a0 reg69_6a1 reg6c_6d2 reg6c_6d3 reg6e_710 reg6e_711 reg6e_712 reg6e_713 phy_dll_sts0 phy_dll_sts1

Address 0x00000158 0x0000015C 0x00000160 0x00000168 0x0000016C 0x00000170 0x00000174 0x0000017C 0x00000180 0x00000184 0x00000188 0x00000190 0x00000194 0x000001A4 0x000001A8 0x000001B0 0x000001B4 0x000001B8 0x000001BC 0x000001C0 0x000001C4 0x000001CC 0x000001D0

Width 20 20 20 21 21 21 21 20 20 20 20 32 20 29 29 29 29 30 30 30 30 27 27

Type rw rw rw rw rw rw rw rw rw rw rw rw rw ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000000 0x00000000 0x00000000 0x00000040 0x00000040 0x00000040 0x00000040 0x00000080 0x00000080 0x00000080 0x00000080 0x10020000 0x00000000 0x000F0000 0x000F0000 0x000F0000 0x000F0000 x x x x 0x00000000 0x00000000

Description PHY write DQS configuration register for data slice 1. PHY write DQS configuration register for data slice 2. PHY write DQS configuration register for data slice 3. PHY FIFO write enable configuration for data slice 0. PHY FIFO write enable configuration for data slice 1. PHY FIFO write enable configuration for data slice 2. PHY FIFO write enable configuration for data slice 3. PHY write data slave ratio config for data slice 0. PHY write data slave ratio config for data slice 1. PHY write data slave ratio config for data slice 2. PHY write data slave ratio config for data slice 3. Training control 2 Training control 3 Training results for data slice 0. Training results for data slice 1. Training results for data slice 2. Training results for data slice 3. Training results (2) for data slice 0. Training results (2) for data slice 1. Training results (2) for data slice 2. Training results (2) for data slice 3. Slave DLL results for data slice 0. Slave DLL results for data slice 1.

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Appendix B: Register Details

Register Name phy_dll_sts2 phy_dll_sts3 dll_lock_sts phy_ctrl_sts phy_ctrl_sts_reg2 axi_id page_mask axi_priority_wr_port0 axi_priority_wr_port1 axi_priority_wr_port2 axi_priority_wr_port3 axi_priority_rd_port0 axi_priority_rd_port1 axi_priority_rd_port2 axi_priority_rd_port3 trusted_mem_cfg excl_access_cfg0 excl_access_cfg1 excl_access_cfg2 excl_access_cfg3 mode_reg_read lpddr_ctrl0 lpddr_ctrl1 lpddr_ctrl2 lpddr_ctrl3

Address 0x000001D4 0x000001D8 0x000001E0 0x000001E4 0x000001E8 0x00000200 0x00000204 0x00000208 0x0000020C 0x00000210 0x00000214 0x00000218 0x0000021C 0x00000220 0x00000224 0x00000290 0x00000294 0x00000298 0x0000029C 0x000002A0 0x000002A4 0x000002A8 0x000002AC 0x000002B0 0x000002B4

Width 27 27 24 30 27 26 32 20 20 20 20 20 20 20 20 16 18 18 18 18 32 12 32 22 18

Type ro ro ro ro ro ro rw mixed mixed mixed mixed mixed mixed mixed mixed rw rw rw rw rw ro rw rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 x 0x00000000 0x00153042 0x00000000 0x000803FF 0x000803FF 0x000803FF 0x000803FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x003C0015 0x00000601

Description Slave DLL results for data slice 2. Slave DLL results for data slice 3. DLL Lock Status, read PHY Control status, read PHY Control status (2), read ID and revision information Page mask AXI Priority control for write port 0. AXI Priority control for write port 1. AXI Priority control for write port 2. AXI Priority control for write port 3. AXI Priority control for read port 0. AXI Priority control for read port 1. AXI Priority control for read port 2. AXI Priority control for read port 3. Trusted Memory configuration Exclusive access configuration for port 0. Exclusive access configuration for port 1. Exclusive access configuration for port 2. Exclusive access configuration for port 3. Mode register read data LPDDR2 Control 0 LPDDR2 Control 1 LPDDR2 Control 2 LPDDR2 Control 3

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Appendix B: Register Details

Register (ddrc) ddrc_ctrl

Name Relative Address Absolute Address Width Access Type Reset Value Description ddrc_ctrl 0x00000000 0xF8006000 32 bits rw 0x00000200 DDRC Control

Register ddrc_ctrl Details

Field Name reserved reg_ddrc_dis_auto_refr esh Bits 31:17 16 Type rw rw Reset Value 0x0 0x0 reserved Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. reg_ddrc_dis_act_bypa ss 15 rw 0x0 Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. reg_ddrc_dis_rd_bypas 14 s rw 0x0 Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. reg_ddrc_rdwr_idle_ga 13:7 p rw 0x4 When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. Description

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Appendix B: Register Details

Field Name reg_ddrc_burst8_refres h

Bits 6:4

Type rw

Reset Value 0x0

Description Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh

reg_ddrc_data_bus_wi dth

3:2

rw

0x0

DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved

reg_ddrc_powerdown_ en

rw

0x0

Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable

reg_ddrc_soft_rstb

rw

0x0

Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.

Register (ddrc) Two_rank_cfg

Name Relative Address Absolute Address Width Access Type Reset Value Two_rank_cfg 0x00000004 0xF8006004 29 bits rw 0x000C1076

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Appendix B: Register Details

Description

Two Rank Configuration

Register Two_rank_cfg Details

Most of this register only applies to a dual rank DRAM system
Field Name reserved reserved reserved reserved reserved Bits 28 27 26:22 21 20:19 Type rw rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x1 0x10 0x1 0x76 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Must be manually set to 0x0 Reserved. Do not modify. tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.

reg_ddrc_addrmap_cs_ 18:14 bit0 reserved reg_ddrc_t_rfc_nom_x 32 13:12 11:0

Register (ddrc) HPR_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description HPR_reg 0x00000008 0xF8006008 26 bits rw 0x03C0780F HPR Queue control

Register HPR_reg Details

Field Name Bits Type rw Reset Value 0xF Description Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).

reg_ddrc_hpr_xact_run 25:22 _length reg_ddrc_hpr_max_sta rve_x32 reg_ddrc_hpr_min_no n_critical_x32 21:11 10:0

rw rw

0xF 0xF

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Appendix B: Register Details

Register (ddrc) LPR_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description LPR_reg 0x0000000C 0xF800600C 26 bits rw 0x03C0780F LPR Queue control

Register LPR_reg Details

Field Name reg_ddrc_lpr_xact_run _length reg_ddrc_lpr_max_star ve_x32 reg_ddrc_lpr_min_non _critical_x32 Bits 25:22 Type rw Reset Value 0xF Description Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks

21:11 10:0

rw rw

0xF 0xF

Register (ddrc) WR_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description WR_reg 0x00000010 0xF8006010 26 bits rw 0x0007F80F WR Queue control

Register WR_reg Details

Field Name Bits Type rw Reset Value 0xF Description Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available Number of clock cycles that the WR queue is guaranteed to be non-critical.

reg_ddrc_w_max_starv 25:15 e_x32 reg_ddrc_w_xact_run_ length reg_ddrc_w_min_non_ critical_x32 14:11

rw

0xF

10:0

rw

0xF

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Appendix B: Register Details

Register (ddrc) DRAM_param_reg0

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_param_reg0 0x00000014 0xF8006014 21 bits rw 0x00041016 DRAM Parameters 0

Register DRAM_param_reg0 Details

Field Name reg_ddrc_post_selfref_ gap_x32 Bits 20:14 Type rw Reset Value 0x10 Description Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. reg_ddrc_t_rc 5:0 rw 0x16 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.

reg_ddrc_t_rfc_min

13:6

rw

0x40

Register (ddrc) DRAM_param_reg1

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_param_reg1 0x00000018 0xF8006018 32 bits rw 0x351B48D9 DRAM Parameters 1

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Appendix B: Register Details

Register DRAM_param_reg1 Details

Field Name reg_ddrc_t_cke Bits 31:28 Type rw Reset Value 0x3 Description Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. reg_ddrc_t_ras_min 26:22 rw 0x14 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. reg_ddrc_t_ras_max 21:16 rw 0x1B tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. reg_ddrc_t_faw 15:10 rw 0x12 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.

reg_ddrc_powerdown_ to_x32

9:5

rw

0x6

reg_ddrc_wr2pre

4:0

rw

0x19

Register (ddrc) DRAM_param_reg2

Name Relative Address Absolute Address Width Access Type DRAM_param_reg2 0x0000001C 0xF800601C 32 bits rw

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Appendix B: Register Details

Reset Value Description

0x83015904 DRAM Parameters 2

Register DRAM_param_reg2 Details

Field Name reg_ddrc_t_rcd Bits 31:28 Type rw Reset Value 0x8 Description tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. reg_ddrc_pad_pd 22:20 rw 0x0 If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. reg_ddrc_t_xp reg_ddrc_wr2rd 19:15 14:10 rw rw 0x2 0x16 tXP: Minimum time after power down exit to any operation. DRAM related. Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.

reg_ddrc_rd2pre

27:23

rw

0x6

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Appendix B: Register Details

Field Name reg_ddrc_rd2wr

Bits 9:5

Type rw

Reset Value 0x8

Description Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.

reg_ddrc_write_latenc y

4:0

rw

0x4

Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4

Register (ddrc) DRAM_param_reg3

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_param_reg3 0x00000020 0xF8006020 32 bits mixed 0x250882D0 DRAM Parameters 3

Register DRAM_param_reg3 Details

Field Name reserved reg_ddrc_dis_pad_pd Bits 31 30 Type rw rw Reset Value 0x0 0x0 Description Reserved. Do not modify. 1: disable the pad power down feature 0: Enable the pad power down feature.

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Appendix B: Register Details

Field Name

Bits

Type rw rw

Reset Value 0x1 0x5 unused

Description

reg_phy_mode_ddr1_d 29 dr2 reg_ddrc_read_latency 28:24

Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.

reg_ddrc_en_dfi_dram _clk_disable

23

rw

0x0

Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down

reg_ddrc_mobile reserved

22 21

rw rw rw

0x0 0x0 0x8

0: DDR2 or DDR3 device. 1: LPDDR2 device. Reserved. Do not modify. If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. tRP - Minimum time from precharge to activate of same bank. DRAM RELATED Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED

reg_ddrc_refresh_to_x3 20:16 2

reg_ddrc_t_rp

15:12

rw

0x8

reg_ddrc_refresh_marg in

11:8

rw

0x2

reg_ddrc_t_rrd

7:5

rw

0x6

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Appendix B: Register Details

Field Name reg_ddrc_t_ccd

Bits 4:2

Type rw

Reset Value 0x4

Description tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. Reserved

reserved

1:0

ro

0x0

Register (ddrc) DRAM_param_reg4

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_param_reg4 0x00000024 0xF8006024 28 bits mixed 0x0000003C DRAM Parameters 4

Register DRAM_param_reg4 Details

Field Name Bits Type clronr d Reset Value 0x0 Description This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. reg_ddrc_mr_type 26 rw 0x0 Indicates whether the Mode register operation is read or write 0: write 1: read ddrc_reg_mr_wr_busy 25 ro 0x0 Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.

reg_ddrc_mr_rdata_val 27 id

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Appendix B: Register Details

Field Name reg_ddrc_mr_data

Bits 24:9

Type rw

Reset Value 0x0

Description DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].

reg_ddrc_mr_addr

8:7

rw

0x0

DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3

reg_ddrc_mr_wr

wo

0x0

A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. Reserved. Do not modify. 1: Bank selector prefers writes over reads 1: DDRC will use 2T timing 0: DDRC will use 1T timing

reserved reg_ddrc_prefer_write reg_ddrc_en_2t_timing _mode

5:2 1 0

rw rw rw

0xF 0x0 0x0

Register (ddrc) DRAM_init_param

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_init_param 0x00000028 0xF8006028 14 bits rw 0x00002007 DRAM Initialization Parameters

Register DRAM_init_param Details

Field Name reg_ddrc_t_mrd Bits 13:11 Type rw Reset Value 0x4 Description tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.

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Appendix B: Register Details

Field Name reg_ddrc_pre_ocd_x32

Bits 10:7

Type rw

Reset Value 0x0

Description Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.

reg_ddrc_final_wait_x3 6:0 2

rw

0x7

Register (ddrc) DRAM_EMR_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_EMR_reg 0x0000002C 0xF800602C 32 bits rw 0x00000008 DRAM EMR2, EMR3 access

Register DRAM_EMR_reg Details

Field Name reg_ddrc_emr3 Bits 31:16 Type rw Reset Value 0x0 Description DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused reg_ddrc_emr2 15:0 rw 0x8 DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register

Register (ddrc) DRAM_EMR_MR_reg

Name Relative Address Absolute Address DRAM_EMR_MR_reg 0x00000030 0xF8006030

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Appendix B: Register Details

Width Access Type Reset Value Description

32 bits rw 0x00000940 DRAM EMR, MR access

Register DRAM_EMR_MR_reg Details

Field Name reg_ddrc_emr Bits 31:16 Type rw Reset Value 0x0 Description DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register reg_ddrc_mr 15:0 rw 0x940 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register

Register (ddrc) DRAM_burst8_rdwr

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_burst8_rdwr 0x00000034 0xF8006034 29 bits mixed 0x00020034 DRAM Burst 8 read/write

Register DRAM_burst8_rdwr Details

Field Name reg_ddrc_burstchop reserved Bits 28 27:26 Type rw ro Reset Value 0x0 0x0 Description Feature not supported. When 1, Controller is out in burstchop mode. Reserved

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Appendix B: Register Details

Field Name reg_ddrc_post_cke_x10 24

Bits 25:16

Type rw

Reset Value 0x2

Description Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.

reserved

15:14

ro rw

0x0 0x3

Reserved Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)

reg_ddrc_pre_cke_x102 13:4 4

reg_ddrc_burst_rdwr

3:0

rw

0x4

Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved

Register (ddrc) DRAM_disable_DQ

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_disable_DQ 0x00000038 0xF8006038 13 bits mixed 0x00000000 DRAM Disable DQ

Register DRAM_disable_DQ Details

Field Name reserved reserved reserved Bits 12:9 8 7 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

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Appendix B: Register Details

Field Name reserved reserved reg_ddrc_dis_dq

Bits 6 5:2 1

Type rw ro rw

Reset Value 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.

reg_ddrc_force_low_pr i_n

rw

0x0

Register (ddrc) DRAM_addr_map_bank

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_addr_map_bank 0x0000003C 0xF800603C 20 bits rw 0x00000F77 Row/Column address bits

Register DRAM_addr_map_bank Details

Note: address bits are relative to a byte address. For example, the value 0x777 in bits[11:0] selects byte address bits [14:12] as bank address bits.
Field Name reg_ddrc_addrmap_col _b6 Bits 19:16 Type rw Reset Value 0x0 Description Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. reg_ddrc_addrmap_col _b5 15:12 rw 0x0 Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.

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Appendix B: Register Details

Field Name reg_ddrc_addrmap_ba nk_b2

Bits 11:8

Type rw

Reset Value 0xF

Description Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.

reg_ddrc_addrmap_ba nk_b1

7:4

rw

0x7

reg_ddrc_addrmap_ba nk_b0

3:0

rw

0x7

Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.

Register (ddrc) DRAM_addr_map_col

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_addr_map_col 0x00000040 0xF8006040 32 bits rw 0xFFF00000 Column address bits

Register DRAM_addr_map_col Details

Selects the address bits used as DRAM column address bits

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Field Name reg_ddrc_addrmap_col _b11

Bits 31:28

Type rw

Reset Value 0xF

Description Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.

reg_ddrc_addrmap_col _b10

27:24

rw

0xF

Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.

reg_ddrc_addrmap_col _b9

23:20

rw

0xF

Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.

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Appendix B: Register Details

Field Name reg_ddrc_addrmap_col _b8

Bits 19:16

Type rw

Reset Value 0x0

Description Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.

reg_ddrc_addrmap_col _b7

15:12

rw

0x0

Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.

reg_ddrc_addrmap_col _b4

11:8

rw

0x0

Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.

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Appendix B: Register Details

Field Name reg_ddrc_addrmap_col _b3

Bits 7:4

Type rw

Reset Value 0x0

Description Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.

reg_ddrc_addrmap_col _b2

3:0

rw

0x0

Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.

Register (ddrc) DRAM_addr_map_row

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_addr_map_row 0x00000044 0xF8006044 28 bits rw 0x0FF55555 Select DRAM row address bits

Register DRAM_addr_map_row Details

Field Name reg_ddrc_addrmap_ro w_b15 Bits 27:24 Type rw Reset Value 0xF Description Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.

reg_ddrc_addrmap_ro w_b14

23:20

rw

0xF

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Field Name reg_ddrc_addrmap_ro w_b13

Bits 19:16

Type rw

Reset Value 0x5

Description Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field

reg_ddrc_addrmap_ro w_b12

15:12

rw

0x5

reg_ddrc_addrmap_ro w_b2_11

11:8

rw

0x5

reg_ddrc_addrmap_ro w_b1

7:4

rw

0x5

reg_ddrc_addrmap_ro w_b0

3:0

rw

0x5

Note: address bits are relative to a byte address. For example, the value 0x0FFF6666 selects byte address bits [29:15] as row ddress bits in a 32-bit bus width configuration.

Register (ddrc) DRAM_ODT_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description DRAM_ODT_reg 0x00000048 0xF8006048 30 bits rw 0x00000249 DRAM ODT control

Register DRAM_ODT_reg Details

Parts of this register are unused.

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Appendix B: Register Details

Field Name reserved reserved reserved reserved reg_phy_idle_local_odt

Bits 29:27 26:24 23:21 20:18 17:16

Type rw rw rw rw rw

Reset Value 0x0 0x0 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

reg_phy_wr_local_odt reg_phy_rd_local_odt

15:14 13:12

rw rw

0x0 0x0

reserved reserved reserved reserved

11:9 8:6 5:3 2:0

rw rw rw rw

0x1 0x1 0x1 0x1

Register (ddrc) phy_dbg_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_dbg_reg 0x0000004C 0xF800604C 20 bits ro 0x00000000 PHY debug

Register phy_dbg_reg Details

Field Name phy_reg_bc_fifo_re3 phy_reg_bc_fifo_we3 Bits 19 18 Type ro ro Reset Value 0x0 0x0 Description Debug read capture FIFO read enable for data slice 3. Debug read capture FIFO write enable, for data slice 3.

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Appendix B: Register Details

Field Name phy_reg_bc_dqs_oe3 phy_reg_bc_dq_oe3 phy_reg_bc_fifo_re2 phy_reg_bc_fifo_we2 phy_reg_bc_dqs_oe2 phy_reg_bc_dq_oe2 phy_reg_bc_fifo_re1 phy_reg_bc_fifo_we1 phy_reg_bc_dqs_oe1 phy_reg_bc_dq_oe1 phy_reg_bc_fifo_re0 phy_reg_bc_fifo_we0 phy_reg_bc_dqs_oe0 phy_reg_bc_dq_oe0 phy_reg_rdc_fifo_rst_e rr_cnt

Bits 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3:0

Type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Description Debug DQS output enable for data slice 3. Debug DQ output enable for data slice 3. Debug read capture FIFO read enable for data slice 2. Debug read capture FIFO write enable, for data slice 2. Debug DQS output enable for data slice 2. Debug DQ output enable for data slice 2. Debug read capture FIFO read enable for data slice 1. Debug read capture FIFO write enable, for data slice 1. Debug DQS output enable for data slice 1. Debug DQ output enable for data slice 1. Debug read capture FIFO read enable for data slice 0. Debug read capture FIFO write enable, for data slice 0. Debug DQS output enable for data slice 0. Debug DQ output enable for data slice 0. Counter for counting how many times the pointers of read capture FIFO differ when they are reset by dll_calib.

Register (ddrc) phy_cmd_timeout_rddata_cpt

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_cmd_timeout_rddata_cpt 0x00000050 0xF8006050 32 bits mixed 0x00010200 PHY command time out and read data capture FIFO

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Appendix B: Register Details

Register phy_cmd_timeout_rddata_cpt Details

Field Name reg_phy_wrlvl_num_o f_dq0 Bits 31:28 Type rw Reset Value 0x0 Description This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 +1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. reg_phy_gatelvl_num_ of_dq0 27:24 rw 0x0 This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. reserved reg_phy_clk_stall_level reg_phy_dis_phy_ctrl_ rstn reg_phy_rdc_fifo_rst_e rr_cnt_clr 23:20 19 18 ro rw rw 0x0 0x0 0x0 Reserved 1: stall clock, for DLL aging control Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. reg_phy_use_fixed_re 16 rw 0x1 When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. reg_phy_rdc_fifo_rst_d isable reserved 15 rw 0x0 When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. Reserved

17

rw

0x0

14:12

ro

0x0

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Appendix B: Register Details

Field Name reg_phy_rdc_we_to_re _delay

Bits 11:8

Type rw

Reset Value 0x2

Description This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.

reg_phy_wr_cmd_to_d ata reg_phy_rd_cmd_to_d ata

7:4 3:0

rw rw

0x0 0x0

Not used in DFI PHY. Not used in DFI PHY.

Register (ddrc) mode_sts_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description mode_sts_reg 0x00000054 0xF8006054 21 bits ro 0x00000000 Controller operation mode status

Register mode_sts_reg Details

Field Name Bits Type ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 Description Indicates the number of entries currently in the High Priority Read (HPR) CAM. Indicates the number of entries currently in the Low Priority Read (LPR) CAM. Indicates the number of entries currently in the Write CAM. 0: commands are being accepted. 1: no commands are accepted by the controller. ddrc_reg_operating_m ode 2:0 Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)

ddrc_reg_dbg_hpr_q_d 20:16 epth ddrc_reg_dbg_lpr_q_d epth ddrc_reg_dbg_wr_q_d epth ddrc_reg_dbg_stall 15:10 9:4 3

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Appendix B: Register Details

Register (ddrc) DLL_calib

Name Relative Address Absolute Address Width Access Type Reset Value Description DLL_calib 0x00000058 0xF8006058 17 bits rw 0x00000101 DLL calibration

Register DLL_calib Details

Field Name reg_ddrc_dis_dll_calib Bits 16 Type rw Reset Value 0x0 Description When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically reserved reserved 15:8 7:0 rw rw 0x1 0x1 Reserved. Do not modify. Reserved. Do not modify.

Register (ddrc) ODT_delay_hold

Name Relative Address Absolute Address Width Access Type Reset Value Description ODT_delay_hold 0x0000005C 0xF800605C 16 bits rw 0x00000023 ODT delay and ODT hold

Register ODT_delay_hold Details

Field Name reg_ddrc_wr_odt_hold Bits 15:12 Type rw Reset Value 0x0 Description Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 Unused

reg_ddrc_rd_odt_hold

11:8

rw

0x0

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Field Name reg_ddrc_wr_odt_dela y

Bits 7:4

Type rw

Reset Value 0x2

Description The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. UNUSED

reg_ddrc_rd_odt_delay

3:0

rw

0x3

Register (ddrc) ctrl_reg1

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg1 0x00000060 0xF8006060 13 bits mixed 0x0000003E Controller 1

Register ctrl_reg1 Details

Field Name reg_ddrc_selfref_en Bits 12 Type rw Reset Value 0x0 Description If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. reserved reg_ddrc_dis_collision _page_opt 11 10 ro rw 0x0 0x0 Always keep this set to 0x0 When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). Disable Write Combine: 0: enable 1: disable

reg_ddrc_dis_wc

rw

0x0

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Appendix B: Register Details

Field Name reg_ddrc_refresh_upda te_level

Bits 8

Type rw

Reset Value 0x0

Description Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.

reg_ddrc_auto_pre_en

rw

0x0

reg_ddrc_lpr_num_ent ries

6:1

rw

0x1F

reg_ddrc_pageclose

rw

0x0

Register (ddrc) ctrl_reg2

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg2 0x00000064 0xF8006064 18 bits mixed 0x00020000 Controller 2

Register ctrl_reg2 Details

Field Name reg_arb_go2critical_en Bits 17 Type rw Reset Value 0x1 Description 0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. reserved 16:13 ro 0x0 Reserved

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Field Name reg_ddrc_go2critical_h ysteresis

Bits 12:5

Type rw

Reset Value 0x0

Description Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. Reserved

reserved

4:0

ro

0x0

Register (ddrc) ctrl_reg3

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg3 0x00000068 0xF8006068 26 bits rw 0x00284027 Controller 3

Register ctrl_reg3 Details

Field Name reg_ddrc_dfi_t_wlmrd Bits 25:16 Type rw Reset Value 0x28 Description DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. reg_ddrc_rdlvl_rr 15:8 rw 0x40 DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. reg_ddrc_wrlvl_ww 7:0 rw 0x27 DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)

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Register (ddrc) ctrl_reg4

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg4 0x0000006C 0xF800606C 16 bits rw 0x00001610 Controller 4

Register ctrl_reg4 Details

Field Name dfi_t_ctrlupd_interval_ max_x1024 Bits 15:8 Type rw Reset Value 0x16 Description This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks

dfi_t_ctrlupd_interval_ min_x1024

7:0

rw

0x10

Register (ddrc) ctrl_reg5

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg5 0x00000078 0xF8006078 32 bits mixed 0x00455111 Controller register 5

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Register ctrl_reg5 Details

Field Name reserved reg_ddrc_t_ckesr Bits 31:26 25:20 Type ro rw Reset Value 0x0 0x4 Reserved Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 reg_ddrc_t_cksrx 19:16 rw 0x5 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX reg_ddrc_t_cksre 15:12 rw 0x5 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE reg_ddrc_dfi_t_dram_c lk_enable 11:8 rw 0x1 Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Description

reg_ddrc_dfi_t_dram_c lk_disable

7:4

rw

0x1

reg_ddrc_dfi_t_ctrl_del ay

3:0

rw

0x1

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Register (ddrc) ctrl_reg6

Name Relative Address Absolute Address Width Access Type Reset Value Description ctrl_reg6 0x0000007C 0xF800607C 32 bits mixed 0x00032222 Controller register 6

Register ctrl_reg6 Details

Field Name reserved reg_ddrc_t_ckcsx Bits 31:20 19:16 Type ro rw Reset Value 0x0 0x3 Reserved This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. reg_ddrc_t_ckdpdx 15:12 rw 0x2 This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. reg_ddrc_t_ckdpde 11:8 rw 0x2 This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. reg_ddrc_t_ckpdx 7:4 rw 0x2 This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. reg_ddrc_t_ckpde 3:0 rw 0x2 This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. Description

Register (ddrc) CHE_REFRESH_TIMER01

Name Relative Address Absolute Address Width CHE_REFRESH_TIMER01 0x000000A0 0xF80060A0 24 bits

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Access Type Reset Value Description

rw 0x00008000 CHE_REFRESH_TIMER01

Register CHE_REFRESH_TIMER01 Details

Field Name reserved reserved Bits 23:12 11:0 Type rw rw Reset Value 0x8 0x0 Description Reserved. Do not modify. Reserved. Do not modify.

Register (ddrc) CHE_T_ZQ

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_T_ZQ 0x000000A4 0xF80060A4 32 bits rw 0x10300802 ZQ parameters

Register CHE_T_ZQ Details

Field Name reg_ddrc_t_zq_short_n op Bits 31:22 Type rw Reset Value 0x40 Description DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. 21:12 rw 0x300 DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. 11:2 1 0 rw rw rw 0x200 0x1 0x0 Mode register set command update delay (minimum d'128) Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. 1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.

reg_ddrc_t_zq_long_n op

reg_ddrc_t_mod reg_ddrc_ddr3 reg_ddrc_dis_auto_zq

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Register (ddrc) CHE_T_ZQ_Short_Interval_Reg

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_T_ZQ_Short_Interval_Reg 0x000000A8 0xF80060A8 28 bits rw 0x0020003A Misc parameters

Register CHE_T_ZQ_Short_Interval_Reg Details

Field Name dram_rstn_x1024 Bits 27:20 Type rw Reset Value 0x2 Description Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.

t_zq_short_interval_x1 024

19:0

rw

0x3A

Register (ddrc) deep_pwrdwn_reg

Name Relative Address Absolute Address Width Access Type Reset Value Description deep_pwrdwn_reg 0x000000AC 0xF80060AC 9 bits rw 0x00000000 Deep powerdown (LPDDR2)

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Register deep_pwrdwn_reg Details

Field Name deeppowerdown_to_x 1024 Bits 8:1 Type rw Reset Value 0x0 Description DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. deeppowerdown_en 0 rw 0x0 DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.

Register (ddrc) reg_2c

Name Relative Address Absolute Address Width Access Type Reset Value Description reg_2c 0x000000B0 0xF80060B0 29 bits mixed 0x00000000 Training control

Register reg_2c Details

Field Name reg_ddrc_dfi_rd_data_ eye_train Bits 28 Type rw Reset Value 0x0 Description DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. reg_ddrc_dfi_rd_dqs_g ate_level 27 rw 0x0 0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 26 rw 0x0 0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs

reg_ddrc_dfi_wr_level _en

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Field Name ddrc_reg_trdlvl_max_e rror

Bits 25

Type ro

Reset Value 0x0

Description DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.

ddrc_reg_twrlvl_max_ error

24

ro

0x0

When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.

dfi_rdlvl_max_x1024

23:12

rw

0x0

Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks

dfi_wrlvl_max_x1024

11:0

rw

0x0

Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks

Register (ddrc) reg_2d

Name Relative Address Absolute Address Width Access Type Reset Value Description reg_2d 0x000000B4 0xF80060B4 11 bits rw 0x00000200 Misc Debug

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Register reg_2d Details

Field Name reserved reg_ddrc_skip_ocd Bits 10 9 Type rw rw Reset Value 0x0 0x1 Description Reserved. Do not modify. This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. reserved 8:0 rw 0x0 Reserved. Do not modify.

Register (ddrc) dfi_timing

Name Relative Address Absolute Address Width Access Type Reset Value Description dfi_timing 0x000000B8 0xF80060B8 25 bits rw 0x00200067 DFI timing

Register dfi_timing Details

Field Name reg_ddrc_dfi_t_ctrlup_ max reg_ddrc_dfi_t_ctrlup_ min reg_ddrc_dfi_t_rddata _en Bits 24:15 14:5 Type rw rw Reset Value 0x40 0x3 Description Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.

4:0

rw

0x7

Register (ddrc) CHE_ECC_CONTROL_REG_OFFSET

Name Relative Address Absolute Address CHE_ECC_CONTROL_REG_OFFSET 0x000000C4 0xF80060C4

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Appendix B: Register Details

Width Access Type Reset Value Description

2 bits rw 0x00000000 ECC error clear

Register CHE_ECC_CONTROL_REG_OFFSET Details

Field Name Clear_Correctable_DR AM_ECC_error Clear_Uncorrectable_D RAM_ECC_error Bits 1 0 Type rw rw Reset Value 0x0 0x0 Description Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.

Register (ddrc) CHE_CORR_ECC_LOG_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_CORR_ECC_LOG_REG_OFFSET 0x000000C8 0xF80060C8 8 bits mixed 0x00000000 ECC error correction

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Register CHE_CORR_ECC_LOG_REG_OFFSET Details

Field Name ECC_CORRECTED_BI T_NUM Bits 7:1 Type clron wr Reset Value 0x0 Description Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. CORR_ECC_LOG_VA LID 0 ro 0x0 Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)

Register (ddrc) CHE_CORR_ECC_ADDR_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_CORR_ECC_ADDR_REG_OFFSET 0x000000CC 0xF80060CC 31 bits ro 0x00000000 ECC error correction address log

Register CHE_CORR_ECC_ADDR_REG_OFFSET Details

Field Name CORR_ECC_LOG_BA NK Bits 30:28 Type ro Reset Value 0x0 Bank [2:0] Description

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Appendix B: Register Details

Field Name CORR_ECC_LOG_RO W CORR_ECC_LOG_CO L

Bits 27:12 11:0

Type ro ro

Reset Value 0x0 0x0 Row [15:0] Column [11:0]

Description

Register (ddrc) CHE_CORR_ECC_DATA_31_0_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_CORR_ECC_DATA_31_0_REG_OFFSET 0x000000D0 0xF80060D0 32 bits ro 0x00000000 ECC error correction data log low

Register CHE_CORR_ECC_DATA_31_0_REG_OFFSET Details

Field Name CORR_ECC_LOG_DA T_31_0 Bits 31:0 Type ro Reset Value 0x0 Description Bits [31:0] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared). Since each ECC engine handles 8-bits of data, only the lower 8-bits of this register have valid data. The upper 24-bits will always be 0.

Register (ddrc) CHE_CORR_ECC_DATA_63_32_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_CORR_ECC_DATA_63_32_REG_OFFSET 0x000000D4 0xF80060D4 32 bits ro 0x00000000 ECC error correction data log mid

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Register CHE_CORR_ECC_DATA_63_32_REG_OFFSET Details

Field Name CORR_ECC_LOG_DA T_63_32 Bits 31:0 Type ro Reset Value 0x0 Description Bits [63:32] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) Since each ECC engine handles 8-bits of data and that is logged in register 0x34, all the 32-bits of this register will always be 0.

Register (ddrc) CHE_CORR_ECC_DATA_71_64_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_CORR_ECC_DATA_71_64_REG_OFFSET 0x000000D8 0xF80060D8 8 bits ro 0x00000000 ECC error correction data log high

Register CHE_CORR_ECC_DATA_71_64_REG_OFFSET Details

Field Name CORR_ECC_LOG_DA T_71_64 Bits 7:0 Type ro Reset Value 0x0 Description Bits [71:64] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) 5-bits of ECC are calculated over 8-bits of data. Bits[68:64] carries these 5-bits. Bits[71:69] are always 0.

Register (ddrc) CHE_UNCORR_ECC_LOG_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_UNCORR_ECC_LOG_REG_OFFSET 0x000000DC 0xF80060DC 1 bits clronwr 0x00000000 ECC unrecoverable error status

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Register CHE_UNCORR_ECC_LOG_REG_OFFSET Details

Field Name UNCORR_ECC_LOG_ VALID Bits 0 Type clron wr Reset Value 0x0 Description Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).

Register (ddrc) CHE_UNCORR_ECC_ADDR_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_UNCORR_ECC_ADDR_REG_OFFSET 0x000000E0 0xF80060E0 31 bits ro 0x00000000 ECC unrecoverable error address

Register CHE_UNCORR_ECC_ADDR_REG_OFFSET Details

Field Name UNCORR_ECC_LOG_ BANK UNCORR_ECC_LOG_ ROW UNCORR_ECC_LOG_ COL Bits 30:28 27:12 11:0 Type ro ro ro Reset Value 0x0 0x0 0x0 Bank [2:0] Row [15:0] Column [11:0] Description

Register (ddrc) CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET 0x000000E4 0xF80060E4 32 bits ro 0x00000000 ECC unrecoverable error data low

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Register CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET Details

Field Name UNCORR_ECC_LOG_ DAT_31_0 Bits 31:0 Type ro Reset Value 0x0 Description bits [31:0] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared). Since each ECC engine handles 8-bits of data, only the lower 8-bits of this register have valid data. The upper 24-bits will always be 0.

Register (ddrc) CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET 0x000000E8 0xF80060E8 32 bits ro 0x00000000 ECC unrecoverable error data middle

Register CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET Details

Field Name UNCORR_ECC_LOG_ DAT_63_32 Bits 31:0 Type ro Reset Value 0x0 Description bits [63:32] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) Since each ECC engine handles 8-bits of data and that is logged in register 0x34, all the 32-bits of this register will always be 0.

Register (ddrc) CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET 0x000000EC 0xF80060EC 8 bits ro 0x00000000 ECC unrecoverable error data high

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Register CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET Details

Field Name UNCORR_ECC_LOG_ DAT_71_64 Bits 7:0 Type ro Reset Value 0x0 Description bits [71:64] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared) 5-bits of ECC are calculated over 8-bits of data. Bits[68:64] carries these 5-bits. Bits[71:69] are always 0.

Register (ddrc) CHE_ECC_STATS_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_ECC_STATS_REG_OFFSET 0x000000F0 0xF80060F0 16 bits clronwr 0x00000000 ECC error count

Register CHE_ECC_STATS_REG_OFFSET Details

Field Name STAT_NUM_CORR_E RR Bits 15:8 Type clron wr Reset Value 0x0 Description Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).

STAT_NUM_UNCORR _ERR

7:0

clron wr

0x0

Register (ddrc) ECC_scrub

Name Relative Address Absolute Address Width Access Type Reset Value Description ECC_scrub 0x000000F4 0xF80060F4 4 bits rw 0x00000008 ECC mode/scrub

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Appendix B: Register Details

Register ECC_scrub Details

Field Name reg_ddrc_dis_scrub Bits 3 Type rw Reset Value 0x1 Description 0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs reg_ddrc_ecc_mode 2:0 rw 0x0 DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved

Register (ddrc) CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET 0x000000F8 0xF80060F8 32 bits ro 0x00000000 ECC data mask low

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Appendix B: Register Details

Register CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET Details

Field Name ddrc_reg_ecc_corr_bit_ mask Bits 31:0 Type ro Reset Value 0x0 Description Bits [31:0] of ddrc_reg_ecc_corr_bit_mask register. Indicates the mask of the corrected data. 1 - on any bit indicates that the bit has been corrected by the DRAM ECC logic 0 - on any bit indicates that the bit has NOT been corrected by the DRAM ECC logic. Valid when any bit of 'ddrc_reg_ecc_corrected_err' is high. This mask doesn't indicate any correction that has been made in the ECC check bits. If there are errors in multiple lanes, then this signal will have the mask for the lowest lane. Each ECC engine works on 8-bits of data. Hence only the lower 8-bits carry valid information. Upper 24-bits are always 0.

Register (ddrc) CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET 0x000000FC 0xF80060FC 32 bits ro 0x00000000 ECC data mask high

Register CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET Details

Field Name ddrc_reg_ecc_corr_bit_ mask Bits 31:0 Type ro Reset Value 0x0 Description Bits [63:32] of ddrc_reg_ecc_corr_bit_mask register. Indicates the mask of the corrected data. 1 - on any bit indicates that the bit has been corrected by the DRAM ECC logic 0 - on any bit indicates that the bit has NOT been corrected by the DRAM ECC logic. Valid when any bit of 'ddrc_reg_ecc_corrected_err' is high. This mask doesn't indicate any correction that has been made in the ECC check bits. If there are errors in multiple lanes, then this signal will have the mask for the lowest lane. Each ECC engine works on 8-bits of data and this is reported in register 0x3E. All 32-bits of this register are 0 always.

Register (ddrc) phy_rcvr_enable

Name phy_rcvr_enable

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000114 0xF8006114 8 bits rw 0x00000000 Phy receiver enable register

Register phy_rcvr_enable Details

Field Name reg_phy_dif_off Bits 7:4 Type rw Reset Value 0x0 Description Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. reg_phy_dif_on 3:0 rw 0x0 Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.

Register (ddrc) PHY_Config0

Name Relative Address Absolute Address Width Access Type Reset Value Description PHY_Config0 0x00000118 0xF8006118 31 bits rw 0x40000001 PHY configuration register for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.

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Appendix B: Register Details

Name PHY_Config0 PHY_Config1 PHY_Config2 PHY_Config3

Address 0xf8006118 0xf800611c 0xf8006120 0xf8006124

Register PHY_Config0 to PHY_Config3 Details

Field Name reg_phy_dq_offset Bits 30:24 Type rw Reset Value 0x40 Description Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. reserved reserved reserved reserved reg_phy_wrlvl_inc_mo de reg_phy_gatelvl_inc_m ode reg_phy_rdlvl_inc_mo de 23:15 14:6 5 4 3 2 1 rw rw rw rw rw rw rw rw 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. reserved reserved reserved Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.

reg_phy_data_slice_in_ 0 use

Register (ddrc) phy_init_ratio0

Name Relative Address Absolute Address Width Access Type phy_init_ratio0 0x0000012C 0xF800612C 20 bits rw

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Reset Value Description

0x00000000 PHY init ratio register for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name phy_init_ratio0 phy_init_ratio1 phy_init_ratio2 phy_init_ratio3 Address 0xf800612c 0xf8006130 0xf8006134 0xf8006138

Register phy_init_ratio0 to phy_init_ratio3 Details

Field Name reg_phy_gatelvl_init_r atio reg_phy_wrlvl_init_rat io Bits 19:10 9:0 Type rw rw Reset Value 0x0 0x0 Description The user programmable init ratio used Gate Leveling FSM The user programmable init ratio used by Write Leveling FSM

Register (ddrc) phy_rd_dqs_cfg0

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_rd_dqs_cfg0 0x00000140 0xF8006140 20 bits rw 0x00000040 PHY read DQS configuration register for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name phy_rd_dqs_cfg0 phy_rd_dqs_cfg1 phy_rd_dqs_cfg2 phy_rd_dqs_cfg3 Address 0xf8006140 0xf8006144 0xf8006148 0xf800614c

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Appendix B: Register Details

Register phy_rd_dqs_cfg0 to phy_rd_dqs_cfg3 Details

Field Name reg_phy_rd_dqs_slave _delay reg_phy_rd_dqs_slave _force Bits 19:11 Type rw Reset Value 0x0 Description If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. 0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. reg_phy_rd_dqs_slave _ratio 9:0 rw 0x40 Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications

10

rw

0x0

Register (ddrc) phy_wr_dqs_cfg0

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_wr_dqs_cfg0 0x00000154 0xF8006154 20 bits rw 0x00000000 PHY write DQS configuration register for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name phy_wr_dqs_cfg0 phy_wr_dqs_cfg1 phy_wr_dqs_cfg2 phy_wr_dqs_cfg3 Address 0xf8006154 0xf8006158 0xf800615c 0xf8006160

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Register phy_wr_dqs_cfg0 to phy_wr_dqs_cfg3 Details

Field Name reg_phy_wr_dqs_slave _delay reg_phy_wr_dqs_slave _force Bits 19:11 Type rw Reset Value 0x0 Description If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. 0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. reg_phy_wr_dqs_slave _ratio 9:0 rw 0x0 Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)

10

rw

0x0

Register (ddrc) phy_we_cfg0

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_we_cfg0 0x00000168 0xF8006168 21 bits rw 0x00000040 PHY FIFO write enable configuration for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name phy_we_cfg0 phy_we_cfg1 phy_we_cfg2 phy_we_cfg3 Address 0xf8006168 0xf800616c 0xf8006170 0xf8006174

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Register phy_we_cfg0 to phy_we_cfg3 Details

Field Name Bits Type rw Reset Value 0x0 Description Delay value to be used when reg_phy_fifo_we_in_force is set to 1. reg_phy_fifo_we_in_fo rce 11 rw 0x0 0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units reg_phy_fifo_we_slave _ratio 10:0 rw 0x40 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.

reg_phy_fifo_we_in_de 20:12 lay

Register (ddrc) wr_data_slv0

Name Relative Address Absolute Address Width Access Type Reset Value Description wr_data_slv0 0x0000017C 0xF800617C 20 bits rw 0x00000080 PHY write data slave ratio config for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name wr_data_slv0 wr_data_slv1 wr_data_slv2 wr_data_slv3 Address 0xf800617c 0xf8006180 0xf8006184 0xf8006188

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Register wr_data_slv0 to wr_data_slv3 Details

Field Name reg_phy_wr_data_slav e_delay reg_phy_wr_data_slav e_force Bits 19:11 Type rw Reset Value 0x0 Description If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. 0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. reg_phy_wr_data_slav e_ratio 9:0 rw 0x80 Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

10

rw

0x0

Register (ddrc) reg_64

Name Relative Address Absolute Address Width Access Type Reset Value Description reg_64 0x00000190 0xF8006190 32 bits rw 0x10020000 Training control 2

Register reg_64 Details

Field Name reserved reg_phy_cmd_latency reg_phy_lpddr reserved reg_phy_ctrl_slave_del ay Bits 31 30 29 28 27:21 Type rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x1 0x0 Description Reserved. Do not modify. If set to 1, command comes to phy_ctrl through a flop. 0: DDR2 or DDR3. 1: LPDDR2. Reserved. Do not modify. If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].

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Appendix B: Register Details

Field Name reg_phy_ctrl_slave_for ce

Bits 20

Type rw

Reset Value 0x0

Description 0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.

reg_phy_ctrl_slave_rati o

19:10

rw

0x80

Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms

reg_phy_sel_logic

rw

0x0

reserved reg_phy_invert_clkout

8 7

rw rw

0x0 0x0

Reserved. Do not modify. Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.

reserved reserved reserved reserved reg_phy_bl2 reserved

6:5 4 3 2 1 0

rw rw rw rw rw rw

0x0 0x0 0x0 0x0 0x0 0x0

Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved for future Use. Reserved. Do not modify.

Register (ddrc) reg_65

Name Relative Address Absolute Address Width Access Type reg_65 0x00000194 0xF8006194 20 bits rw

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Appendix B: Register Details

Reset Value Description

0x00000000 Training control 3

Register reg_65 Details

Field Name reg_phy_ctrl_slave_del ay reg_phy_dis_calib_rst Bits 19:18 Type rw Reset Value 0x0 Description If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs reg_phy_use_rd_data_ eye_level 16 rw 0x0 Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure reg_phy_use_rd_dqs_g ate_level 15 rw 0x0 Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. reg_phy_use_wr_level 14 rw 0x0 Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. reg_phy_dll_lock_diff 13:10 rw 0x0 The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted

17

rw

0x0

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Appendix B: Register Details

Field Name reg_phy_rd_rl_delay

Bits 9:5

Type rw

Reset Value 0x0

Description This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency 3) with a minimum value of 1.

reg_phy_wr_rl_delay

4:0

rw

0x0

This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency 4) with a minimum value of 1.

The fifo_we_slave ratios for each slice(0 through 3) must be interpreted by software in the following way: Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]} Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]} Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]} Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}

Register (ddrc) reg69_6a0

Name Relative Address Absolute Address Width Access Type Reset Value Description reg69_6a0 0x000001A4 0xF80061A4 29 bits ro 0x000F0000 Training results for data slice 0.

Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name reg69_6a0 reg69_6a1 Address 0xf80061a4 0xf80061a8

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Appendix B: Register Details

Register reg69_6a0 to reg69_6a1 Details

Field Name phy_reg_status_fifo_w e_slave_dll_value phy_reg_rdlvl_fifowei n_ratio reserved Bits 28:20 19:9 8:0 Type ro ro ro Reset Value 0x0 0x780 0x0 Description Delay value applied to FIFO WE slave DLL. Ratio value generated by Read Gate training FSM. Reserved. Do not modify.

Register (ddrc) reg6c_6d2

Name Relative Address Absolute Address Width Access Type Reset Value Description reg6c_6d2 0x000001B0 0xF80061B0 29 bits ro 0x000F0000 Training results for data slice 2.

Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name reg6c_6d2 reg6c_6d3 Address 0xf80061b0 0xf80061b4

Register reg6c_6d2 to reg6c_6d3 Details

Field Name phy_reg_status_fifo_w e_slave_dll_value phy_reg_rdlvl_fifowei n_ratio phy_reg_bist_err Bits 28:20 19:9 8:0 Type ro ro ro Reset Value 0x0 0x780 0x0 Description Delay value applied to FIFO WE slave DLL. Ratio value generated by Read Gate training FSM. Mismatch error flag from the BIST Checker. 1 bit per data slice. 1'b1: Pattern mismatch error 1'b0: All patterns matched This is a sticky flag. In order to clear this bit, port reg_phy_bist_err_clr must be set HIGH. Note that reg6b is unused.

Register (ddrc) reg6e_710

Name reg6e_710

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x000001B8 0xF80061B8 30 bits ro x Training results (2) for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name reg6e_710 reg6e_711 reg6e_712 reg6e_713 Address 0xf80061b8 0xf80061bc 0xf80061c0 0xf80061c4

Register reg6e_710 to reg6e_713 Details

Field Name Bits Type ro ro ro Reset Value x x x Description Ratio value generated by Read Data Eye training FSM. Ratio value generated by the write leveling FSM for Write Data. Ratio value generated by the write leveling FSM for Write DQS.

phy_reg_rdlvl_dqs_rati 29:20 o phy_reg_wrlvl_dq_rati o phy_reg_wrlvl_dqs_rat io 19:10 9:0

Register (ddrc) phy_dll_sts0

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_dll_sts0 0x000001CC 0xF80061CC 27 bits ro 0x00000000 Slave DLL results for data slice 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.

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Appendix B: Register Details

Name phy_dll_sts0 phy_dll_sts1 phy_dll_sts2 phy_dll_sts3

Address 0xf80061cc 0xf80061d0 0xf80061d4 0xf80061d8

Register phy_dll_sts0 to phy_dll_sts3 Details

Field Name phy_reg_status_wr_dq s_slave_dll_value Bits 26:18 Type ro ro ro Reset Value 0x0 0x0 0x0 Description Delay value applied to write DQS slave DLL Delay value applied to write data slave DLL Delay value applied to read data slave DLL

phy_reg_status_wr_dat 17:9 a_slave_dll_value phy_reg_status_rd_dqs _slave_dll_value 8:0

Register (ddrc) dll_lock_sts

Name Relative Address Absolute Address Width Access Type Reset Value Description dll_lock_sts 0x000001E0 0xF80061E0 24 bits ro 0x00000000 DLL Lock Status, read

Register dll_lock_sts Details

Field Name phy_reg_rdlvl_fifowei n_ratio_slice3_msb Bits 23:20 Type ro Reset Value 0x0 Description Used as 4-msbits of slice3's ratio value generated by Read Gate training FSM. Refer to description of reg69_6a[1:0], fifo_we_slave ratio, for more details phy_reg_status_dll_sla ve_value_1 19:11 ro 0x0 Shows the current Coarse and Fine delay values going to all the Slave DLLs [1:0] - Fine value [8:2] - Coarse value (For Master DLL 1) phy_reg_status_dll_sla ve_value_0 10:2 ro 0x0 Shows the current Coarse and Fine delay values going to all the Slave DLLs [1:0] - Fine value [8:2] - Coarse value (For Master DLL 0)

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Appendix B: Register Details

Field Name phy_reg_status_dll_loc k_1

Bits 1

Type ro

Reset Value 0x0

Description Status Master DLL 1 signal: 0: not locked 1: locked

phy_reg_status_dll_loc k_0

ro

0x0

Master DLL 0 Status signal: 0: not locked 1: locked

Register (ddrc) phy_ctrl_sts

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_ctrl_sts 0x000001E4 0xF80061E4 30 bits ro x PHY Control status, read

Register phy_ctrl_sts Details

Field Name phy_reg_status_phy_ct rl_of_in_lock_state Bits 29:28 Type ro Reset Value 0x0 Description Lock status from Master DLL Output Filter. 0: not locked, 1: locked. Bit 28: Fine delay line. Bit 29: Coarse delay line. phy_reg_status_phy_ct rl_dll_slave_value 27:20 ro 0x0 Values applied to the PHY_CTRL Slave DLL: Bit field 21:20 is the Fine value Bit field 27:22 is the Course value phy_reg_status_phy_ct rl_dll_lock phy_reg_status_of_out _delay_value 19 18:10 ro ro 0x0 x PHY Control Master DLL Status: 0: not locked, 1: locked Values from Master DDL Output Filter (no default value). Bit field 11:10 is the Fine value Bit field 18:12 is the Coarse value phy_reg_status_of_in_ delay_value 9:0 ro x Values applied to Master DDL Output Filter (no default value): Bit field 1:0 is the Fine value Bit field 9:2 is the Coarse value

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Appendix B: Register Details

Register (ddrc) phy_ctrl_sts_reg2

Name Relative Address Absolute Address Width Access Type Reset Value Description phy_ctrl_sts_reg2 0x000001E8 0xF80061E8 27 bits ro 0x00000000 PHY Control status (2), read

Register phy_ctrl_sts_reg2 Details

Field Name phy_reg_status_phy_ct rl_slave_dll_value reserved phy_reg_status_phy_ct rl_of_in_delay_value Bits 26:18 17:9 8:0 Type ro ro ro Reset Value 0x0 0x0 0x0 Description Delay value applied to read DQS slave DLL. reserved Values applied to Master DLL Output Filter: Bit field 1:0 is the Fine value Bit field 8:2 is the Coarse value

Register (ddrc) axi_id

Name Relative Address Absolute Address Width Access Type Reset Value Description axi_id 0x00000200 0xF8006200 26 bits ro 0x00153042 ID and revision information

Register axi_id Details

Field Name reg_arb_rev_num reg_arb_prov_num reg_arb_part_num Bits 25:20 19:12 11:0 Type ro ro ro Reset Value 0x1 0x53 0x42 Revision Number Prov number Part Number Description

Register (ddrc) page_mask

Name page_mask

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000204 0xF8006204 32 bits rw 0x00000000 Page mask

Register page_mask Details

Field Name reg_arb_page_addr_m ask Bits 31:0 Type rw Reset Value 0x0 Description Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.

Register (ddrc) axi_priority_wr_port0

Name Relative Address Absolute Address Width Access Type Reset Value Description axi_priority_wr_port0 0x00000208 0xF8006208 20 bits mixed 0x000803FF AXI Priority control for write port 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name axi_priority_wr_port0 axi_priority_wr_port1 axi_priority_wr_port2 axi_priority_wr_port3 Address 0xf8006208 0xf800620c 0xf8006210 0xf8006214

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Appendix B: Register Details

Register axi_priority_wr_port0 to axi_priority_wr_port3 Details

Field Name reserved reg_arb_dis_page_mat ch_wr_portn reg_arb_disable_urgen t_wr_portn reg_arb_disable_aging _wr_portn reserved reg_arb_pri_wr_portn Bits 19 18 17 16 15:10 9:0 Type rw rw rw rw ro rw Reset Value 0x1 0x0 0x0 0x0 0x0 0x3FF Description Reserved. Do not modify. Disable the page match feature. Disable urgent for this Write Port. Disable aging for this Write Port. Reserved Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. Note that the minimum write priority should be set to 0x4.

Register (ddrc) axi_priority_rd_port0

Name Relative Address Absolute Address Width Access Type Reset Value Description axi_priority_rd_port0 0x00000218 0xF8006218 20 bits mixed 0x000003FF AXI Priority control for read port 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name axi_priority_rd_port0 axi_priority_rd_port1 axi_priority_rd_port2 axi_priority_rd_port3 Address 0xf8006218 0xf800621c 0xf8006220 0xf8006224

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Register axi_priority_rd_port0 to axi_priority_rd_port3 Details

Field Name reg_arb_set_hpr_rd_po rtn reg_arb_dis_page_mat ch_rd_portn reg_arb_disable_urgen t_rd_portn reg_arb_disable_aging _rd_portn reserved reg_arb_pri_rd_portn Bits 19 18 17 16 15:10 9:0 Type rw rw rw rw ro rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x3FF Description Enable reads to be generated as HPR for this Read Port. Disable the page match feature. Disable urgent for this Read Port. Disable aging for this Read Port. Reserved. Do not modify. Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.

Register (ddrc) trusted_mem_cfg

Name Relative Address Absolute Address Width Access Type Reset Value Description trusted_mem_cfg 0x00000290 0xF8006290 16 bits rw 0x00000000 Trusted Memory configuration

Register trusted_mem_cfg Details

Field Name reg_decprot Bits 15:0 Type rw Reset Value 0x0 Description Sets the memory regions to be secure or non-secure. The memory is divided into 64Mb sections. For a 1 Gb part, the number of regions is 16. 0 - non-secure region 1 - secure region Reserved. Not used any more.

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Register (ddrc) excl_access_cfg0

Name Relative Address Absolute Address Width Access Type Reset Value Description excl_access_cfg0 0x00000294 0xF8006294 18 bits rw 0x00000000 Exclusive access configuration for port 0.

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name excl_access_cfg0 excl_access_cfg1 excl_access_cfg2 excl_access_cfg3 Address 0xf8006294 0xf8006298 0xf800629c 0xf80062a0

Register excl_access_cfg0 to excl_access_cfg3 Details

Field Name reg_excl_acc_id1_port reg_excl_acc_id0_port Bits 17:9 8:0 Type rw rw Reset Value 0x0 0x0 Reserved Reserved Description

Register (ddrc) mode_reg_read

Name Relative Address Absolute Address Width Access Type Reset Value Description mode_reg_read 0x000002A4 0xF80062A4 32 bits ro 0x00000000 Mode register read data

Register mode_reg_read Details

This registers is applicable only when LPDDR2 is selected.

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Field Name ddrc_reg_rd_mrr_data

Bits 31:0

Type ro

Reset Value 0x0

Description Mode register read Data. Valid when ddrc_co_rd_mrr_data_valid is high. Bits[7:0] carry the 8-bit MRR value. Valid for LPDDR2 only.

Register (ddrc) lpddr_ctrl0

Name Relative Address Absolute Address Width Access Type Reset Value Description lpddr_ctrl0 0x000002A8 0xF80062A8 12 bits rw 0x00000000 LPDDR2 Control 0

Register lpddr_ctrl0 Details

This registers is applicable only when LPDDR2 is selected.
Field Name reg_ddrc_mr4_margin reserved reg_ddrc_derate_enabl e Bits 11:4 3 2 Type rw rw rw Reset Value 0x0 0x0 0x0 UNUSED Reserved. Datasheet does not mention this field 0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed reserved reg_ddrc_lpddr2 1 0 rw rw 0x0 0x0 Reserved. Do not modify. 0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. Description

Register (ddrc) lpddr_ctrl1

Name Relative Address Absolute Address Width Access Type Reset Value Description lpddr_ctrl1 0x000002AC 0xF80062AC 32 bits rw 0x00000000 LPDDR2 Control 1

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Register lpddr_ctrl1 Details

Field Name Bits Type rw Reset Value 0x0 Description Interval between two MR4 reads, USED to derate the timing parameters.

reg_ddrc_mr4_read_int 31:0 erval

Register (ddrc) lpddr_ctrl2

Name Relative Address Absolute Address Width Access Type Reset Value Description lpddr_ctrl2 0x000002B0 0xF80062B0 22 bits rw 0x003C0015 LPDDR2 Control 2

Register lpddr_ctrl2 Details

Field Name reg_ddrc_t_mrw Bits 21:12 Type rw Reset Value 0x3C0 Description Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. Idle time after the reset command, tINIT4. Units: 32 clock cycles. 3:0 rw 0x5 Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.

reg_ddrc_idle_after_re set_x32 reg_ddrc_min_stable_c lock_x1

11:4

rw

0x1

Register (ddrc) lpddr_ctrl3

Name Relative Address Absolute Address Width Access Type Reset Value Description lpddr_ctrl3 0x000002B4 0xF80062B4 18 bits rw 0x00000601 LPDDR2 Control 3

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Register lpddr_ctrl3 Details

Field Name reg_ddrc_dev_zqinit_x 32 reg_ddrc_max_auto_in it_x1024 Bits 17:8 Type rw Reset Value 0x6 Description ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. 7:0 rw 0x1 Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.

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B.7 CoreSight Cross Trigger Interface (cti)

Module Name Base Address CoreSight Cross Trigger Interface (cti) 0xF8898000 debug_cpu_cti0 0xF8899000 debug_cpu_cti1 0xF8802000 debug_cti_etb_tpiu 0xF8809000 debug_cti_ftm Description Vendor Info Cross Trigger Interface

Register Summary
Register Name CTICONTROL CTIINTACK CTIAPPSET CTIAPPCLEAR CTIAPPPULSE CTIINEN0 CTIINEN1 CTIINEN2 CTIINEN3 CTIINEN4 CTIINEN5 CTIINEN6 CTIINEN7 CTIOUTEN0 Address 0x00000000 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x000000A0 Width 1 8 4 4 4 4 4 4 4 4 4 4 4 4 Type rw wo rw wo wo rw rw rw rw rw rw rw rw rw Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description CTI Control Register CTI Interrupt Acknowledge Register CTI Application Trigger Set Register CTI Application Trigger Clear Register CTI Application Pulse Register CTI Trigger to Channel Enable 0 Register CTI Trigger to Channel Enable 1 Register CTI Trigger to Channel Enable 2 Register CTI Trigger to Channel Enable 3 Register CTI Trigger to Channel Enable 4 Register CTI Trigger to Channel Enable 5 Register CTI Trigger to Channel Enable 6 Register CTI Trigger to Channel Enable 7 Register CTI Channel to Trigger Enable 0 Register

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Register Name CTIOUTEN1 CTIOUTEN2 CTIOUTEN3 CTIOUTEN4 CTIOUTEN5 CTIOUTEN6 CTIOUTEN7 CTITRIGINSTATUS CTITRIGOUTSTATUS CTICHINSTATUS CTICHOUTSTATUS CTIGATE ASICCTL ITCHINACK ITTRIGINACK ITCHOUT ITTRIGOUT ITCHOUTACK ITTRIGOUTACK ITCHIN ITTRIGIN ITCTRL CTSR CTCR LAR LSR ASR DEVID

Address 0x000000A4 0x000000A8 0x000000AC 0x000000B0 0x000000B4 0x000000B8 0x000000BC 0x00000130 0x00000134 0x00000138 0x0000013C 0x00000140 0x00000144 0x00000EDC 0x00000EE0 0x00000EE4 0x00000EE8 0x00000EEC 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8

Width 4 4 4 4 4 4 4 8 8 4 4 4 8 4 8 4 8 4 8 4 8 1 4 4 32 3 4 20

Type rw rw rw rw rw rw rw ro ro ro ro rw rw wo wo wo wo ro ro ro ro rw rw rw wo ro ro ro

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 x 0x00000000 x 0x00000000 0x0000000F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000000F 0x00000000 0x00000000 0x00000003 x 0x00040800

Description CTI Channel to Trigger Enable 1 Register CTI Channel to Trigger Enable 2 Register CTI Channel to Trigger Enable 3 Register CTI Channel to Trigger Enable 4 Register CTI Channel to Trigger Enable 5 Register CTI Channel to Trigger Enable 6 Register CTI Channel to Trigger Enable 7 Register CTI Trigger In Status Register CTI Trigger Out Status Register CTI Channel In Status Register CTI Channel Out Status Register Enable CTI Channel Gate Register External Multiplexor Control Register ITCHINACK Register ITTRIGINACK Register ITCHOUT Register ITTRIGOUT Register ITCHOUTACK Register ITTRIGOUTACK Register ITCHIN Register ITTRIGIN Register IT Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID

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Register Name DTIR PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 8 8 8 8 8 8 8 8 8 8 8 8 8

Type ro ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000014 0x00000004 0x00000000 0x00000000 0x00000000 0x00000006 0x000000B9 0x0000002B 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description Device Type Identifier Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (cti) CTICONTROL

Name Relative Address Absolute Address CTICONTROL 0x00000000 debug_cpu_cti0: 0xF8898000 debug_cpu_cti1: 0xF8899000 debug_cti_etb_tpiu: 0xF8802000 debug_cti_ftm: 0xF8809000 Width Access Type Reset Value Description 1 bits rw 0x00000000 CTI Control Register

Register CTICONTROL Details

Field Name GLBEN Bits 0 Type rw Reset Value 0x0 Description Enables or disables the ECT. When disabled, all cross triggering mapping logic functionality is disabled for this processor.

Register (cti) CTIINTACK

Name CTIINTACK

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Relative Address Absolute Address

0x00000010 debug_cpu_cti0: 0xF8898010 debug_cpu_cti1: 0xF8899010 debug_cti_etb_tpiu: 0xF8802010 debug_cti_ftm: 0xF8809010

Width Access Type Reset Value Description

8 bits wo 0x00000000 CTI Interrupt Acknowledge Register

Register CTIINTACK Details

Field Name INTACK Bits 7:0 Type wo Reset Value 0x0 Description Acknowledges the corresponding CTITRIGOUT output: 1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW. 0 = no effect There is one bit of the register for each CTITRIGOUT output.

Register (cti) CTIAPPSET

Name Relative Address Absolute Address CTIAPPSET 0x00000014 debug_cpu_cti0: 0xF8898014 debug_cpu_cti1: 0xF8899014 debug_cti_etb_tpiu: 0xF8802014 debug_cti_ftm: 0xF8809014 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Application Trigger Set Register

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Register CTIAPPSET Details

Field Name APPSET Bits 3:0 Type rw Reset Value 0x0 Description Setting a bit HIGH generates a channel event for the selected channel. Read: 0 = application trigger inactive (reset) 1 = application trigger active. Write: 0 = no effect 1 = generate channel event. There is one bit of the register for each channel.

Register (cti) CTIAPPCLEAR

Name Relative Address Absolute Address CTIAPPCLEAR 0x00000018 debug_cpu_cti0: 0xF8898018 debug_cpu_cti1: 0xF8899018 debug_cti_etb_tpiu: 0xF8802018 debug_cti_ftm: 0xF8809018 Width Access Type Reset Value Description 4 bits wo 0x00000000 CTI Application Trigger Clear Register

Register CTIAPPCLEAR Details

Field Name APPCLEAR Bits 3:0 Type wo Reset Value 0x0 Description Clears corresponding bits in the CTIAPPSET register. 1 = application trigger disabled in the CTIAPPSET register 0 = no effect. There is one bit of the register for each channel.

Register (cti) CTIAPPPULSE

Name Relative Address CTIAPPPULSE 0x0000001C

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Absolute Address

debug_cpu_cti0: 0xF889801C debug_cpu_cti1: 0xF889901C debug_cti_etb_tpiu: 0xF880201C debug_cti_ftm: 0xF880901C

Width Access Type Reset Value Description

4 bits wo 0x00000000 CTI Application Pulse Register

Register CTIAPPPULSE Details

Field Name APPULSE Bits 3:0 Type wo Reset Value 0x0 Description Setting a bit HIGH generates a channel event pulse for the selected channel. Write: 1 = channel event pulse generated for one CTICLK period 0 = no effect. There is one bit of the register for each channel.

Register (cti) CTIINEN0

Name Relative Address Absolute Address CTIINEN0 0x00000020 debug_cpu_cti0: 0xF8898020 debug_cpu_cti1: 0xF8899020 debug_cti_etb_tpiu: 0xF8802020 debug_cti_ftm: 0xF8809020 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 0 Register

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Register CTIINEN0 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

Register (cti) CTIINEN1

Name Relative Address Absolute Address CTIINEN1 0x00000024 debug_cpu_cti0: 0xF8898024 debug_cpu_cti1: 0xF8899024 debug_cti_etb_tpiu: 0xF8802024 debug_cti_ftm: 0xF8809024 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 1 Register

Register CTIINEN1 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

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Register (cti) CTIINEN2

Name Relative Address Absolute Address CTIINEN2 0x00000028 debug_cpu_cti0: 0xF8898028 debug_cpu_cti1: 0xF8899028 debug_cti_etb_tpiu: 0xF8802028 debug_cti_ftm: 0xF8809028 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 2 Register

Register CTIINEN2 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

Register (cti) CTIINEN3

Name Relative Address Absolute Address CTIINEN3 0x0000002C debug_cpu_cti0: 0xF889802C debug_cpu_cti1: 0xF889902C debug_cti_etb_tpiu: 0xF880202C debug_cti_ftm: 0xF880902C Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 3 Register

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Register CTIINEN3 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

Register (cti) CTIINEN4

Name Relative Address Absolute Address CTIINEN4 0x00000030 debug_cpu_cti0: 0xF8898030 debug_cpu_cti1: 0xF8899030 debug_cti_etb_tpiu: 0xF8802030 debug_cti_ftm: 0xF8809030 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 4 Register

Register CTIINEN4 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

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Register (cti) CTIINEN5

Name Relative Address Absolute Address CTIINEN5 0x00000034 debug_cpu_cti0: 0xF8898034 debug_cpu_cti1: 0xF8899034 debug_cti_etb_tpiu: 0xF8802034 debug_cti_ftm: 0xF8809034 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 5 Register

Register CTIINEN5 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

Register (cti) CTIINEN6

Name Relative Address Absolute Address CTIINEN6 0x00000038 debug_cpu_cti0: 0xF8898038 debug_cpu_cti1: 0xF8899038 debug_cti_etb_tpiu: 0xF8802038 debug_cti_ftm: 0xF8809038 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 6 Register

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Register CTIINEN6 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

Register (cti) CTIINEN7

Name Relative Address Absolute Address CTIINEN7 0x0000003C debug_cpu_cti0: 0xF889803C debug_cpu_cti1: 0xF889903C debug_cti_etb_tpiu: 0xF880203C debug_cti_ftm: 0xF880903C Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Trigger to Channel Enable 7 Register

Register CTIINEN7 Details

Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0. 0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM.

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Register (cti) CTIOUTEN0

Name Relative Address Absolute Address CTIOUTEN0 0x000000A0 debug_cpu_cti0: 0xF88980A0 debug_cpu_cti1: 0xF88990A0 debug_cti_etb_tpiu: 0xF88020A0 debug_cti_ftm: 0xF88090A0 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 0 Register

Register CTIOUTEN0 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTIOUTEN1

Name Relative Address Absolute Address CTIOUTEN1 0x000000A4 debug_cpu_cti0: 0xF88980A4 debug_cpu_cti1: 0xF88990A4 debug_cti_etb_tpiu: 0xF88020A4 debug_cti_ftm: 0xF88090A4 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 1 Register

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Register CTIOUTEN1 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTIOUTEN2

Name Relative Address Absolute Address CTIOUTEN2 0x000000A8 debug_cpu_cti0: 0xF88980A8 debug_cpu_cti1: 0xF88990A8 debug_cti_etb_tpiu: 0xF88020A8 debug_cti_ftm: 0xF88090A8 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 2 Register

Register CTIOUTEN2 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

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Register (cti) CTIOUTEN3

Name Relative Address Absolute Address CTIOUTEN3 0x000000AC debug_cpu_cti0: 0xF88980AC debug_cpu_cti1: 0xF88990AC debug_cti_etb_tpiu: 0xF88020AC debug_cti_ftm: 0xF88090AC Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 3 Register

Register CTIOUTEN3 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTIOUTEN4

Name Relative Address Absolute Address CTIOUTEN4 0x000000B0 debug_cpu_cti0: 0xF88980B0 debug_cpu_cti1: 0xF88990B0 debug_cti_etb_tpiu: 0xF88020B0 debug_cti_ftm: 0xF88090B0 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 4 Register

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Register CTIOUTEN4 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTIOUTEN5

Name Relative Address Absolute Address CTIOUTEN5 0x000000B4 debug_cpu_cti0: 0xF88980B4 debug_cpu_cti1: 0xF88990B4 debug_cti_etb_tpiu: 0xF88020B4 debug_cti_ftm: 0xF88090B4 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 5 Register

Register CTIOUTEN5 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

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Register (cti) CTIOUTEN6

Name Relative Address Absolute Address CTIOUTEN6 0x000000B8 debug_cpu_cti0: 0xF88980B8 debug_cpu_cti1: 0xF88990B8 debug_cti_etb_tpiu: 0xF88020B8 debug_cti_ftm: 0xF88090B8 Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 6 Register

Register CTIOUTEN6 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTIOUTEN7

Name Relative Address Absolute Address CTIOUTEN7 0x000000BC debug_cpu_cti0: 0xF88980BC debug_cpu_cti1: 0xF88990BC debug_cti_etb_tpiu: 0xF88020BC debug_cti_ftm: 0xF88090BC Width Access Type Reset Value Description 4 bits rw 0x00000000 CTI Channel to Trigger Enable 7 Register

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Register CTIOUTEN7 Details

Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels. For example in register CTIOUTEN0, enabling bit 0 enables CTICHIN[0] to cause a trigger event on the CTITRIGOUT[0] output.

Register (cti) CTITRIGINSTATUS

Name Relative Address Absolute Address CTITRIGINSTATUS 0x00000130 debug_cpu_cti0: 0xF8898130 debug_cpu_cti1: 0xF8899130 debug_cti_etb_tpiu: 0xF8802130 debug_cti_ftm: 0xF8809130 Width Access Type Reset Value Description 8 bits ro x CTI Trigger In Status Register

Register CTITRIGINSTATUS Details

Field Name TRIGINSTATUS Bits 7:0 Type ro Reset Value x Description Shows the status of the CTITRIGIN inputs: 1 = CTITRIGIN is active 0 = CTITRIGIN is inactive. Because the register provides a view of the raw CTITRIGIN inputs, the reset value is unknown. There is one bit of the register for each trigger input.

Register (cti) CTITRIGOUTSTATUS

Name Relative Address CTITRIGOUTSTATUS 0x00000134

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Absolute Address

debug_cpu_cti0: 0xF8898134 debug_cpu_cti1: 0xF8899134 debug_cti_etb_tpiu: 0xF8802134 debug_cti_ftm: 0xF8809134

Width Access Type Reset Value Description

8 bits ro 0x00000000 CTI Trigger Out Status Register

Register CTITRIGOUTSTATUS Details

Field Name TRIGOUTSTATUS Bits 7:0 Type ro Reset Value 0x0 Description Shows the status of the CTITRIGOUT outputs. 1 = CTITRIGOUT is active 0 = CTITRIGOUT is inactive (reset). There is one bit of the register for each trigger output.

Register (cti) CTICHINSTATUS

Name Relative Address Absolute Address CTICHINSTATUS 0x00000138 debug_cpu_cti0: 0xF8898138 debug_cpu_cti1: 0xF8899138 debug_cti_etb_tpiu: 0xF8802138 debug_cti_ftm: 0xF8809138 Width Access Type Reset Value Description 4 bits ro x CTI Channel In Status Register

Register CTICHINSTATUS Details

Field Name CTCHINSTATUS Bits 3:0 Type ro Reset Value x Description Shows the status of the CTICHIN inputs: 1 = CTICHIN is active 0 = CTICHIN is inactive. Because the register provides a view of the raw CTICHIN inputs from the CTM, the reset value is unknown. There is one bit of the register for each channel input.

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Register (cti) CTICHOUTSTATUS

Name Relative Address Absolute Address CTICHOUTSTATUS 0x0000013C debug_cpu_cti0: 0xF889813C debug_cpu_cti1: 0xF889913C debug_cti_etb_tpiu: 0xF880213C debug_cti_ftm: 0xF880913C Width Access Type Reset Value Description 4 bits ro 0x00000000 CTI Channel Out Status Register

Register CTICHOUTSTATUS Details

Field Name CTCHOUTSTATUS Bits 3:0 Type ro Reset Value 0x0 Description Shows the status of the CTICHOUT outputs. 1 = CTICHOUT is active 0 = CTICHOUT is inactive (reset). There is one bit of the register for each channel output.

Register (cti) CTIGATE

Name Relative Address Absolute Address CTIGATE 0x00000140 debug_cpu_cti0: 0xF8898140 debug_cpu_cti1: 0xF8899140 debug_cti_etb_tpiu: 0xF8802140 debug_cti_ftm: 0xF8809140 Width Access Type Reset Value Description 4 bits rw 0x0000000F Enable CTI Channel Gate Register

Register CTIGATE Details

Field Name CTIGATEEN3 CTIGATEEN2 Bits 3 2 Type rw rw Reset Value 0x1 0x1 Description Enable CTICHOUT3. Enable CTICHOUT2.

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Appendix B: Register Details

Field Name CTIGATEEN1 CTIGATEEN0

Bits 1 0

Type rw rw

Reset Value 0x1 0x1

Description Enable CTICHOUT1. Enable CTICHOUT0.

Register (cti) ASICCTL

Name Relative Address Absolute Address ASICCTL 0x00000144 debug_cpu_cti0: 0xF8898144 debug_cpu_cti1: 0xF8899144 debug_cti_etb_tpiu: 0xF8802144 debug_cti_ftm: 0xF8809144 Width Access Type Reset Value Description 8 bits rw 0x00000000 External Multiplexor Control Register

Register ASICCTL Details

Field Name ASICCTL Bits 7:0 Type rw Reset Value 0x0 Description Implementation defined ASIC control, value written to the register is output on ASICCTL[7:0].

Register (cti) ITCHINACK

Name Relative Address Absolute Address ITCHINACK 0x00000EDC debug_cpu_cti0: 0xF8898EDC debug_cpu_cti1: 0xF8899EDC debug_cti_etb_tpiu: 0xF8802EDC debug_cti_ftm: 0xF8809EDC Width Access Type Reset Value Description 4 bits wo 0x00000000 ITCHINACK Register

Register ITCHINACK Details

Field Name CTCHINACK Bits 3:0 Type wo Reset Value 0x0 Description Set the value of the CTCHINACK outputs

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Register (cti) ITTRIGINACK

Name Relative Address Absolute Address ITTRIGINACK 0x00000EE0 debug_cpu_cti0: 0xF8898EE0 debug_cpu_cti1: 0xF8899EE0 debug_cti_etb_tpiu: 0xF8802EE0 debug_cti_ftm: 0xF8809EE0 Width Access Type Reset Value Description 8 bits wo 0x00000000 ITTRIGINACK Register

Register ITTRIGINACK Details

Field Name CTTRIGINACK Bits 7:0 Type wo Reset Value 0x0 Description Set the value of the CTTRIGINACK outputs

Register (cti) ITCHOUT

Name Relative Address Absolute Address ITCHOUT 0x00000EE4 debug_cpu_cti0: 0xF8898EE4 debug_cpu_cti1: 0xF8899EE4 debug_cti_etb_tpiu: 0xF8802EE4 debug_cti_ftm: 0xF8809EE4 Width Access Type Reset Value Description 4 bits wo 0x00000000 ITCHOUT Register

Register ITCHOUT Details

Field Name CTCHOUT Bits 3:0 Type wo Reset Value 0x0 Description Set the value of the CTCHOUT outputs

Register (cti) ITTRIGOUT

Name Relative Address ITTRIGOUT 0x00000EE8

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Appendix B: Register Details

Absolute Address

debug_cpu_cti0: 0xF8898EE8 debug_cpu_cti1: 0xF8899EE8 debug_cti_etb_tpiu: 0xF8802EE8 debug_cti_ftm: 0xF8809EE8

Width Access Type Reset Value Description

8 bits wo 0x00000000 ITTRIGOUT Register

Register ITTRIGOUT Details

Field Name CTTRIGOUT Bits 7:0 Type wo Reset Value 0x0 Description Set the value of the CTTRIGOUT outputs

Register (cti) ITCHOUTACK

Name Relative Address Absolute Address ITCHOUTACK 0x00000EEC debug_cpu_cti0: 0xF8898EEC debug_cpu_cti1: 0xF8899EEC debug_cti_etb_tpiu: 0xF8802EEC debug_cti_ftm: 0xF8809EEC Width Access Type Reset Value Description 4 bits ro 0x00000000 ITCHOUTACK Register

Register ITCHOUTACK Details

Field Name CTCHOUTACK Bits 3:0 Type ro Reset Value 0x0 Description Read the values of the CTCHOUTACK inputs

Register (cti) ITTRIGOUTACK

Name Relative Address Absolute Address ITTRIGOUTACK 0x00000EF0 debug_cpu_cti0: 0xF8898EF0 debug_cpu_cti1: 0xF8899EF0 debug_cti_etb_tpiu: 0xF8802EF0 debug_cti_ftm: 0xF8809EF0

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Width Access Type Reset Value Description

8 bits ro 0x00000000 ITTRIGOUTACK Register

Register ITTRIGOUTACK Details

Field Name CTTRIGOUTACK Bits 7:0 Type ro Reset Value 0x0 Description Read the values of the CTTRIGOUTACK inputs

Register (cti) ITCHIN

Name Relative Address Absolute Address ITCHIN 0x00000EF4 debug_cpu_cti0: 0xF8898EF4 debug_cpu_cti1: 0xF8899EF4 debug_cti_etb_tpiu: 0xF8802EF4 debug_cti_ftm: 0xF8809EF4 Width Access Type Reset Value Description 4 bits ro 0x00000000 ITCHIN Register

Register ITCHIN Details

Field Name CTCHIN Bits 3:0 Type ro Reset Value 0x0 Description Read the values of the CTCHIN inputs

Register (cti) ITTRIGIN

Name Relative Address Absolute Address ITTRIGIN 0x00000EF8 debug_cpu_cti0: 0xF8898EF8 debug_cpu_cti1: 0xF8899EF8 debug_cti_etb_tpiu: 0xF8802EF8 debug_cti_ftm: 0xF8809EF8 Width Access Type Reset Value 8 bits ro 0x00000000

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Appendix B: Register Details

Description

ITTRIGIN Register

Register ITTRIGIN Details

Field Name CTTRIGIN Bits 7:0 Type ro Reset Value 0x0 Description Read the values of the CTTRIGIN inputs

Register (cti) ITCTRL

Name Relative Address Absolute Address ITCTRL 0x00000F00 debug_cpu_cti0: 0xF8898F00 debug_cpu_cti1: 0xF8899F00 debug_cti_etb_tpiu: 0xF8802F00 debug_cti_ftm: 0xF8809F00 Width Access Type Reset Value Description 1 bits rw 0x00000000 IT Control Register

Register ITCTRL Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable IT Registers

Register (cti) CTSR

Name Relative Address Absolute Address CTSR 0x00000FA0 debug_cpu_cti0: 0xF8898FA0 debug_cpu_cti1: 0xF8899FA0 debug_cti_etb_tpiu: 0xF8802FA0 debug_cti_ftm: 0xF8809FA0 Width Access Type Reset Value Description 4 bits rw 0x0000000F Claim Tag Set Register

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Appendix B: Register Details

Register CTSR Details

Field Name SET Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (cti) CTCR

Name Relative Address Absolute Address CTCR 0x00000FA4 debug_cpu_cti0: 0xF8898FA4 debug_cpu_cti1: 0xF8899FA4 debug_cti_etb_tpiu: 0xF8802FA4 debug_cti_ftm: 0xF8809FA4 Width Access Type Reset Value Description 4 bits rw 0x00000000 Claim Tag Clear Register

Register CTCR Details

Field Name CLEAR Bits 3:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

Register (cti) LAR

Name Relative Address Absolute Address LAR 0x00000FB0 debug_cpu_cti0: 0xF8898FB0 debug_cpu_cti1: 0xF8899FB0 debug_cti_etb_tpiu: 0xF8802FB0 debug_cti_ftm: 0xF8809FB0

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Appendix B: Register Details

Width Access Type Reset Value Description

32 bits wo 0x00000000 Lock Access Register

Register LAR Details

Field Name KEY Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

Register (cti) LSR

Name Relative Address Absolute Address LSR 0x00000FB4 debug_cpu_cti0: 0xF8898FB4 debug_cpu_cti1: 0xF8899FB4 debug_cti_etb_tpiu: 0xF8802FB4 debug_cti_ftm: 0xF8809FB4 Width Access Type Reset Value Description 3 bits ro 0x00000003 Lock Status Register

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Appendix B: Register Details

Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since CTI implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (cti) ASR

Name Relative Address Absolute Address ASR 0x00000FB8 debug_cpu_cti0: 0xF8898FB8 debug_cpu_cti1: 0xF8899FB8 debug_cti_etb_tpiu: 0xF8802FB8 debug_cti_ftm: 0xF8809FB8 Width Access Type Reset Value Description 4 bits ro x Authentication Status Register

Register ASR Details

Field Name NIDEN NIDEN_CTL IDEN IDEN_CTL Bits 3 2 1 0 Type ro ro ro ro Reset Value x 0x1 x 0x1 Description Current value of noninvasive debug enable signals Non-invasive debug controlled Current value of invasive debug enable signals Invasive debug controlled

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Appendix B: Register Details

Register (cti) DEVID

Name Relative Address Absolute Address DEVID 0x00000FC8 debug_cpu_cti0: 0xF8898FC8 debug_cpu_cti1: 0xF8899FC8 debug_cti_etb_tpiu: 0xF8802FC8 debug_cti_ftm: 0xF8809FC8 Width Access Type Reset Value Description 20 bits ro 0x00040800 Device ID

Register DEVID Details

Field Name NumChan NumTrig res ExtMux Bits 19:16 15:8 7:5 4:0 Type ro ro ro ro Reset Value 0x4 0x8 0x0 0x0 Description Number of channels available Number of triggers available reserved no external muxing

Register (cti) DTIR

Name Relative Address Absolute Address DTIR 0x00000FCC debug_cpu_cti0: 0xF8898FCC debug_cpu_cti1: 0xF8899FCC debug_cti_etb_tpiu: 0xF8802FCC debug_cti_ftm: 0xF8809FCC Width Access Type Reset Value Description 8 bits ro 0x00000014 Device Type Identifier Register

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x14 Description major type is a debug control logic component, sub-type is cross trigger

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Appendix B: Register Details

Register (cti) PERIPHID4

Name Relative Address Absolute Address PERIPHID4 0x00000FD0 debug_cpu_cti0: 0xF8898FD0 debug_cpu_cti1: 0xF8899FD0 debug_cti_etb_tpiu: 0xF8802FD0 debug_cti_ftm: 0xF8809FD0 Width Access Type Reset Value Description 8 bits ro 0x00000004 Peripheral ID4

Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (cti) PERIPHID5

Name Relative Address Absolute Address PERIPHID5 0x00000FD4 debug_cpu_cti0: 0xF8898FD4 debug_cpu_cti1: 0xF8899FD4 debug_cti_etb_tpiu: 0xF8802FD4 debug_cti_ftm: 0xF8809FD4 Width Access Type Reset Value Description 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (cti) PERIPHID6

Name PERIPHID6

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Relative Address Absolute Address

0x00000FD8 debug_cpu_cti0: 0xF8898FD8 debug_cpu_cti1: 0xF8899FD8 debug_cti_etb_tpiu: 0xF8802FD8 debug_cti_ftm: 0xF8809FD8

Width Access Type Reset Value Description

8 bits ro 0x00000000 Peripheral ID6

Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (cti) PERIPHID7

Name Relative Address Absolute Address PERIPHID7 0x00000FDC debug_cpu_cti0: 0xF8898FDC debug_cpu_cti1: 0xF8899FDC debug_cti_etb_tpiu: 0xF8802FDC debug_cti_ftm: 0xF8809FDC Width Access Type Reset Value Description 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (cti) PERIPHID0

Name Relative Address PERIPHID0 0x00000FE0

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Appendix B: Register Details

Absolute Address

debug_cpu_cti0: 0xF8898FE0 debug_cpu_cti1: 0xF8899FE0 debug_cti_etb_tpiu: 0xF8802FE0 debug_cti_ftm: 0xF8809FE0

Width Access Type Reset Value Description

8 bits ro 0x00000006 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x6 PartNumber0 Description

Register (cti) PERIPHID1

Name Relative Address Absolute Address PERIPHID1 0x00000FE4 debug_cpu_cti0: 0xF8898FE4 debug_cpu_cti1: 0xF8899FE4 debug_cti_etb_tpiu: 0xF8802FE4 debug_cti_ftm: 0xF8809FE4 Width Access Type Reset Value Description 8 bits ro 0x000000B9 Peripheral ID1

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (cti) PERIPHID2

Name Relative Address PERIPHID2 0x00000FE8

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Appendix B: Register Details

Absolute Address

debug_cpu_cti0: 0xF8898FE8 debug_cpu_cti1: 0xF8899FE8 debug_cti_etb_tpiu: 0xF8802FE8 debug_cti_ftm: 0xF8809FE8

Width Access Type Reset Value Description

8 bits ro 0x0000002B Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x2 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (cti) PERIPHID3

Name Relative Address Absolute Address PERIPHID3 0x00000FEC debug_cpu_cti0: 0xF8898FEC debug_cpu_cti1: 0xF8899FEC debug_cti_etb_tpiu: 0xF8802FEC debug_cti_ftm: 0xF8809FEC Width Access Type Reset Value Description 8 bits ro 0x00000000 Peripheral ID3

Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

Register (cti) COMPID0

Name Relative Address COMPID0 0x00000FF0

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Appendix B: Register Details

Absolute Address

debug_cpu_cti0: 0xF8898FF0 debug_cpu_cti1: 0xF8899FF0 debug_cti_etb_tpiu: 0xF8802FF0 debug_cti_ftm: 0xF8809FF0

Width Access Type Reset Value Description

8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (cti) COMPID1

Name Relative Address Absolute Address COMPID1 0x00000FF4 debug_cpu_cti0: 0xF8898FF4 debug_cpu_cti1: 0xF8899FF4 debug_cti_etb_tpiu: 0xF8802FF4 debug_cti_ftm: 0xF8809FF4 Width Access Type Reset Value Description 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (cti) COMPID2

Name Relative Address Absolute Address COMPID2 0x00000FF8 debug_cpu_cti0: 0xF8898FF8 debug_cpu_cti1: 0xF8899FF8 debug_cti_etb_tpiu: 0xF8802FF8 debug_cti_ftm: 0xF8809FF8

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Width Access Type Reset Value Description

8 bits ro 0x00000005 Component ID2

Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (cti) COMPID3

Name Relative Address Absolute Address COMPID3 0x00000FFC debug_cpu_cti0: 0xF8898FFC debug_cpu_cti1: 0xF8899FFC debug_cti_etb_tpiu: 0xF8802FFC debug_cti_ftm: 0xF8809FFC Width Access Type Reset Value Description 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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Appendix B: Register Details

B.8 Performance Monitor Unit (cortexa9_pmu)

Module Name Base Address Description Vendor Info Performance Monitor Unit (cortexa9_pmu) 0xF8891000 debug_cpu_pmu0 0xF8893000 debug_cpu_pmu1 Cortex A9 Performance Monitoring Unit ARM

Register Summary
Register Name PMXEVCNTR0 PMXEVCNTR1 PMXEVCNTR2 PMXEVCNTR3 PMXEVCNTR4 PMXEVCNTR5 PMCCNTR PMXEVTYPER0 PMXEVTYPER1 PMXEVTYPER2 PMXEVTYPER3 PMXEVTYPER4 PMXEVTYPER5 PMCNTENSET PMCNTENCLR PMINTENSET PMINTENCLR PMOVSR PMSWINC PMCR PMUSERENR Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x0000007C 0x00000400 0x00000404 0x00000408 0x0000040C 0x00000410 0x00000414 0x00000C00 0x00000C20 0x00000C40 0x00000C60 0x00000C80 0x00000CA0 0x00000E04 0x00000E08 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw wo rw rw Reset Value x x x x x x x x x x x x x 0x00000000 0x00000000 0x00000000 0x00000000 x x 0x41093000 0x00000000 Description PMU event counter 0 PMU event counter 1 PMU event counter 2 PMU event counter 3 PMU event counter 4 PMU event counter 5 pmccntr pmevtyper0 pmevtyper1 pmevtyper2 pmevtyper3 pmevtyper4 pmevtyper5 pmcntenset pmcntenclr pmintenset pmintenclr pmovsr pmswinc pmcr pmuserenr

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Register (cortexa9_pmu) PMXEVCNTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVCNTR0 0x00000000 debug_cpu_pmu0: 0xF8891000 debug_cpu_pmu1: 0xF8893000 32 bits rw x PMU event counter 0

Register PMXEVCNTR0 Details

Field Name PMXEVCNTR0 Bits 31:0 Type rw Reset Value x Description PMU event counter 0

Register (cortexa9_pmu) PMXEVCNTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVCNTR1 0x00000004 debug_cpu_pmu0: 0xF8891004 debug_cpu_pmu1: 0xF8893004 32 bits rw x PMU event counter 1

Register PMXEVCNTR1 Details

Field Name PMXEVCNTR1 Bits 31:0 Type rw Reset Value x Description PMU event counter 1

Register (cortexa9_pmu) PMXEVCNTR2

Name Relative Address Absolute Address Width PMXEVCNTR2 0x00000008 debug_cpu_pmu0: 0xF8891008 debug_cpu_pmu1: 0xF8893008 32 bits

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Access Type Reset Value Description

rw x PMU event counter 2

Register PMXEVCNTR2 Details

Field Name PMXEVCNTR2 Bits 31:0 Type rw Reset Value x Description PMU event counter 2

Register (cortexa9_pmu) PMXEVCNTR3

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVCNTR3 0x0000000C debug_cpu_pmu0: 0xF889100C debug_cpu_pmu1: 0xF889300C 32 bits rw x PMU event counter 3

Register PMXEVCNTR3 Details

Field Name PMXEVCNTR3 Bits 31:0 Type rw Reset Value x Description PMU event counter 3

Register (cortexa9_pmu) PMXEVCNTR4

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVCNTR4 0x00000010 debug_cpu_pmu0: 0xF8891010 debug_cpu_pmu1: 0xF8893010 32 bits rw x PMU event counter 4

Register PMXEVCNTR4 Details

Field Name PMXEVCNTR4 Bits 31:0 Type rw Reset Value x Description PMU event counter 4

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Register (cortexa9_pmu) PMXEVCNTR5

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVCNTR5 0x00000014 debug_cpu_pmu0: 0xF8891014 debug_cpu_pmu1: 0xF8893014 32 bits rw x PMU event counter 5

Register PMXEVCNTR5 Details

Field Name PMXEVCNTR5 Bits 31:0 Type rw Reset Value x Description PMU event counter 5

Register (cortexa9_pmu) PMCCNTR

Name Relative Address Absolute Address Width Access Type Reset Value Description PMCCNTR 0x0000007C debug_cpu_pmu0: 0xF889107C debug_cpu_pmu1: 0xF889307C 32 bits rw x pmccntr

Register PMCCNTR Details

Field Name PMCCNTR Bits 31:0 Type rw Reset Value x pmccntr Description

Register (cortexa9_pmu) PMXEVTYPER0

Name Relative Address Absolute Address Width PMXEVTYPER0 0x00000400 debug_cpu_pmu0: 0xF8891400 debug_cpu_pmu1: 0xF8893400 32 bits

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Access Type Reset Value Description

rw x pmevtyper0

Register PMXEVTYPER0 Details

Field Name PMXEVTYPER0 Bits 31:0 Type rw Reset Value x pmevtyper0 Description

Register (cortexa9_pmu) PMXEVTYPER1

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVTYPER1 0x00000404 debug_cpu_pmu0: 0xF8891404 debug_cpu_pmu1: 0xF8893404 32 bits rw x pmevtyper1

Register PMXEVTYPER1 Details

Field Name PMXEVTYPER1 Bits 31:0 Type rw Reset Value x pmevtyper1 Description

Register (cortexa9_pmu) PMXEVTYPER2

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVTYPER2 0x00000408 debug_cpu_pmu0: 0xF8891408 debug_cpu_pmu1: 0xF8893408 32 bits rw x pmevtyper2

Register PMXEVTYPER2 Details

Field Name PMXEVTYPER2 Bits 31:0 Type rw Reset Value x pmevtyper2 Description

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Register (cortexa9_pmu) PMXEVTYPER3

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVTYPER3 0x0000040C debug_cpu_pmu0: 0xF889140C debug_cpu_pmu1: 0xF889340C 32 bits rw x pmevtyper3

Register PMXEVTYPER3 Details

Field Name PMXEVTYPER3 Bits 31:0 Type rw Reset Value x pmevtyper3 Description

Register (cortexa9_pmu) PMXEVTYPER4

Name Relative Address Absolute Address Width Access Type Reset Value Description PMXEVTYPER4 0x00000410 debug_cpu_pmu0: 0xF8891410 debug_cpu_pmu1: 0xF8893410 32 bits rw x pmevtyper4

Register PMXEVTYPER4 Details

Field Name PMXEVTYPER4 Bits 31:0 Type rw Reset Value x pmevtyper4 Description

Register (cortexa9_pmu) PMXEVTYPER5

Name Relative Address Absolute Address Width PMXEVTYPER5 0x00000414 debug_cpu_pmu0: 0xF8891414 debug_cpu_pmu1: 0xF8893414 32 bits

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Access Type Reset Value Description

rw x pmevtyper5

Register PMXEVTYPER5 Details

Field Name PMXEVTYPER5 Bits 31:0 Type rw Reset Value x pmevtyper5 Description

Register (cortexa9_pmu) PMCNTENSET

Name Relative Address Absolute Address Width Access Type Reset Value Description PMCNTENSET 0x00000C00 debug_cpu_pmu0: 0xF8891C00 debug_cpu_pmu1: 0xF8893C00 32 bits rw 0x00000000 pmcntenset

Register PMCNTENSET Details

Field Name PMCNTENSET Bits 31:0 Type rw Reset Value 0x0 pmcntenset Description

Register (cortexa9_pmu) PMCNTENCLR

Name Relative Address Absolute Address Width Access Type Reset Value Description PMCNTENCLR 0x00000C20 debug_cpu_pmu0: 0xF8891C20 debug_cpu_pmu1: 0xF8893C20 32 bits rw 0x00000000 pmcntenclr

Register PMCNTENCLR Details

Field Name PMCNTENCLR Bits 31:0 Type rw Reset Value 0x0 pmcntenclr Description

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Register (cortexa9_pmu) PMINTENSET

Name Relative Address Absolute Address Width Access Type Reset Value Description PMINTENSET 0x00000C40 debug_cpu_pmu0: 0xF8891C40 debug_cpu_pmu1: 0xF8893C40 32 bits rw 0x00000000 pmintenset

Register PMINTENSET Details

Field Name PMINTENSET Bits 31:0 Type rw Reset Value 0x0 pmintenset Description

Register (cortexa9_pmu) PMINTENCLR

Name Relative Address Absolute Address Width Access Type Reset Value Description PMINTENCLR 0x00000C60 debug_cpu_pmu0: 0xF8891C60 debug_cpu_pmu1: 0xF8893C60 32 bits rw 0x00000000 pmintenclr

Register PMINTENCLR Details

Field Name PMINTENCLR Bits 31:0 Type rw Reset Value 0x0 pmintenclr Description

Register (cortexa9_pmu) PMOVSR

Name Relative Address Absolute Address Width PMOVSR 0x00000C80 debug_cpu_pmu0: 0xF8891C80 debug_cpu_pmu1: 0xF8893C80 32 bits

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Access Type Reset Value Description

rw x pmovsr

Register PMOVSR Details

Field Name PMOVSR Bits 31:0 Type rw Reset Value x pmovsr Description

Register (cortexa9_pmu) PMSWINC

Name Relative Address Absolute Address Width Access Type Reset Value Description PMSWINC 0x00000CA0 debug_cpu_pmu0: 0xF8891CA0 debug_cpu_pmu1: 0xF8893CA0 32 bits wo x pmswinc

Register PMSWINC Details

Field Name PMSWINC Bits 31:0 Type wo Reset Value x pmswinc Description

Register (cortexa9_pmu) PMCR

Name Relative Address Absolute Address Width Access Type Reset Value Description PMCR 0x00000E04 debug_cpu_pmu0: 0xF8891E04 debug_cpu_pmu1: 0xF8893E04 32 bits rw 0x41093000 pmcr

Register PMCR Details

Field Name PMCR Bits 31:0 Type rw Reset Value 0x41093000 pmcr Description

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Register (cortexa9_pmu) PMUSERENR

Name Relative Address Absolute Address Width Access Type Reset Value Description PMUSERENR 0x00000E08 debug_cpu_pmu0: 0xF8891E08 debug_cpu_pmu1: 0xF8893E08 32 bits rw 0x00000000 pmuserenr

Register PMUSERENR Details

Field Name PMUSERENR Bits 31:0 Type rw Reset Value 0x0 pmuserenr This register is read-only in user mode. Description

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B.9 CoreSight Program Trace Macrocell (ptm)

Module Name Base Address Description Vendor Info CoreSight Program Trace Macrocell (ptm) 0xF889C000 debug_cpu_ptm0 0xF889D000 debug_cpu_ptm1 CoreSight PTM-A9

Register Summary
Register Name ETMCR ETMCCR ETMTRIGGER ETMSR ETMSCR ETMTSSCR ETMTECR1 ETMACVR1 ETMACVR2 ETMACVR3 ETMACVR4 ETMACVR5 ETMACVR6 ETMACVR7 ETMACVR8 ETMACTR1 ETMACTR2 Address 0x00000000 0x00000004 0x00000008 0x00000010 0x00000014 0x00000018 0x00000024 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000050 0x00000054 0x00000058 0x0000005C 0x00000080 0x00000084 Width 30 32 17 4 15 24 26 32 32 32 32 32 32 32 32 12 12 Type rw ro rw mixed ro rw rw rw rw rw rw rw rw rw rw mixed mixed Reset Value 0x00000400 0x8D294004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 Description Main Control Register Configuration Code Register Trigger Event Register Status Register System Configuration Register TraceEnable Start/Stop Control Register TraceEnable Control Register 1 Address Comparator Value Register 1 Address Comparator Value Register 2 Address Comparator Value Register 3 Address Comparator Value Register 4 Address Comparator Value Register 5 Address Comparator Value Register 6 Address Comparator Value Register 7 Address Comparator Value Register 8 Address Comparator Access Type Register 1 Address Comparator Access Type Register 2

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Register Name ETMACTR3 ETMACTR4 ETMACTR5 ETMACTR6 ETMACTR7 ETMACTR8 ETMCNTRLDVR1 ETMCNTRLDVR2 ETMCNTENR1 ETMCNTENR2 ETMCNTRLDEVR1 ETMCNTRLDEVR2 ETMCNTVR1 ETMCNTVR2 ETMSQ12EVR ETMSQ21EVR ETMSQ23EVR ETMSQ31EVR ETMSQ32EVR ETMSQ13EVR ETMSQR ETMEXTOUTEVR1 ETMEXTOUTEVR2 ETMCIDCVR1

Address 0x00000088 0x0000008C 0x00000090 0x00000094 0x00000098 0x0000009C 0x00000140 0x00000144 0x00000150 0x00000154 0x00000160 0x00000164 0x00000170 0x00000174 0x00000180 0x00000184 0x00000188 0x0000018C 0x00000190 0x00000194 0x0000019C 0x000001A0 0x000001A4 0x000001B0

Width 12 12 12 12 12 12 16 16 18 18 17 17 16 16 17 17 17 17 17 17 2 17 17 32

Type mixed mixed mixed mixed mixed mixed rw rw mixed mixed rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000000 0x00000000 0x00020000 0x00020000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description Address Comparator Access Type Register 3 Address Comparator Access Type Register 4 Address Comparator Access Type Register 5 Address Comparator Access Type Register 6 Address Comparator Access Type Register 7 Address Comparator Access Type Register 8 Counter Reload Value Register 1 Counter Reload Value Register 2 Counter Enable Event Register 1 Counter Enable Event Register 2 Counter Reload Event Register 1 Counter Reload Event Register 2 Counter Value Register 1 Counter Value Register 2 Sequencer State Transition Event Register 12 Sequencer State Transition Event Register 21 Sequencer State Transition Event Register 23 Sequencer State Transition Event Register 31 Sequencer State Transition Event Register 32 Sequencer State Transition Event Register 13 Current Sequencer State Register External Output Event Register 1 External Output Event Register 2 Context ID Comparator Value Register

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Register Name ETMCIDCMR ETMSYNCFR ETMIDR ETMCCER ETMEXTINSELR ETMAUXCR ETMTRACEIDR OSLSR ETMPDSR ITMISCOUT ITMISCIN ITTRIGGER ITATBDATA0 ITATBCTR2 ITATBID ITATBCTR0 ETMITCTRL CTSR CTCR LAR LSR ASR DEVID DTIR PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1

Address 0x000001BC 0x000001E0 0x000001E4 0x000001E8 0x000001EC 0x000001FC 0x00000200 0x00000304 0x00000314 0x00000EDC 0x00000EE0 0x00000EE8 0x00000EEC 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4

Width 32 12 32 26 14 4 7 32 32 10 7 1 5 2 7 10 1 8 8 32 3 8 32 8 8 8 8 8 8 8

Type rw mixed ro ro rw rw rw ro ro wo ro wo wo ro wo wo rw rw rw wo ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000000 0x00000400 0x411CF300 0x00C019A2 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000000 x 0x00000000 0x00000000 x 0x00000000 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x00000003 x 0x00000000 0x00000013 0x00000004 0x00000000 0x00000000 0x00000000 0x00000050 0x000000B9

Description Context ID Comparator Mask Register Synchronization Frequency Register ID Register Configuration Code Extension Register Extended External Input Selection Register Auxiliary Control Register CoreSight Trace ID Register OS Lock Status Register Device Powerdown Status Register Miscellaneous Outputs Register Miscellaneous Inputs Register Trigger Register ATB Data 0 Register ATB Control 2 Register ATB Identification Register ATB Control 0 Register Integration Mode Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID Device Type Identifier Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1

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Appendix B: Register Details

Register Name PERIPHID2 PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 8 8 8 8 8 8

Type ro ro ro ro ro ro

Reset Value 0x0000001B 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (ptm) ETMCR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCR 0x00000000 debug_cpu_ptm0: 0xF889C000 debug_cpu_ptm1: 0xF889D000 30 bits rw 0x00000400 Main Control Register

Register ETMCR Details

Field Name ReturnStackEn TimestampEn ProcSelect reserved ContexIDSize Bits 29 28 27:25 24:16 15:14 Type rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 Description Return stack enable Timestamp enable Select for external multiplexor if PTM is shared between multiple processors. Reserved Context ID Size Enumerated Value List: NONE=0. 8BIT=1. 16BIT=2. 32BIT=3. reserved CycleAccurate reserved ProgBit 13 12 11 10 rw rw rw rw 0x0 0x0 0x0 0x1 Reserved Enables cycle counting Reserved This bit must be set to b1 when the PTM is being programmed.

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Appendix B: Register Details

Field Name DebugReqCtrl

Bits 9

Type rw

Reset Value 0x0

Description Debug Request Control When set to b1 and the trigger event occurs, the PTMDBGRQ output is asserted until PTMDBGACK is observed. This enables a debugger to force the processor into Debug state.

BranchOutput reserved PowerDown

8 7:1 0

rw rw rw

0x0 0x0 0x0

When this bit is set to b1, addresses are output for all executed branches, both direct and indirect. Reserved This bit enables external control of the PTM. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to b0, both the PTM and the trace interface in the processor are enabled. To avoid corruption of trace data, this bit must not be set before the Programming Status bit in the PTM Status Register has been read as 1.

Register (ptm) ETMCCR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCCR 0x00000004 debug_cpu_ptm0: 0xF889C004 debug_cpu_ptm1: 0xF889D004 32 bits ro 0x8D294004 Configuration Code Register

Register ETMCCR Details

Field Name IDRegPresent reserved SoftwareAccess TraceSSB NumCntxtIDComp FIFOFULLLogic NumExtOut Bits 31 30:28 27 26 25:24 23 22:20 Type ro ro ro ro ro ro ro Reset Value 0x1 0x0 0x1 0x1 0x1 0x0 0x2 Description Indicates that the ID Register is present. Reserved Indicates that software access is supported. Indicates that the trace start/stop block is present. Specifies the number of Context ID comparators, one. Indicates that it is not possible to stall the processor to prevent FIFO overflow. Specifies the number of external outputs, two.

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Appendix B: Register Details

Field Name NumExtIn Sequencer NumCounters reserved NumAddrComp

Bits 19:17 16 15:13 12:4 3:0

Type ro ro ro ro ro

Reset Value 0x4 0x1 0x2 0x0 0x4

Description Specifies the number of external inputs, four. Indicates that the sequencer is present. Specifies the number of counters, two. Reserved Specifies the number of address comparator pairs, four.

Register (ptm) ETMTRIGGER

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMTRIGGER 0x00000008 debug_cpu_ptm0: 0xF889C008 debug_cpu_ptm1: 0xF889D008 17 bits rw 0x00000000 Trigger Event Register

Register ETMTRIGGER Details

Field Name TrigEvent Bits 16:0 Type rw Reset Value 0x0 Description Trigger event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSR

Name Relative Address Absolute Address Width Access Type Reset Value ETMSR 0x00000010 debug_cpu_ptm0: 0xF889C010 debug_cpu_ptm1: 0xF889D010 4 bits mixed 0x00000000

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Description

Status Register

Register ETMSR Details

Field Name TrigFlag Bits 3 Type rw Reset Value 0x0 Description Trigger bit. Set when the trigger occurs and prevents the trigger from being output until the PTM is next programmed. Holds the current status of the trace start/stop resource. If set to 1, indicates that a trace start address has been matched, without a corresponding trace stop address match. Effective state of the Programming bit. You must wait for this bit to go to b1 before starting to program the PTM. If set to 1, there is an overflow that has not yet been traced.

TSSRStat

rw

0x0

ProgBit

ro

0x0

Overflow

ro

0x0

Register (ptm) ETMSCR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSCR 0x00000014 debug_cpu_ptm0: 0xF889C014 debug_cpu_ptm1: 0xF889D014 15 bits ro 0x00000000 System Configuration Register

Register ETMSCR Details

Field Name NumProcs reserved FIFOFULL reserved Bits 14:12 11:9 8 7:0 Type ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 Description Number of supported processors minus 1. Reserved FIFOFULL not supported Reserved

Register (ptm) ETMTSSCR

Name Relative Address ETMTSSCR 0x00000018

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Absolute Address Width Access Type Reset Value Description

debug_cpu_ptm0: 0xF889C018 debug_cpu_ptm1: 0xF889D018 24 bits rw 0x00000000 TraceEnable Start/Stop Control Register

Register ETMTSSCR Details

Field Name StopAddrSel Bits 23:16 Type rw Reset Value 0x0 Description When a bit is set to 1, it selects a single address comparator (8-1) as a stop address for the TraceEnable Start/Stop block. For example, if you set bit [16] to 1 it selects single address comparator 1 as a stop address. reserved StartAddrSel 15:8 7:0 rw rw 0x0 0x0 Reserved When a bit is set to 1, it selects a single address comparator (8-1) as a start address for the TraceEnable Start/Stop block. For example, if you set bit [0] to 1 it selects single address comparator 1 as a start address.

Register (ptm) ETMTECR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMTECR1 0x00000024 debug_cpu_ptm0: 0xF889C024 debug_cpu_ptm1: 0xF889D024 26 bits rw 0x00000000 TraceEnable Control Register 1

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Appendix B: Register Details

Register ETMTECR1 Details

Field Name TraceSSEn Bits 25 Type rw Reset Value 0x0 Description Trace start/stop control enable. The possible values of this bit are: 0 Tracing is unaffected by the trace start/stop logic. 1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. The trace start/stop resource is not affected by the value of this bit. ExcIncFlag 24 rw 0x0 Exclude/include flag. The possible values of this bit are: 0 Include. The specified address range comparators indicate the regions where tracing can occur. No tracing occurs outside this region. 1 Exclude. The specified address range comparators indicate regions to be excluded from the trace. When outside an exclude region, tracing can occur. reserved AddrCompSel 23:4 3:0 rw rw 0x0 0x0 Reserved When a bit is set to 1, it selects an address range comparator, 4-1, for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1.

Register (ptm) ETMACVR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR1 0x00000040 debug_cpu_ptm0: 0xF889C040 debug_cpu_ptm1: 0xF889D040 32 bits rw 0x00000000 Address Comparator Value Register 1

Register ETMACVR1 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

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Register (ptm) ETMACVR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR2 0x00000044 debug_cpu_ptm0: 0xF889C044 debug_cpu_ptm1: 0xF889D044 32 bits rw 0x00000000 Address Comparator Value Register 2

Register ETMACVR2 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACVR3

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR3 0x00000048 debug_cpu_ptm0: 0xF889C048 debug_cpu_ptm1: 0xF889D048 32 bits rw 0x00000000 Address Comparator Value Register 3

Register ETMACVR3 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACVR4

Name Relative Address Absolute Address Width ETMACVR4 0x0000004C debug_cpu_ptm0: 0xF889C04C debug_cpu_ptm1: 0xF889D04C 32 bits

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Appendix B: Register Details

Access Type Reset Value Description

rw 0x00000000 Address Comparator Value Register 4

Register ETMACVR4 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACVR5

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR5 0x00000050 debug_cpu_ptm0: 0xF889C050 debug_cpu_ptm1: 0xF889D050 32 bits rw 0x00000000 Address Comparator Value Register 5

Register ETMACVR5 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACVR6

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR6 0x00000054 debug_cpu_ptm0: 0xF889C054 debug_cpu_ptm1: 0xF889D054 32 bits rw 0x00000000 Address Comparator Value Register 6

Register ETMACVR6 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

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Register (ptm) ETMACVR7

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR7 0x00000058 debug_cpu_ptm0: 0xF889C058 debug_cpu_ptm1: 0xF889D058 32 bits rw 0x00000000 Address Comparator Value Register 7

Register ETMACVR7 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACVR8

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACVR8 0x0000005C debug_cpu_ptm0: 0xF889C05C debug_cpu_ptm1: 0xF889D05C 32 bits rw 0x00000000 Address Comparator Value Register 8

Register ETMACVR8 Details

Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison

Register (ptm) ETMACTR1

Name Relative Address Absolute Address Width ETMACTR1 0x00000080 debug_cpu_ptm0: 0xF889C080 debug_cpu_ptm1: 0xF889D080 12 bits

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Access Type Reset Value Description

mixed 0x00000001 Address Comparator Access Type Register 1

Register ETMACTR1 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR2 0x00000084 debug_cpu_ptm0: 0xF889C084 debug_cpu_ptm1: 0xF889D084 12 bits mixed 0x00000001 Address Comparator Access Type Register 2

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Register ETMACTR2 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR3

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR3 0x00000088 debug_cpu_ptm0: 0xF889C088 debug_cpu_ptm1: 0xF889D088 12 bits mixed 0x00000001 Address Comparator Access Type Register 3

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Register ETMACTR3 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR4

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR4 0x0000008C debug_cpu_ptm0: 0xF889C08C debug_cpu_ptm1: 0xF889D08C 12 bits mixed 0x00000001 Address Comparator Access Type Register 4

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Register ETMACTR4 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR5

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR5 0x00000090 debug_cpu_ptm0: 0xF889C090 debug_cpu_ptm1: 0xF889D090 12 bits mixed 0x00000001 Address Comparator Access Type Register 5

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Register ETMACTR5 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR6

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR6 0x00000094 debug_cpu_ptm0: 0xF889C094 debug_cpu_ptm1: 0xF889D094 12 bits mixed 0x00000001 Address Comparator Access Type Register 6

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Register ETMACTR6 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR7

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR7 0x00000098 debug_cpu_ptm0: 0xF889C098 debug_cpu_ptm1: 0xF889D098 12 bits mixed 0x00000001 Address Comparator Access Type Register 7

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Register ETMACTR7 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMACTR8

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMACTR8 0x0000009C debug_cpu_ptm0: 0xF889C09C debug_cpu_ptm1: 0xF889D09C 12 bits mixed 0x00000001 Address Comparator Access Type Register 8

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Register ETMACTR8 Details

Field Name SecLevelCtrl Bits 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved AccessType 7:3 2:0 rw ro 0x0 0x1 Reserved Access type. Returns the value: Instruction execute.

Register (ptm) ETMCNTRLDVR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTRLDVR1 0x00000140 debug_cpu_ptm0: 0xF889C140 debug_cpu_ptm1: 0xF889D140 16 bits rw 0x00000000 Counter Reload Value Register 1

Register ETMCNTRLDVR1 Details

Field Name InitValue Bits 15:0 Type rw Reset Value 0x0 Description Counter initial value

Register (ptm) ETMCNTRLDVR2

Name Relative Address Absolute Address ETMCNTRLDVR2 0x00000144 debug_cpu_ptm0: 0xF889C144 debug_cpu_ptm1: 0xF889D144

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Width Access Type Reset Value Description

16 bits rw 0x00000000 Counter Reload Value Register 2

Register ETMCNTRLDVR2 Details

Field Name InitValue Bits 15:0 Type rw Reset Value 0x0 Description Counter initial value

Register (ptm) ETMCNTENR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTENR1 0x00000150 debug_cpu_ptm0: 0xF889C150 debug_cpu_ptm1: 0xF889D150 18 bits mixed 0x00020000 Counter Enable Event Register 1

Register ETMCNTENR1 Details

Field Name Reserved_1 ExtOutEvent Bits 17 16:0 Type ro rw Reset Value 0x1 0x0 Description Reserved, RAO/WI Count enable event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMCNTENR2

Name Relative Address Absolute Address ETMCNTENR2 0x00000154 debug_cpu_ptm0: 0xF889C154 debug_cpu_ptm1: 0xF889D154

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Width Access Type Reset Value Description

18 bits mixed 0x00020000 Counter Enable Event Register 2

Register ETMCNTENR2 Details

Field Name Reserved_1 ExtOutEvent Bits 17 16:0 Type ro rw Reset Value 0x1 0x0 Description Reserved, RAO/WI Count enable event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMCNTRLDEVR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTRLDEVR1 0x00000160 debug_cpu_ptm0: 0xF889C160 debug_cpu_ptm1: 0xF889D160 17 bits rw 0x00000000 Counter Reload Event Register 1

Register ETMCNTRLDEVR1 Details

Field Name CntReloadEvent Bits 16:0 Type rw Reset Value 0x0 Description Count reload event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

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Register (ptm) ETMCNTRLDEVR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTRLDEVR2 0x00000164 debug_cpu_ptm0: 0xF889C164 debug_cpu_ptm1: 0xF889D164 17 bits rw 0x00000000 Counter Reload Event Register 2

Register ETMCNTRLDEVR2 Details

Field Name CntReloadEvent Bits 16:0 Type rw Reset Value 0x0 Description Count reload event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMCNTVR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTVR1 0x00000170 debug_cpu_ptm0: 0xF889C170 debug_cpu_ptm1: 0xF889D170 16 bits rw 0x00000000 Counter Value Register 1

Register ETMCNTVR1 Details

Field Name CurrCount Bits 15:0 Type rw Reset Value 0x0 Description Current counter value.

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Register (ptm) ETMCNTVR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCNTVR2 0x00000174 debug_cpu_ptm0: 0xF889C174 debug_cpu_ptm1: 0xF889D174 16 bits rw 0x00000000 Counter Value Register 2

Register ETMCNTVR2 Details

Field Name CurrCount Bits 15:0 Type rw Reset Value 0x0 Description Current counter value.

Register (ptm) ETMSQ12EVR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQ12EVR 0x00000180 debug_cpu_ptm0: 0xF889C180 debug_cpu_ptm1: 0xF889D180 17 bits rw 0x00000000 Sequencer State Transition Event Register 12

Register ETMSQ12EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

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Register (ptm) ETMSQ21EVR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQ21EVR 0x00000184 debug_cpu_ptm0: 0xF889C184 debug_cpu_ptm1: 0xF889D184 17 bits rw 0x00000000 Sequencer State Transition Event Register 21

Register ETMSQ21EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSQ23EVR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQ23EVR 0x00000188 debug_cpu_ptm0: 0xF889C188 debug_cpu_ptm1: 0xF889D188 17 bits rw 0x00000000 Sequencer State Transition Event Register 23

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Register ETMSQ23EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSQ31EVR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQ31EVR 0x0000018C debug_cpu_ptm0: 0xF889C18C debug_cpu_ptm1: 0xF889D18C 17 bits rw 0x00000000 Sequencer State Transition Event Register 31

Register ETMSQ31EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSQ32EVR

Name ETMSQ32EVR

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000190 debug_cpu_ptm0: 0xF889C190 debug_cpu_ptm1: 0xF889D190 17 bits rw 0x00000000 Sequencer State Transition Event Register 32

Register ETMSQ32EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSQ13EVR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQ13EVR 0x00000194 debug_cpu_ptm0: 0xF889C194 debug_cpu_ptm1: 0xF889D194 17 bits rw 0x00000000 Sequencer State Transition Event Register 13

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Register ETMSQ13EVR Details

Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMSQR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSQR 0x0000019C debug_cpu_ptm0: 0xF889C19C debug_cpu_ptm1: 0xF889D19C 2 bits rw 0x00000000 Current Sequencer State Register

Register ETMSQR Details

Field Name CurrentSeqState Bits 1:0 Type rw Reset Value 0x0 Description Indicates the current sequencer state

Register (ptm) ETMEXTOUTEVR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMEXTOUTEVR1 0x000001A0 debug_cpu_ptm0: 0xF889C1A0 debug_cpu_ptm1: 0xF889D1A0 17 bits rw 0x00000000 External Output Event Register 1

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Register ETMEXTOUTEVR1 Details

Field Name ExtOutputEvent Bits 16:0 Type rw Reset Value 0x0 Description External output event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMEXTOUTEVR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMEXTOUTEVR2 0x000001A4 debug_cpu_ptm0: 0xF889C1A4 debug_cpu_ptm1: 0xF889D1A4 17 bits rw 0x00000000 External Output Event Register 2

Register ETMEXTOUTEVR2 Details

Field Name ExtOutputEvent Bits 16:0 Type rw Reset Value 0x0 Description External output event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.

Register (ptm) ETMCIDCVR1

Name Relative Address Absolute Address Width ETMCIDCVR1 0x000001B0 debug_cpu_ptm0: 0xF889C1B0 debug_cpu_ptm1: 0xF889D1B0 32 bits

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Access Type Reset Value Description

rw 0x00000000 Context ID Comparator Value Register

Register ETMCIDCVR1 Details

Field Name ContextID Bits 31:0 Type rw Reset Value 0x0 Description Holds a 32-bit Context ID value

Register (ptm) ETMCIDCMR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMCIDCMR 0x000001BC debug_cpu_ptm0: 0xF889C1BC debug_cpu_ptm1: 0xF889D1BC 32 bits rw 0x00000000 Context ID Comparator Mask Register

Register ETMCIDCMR Details

Field Name ContextMask Bits 31:0 Type rw Reset Value 0x0 Description Holds a 32-bit Context ID mask

Register (ptm) ETMSYNCFR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMSYNCFR 0x000001E0 debug_cpu_ptm0: 0xF889C1E0 debug_cpu_ptm1: 0xF889D1E0 12 bits mixed 0x00000400 Synchronization Frequency Register

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Register ETMSYNCFR Details

Field Name SyncFreq reserved Bits 11:2 1:0 Type rw ro Reset Value 0x100 0x0 Description Synchronization frequency Reserved

Register (ptm) ETMIDR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMIDR 0x000001E4 debug_cpu_ptm0: 0xF889C1E4 debug_cpu_ptm1: 0xF889D1E4 32 bits ro 0x411CF300 ID Register

Register ETMIDR Details

Field Name ImplCode reserved reserved SecExtSupp Thumb32Supp reserved Reserved_F MajorVer MinorVer ImplRev Bits 31:24 23:21 20 19 18 17:16 15:12 11:8 7:4 3:0 Type ro ro ro ro ro ro ro ro ro ro Reset Value 0x41 0x0 0x1 0x1 0x1 0x0 0xF 0x3 0x0 0x0 Description Implementor code. The field reads 0x41, ASCII code for A, indicating ARM Limited. Reserved Reserved, RAO Support for security extensions. Support for 32-bit Thumb instructions. Reserved Reserved, 0b1111 Major architecture version number, 0b0011 Minor architecture version number, 0b0000 Implementation revision.

Register (ptm) ETMCCER

Name Relative Address Absolute Address Width ETMCCER 0x000001E8 debug_cpu_ptm0: 0xF889C1E8 debug_cpu_ptm1: 0xF889D1E8 26 bits

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Access Type Reset Value Description

ro 0x00C019A2 Configuration Code Extension Register

Register ETMCCER Details

Field Name BarrTS BarrWP RetStack Timestamp reserved InstrumRes Reserved_1 RegReads ExtInSize ExtInSel Bits 25 24 23 22 21:16 15:13 12 11 10:3 2:0 Type ro ro ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x1 0x1 0x0 0x0 0x1 0x1 0x34 0x2 Description Timestamps are not generated for DMB/DSB DMB/DSB instructions are not treated as waypoints. Return stack implemented. Timestamping implemented. Reserved Specifies the number of instrumentation resources. Reserved, RAO Indicates that all registers, except some Integration Test Registers, are readable. Specifies the size of the extended external input bus, 52. Specifies the number of extended external input selectors, 2.

Register (ptm) ETMEXTINSELR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMEXTINSELR 0x000001EC debug_cpu_ptm0: 0xF889C1EC debug_cpu_ptm1: 0xF889D1EC 14 bits rw 0x00000000 Extended External Input Selection Register

Register ETMEXTINSELR Details

Field Name ExtInSel2 reserved ExtInSel1 Bits 13:8 7:6 5:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Second extended external input selector Reserved First extended external input selector

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Register (ptm) ETMAUXCR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMAUXCR 0x000001FC debug_cpu_ptm0: 0xF889C1FC debug_cpu_ptm1: 0xF889D1FC 4 bits rw 0x00000000 Auxiliary Control Register

Register ETMAUXCR Details

Field Name ForceSyncInsert Bits 3 Type rw Reset Value 0x0 Description Force insertion of synchronization packets, regardless of current trace activity. Possible values for this bit are: b0 = Synchronization packets delayed when trace activity is high. This is the reset value. b1 = Synchronization packets inserted regardless of trace activity. This bit might be set if synchronization packets occur too far apart. Setting this bit might cause the trace FIFO to overflow more frequently when trace activity is high. DisableWPUpdate 2 rw 0x0 Specifies whether the PTM issues waypoint update packets if there are more than 4096 bytes between waypoints. Possible values for this bit are: b0 = PTM always issues update packets if there are more than 4096 bytes between waypoints. This is the reset value. b1 = PTM does not issue waypoint update packets unless required to do so as the result of an exception or debug entry.

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Appendix B: Register Details

Field Name DisableTSOnBarr

Bits 1

Type rw

Reset Value 0x0

Description Specifies whether the PTM issues a timestamp on a barrier instruction. Possible values for this bit are: b0 = PTM issues timestamps on barrier instructions. This is the reset value. b1 = PTM does not issue timestamps on barriers

DisableForcedOF

rw

0x0

Specifies whether the PTM enters overflow state when synchronization is requested, and the previous synchronization sequence has not yet completed. This does not affect entry to overflow state when the FIFO becomes full. Possible values for this bit are: b0 = Forced overflow enabled. This is the reset value. b1 = Forced overflow disabled.

Register (ptm) ETMTRACEIDR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMTRACEIDR 0x00000200 debug_cpu_ptm0: 0xF889C200 debug_cpu_ptm1: 0xF889D200 7 bits rw 0x00000000 CoreSight Trace ID Register

Register ETMTRACEIDR Details

Field Name TraceID Bits 6:0 Type rw Reset Value 0x0 Description Before trace is generated, you must program this register with a non-reserved value. Reserved values are 0x00 and any value in the range 0x70-0x7F. The reset value of this register is 0x00.

Register (ptm) OSLSR

Name Relative Address Absolute Address OSLSR 0x00000304 debug_cpu_ptm0: 0xF889C304 debug_cpu_ptm1: 0xF889D304

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Width Access Type Reset Value Description

32 bits ro 0x00000000 OS Lock Status Register

Register OSLSR Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description Shows that OS Locking is not implemented.

Register (ptm) ETMPDSR

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMPDSR 0x00000314 debug_cpu_ptm0: 0xF889C314 debug_cpu_ptm1: 0xF889D314 32 bits ro 0x00000001 Device Powerdown Status Register

Register ETMPDSR Details

Field Name Bits 31:0 Type ro Reset Value 0x1 Description Indicates that the PTM Trace Registers can be accessed.

Register (ptm) ITMISCOUT

Name Relative Address Absolute Address Width Access Type Reset Value Description ITMISCOUT 0x00000EDC debug_cpu_ptm0: 0xF889CEDC debug_cpu_ptm1: 0xF889DEDC 10 bits wo 0x00000000 Miscellaneous Outputs Register

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Register ITMISCOUT Details

Field Name PTMEXTOUT reserved PTMIDLEACK PTMDBGREQ reserved Bits 9:8 7:6 5 4 3:0 Type wo wo wo wo wo Reset Value 0x0 0x0 0x0 0x0 0x0 Description Drives the PTMEXTOUT[1:0] outputs Reserved Drives the PTMIDLEACK output Drives the PTMDBGREQ output Reserved

Register (ptm) ITMISCIN

Name Relative Address Absolute Address Width Access Type Reset Value Description ITMISCIN 0x00000EE0 debug_cpu_ptm0: 0xF889CEE0 debug_cpu_ptm1: 0xF889DEE0 7 bits ro x Miscellaneous Inputs Register

Register ITMISCIN Details

Field Name STANDBYWFI reserved PTMDBGACK EXTIN Bits 6 5 4 3:0 Type ro ro ro ro Reset Value x 0x0 x x Description Returns the value of the STANDBYWFI input Reserved Returns the value of the PTMDBGACK input Returns the value of the EXTIN[3:0] inputs

Register (ptm) ITTRIGGER

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRIGGER 0x00000EE8 debug_cpu_ptm0: 0xF889CEE8 debug_cpu_ptm1: 0xF889DEE8 1 bits wo 0x00000000 Trigger Register

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Register ITTRIGGER Details

Field Name PTMTRIGGER Bits 0 Type wo Reset Value 0x0 Description Drives the PTMTRIGGER output

Register (ptm) ITATBDATA0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBDATA0 0x00000EEC debug_cpu_ptm0: 0xF889CEEC debug_cpu_ptm1: 0xF889DEEC 5 bits wo 0x00000000 ATB Data 0 Register

Register ITATBDATA0 Details

Field Name ATDATAM31 ATDATAM23 ATDATAM15 ATDATAM7 ATDATAM0 Bits 4 3 2 1 0 Type wo wo wo wo wo Reset Value 0x0 0x0 0x0 0x0 0x0 Description Drives the ATDATAM[31] output Drives the ATDATAM[23] output Drives the ATDATAM[15] output Drives the ATDATAM[7] output Drives the ATDATAM[0] output

Register (ptm) ITATBCTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR2 0x00000EF0 debug_cpu_ptm0: 0xF889CEF0 debug_cpu_ptm1: 0xF889DEF0 2 bits ro x ATB Control 2 Register

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Appendix B: Register Details

Register ITATBCTR2 Details

Field Name AFVALIDM ATREADYM Bits 1 0 Type ro ro Reset Value x x Description Returns the value of the AFVALIDM input Returns the value of the ATREADYM input

Register (ptm) ITATBID

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBID 0x00000EF4 debug_cpu_ptm0: 0xF889CEF4 debug_cpu_ptm1: 0xF889DEF4 7 bits wo 0x00000000 ATB Identification Register

Register ITATBID Details

Field Name ATIDM Bits 6:0 Type wo Reset Value 0x0 Description Drives the ATIDM[6:0] outputs

Register (ptm) ITATBCTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR0 0x00000EF8 debug_cpu_ptm0: 0xF889CEF8 debug_cpu_ptm1: 0xF889DEF8 10 bits wo 0x00000000 ATB Control 0 Register

Register ITATBCTR0 Details

Field Name ATBYTESM reserved Bits 9:8 7:2 Type wo wo Reset Value 0x0 0x0 Description Drives the ATBYTESM[9:8] outputs Reserved

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Appendix B: Register Details

Field Name AFREADYM ATVALIDM

Bits 1 0

Type wo wo

Reset Value 0x0 0x0

Description Drives the AFREADYM output Drives the ATVALIDM output

Register (ptm) ETMITCTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description ETMITCTRL 0x00000F00 debug_cpu_ptm0: 0xF889CF00 debug_cpu_ptm1: 0xF889DF00 1 bits rw 0x00000000 Integration Mode Control Register

Register ETMITCTRL Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers. Before entering integration mode, the PTM must be powered up and in programming mode. THis means bit 0 of the Main Control Register is set to 0, and bit 10 of the Main Control Register ist set 1. After leaving integration mode, the PTM must be reset before attempting to perform tracing.

Register (ptm) CTSR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTSR 0x00000FA0 debug_cpu_ptm0: 0xF889CFA0 debug_cpu_ptm1: 0xF889DFA0 8 bits rw 0x000000FF Claim Tag Set Register

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Register CTSR Details

Field Name Bits 7:0 Type rw Reset Value 0xFF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (ptm) CTCR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTCR 0x00000FA4 debug_cpu_ptm0: 0xF889CFA4 debug_cpu_ptm1: 0xF889DFA4 8 bits rw 0x00000000 Claim Tag Clear Register

Register CTCR Details

Field Name Bits 7:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

Register (ptm) LAR

Name Relative Address Absolute Address Width Access Type Reset Value LAR 0x00000FB0 debug_cpu_ptm0: 0xF889CFB0 debug_cpu_ptm1: 0xF889DFB0 32 bits wo 0x00000000

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Appendix B: Register Details

Description

Lock Access Register

Register LAR Details

Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), PTM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): PTM is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

Register (ptm) LSR

Name Relative Address Absolute Address Width Access Type Reset Value Description LSR 0x00000FB4 debug_cpu_ptm0: 0xF889CFB4 debug_cpu_ptm1: 0xF889DFB4 3 bits ro 0x00000003 Lock Status Register

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Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since PTM implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether PTM is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (ptm) ASR

Name Relative Address Absolute Address Width Access Type Reset Value Description ASR 0x00000FB8 debug_cpu_ptm0: 0xF889CFB8 debug_cpu_ptm1: 0xF889DFB8 8 bits ro x Authentication Status Register

Register ASR Details

Field Name SNI Bits 7:6 Type ro Reset Value 0x0 Description Secure non-invasive debug Always 2'b00,. This functionality is not implemented SI 5:4 ro 0x0 Secure invasive debug Always 2'b00. This functionality is not implemented.

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Appendix B: Register Details

Field Name NSNI

Bits 3:2

Type ro

Reset Value x

Description Non-secure non-invasive debug IF NIDEN or DBGEN is 1, this field is 2'b11, indicating the functionality is implemented and enabled. Otherwise, this field is 2'b10 (implemented but disabled)

NSI

1:0

ro

0x0

Non-secure invasive debug Always 2'b00. This functionality is not implemented.

Register (ptm) DEVID

Name Relative Address Absolute Address Width Access Type Reset Value Description DEVID 0x00000FC8 debug_cpu_ptm0: 0xF889CFC8 debug_cpu_ptm1: 0xF889DFC8 32 bits ro 0x00000000 Device ID

Register DEVID Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description Component capability

Register (ptm) DTIR

Name Relative Address Absolute Address Width Access Type Reset Value Description DTIR 0x00000FCC debug_cpu_ptm0: 0xF889CFCC debug_cpu_ptm1: 0xF889DFCC 8 bits ro 0x00000013 Device Type Identifier Register

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Appendix B: Register Details

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x13 Description A trace source and processor trace

Register (ptm) PERIPHID4

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID4 0x00000FD0 debug_cpu_ptm0: 0xF889CFD0 debug_cpu_ptm1: 0xF889DFD0 8 bits ro 0x00000004 Peripheral ID4

Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (ptm) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 debug_cpu_ptm0: 0xF889CFD4 debug_cpu_ptm1: 0xF889DFD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

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Register (ptm) PERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID6 0x00000FD8 debug_cpu_ptm0: 0xF889CFD8 debug_cpu_ptm1: 0xF889DFD8 8 bits ro 0x00000000 Peripheral ID6

Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (ptm) PERIPHID7

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID7 0x00000FDC debug_cpu_ptm0: 0xF889CFDC debug_cpu_ptm1: 0xF889DFDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (ptm) PERIPHID0

Name Relative Address Absolute Address Width PERIPHID0 0x00000FE0 debug_cpu_ptm0: 0xF889CFE0 debug_cpu_ptm1: 0xF889DFE0 8 bits

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Appendix B: Register Details

Access Type Reset Value Description

ro 0x00000050 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x50 PartNumber0 Description

Register (ptm) PERIPHID1

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID1 0x00000FE4 debug_cpu_ptm0: 0xF889CFE4 debug_cpu_ptm1: 0xF889DFE4 8 bits ro 0x000000B9 Peripheral ID1

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (ptm) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 debug_cpu_ptm0: 0xF889CFE8 debug_cpu_ptm1: 0xF889DFE8 8 bits ro 0x0000001B Peripheral ID2

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Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x1 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (ptm) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC debug_cpu_ptm0: 0xF889CFEC debug_cpu_ptm1: 0xF889DFEC 8 bits ro 0x00000000 Peripheral ID3

Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

Register (ptm) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 debug_cpu_ptm0: 0xF889CFF0 debug_cpu_ptm1: 0xF889DFF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

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Register (ptm) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID1 0x00000FF4 debug_cpu_ptm0: 0xF889CFF4 debug_cpu_ptm1: 0xF889DFF4 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (ptm) COMPID2

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID2 0x00000FF8 debug_cpu_ptm0: 0xF889CFF8 debug_cpu_ptm1: 0xF889DFF8 8 bits ro 0x00000005 Component ID2

Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (ptm) COMPID3

Name Relative Address Absolute Address Width COMPID3 0x00000FFC debug_cpu_ptm0: 0xF889CFFC debug_cpu_ptm1: 0xF889DFFC 8 bits

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Access Type Reset Value Description

ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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B.10 Debug Access Port (dap)

Module Name Base Address Description Vendor Info Debug Access Port (dap) 0xF8800000 debug_dap_rom Debug Access Port ROM Table

Register Summary
Register Name ROMENTRY00 ROMENTRY01 ROMENTRY02 ROMENTRY03 ROMENTRY04 ROMENTRY05 ROMENTRY06 ROMENTRY07 ROMENTRY08 ROMENTRY09 ROMENTRY10 ROMENTRY11 ROMENTRY12 ROMENTRY13 ROMENTRY14 ROMENTRY15 PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 PERIPHID3 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 8 8 8 8 8 8 8 Type ro ro ro ro ro ro ro ro ro ro rw rw rw rw rw rw ro ro ro ro ro ro ro ro Reset Value 0x00001003 0x00002003 0x00003003 0x00004003 0x00005003 0x00009003 0x0000A003 0x0000B003 0x0000C003 0x00080003 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00000000 0x000000B2 0x00000093 0x00000008 0x00000000 Description ROM entry 00 ROM entry 01 ROM entry 02 ROM entry 03 ROM entry 04 ROM entry 05 ROM entry 06 ROM entry 07 ROM entry 08 ROM entry 09 ROM entry 10 ROM entry 11 ROM entry 12 ROM entry 13 ROM entry 14 ROM entry 15 Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3

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Register Name COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 8 8 8 8

Type ro ro ro ro

Reset Value 0x0000000D 0x00000010 0x00000005 0x000000B1

Description Component ID0 Component ID1 Component ID2 Component ID3

Register (dap) ROMENTRY00

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY00 0x00000000 0xF8800000 32 bits ro 0x00001003 ROM entry 00

Register ROMENTRY00 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x1 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY01

Name Relative Address Absolute Address Width Access Type ROMENTRY01 0x00000004 0xF8800004 32 bits ro

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Reset Value Description

0x00002003 ROM entry 01

Register ROMENTRY01 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x2 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY02

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY02 0x00000008 0xF8800008 32 bits ro 0x00003003 ROM entry 02

Register ROMENTRY02 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x3 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Reserved

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Appendix B: Register Details

Field Name Format

Bits 1

Type ro

Reset Value 0x1

Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.

EntryPresent

ro

0x1

Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY03

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY03 0x0000000C 0xF880000C 32 bits ro 0x00004003 ROM entry 03

Register ROMENTRY03 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x4 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY04

Name Relative Address Absolute Address Width Access Type ROMENTRY04 0x00000010 0xF8800010 32 bits ro

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Appendix B: Register Details

Reset Value Description

0x00005003 ROM entry 04

Register ROMENTRY04 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x5 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY05

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY05 0x00000014 0xF8800014 32 bits ro 0x00009003 ROM entry 05

Register ROMENTRY05 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x9 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Reserved

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Appendix B: Register Details

Field Name Format

Bits 1

Type ro

Reset Value 0x1

Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.

EntryPresent

ro

0x1

Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY06

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY06 0x00000018 0xF8800018 32 bits ro 0x0000A003 ROM entry 06

Register ROMENTRY06 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0xA Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY07

Name Relative Address Absolute Address Width Access Type ROMENTRY07 0x0000001C 0xF880001C 32 bits ro

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Appendix B: Register Details

Reset Value Description

0x0000B003 ROM entry 07

Register ROMENTRY07 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0xB Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY08

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY08 0x00000020 0xF8800020 32 bits ro 0x0000C003 ROM entry 08

Register ROMENTRY08 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0xC Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Reserved

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Appendix B: Register Details

Field Name Format

Bits 1

Type ro

Reset Value 0x1

Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.

EntryPresent

ro

0x1

Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY09

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY09 0x00000024 0xF8800024 32 bits ro 0x00080003 ROM entry 09

Register ROMENTRY09 Details

Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x80 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved Format 11:2 1 ro ro 0x0 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.

Register (dap) ROMENTRY10

Name Relative Address Absolute Address Width Access Type ROMENTRY10 0x00000028 0xF8800028 32 bits rw

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Appendix B: Register Details

Reset Value Description

0x00000000 ROM entry 10

Register ROMENTRY10 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

Register (dap) ROMENTRY11

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY11 0x0000002C 0xF880002C 32 bits rw 0x00000000 ROM entry 11

Register ROMENTRY11 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

Register (dap) ROMENTRY12

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY12 0x00000030 0xF8800030 32 bits rw 0x00000000 ROM entry 12

Register ROMENTRY12 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

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Appendix B: Register Details

Register (dap) ROMENTRY13

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY13 0x00000034 0xF8800034 32 bits rw 0x00000000 ROM entry 13

Register ROMENTRY13 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

Register (dap) ROMENTRY14

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY14 0x00000038 0xF8800038 32 bits rw 0x00000000 ROM entry 14

Register ROMENTRY14 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

Register (dap) ROMENTRY15

Name Relative Address Absolute Address Width Access Type Reset Value Description ROMENTRY15 0x0000003C 0xF880003C 32 bits rw 0x00000000 ROM entry 15

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Appendix B: Register Details

Register ROMENTRY15 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Invalid entry Description

Register (dap) PERIPHID4

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID4 0x00000FD0 0xF8800FD0 8 bits ro 0x00000003 Peripheral ID4

Register PERIPHID4 Details

Field Name 4KB_count Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x3 Description 4KB Count, set to 0 JEP106 continuation code

Register (dap) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 0xF8800FD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (dap) PERIPHID6

Name PERIPHID6

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FD8 0xF8800FD8 8 bits ro 0x00000000 Peripheral ID6

Register PERIPHID6 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (dap) PERIPHID7

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID7 0x00000FDC 0xF8800FDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (dap) PERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID0 0x00000FE0 0xF8800FE0 8 bits ro 0x000000B2 Peripheral ID0

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Appendix B: Register Details

Register PERIPHID0 Details

Field Name PartNumber0 Bits 7:0 Type ro Reset Value 0xB2 PartNumber0 Description

Register (dap) PERIPHID1

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID1 0x00000FE4 0xF8800FE4 8 bits ro 0x00000093 Peripheral ID1

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0x9 0x3 Description JEP106 Identity Code [3:0] PartNumber1

Register (dap) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 0xF8800FE8 8 bits ro 0x00000008 Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x0 0x1 0x0 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

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Appendix B: Register Details

Register (dap) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC 0xF8800FEC 8 bits ro 0x00000000 Peripheral ID3

Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

Register (dap) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 0xF8800FF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (dap) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value COMPID1 0x00000FF4 0xF8800FF4 8 bits ro 0x00000010

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Appendix B: Register Details

Description

Component ID1

Register COMPID1 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0x10 Preamble Description

Register (dap) COMPID2

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID2 0x00000FF8 0xF8800FF8 8 bits ro 0x00000005 Component ID2

Register COMPID2 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (dap) COMPID3

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID3 0x00000FFC 0xF8800FFC 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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Appendix B: Register Details

B.11 CoreSight Embedded Trace Buffer (etb)

Module Name Base Address Description Vendor Info CoreSight Embedded Trace Buffer (etb) 0xF8801000 debug_etb Embedded Trace Buffer

Register Summary
Register Name RDP STS RRD RRP RWP TRG CTL RWD FFSR FFCR ITMISCOP0 ITTRFLINACK ITTRFLIN ITATBDATA0 ITATBCTR2 ITATBCTR1 ITATBCTR0 IMCR Address 0x00000004 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000300 0x00000304 0x00000EE0 0x00000EE4 0x00000EE8 0x00000EEC 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 Width 32 4 32 10 10 10 1 32 2 14 2 2 2 5 2 7 10 1 Type ro ro ro rw rw rw rw rw ro mixed wo wo wo ro wo ro ro rw Reset Value 0x00000400 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000200 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description RAM Depth Register Status Register RAM Read Data Register RAM Read Pointer Register RAM Write Pointer Register Trigger Counter Register Control Register RAM Write Data Register Formatter and Flush Status Register Formatter and Flush Control Register Integration Test Miscellaneous Output Register 0 Integration Test Trigger In and Flush In Acknowledge Register Integration Test Trigger In and Flush In Register Integration Test ATB Data Register Integration Test ATB Control Register 2 Integration Test ATB Control Register 1 Integration Test ATB Control Register 0 Integration Mode Control Register

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Appendix B: Register Details

Register Name CTSR CTCR LAR LSR ASR DEVID DTIR PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 4 4 32 3 8 6 8 8 8 8 8 8 8 8 8 8 8 8 8

Type rw rw wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x0000000F 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00000021 0x00000004 0x00000000 0x00000000 0x00000000 0x00000007 0x000000B9 0x0000002B 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID Device Type Identifier Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (etb) RDP

Name Relative Address Absolute Address Width Access Type Reset Value Description RDP 0x00000004 0xF8801004 32 bits ro 0x00000400 RAM Depth Register

Register RDP Details

Field Name Bits 31:0 Type ro Reset Value 0x400 Description Defines the depth, in words, of the trace RAM.

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Appendix B: Register Details

Register (etb) STS

Name Relative Address Absolute Address Width Access Type Reset Value Description STS 0x0000000C 0xF880100C 4 bits ro 0x00000000 Status Register

Register STS Details

Field Name FtEmpty AcqComp Bits 3 2 Type ro ro Reset Value 0x0 0x0 Description Formatter pipeline empty. All data stored to RAM. Acquisition complete. The acquisition complete flag indicates that capture has been completed when the formatter stops because of any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also results in FtStopped in the Formatter and Flush Status Register going HIGH. Triggered 1 ro 0x0 The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been embedded in the trace data by the formatter, but is determined by the programming of the Formatter and Flush Control Register. RAM Full. The flag indicates when the RAM write pointer has wrapped around.

Full

ro

0x0

Register (etb) RRD

Name Relative Address Absolute Address Width Access Type Reset Value Description RRD 0x00000010 0xF8801010 32 bits ro 0x00000000 RAM Read Data Register

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Appendix B: Register Details

Register RRD Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description Data read from the ETB Trace RAM.

Register (etb) RRP

Name Relative Address Absolute Address Width Access Type Reset Value Description RRP 0x00000014 0xF8801014 10 bits rw 0x00000000 RAM Read Pointer Register

Register RRP Details

Field Name Bits 9:0 Type rw Reset Value 0x0 Description Sets the read pointer used to read entries from the Trace RAM over the APB interface.

Register (etb) RWP

Name Relative Address Absolute Address Width Access Type Reset Value Description RWP 0x00000018 0xF8801018 10 bits rw 0x00000000 RAM Write Pointer Register

Register RWP Details

Field Name Bits 9:0 Type rw Reset Value 0x0 Description Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM

Register (etb) TRG

Name TRG

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x0000001C 0xF880101C 10 bits rw 0x00000000 Trigger Counter Register

Register TRG Details

Field Name Bits 9:0 Type rw Reset Value 0x0 Description The counter is used as follows: - Trace after The counter is set to a large value, slightly less than the number of entries in the RAM. - Trace before The counter is set to a small value. - Trace about The counter is set to half the depth of the Trace RAM. This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the register is not updated. A read access is permitted with trace capture enabled.

Register (etb) CTL

Name Relative Address Absolute Address Width Access Type Reset Value Description CTL 0x00000020 0xF8801020 1 bits rw 0x00000000 Control Register

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Appendix B: Register Details

Register CTL Details

Field Name TraceCaptEn Bits 0 Type rw Reset Value 0x0 Description ETB Trace Capture Enable. 1 = enable trace capture 0 = disable trace capture. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH.

Register (etb) RWD

Name Relative Address Absolute Address Width Access Type Reset Value Description RWD 0x00000024 0xF8801024 32 bits rw 0x00000000 RAM Write Data Register

Register RWD Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Data written to the ETB Trace RAM. When trace capture is disabled, the contents of this register are placed into the ETB Trace RAM when this register is written to. Writing to this register increments the RAM Write Pointer Register. If trace capture is enabled, and this register is accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a synchronization output from the ETB. If a write access is attempted, the data is not written into Trace RAM.

Register (etb) FFSR

Name FFSR

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000300 0xF8801300 2 bits ro 0x00000000 Formatter and Flush Status Register

Register FFSR Details

Field Name FtStopped Bits 1 Type ro Reset Value 0x0 Description Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH. Flush In Progress. This is an indication of the current state of AFVALIDS.

FlInProg

ro

0x0

Register (etb) FFCR

Name Relative Address Absolute Address Width Access Type Reset Value Description FFCR 0x00000304 0xF8801304 14 bits mixed 0x00000200 Formatter and Flush Control Register

Register FFCR Details

Field Name StopTrig StopFl Bits 13 12 Type rw rw Reset Value 0x0 0x0 Description Stop the formatter when a Trigger Event has been observed. Stop the formatter when a flush has completed (return of AFREADYS). This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset (disabled). Reserved Indicate a trigger on Flush completion (AFREADYS being returned). Indicate a trigger on a Trigger Event.

reserved TrigFl TrigEvt

11 10 9

ro rw rw

0x0 0x0 0x1

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Appendix B: Register Details

Field Name TrigIn reserved FOnMan

Bits 8 7 6

Type rw ro rw

Reset Value 0x0 0x0 0x0

Description Indicate a trigger on TRIGIN being asserted. Reserved Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when the flush has been serviced. This bit is clear on reset. Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs. This bit is clear on reset. Generate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection. This bit is clear on reset. Reserved Continuous Formatting. Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed when FtStopped is HIGH. This bit is clear on reset. Enable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset.

FOnTrig

rw

0x0

FOnFlIn

rw

0x0

reserved EnFCont

3:2 1

ro rw

0x0 0x0

EnFTC

rw

0x0

Register (etb) ITMISCOP0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITMISCOP0 0x00000EE0 0xF8801EE0 2 bits wo 0x00000000 Integration Test Miscellaneous Output Register 0

Register ITMISCOP0 Details

Field Name FULL ACQCOMP Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of FULL Set the value of ACQCOMP

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Appendix B: Register Details

Register (etb) ITTRFLINACK

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRFLINACK 0x00000EE4 0xF8801EE4 2 bits wo 0x00000000 Integration Test Trigger In and Flush In Acknowledge Register

Register ITTRFLINACK Details

Field Name FLUSHINACK TRIGINACK Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of FLUSHINACK Set the value of TRIGINACK

Register (etb) ITTRFLIN

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRFLIN 0x00000EE8 0xF8801EE8 2 bits wo 0x00000000 Integration Test Trigger In and Flush In Register

Register ITTRFLIN Details

Field Name FLUSHIN TRIGIN Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Read the value of FLUSHIN Read the value of TRIGIN

Register (etb) ITATBDATA0

Name Relative Address Absolute Address Width Access Type ITATBDATA0 0x00000EEC 0xF8801EEC 5 bits ro

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Appendix B: Register Details

Reset Value Description

0x00000000 Integration Test ATB Data Register

Register ITATBDATA0 Details

Field Name ATDATA31 ATDATA23 ATDATA15 ATDATA7 ATDATA0 Bits 4 3 2 1 0 Type ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 Description Read the value of ATDATA[31] Read the value of ATDATA[23] Read the value of ATDATA[15] Read the value of ATDATA[7] Read the value of ATDATA[0]

Register (etb) ITATBCTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR2 0x00000EF0 0xF8801EF0 2 bits wo 0x00000000 Integration Test ATB Control Register 2

Register ITATBCTR2 Details

Field Name AFVALIDS ATREADYS Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of AFVALIDS Set the value of ATREADYS

Register (etb) ITATBCTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR1 0x00000EF4 0xF8801EF4 7 bits ro 0x00000000 Integration Test ATB Control Register 1

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Appendix B: Register Details

Register ITATBCTR1 Details

Field Name ATID Bits 6:0 Type ro Reset Value 0x0 Description Read the value of ATIDS

Register (etb) ITATBCTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR0 0x00000EF8 0xF8801EF8 10 bits ro 0x00000000 Integration Test ATB Control Register 0

Register ITATBCTR0 Details

Field Name ATBYTES reserved AFREADY ATVALID Bits 9:8 7:2 1 0 Type ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 Description Read the value of ATBYTES Reserved Read the value of AFREADYS Read the value of ATVALIDS

Register (etb) IMCR

Name Relative Address Absolute Address Width Access Type Reset Value Description IMCR 0x00000F00 0xF8801F00 1 bits rw 0x00000000 Integration Mode Control Register

Register IMCR Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers.

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Appendix B: Register Details

Register (etb) CTSR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTSR 0x00000FA0 0xF8801FA0 4 bits rw 0x0000000F Claim Tag Set Register

Register CTSR Details

Field Name Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (etb) CTCR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTCR 0x00000FA4 0xF8801FA4 4 bits rw 0x00000000 Claim Tag Clear Register

Register CTCR Details

Field Name Bits 3:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

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Appendix B: Register Details

Register (etb) LAR

Name Relative Address Absolute Address Width Access Type Reset Value Description LAR 0x00000FB0 0xF8801FB0 32 bits wo 0x00000000 Lock Access Register

Register LAR Details

Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), ETB is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): ETB is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

Register (etb) LSR

Name Relative Address Absolute Address Width Access Type Reset Value Description LSR 0x00000FB4 0xF8801FB4 3 bits ro 0x00000003 Lock Status Register

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Appendix B: Register Details

Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since ETB implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether ETB is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (etb) ASR

Name Relative Address Absolute Address Width Access Type Reset Value Description ASR 0x00000FB8 0xF8801FB8 8 bits ro 0x00000000 Authentication Status Register

Register ASR Details

Field Name Bits 7:0 Type ro Reset Value 0x0 Description Indicates functionality not implemented

Register (etb) DEVID

Name Relative Address Absolute Address Width DEVID 0x00000FC8 0xF8801FC8 6 bits

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Appendix B: Register Details

Access Type Reset Value Description

ro 0x00000000 Device ID

Register DEVID Details

Field Name SyncATCLK InputMux Bits 5 4:0 Type ro ro Reset Value 0x0 0x0 Description ETB RAM is synchronous to ATCLK no input multiplexing

Register (etb) DTIR

Name Relative Address Absolute Address Width Access Type Reset Value Description DTIR 0x00000FCC 0xF8801FCC 8 bits ro 0x00000021 Device Type Identifier Register

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x21 Description A trace sink and specifically an ETB

Register (etb) PERIPHID4

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID4 0x00000FD0 0xF8801FD0 8 bits ro 0x00000004 Peripheral ID4

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Appendix B: Register Details

Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (etb) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 0xF8801FD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (etb) PERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID6 0x00000FD8 0xF8801FD8 8 bits ro 0x00000000 Peripheral ID6

Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (etb) PERIPHID7

Name PERIPHID7

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FDC 0xF8801FDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (etb) PERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID0 0x00000FE0 0xF8801FE0 8 bits ro 0x00000007 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x7 PartNumber0 Description

Register (etb) PERIPHID1

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID1 0x00000FE4 0xF8801FE4 8 bits ro 0x000000B9 Peripheral ID1

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Appendix B: Register Details

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (etb) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 0xF8801FE8 8 bits ro 0x0000002B Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x2 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (etb) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC 0xF8801FEC 8 bits ro 0x00000000 Peripheral ID3

Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

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Appendix B: Register Details

Register (etb) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 0xF8801FF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (etb) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID1 0x00000FF4 0xF8801FF4 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (etb) COMPID2

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID2 0x00000FF8 0xF8801FF8 8 bits ro 0x00000005 Component ID2

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Appendix B: Register Details

Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (etb) COMPID3

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID3 0x00000FFC 0xF8801FFC 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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Appendix B: Register Details

B.12 PL Fabric Trace Monitor (ftm)

Module Name Base Address Description Vendor Info PL Fabric Trace Monitor (ftm) 0xF880B000 debug_ftm Fabric Trace Macrocell

Register Summary
Register Name FTMGLBCTRL FTMSTATUS FTMCONTROL FTMP2FDBG0 FTMP2FDBG1 FTMP2FDBG2 FTMP2FDBG3 FTMF2PDBG0 FTMF2PDBG1 FTMF2PDBG2 FTMF2PDBG3 CYCOUNTPRE FTMSYNCRELOAD FTMSYNCCOUT FTMATID FTMITTRIGOUTACK FTMITTRIGGER FTMITTRACEDIS FTMITCYCCOUNT FTMITATBDATA0 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000400 0x00000ED0 0x00000ED4 0x00000ED8 0x00000EDC 0x00000EEC Width 1 8 3 8 8 8 8 8 8 8 8 4 12 12 7 4 4 1 32 5 Type rw ro rw rw rw rw rw ro ro ro ro rw rw ro rw ro wo ro rw wo Reset Value 0x00000000 0x00000082 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000000 Description FTM Global Control Register FTM Status Register FTM Configuration FPGA Debug Register P2F0 FPGA Debug Register P2F1 FPGA Debug Register P2F2 FPGA Debug Register P2F3 FPGA Debug Register F2P0 FPGA Debug Register F2P1 FPGA Debug Register F2P2 FPGA Debug Register F2P3 AXI Cycle Count clock pre-scaler FTM Synchronization Counter reload value FTM Synchronization Counter value FTM ATID Value Register Trigger Output Acknowledge Integration Test Register Trigger Output Integration Test Register External Trace Disable Integration Test Register Cycle Counter Test Register ATB Data Integration Test Register 0

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Appendix B: Register Details

Register Name FTMITATBCTR2 FTMITATBCTR1 FTMITATBCTR0 FTMITCR CLAIMTAGSET CLAIMTAGCLR LOCK_ACCESS LOCK_STATUS FTMAUTHSTATUS FTMDEVID FTMDEV_TYPE FTMPERIPHID4 FTMPERIPHID5 FTMPERIPHID6 FTMPERIPHID7 FTMPERIPHID0 FTMPERIPHID1 FTMPERIPHID2 FTMPERIPHID3 FTMCOMPONID0 FTMCOMPONID1 FTMCOMPONID2 FTMCOMPONID3

Address 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 2 7 10 1 8 8 32 3 8 1 8 8 8 8 8 8 8 8 8 8 8 8 8

Type ro rw wo rw rw rw wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000001 0x00000000 0x00000000 0x00000000 0x000000FF 0x000000FF 0x00000000 0x00000003 0x00000088 0x00000000 0x00000033 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000090 0x0000000C 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description ATB Control Integration Test Register 2 ATB Control Integration Test Register 1 ATB Control Integration Test Register 0 FTM Test Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device Configuration Register Device Type Identification Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (ftm) FTMGLBCTRL

Name Relative Address Absolute Address Width Access Type FTMGLBCTRL 0x00000000 0xF880B000 1 bits rw

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Appendix B: Register Details

Reset Value Description

0x00000000 FTM Global Control Register

Register FTMGLBCTRL Details

Field Name FTMENABLE Bits 0 Type rw Reset Value 0x0 Enable FTM Description

Register (ftm) FTMSTATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMSTATUS 0x00000004 0xF880B004 8 bits ro 0x00000082 FTM Status Register

Register FTMSTATUS Details

Field Name IDLE SPIDEN DBGEN SPNIDEN NIDEN FIFOFULL FIFOEMPTY LOCKED Bits 7 6 5 4 3 2 1 0 Type ro ro ro ro ro ro ro ro Reset Value 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 FTM IDLE Status Trustzone SPIDEN signal status Trustzone DBGEN signal status Trustzone SPNIDEN signal status Trustzone NIDEN signal status 1 = FIFO is full 1 = FIFO is empty Always read as zero Description

Register (ftm) FTMCONTROL

Name Relative Address Absolute Address Width Access Type Reset Value FTMCONTROL 0x00000008 0xF880B008 3 bits rw 0x00000000

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Appendix B: Register Details

Description

FTM Configuration

Register FTMCONTROL Details

Field Name CYCEN TRACEN PROG Bits 2 1 0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Enable Cycle Count packets Enable Trace packets Not used

Register (ftm) FTMP2FDBG0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMP2FDBG0 0x0000000C 0xF880B00C 8 bits rw 0x00000000 FPGA Debug Register P2F0

Register FTMP2FDBG0 Details

Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.

Register (ftm) FTMP2FDBG1

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMP2FDBG1 0x00000010 0xF880B010 8 bits rw 0x00000000 FPGA Debug Register P2F1

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Appendix B: Register Details

Register FTMP2FDBG1 Details

Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.

Register (ftm) FTMP2FDBG2

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMP2FDBG2 0x00000014 0xF880B014 8 bits rw 0x00000000 FPGA Debug Register P2F2

Register FTMP2FDBG2 Details

Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.

Register (ftm) FTMP2FDBG3

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMP2FDBG3 0x00000018 0xF880B018 8 bits rw 0x00000000 FPGA Debug Register P2F3

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Appendix B: Register Details

Register FTMP2FDBG3 Details

Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.

Register (ftm) FTMF2PDBG0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMF2PDBG0 0x0000001C 0xF880B01C 8 bits ro 0x00000000 FPGA Debug Register F2P0

Register FTMF2PDBG0 Details

Field Name FPGA2PSS Bits 7:0 Type ro Reset Value 0x0 Description Signals that are presented to the PSS from the Fabric.

Register (ftm) FTMF2PDBG1

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMF2PDBG1 0x00000020 0xF880B020 8 bits ro 0x00000000 FPGA Debug Register F2P1

Register FTMF2PDBG1 Details

Field Name FPGA2PSS Bits 7:0 Type ro Reset Value 0x0 Description Signals that are presented to the PSS from the Fabric.

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Appendix B: Register Details

Register (ftm) FTMF2PDBG2

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMF2PDBG2 0x00000024 0xF880B024 8 bits ro 0x00000000 FPGA Debug Register F2P2

Register FTMF2PDBG2 Details

Field Name FPGA2PSS Bits 7:0 Type ro Reset Value 0x0 Description Signals that are presented to the PSS from the Fabric.

Register (ftm) FTMF2PDBG3

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMF2PDBG3 0x00000028 0xF880B028 8 bits ro 0x00000000 FPGA Debug Register F2P3

Register FTMF2PDBG3 Details

Field Name FPGA2PSS Bits 7:0 Type ro Reset Value 0x0 Description Signals that are presented to the PSS from the Fabric.

Register (ftm) CYCOUNTPRE

Name Relative Address Absolute Address Width Access Type Reset Value CYCOUNTPRE 0x0000002C 0xF880B02C 4 bits rw 0x00000000

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Appendix B: Register Details

Description

AXI Cycle Count clock pre-scaler

Register CYCOUNTPRE Details

Field Name PRESCALE Bits 3:0 Type rw Reset Value 0x0 Description The incoming clock is divided by 2^ PRESCALE. For example: PRESCALE = 15 indicates that the Cycle Counter runs at the AXI clock divided by 2^15 = 32,768 (PRESCALE = 0 indicates no clock scaling)

Register (ftm) FTMSYNCRELOAD

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMSYNCRELOAD 0x00000030 0xF880B030 12 bits rw 0x00000000 FTM Synchronization Counter reload value

Register FTMSYNCRELOAD Details

Field Name SYNCCOUNTTERM Bits 11:0 Type rw Reset Value 0x0 Description Reset FTM Synchronization packet counter when this number of packets has been transmitted. THIS NUMBER HAS A MINIMUM VALUE of 12.

Register (ftm) FTMSYNCCOUT

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMSYNCCOUT 0x00000034 0xF880B034 12 bits ro 0x00000000 FTM Synchronization Counter value

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Appendix B: Register Details

Register FTMSYNCCOUT Details

Field Name SYNCCOUT Bits 11:0 Type ro Reset Value 0x0 Description Current value of the Synchronization packet counter. The initial value is zero. The counter value increments every time a packet is issued by the FTM. When the counter reaches SYNCCOUNTTERM, a Synchronization packet is emitted.

Register (ftm) FTMATID

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMATID 0x00000400 0xF880B400 7 bits rw 0x00000000 FTM ATID Value Register

Register FTMATID Details

Field Name ATID Bits 6:0 Type rw Reset Value 0x0 Description ATID value supplied to ATB bus. The upper three bits, ATID[6:4], are directly driven from this register. The lower four bits, ATID[3:0], are OR-ed with the FPGAATID[3:0] pins.

Register (ftm) FTMITTRIGOUTACK

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITTRIGOUTACK 0x00000ED0 0xF880BED0 4 bits ro 0x00000000 Trigger Output Acknowledge Integration Test Register

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Appendix B: Register Details

Register FTMITTRIGOUTACK Details

Field Name TRIGACK Bits 3:0 Type ro Reset Value 0x0 Description Read the current value of the FTMTrigOutAck[3:0] inputs

Register (ftm) FTMITTRIGGER

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITTRIGGER 0x00000ED4 0xF880BED4 4 bits wo 0x00000000 Trigger Output Integration Test Register

Register FTMITTRIGGER Details

Field Name TRIGGER Bits 3:0 Type wo Reset Value 0x0 Description When ITEN is 1, this field determines the FTMTrigOut[3:0]

Register (ftm) FTMITTRACEDIS

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITTRACEDIS 0x00000ED8 0xF880BED8 1 bits ro 0x00000000 External Trace Disable Integration Test Register

Register FTMITTRACEDIS Details

Field Name TRACEDIS Bits 0 Type ro Reset Value 0x0 Description Always read as zero.

Register (ftm) FTMITCYCCOUNT

Name FTMITCYCCOUNT

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000EDC 0xF880BEDC 32 bits rw 0x00000001 Cycle Counter Test Register

Register FTMITCYCCOUNT Details

Field Name FTMCYCCOUNT Bits 31:0 Type rw Reset Value 0x1 Description Read/write the value of the cycle counter

Register (ftm) FTMITATBDATA0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITATBDATA0 0x00000EEC 0xF880BEEC 5 bits wo 0x00000000 ATB Data Integration Test Register 0

Register FTMITATBDATA0 Details

Field Name ATDATA31 ATDATA23 ATDATA15 ATDATA7 ATDATA0 Bits 4 3 2 1 0 Type wo wo wo wo wo Reset Value 0x0 0x0 0x0 0x0 0x0 Description When ITEN is 1, this value determines the ATDATAM[31] output When ITEN is 1, this value determines the ATDATAM[23] output When ITEN is 1, this value determines the ATDATAM[15] output When ITEN is 1, this value determines the ATDATAM[7] output When ITEN is 1, this value determines the ATDATAM[0] output

Register (ftm) FTMITATBCTR2

Name Relative Address FTMITATBCTR2 0x00000EF0

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

0xF880BEF0 2 bits ro 0x00000001 ATB Control Integration Test Register 2

Register FTMITATBCTR2 Details

Field Name AFVALID ATREADY Bits 1 0 Type ro ro Reset Value 0x0 0x1 Description Read the current value of the AFVALIDM input Read the current value of the ATREADYM input

Register (ftm) FTMITATBCTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITATBCTR1 0x00000EF4 0xF880BEF4 7 bits rw 0x00000000 ATB Control Integration Test Register 1

Register FTMITATBCTR1 Details

Field Name ATID_test Bits 6:0 Type rw Reset Value 0x0 Description When ITEN is 1, this value determines the ATID output

Register (ftm) FTMITATBCTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITATBCTR0 0x00000EF8 0xF880BEF8 10 bits wo 0x00000000 ATB Control Integration Test Register 0

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Appendix B: Register Details

Register FTMITATBCTR0 Details

Field Name ATBYTES reserved AFREADY ATVALID Bits 9:8 7:2 1 0 Type wo wo wo wo Reset Value 0x0 0x0 0x0 0x0 Description When ITEN is 1, this value determines the ATBYTESM[1:0] output Reserved When ITEN is 1, this value determines the AFREADY output When ITEN is 1, this value determines the ATVALID output

Register (ftm) FTMITCR

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMITCR 0x00000F00 0xF880BF00 1 bits rw 0x00000000 FTM Test Control Register

Register FTMITCR Details

Field Name ITEN Bits 0 Type rw Reset Value 0x0 Description Integration Test Enable

Register (ftm) CLAIMTAGSET

Name Relative Address Absolute Address Width Access Type Reset Value Description CLAIMTAGSET 0x00000FA0 0xF880BFA0 8 bits rw 0x000000FF Claim Tag Set Register

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Appendix B: Register Details

Register CLAIMTAGSET Details

Field Name CLAIMTAGSETVAL Bits 7:0 Type rw Reset Value 0xFF Description Read: 1 = Claim tag implemented, 0 = not implemented Write: 1 = Set claim tag bit, 0 = no effect

Register (ftm) CLAIMTAGCLR

Name Relative Address Absolute Address Width Access Type Reset Value Description CLAIMTAGCLR 0x00000FA4 0xF880BFA4 8 bits rw 0x000000FF Claim Tag Clear Register

Register CLAIMTAGCLR Details

Field Name CLAIMTAGCLRVAL Bits 7:0 Type rw Reset Value 0xFF Description Read: value of CLAIMTAGSETVAL Write: 1 = Clear claim tag bit, 0 = no effect

Register (ftm) LOCK_ACCESS

Name Relative Address Absolute Address Width Access Type Reset Value Description LOCK_ACCESS 0x00000FB0 0xF880BFB0 32 bits wo 0x00000000 Lock Access Register

Register LOCK_ACCESS Details

Field Name LOCKACCESS Bits 31:0 Type wo Reset Value 0x0 Description A value of 0xC5ACCE55 allows write access to FTM, any other value blocks write access

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Appendix B: Register Details

Register (ftm) LOCK_STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description LOCK_STATUS 0x00000FB4 0xF880BFB4 3 bits ro 0x00000003 Lock Status Register

Register LOCK_STATUS Details

Field Name 8BITACCESS LOCKSTATUS LOCKIMP Bits 2 1 0 Type ro ro ro Reset Value 0x0 0x1 0x1 Description 8-bit lock access is not used 1:Access Locked, 0:Access OK 1:Lock exists if PADDRDBG31 is low, else 0

Register (ftm) FTMAUTHSTATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMAUTHSTATUS 0x00000FB8 0xF880BFB8 8 bits ro 0x00000088 Authentication Status Register

Register FTMAUTHSTATUS Details

Field Name AUTH_SPNIDEN reserved AUTH_NIDEN reserved Bits 7:6 5:4 3:2 1:0 Type ro ro ro ro Reset Value 0x2 0x0 0x2 0x0 Description Secure Non-Invasive Debug Secure Invasive Debug Non-Secure Non-Invasive Debug Non-Secure Invasive Debug

Register (ftm) FTMDEVID

Name Relative Address FTMDEVID 0x00000FC8

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

0xF880BFC8 1 bits ro 0x00000000 Device Configuration Register

Register FTMDEVID Details

Field Name reserved Bits 0 Type ro Reset Value 0x0 Reserved Description

Register (ftm) FTMDEV_TYPE

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMDEV_TYPE 0x00000FCC 0xF880BFCC 8 bits ro 0x00000033 Device Type Identification Register

Register FTMDEV_TYPE Details

Field Name SubType MajorType Bits 7:4 3:0 Type ro ro Reset Value 0x3 0x3 Description Sub Type: Associated with a Data Engine or Co-processor Major Type: Trace Source

Register (ftm) FTMPERIPHID4

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID4 0x00000FD0 0xF880BFD0 8 bits ro 0x00000000 Peripheral ID4

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Appendix B: Register Details

Register FTMPERIPHID4 Details

Field Name 4KBCount JEP106 Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 4KB Count JEP106 Continuation Code Description

Register (ftm) FTMPERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID5 0x00000FD4 0xF880BFD4 8 bits ro 0x00000000 Peripheral ID5

Register FTMPERIPHID5 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (ftm) FTMPERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID6 0x00000FD8 0xF880BFD8 8 bits ro 0x00000000 Peripheral ID6

Register FTMPERIPHID6 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (ftm) FTMPERIPHID7

Name FTMPERIPHID7

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FDC 0xF880BFDC 8 bits ro 0x00000000 Peripheral ID7

Register FTMPERIPHID7 Details

Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Reserved Description

Register (ftm) FTMPERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID0 0x00000FE0 0xF880BFE0 8 bits ro 0x00000001 Peripheral ID0

Register FTMPERIPHID0 Details

Field Name PARTNUMLOWER Bits 7:0 Type ro Reset Value 0x1 Description Part Number Lower

Register (ftm) FTMPERIPHID1

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID1 0x00000FE4 0xF880BFE4 8 bits ro 0x00000090 Peripheral ID1

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Appendix B: Register Details

Register FTMPERIPHID1 Details

Field Name JEP106 PARTNUMUPPER Bits 7:4 3:0 Type ro ro Reset Value 0x9 0x0 Description JEP106 identity bits [3:0] Part Number Upper [11:8]

Register (ftm) FTMPERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID2 0x00000FE8 0xF880BFE8 8 bits ro 0x0000000C Peripheral ID2

Register FTMPERIPHID2 Details

Field Name REVISION JEDEC JEP106 Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x0 0x1 0x4 Revision JEDEC used JEP106 Identity [6:4] Description

Register (ftm) FTMPERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMPERIPHID3 0x00000FEC 0xF880BFEC 8 bits ro 0x00000000 Peripheral ID3

Register FTMPERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 RevAnd Customer Modified Description

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Appendix B: Register Details

Register (ftm) FTMCOMPONID0

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMCOMPONID0 0x00000FF0 0xF880BFF0 8 bits ro 0x0000000D Component ID0

Register FTMCOMPONID0 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (ftm) FTMCOMPONID1

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMCOMPONID1 0x00000FF4 0xF880BFF4 8 bits ro 0x00000090 Component ID1

Register FTMCOMPONID1 Details

Field Name CompClass Preamble Bits 7:4 3:0 Type ro ro Reset Value 0x9 0x0 Description Component Class :CoreSight Component Preamble

Register (ftm) FTMCOMPONID2

Name Relative Address Absolute Address Width Access Type Reset Value FTMCOMPONID2 0x00000FF8 0xF880BFF8 8 bits ro 0x00000005

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Appendix B: Register Details

Description

Component ID2

Register FTMCOMPONID2 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (ftm) FTMCOMPONID3

Name Relative Address Absolute Address Width Access Type Reset Value Description FTMCOMPONID3 0x00000FFC 0xF880BFFC 8 bits ro 0x000000B1 Component ID3

Register FTMCOMPONID3 Details

Field Name Preamble Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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Appendix B: Register Details

B.13 CoreSight Trace Funnel (funnel)

Module Name Base Address Description Vendor Info CoreSight Trace Funnel (funnel) 0xF8804000 debug_funnel CoreSight Trace Funnel

Register Summary
Register Name Control PriControl ITATBDATA0 ITATBCTR2 ITATBCTR1 ITATBCTR0 IMCR CTSR CTCR LAR LSR ASR DEVID DTIR PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 Address 0x00000000 0x00000004 0x00000EEC 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 Width 12 24 5 2 7 10 1 4 4 32 3 8 8 8 8 8 8 8 8 8 8 Type rw rw rw rw rw mixed rw rw rw wo ro ro ro ro ro ro ro ro ro ro ro Reset Value 0x00000300 0x00FAC688 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000000F 0x00000000 0x00000000 0x00000003 0x00000000 0x00000028 0x00000012 0x00000004 0x00000000 0x00000000 0x00000000 0x00000008 0x000000B9 0x0000001B Description CSTF Control Register CSTF Priority Control Register Integration Test ATB Data 0 Register Integration Test ATB Control 2 Register Integration Test ATB Control 1 Register Integration Test ATB Control 0 Register Integration Mode Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID Device Type Identifier Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2

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Appendix B: Register Details

Register Name PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 8 8 8 8 8

Type ro ro ro ro ro

Reset Value 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (funnel) Control

Name Relative Address Absolute Address Width Access Type Reset Value Description Control 0x00000000 0xF8804000 12 bits rw 0x00000300 CSTF Control Register

Register Control Details

Field Name MinHoldTime Bits 11:8 Type rw Reset Value 0x3 Description The formatting scheme can easily become inefficient if fast switching occurs, so, where possible, this must be minimized. If a source has nothing to transmit, then another source is selected irrespective of the minimum number of cycles. Reset is 0x3. The CSTF holds for the minimum hold time and one additional cycle. The mFunnelum value that can be entered is 0xE and this equates to 15 cycles. 0xF is reserved. EnableSlave7 7 rw 0x0 Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.

EnableSlave6

rw

0x0

EnableSlave5

rw

0x0

EnableSlave4

rw

0x0

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Appendix B: Register Details

Field Name EnableSlave3

Bits 3

Type rw

Reset Value 0x0

Description Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme.

EnableSlave2

rw

0x0

EnableSlave1

rw

0x0

EnableSlave0

rw

0x0

Register (funnel) PriControl

Name Relative Address Absolute Address Width Access Type Reset Value Description PriControl 0x00000004 0xF8804004 24 bits rw 0x00FAC688 CSTF Priority Control Register

Register PriControl Details

Field Name PriPort7 PriPort6 PriPort5 PriPort4 PriPort3 PriPort2 PriPort1 PriPort0 Bits 23:21 20:18 17:15 14:12 11:9 8:6 5:3 2:0 Type rw rw rw rw rw rw rw rw Reset Value 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Description 8th port priority value. 7th port priority value. 6th port priority value. 5th port priority value. 4th port priority value. 3rd port priority value. 2nd port priority value. 1st port priority value.

Register (funnel) ITATBDATA0

Name Relative Address ITATBDATA0 0x00000EEC

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Absolute Address Width Access Type Reset Value Description

0xF8804EEC 5 bits rw 0x00000000 Integration Test ATB Data 0 Register

Register ITATBDATA0 Details

Field Name ATDATA31 ATDATA23 ATDATA15 ATDATA7 ATDATA0 Bits 4 3 2 1 0 Type rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 Description Read the value of ATDATAS[31], set the value of ATDATAM[31] Read the value of ATDATAS[23], set the value of ATDATAM[23] Read the value of ATDATAS[15], set the value of ATDATAM[15] Read the value of ATDATAS[7], set the value of ATDATAM[7] Read the value of ATDATAS[0], set the value of ATDATAM[0]

Register (funnel) ITATBCTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR2 0x00000EF0 0xF8804EF0 2 bits rw 0x00000000 Integration Test ATB Control 2 Register

Register ITATBCTR2 Details

Field Name AFREADY Bits 1 Type rw Reset Value 0x0 Description Read the value of AFVALIDM. Set the value of AFVALIDS<n>, where <n> is defined by the status of the CSTF Control Register. Read the value of ATREADYM. Set the value of ATREADYS<n>, where <n> is defined by the status of the CSTF Control Register.

rw

0x0

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Appendix B: Register Details

Register (funnel) ITATBCTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR1 0x00000EF4 0xF8804EF4 7 bits rw 0x00000000 Integration Test ATB Control 1 Register

Register ITATBCTR1 Details

Field Name ATID Bits 6:0 Type rw Reset Value 0x0 Description Read the value of ATIDS. Set the value of ATIDM.

Register (funnel) ITATBCTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR0 0x00000EF8 0xF8804EF8 10 bits mixed 0x00000000 Integration Test ATB Control 0 Register

Register ITATBCTR0 Details

Field Name ATBYTES reserved AFREADY ATVALID Bits 9:8 7:2 1 0 Type rw ro rw rw Reset Value 0x0 0x0 0x0 0x0 Description Read the value of ATBYTESS<n>. Set the value of ATBYTESM. Reserved Read the value of AFREADYS<n>. Set the value of AFREADYM. Read the value of ATVALIDS<n>. Set the value of ATVALIDM.

Register (funnel) IMCR

Name Relative Address IMCR 0x00000F00

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

0xF8804F00 1 bits rw 0x00000000 Integration Mode Control Register

Register IMCR Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers.

Register (funnel) CTSR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTSR 0x00000FA0 0xF8804FA0 4 bits rw 0x0000000F Claim Tag Set Register

Register CTSR Details

Field Name Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (funnel) CTCR

Name Relative Address Absolute Address Width Access Type CTCR 0x00000FA4 0xF8804FA4 4 bits rw

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Appendix B: Register Details

Reset Value Description

0x00000000 Claim Tag Clear Register

Register CTCR Details

Field Name Bits 3:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

Register (funnel) LAR

Name Relative Address Absolute Address Width Access Type Reset Value Description LAR 0x00000FB0 0xF8804FB0 32 bits wo 0x00000000 Lock Access Register

Register LAR Details

Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), Funnel is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): Funnel is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

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Register (funnel) LSR

Name Relative Address Absolute Address Width Access Type Reset Value Description LSR 0x00000FB4 0xF8804FB4 3 bits ro 0x00000003 Lock Status Register

Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since Funnel implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether Funnel is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (funnel) ASR

Name Relative Address Absolute Address Width Access Type Reset Value Description ASR 0x00000FB8 0xF8804FB8 8 bits ro 0x00000000 Authentication Status Register

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Appendix B: Register Details

Register ASR Details

Field Name Bits 7:0 Type ro Reset Value 0x0 Description Indicates functionality not implemented

Register (funnel) DEVID

Name Relative Address Absolute Address Width Access Type Reset Value Description DEVID 0x00000FC8 0xF8804FC8 8 bits ro 0x00000028 Device ID

Register DEVID Details

Field Name StaticPrio NumInPorts Bits 7:4 3:0 Type ro ro Reset Value 0x2 0x8 Description CSTF implements a static priority scheme Number of input ports

Register (funnel) DTIR

Name Relative Address Absolute Address Width Access Type Reset Value Description DTIR 0x00000FCC 0xF8804FCC 8 bits ro 0x00000012 Device Type Identifier Register

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x12 Description a trace link and specifically a funnel/router

Register (funnel) PERIPHID4

Name PERIPHID4

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FD0 0xF8804FD0 8 bits ro 0x00000004 Peripheral ID4

Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (funnel) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 0xF8804FD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (funnel) PERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID6 0x00000FD8 0xF8804FD8 8 bits ro 0x00000000 Peripheral ID6

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Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (funnel) PERIPHID7

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID7 0x00000FDC 0xF8804FDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (funnel) PERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID0 0x00000FE0 0xF8804FE0 8 bits ro 0x00000008 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x8 PartNumber0 Description

Register (funnel) PERIPHID1

Name Relative Address PERIPHID1 0x00000FE4

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Absolute Address Width Access Type Reset Value Description

0xF8804FE4 8 bits ro 0x000000B9 Peripheral ID1

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (funnel) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 0xF8804FE8 8 bits ro 0x0000001B Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x1 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (funnel) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC 0xF8804FEC 8 bits ro 0x00000000 Peripheral ID3

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Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

Register (funnel) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 0xF8804FF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (funnel) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID1 0x00000FF4 0xF8804FF4 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (funnel) COMPID2

Name COMPID2

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FF8 0xF8804FF8 8 bits ro 0x00000005 Component ID2

Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (funnel) COMPID3

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID3 0x00000FFC 0xF8804FFC 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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B.14 CoreSight Intstrumentation Trace Macrocell (itm)

Module Name Base Address Description Vendor Info CoreSight Intstrumentation Trace Macrocell (itm) 0xF8805000 debug_itm Instrumentation Trace Macrocell

Register Summary
Register Name StimPort00 StimPort01 StimPort02 StimPort03 StimPort04 StimPort05 StimPort06 StimPort07 StimPort08 StimPort09 StimPort10 StimPort11 StimPort12 StimPort13 StimPort14 StimPort15 StimPort16 StimPort17 StimPort18 StimPort19 StimPort20 StimPort21 StimPort22 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000050 0x00000054 0x00000058 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description Stimulus Port Register 0 Stimulus Port Register 1 Stimulus Port Register 2 Stimulus Port Register 3 Stimulus Port Register 4 Stimulus Port Register 5 Stimulus Port Register 6 Stimulus Port Register 7 Stimulus Port Register 8 Stimulus Port Register 9 Stimulus Port Register 10 Stimulus Port Register 11 Stimulus Port Register 12 Stimulus Port Register 13 Stimulus Port Register 14 Stimulus Port Register 15 Stimulus Port Register 16 Stimulus Port Register 17 Stimulus Port Register 18 Stimulus Port Register 19 Stimulus Port Register 20 Stimulus Port Register 21 Stimulus Port Register 22

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Register Name StimPort23 StimPort24 StimPort25 StimPort26 StimPort27 StimPort28 StimPort29 StimPort30 StimPort31 TER TTR CR SCR ITTRIGOUTACK ITTRIGOUT ITATBDATA0 ITATBCTR2 ITATABCTR1 ITATBCTR0 IMCR CTSR CTCR LAR LSR ASR DEVID DTIR PERIPHID4 PERIPHID5

Address 0x0000005C 0x00000060 0x00000064 0x00000068 0x0000006C 0x00000070 0x00000074 0x00000078 0x0000007C 0x00000E00 0x00000E20 0x00000E80 0x00000E90 0x00000EE4 0x00000EE8 0x00000EEC 0x00000EF0 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4

Width 32 32 32 32 32 32 32 32 32 32 32 24 12 1 1 2 1 7 2 1 8 8 32 3 8 13 8 8 8

Type rw rw rw rw rw rw rw rw rw rw rw mixed rw ro wo wo ro wo wo rw rw rw wo ro ro ro ro ro ro

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000004 0x00000400 0x00000000 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x00000003 0x00000088 0x00000020 0x00000043 0x00000004 0x00000000

Description Stimulus Port Register 23 Stimulus Port Register 24 Stimulus Port Register 25 Stimulus Port Register 26 Stimulus Port Register 27 Stimulus Port Register 28 Stimulus Port Register 29 Stimulus Port Register 30 Stimulus Port Register 31 Trace Enable Register Trace Trigger Register Control Register Synchronization Control Register Integration Test Trigger Out Acknowledge Register Integration Test Trigger Out Register Integration Test ATB Data Register 0 Integration Test ATB Control Register 2 Integration Test ATB Control Register 1 Integration Test ATB Control Register 0 Integration Mode Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID Device Type Identifier Register Peripheral ID4 Peripheral ID5

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Register Name PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 8 8 8 8 8 8 8 8 8 8

Type ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000000 0x00000000 0x00000013 0x000000B9 0x0000002B 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Description Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (itm) StimPort00

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort00 0x00000000 0xF8805000 32 bits rw 0x00000000 Stimulus Port Register 0

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Register StimPort00 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort01

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort01 0x00000004 0xF8805004 32 bits rw 0x00000000 Stimulus Port Register 1

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Register StimPort01 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort02

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort02 0x00000008 0xF8805008 32 bits rw 0x00000000 Stimulus Port Register 2

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Register StimPort02 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort03

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort03 0x0000000C 0xF880500C 32 bits rw 0x00000000 Stimulus Port Register 3

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Register StimPort03 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort04

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort04 0x00000010 0xF8805010 32 bits rw 0x00000000 Stimulus Port Register 4

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Register StimPort04 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort05

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort05 0x00000014 0xF8805014 32 bits rw 0x00000000 Stimulus Port Register 5

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Register StimPort05 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort06

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort06 0x00000018 0xF8805018 32 bits rw 0x00000000 Stimulus Port Register 6

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Register StimPort06 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort07

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort07 0x0000001C 0xF880501C 32 bits rw 0x00000000 Stimulus Port Register 7

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Register StimPort07 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort08

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort08 0x00000020 0xF8805020 32 bits rw 0x00000000 Stimulus Port Register 8

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Register StimPort08 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort09

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort09 0x00000024 0xF8805024 32 bits rw 0x00000000 Stimulus Port Register 9

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Register StimPort09 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort10

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort10 0x00000028 0xF8805028 32 bits rw 0x00000000 Stimulus Port Register 10

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Register StimPort10 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort11

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort11 0x0000002C 0xF880502C 32 bits rw 0x00000000 Stimulus Port Register 11

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Register StimPort11 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort12

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort12 0x00000030 0xF8805030 32 bits rw 0x00000000 Stimulus Port Register 12

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Appendix B: Register Details

Register StimPort12 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort13

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort13 0x00000034 0xF8805034 32 bits rw 0x00000000 Stimulus Port Register 13

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Register StimPort13 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort14

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort14 0x00000038 0xF8805038 32 bits rw 0x00000000 Stimulus Port Register 14

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Appendix B: Register Details

Register StimPort14 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort15

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort15 0x0000003C 0xF880503C 32 bits rw 0x00000000 Stimulus Port Register 15

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Register StimPort15 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort16

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort16 0x00000040 0xF8805040 32 bits rw 0x00000000 Stimulus Port Register 16

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Appendix B: Register Details

Register StimPort16 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort17

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort17 0x00000044 0xF8805044 32 bits rw 0x00000000 Stimulus Port Register 17

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Register StimPort17 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort18

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort18 0x00000048 0xF8805048 32 bits rw 0x00000000 Stimulus Port Register 18

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Register StimPort18 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort19

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort19 0x0000004C 0xF880504C 32 bits rw 0x00000000 Stimulus Port Register 19

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Register StimPort19 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort20

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort20 0x00000050 0xF8805050 32 bits rw 0x00000000 Stimulus Port Register 20

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Register StimPort20 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort21

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort21 0x00000054 0xF8805054 32 bits rw 0x00000000 Stimulus Port Register 21

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Register StimPort21 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort22

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort22 0x00000058 0xF8805058 32 bits rw 0x00000000 Stimulus Port Register 22

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Appendix B: Register Details

Register StimPort22 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort23

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort23 0x0000005C 0xF880505C 32 bits rw 0x00000000 Stimulus Port Register 23

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Register StimPort23 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort24

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort24 0x00000060 0xF8805060 32 bits rw 0x00000000 Stimulus Port Register 24

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Appendix B: Register Details

Register StimPort24 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort25

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort25 0x00000064 0xF8805064 32 bits rw 0x00000000 Stimulus Port Register 25

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Appendix B: Register Details

Register StimPort25 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort26

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort26 0x00000068 0xF8805068 32 bits rw 0x00000000 Stimulus Port Register 26

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Appendix B: Register Details

Register StimPort26 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort27

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort27 0x0000006C 0xF880506C 32 bits rw 0x00000000 Stimulus Port Register 27

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Register StimPort27 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort28

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort28 0x00000070 0xF8805070 32 bits rw 0x00000000 Stimulus Port Register 28

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Register StimPort28 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort29

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort29 0x00000074 0xF8805074 32 bits rw 0x00000000 Stimulus Port Register 29

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Register StimPort29 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort30

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort30 0x00000078 0xF8805078 32 bits rw 0x00000000 Stimulus Port Register 30

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Register StimPort30 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) StimPort31

Name Relative Address Absolute Address Width Access Type Reset Value Description StimPort31 0x0000007C 0xF880507C 32 bits rw 0x00000000 Stimulus Port Register 31

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Register StimPort31 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled. This enables more efficient core register allocation because the stimulus address has already been generated. The ITM transmits SWIT packets using leading zero compression. Packets can be 8, 16, or 32 bits. The bank of 32 registers is split into a low-16 (0 to 15) and a high-16 (16 to 31). Writes to the high-16 are discarded by the ITM whenever secure non-invasive trace is disabled, regardless of how the Trace Enable Register bits [31:16] are set. Both the high-16 and low-16 are be disabled when non-invasive trace is disabled. When an input is disabled it must not alter the interface response and must always return an OK without stalling.

Register (itm) TER

Name Relative Address Absolute Address Width Access Type Reset Value Description TER 0x00000E00 0xF8805E00 32 bits rw 0x00000000 Trace Enable Register

Register TER Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Bit mask to enable tracing on ITM stimulus ports.

Register (itm) TTR

Name Relative Address TTR 0x00000E20

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Absolute Address Width Access Type Reset Value Description

0xF8805E20 32 bits rw 0x00000000 Trace Trigger Register

Register TTR Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Bit mask to enable trigger generation, TRIGOUT, on selected writes to the Stimulus Registers.

Register (itm) CR
Name Relative Address Absolute Address Width Access Type Reset Value Description CR 0x00000E80 0xF8805E80 24 bits mixed 0x00000004 Control Register

Register CR Details
Field Name ITMBusy TraceID reserved TSPrescale Bits 23 22:16 15:10 9:8 Type rw rw ro rw Reset Value 0x0 0x0 0x0 0x0 Description ITM is transmitting trace and FIFO is not empty ATIDM[6:0] value Reserved Timestamp Prescaler Enumerated Value List: DIVBY1=0. DIVBY4=1. DIVBY16=2. DIVBY64=3. reserved DWTEn SYNCEn TSSEn ITMEn 7:4 3 2 1 0 ro ro ro rw rw 0x0 0x0 0x1 0x0 0x0 Reserved Enable DWT input port Enable sync packets Enable timestamps, delta Enable ITM Stimulus, also acts as a global enable

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Register (itm) SCR

Name Relative Address Absolute Address Width Access Type Reset Value Description SCR 0x00000E90 0xF8805E90 12 bits rw 0x00000400 Synchronization Control Register

Register SCR Details

Field Name SyncCount Bits 11:0 Type rw Reset Value 0x400 Description Counter value for time between synchronization markers

Register (itm) ITTRIGOUTACK

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRIGOUTACK 0x00000EE4 0xF8805EE4 1 bits ro 0x00000000 Integration Test Trigger Out Acknowledge Register

Register ITTRIGOUTACK Details

Field Name ITTRIGOUTACK Bits 0 Type ro Reset Value 0x0 Description Read the value of TRIGOUTACK

Register (itm) ITTRIGOUT

Name Relative Address Absolute Address Width Access Type Reset Value ITTRIGOUT 0x00000EE8 0xF8805EE8 1 bits wo 0x00000000

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Appendix B: Register Details

Description

Integration Test Trigger Out Register

Register ITTRIGOUT Details

Field Name ITTRIGOUT Bits 0 Type wo Reset Value 0x0 Description Set the value of TRIGOUT

Register (itm) ITATBDATA0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBDATA0 0x00000EEC 0xF8805EEC 2 bits wo 0x00000000 Integration Test ATB Data Register 0

Register ITATBDATA0 Details

Field Name ITATDATAM7 ITATDATAM0 Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of ATDATAM[7] Set the value of ATDATAM[0]

Register (itm) ITATBCTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR2 0x00000EF0 0xF8805EF0 1 bits ro 0x00000001 Integration Test ATB Control Register 2

Register ITATBCTR2 Details

Field Name ITATREADYM Bits 0 Type ro Reset Value 0x1 Description Read the value of ATREADYM

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Register (itm) ITATABCTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATABCTR1 0x00000EF4 0xF8805EF4 7 bits wo 0x00000000 Integration Test ATB Control Register 1

Register ITATABCTR1 Details

Field Name ITATIDM Bits 6:0 Type wo Reset Value 0x0 Description Set the value of ATIDM[6:0]

Register (itm) ITATBCTR0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR0 0x00000EF8 0xF8805EF8 2 bits wo 0x00000000 Integration Test ATB Control Register 0

Register ITATBCTR0 Details

Field Name ITAFREADYM ITATVALIDM Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of AFREADYM Set the value of ATVALIDM

Register (itm) IMCR

Name Relative Address Absolute Address Width Access Type Reset Value IMCR 0x00000F00 0xF8805F00 1 bits rw 0x00000000

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Appendix B: Register Details

Description

Integration Mode Control Register

Register IMCR Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers.

Register (itm) CTSR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTSR 0x00000FA0 0xF8805FA0 8 bits rw 0x000000FF Claim Tag Set Register

Register CTSR Details

Field Name Bits 7:0 Type rw Reset Value 0xFF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (itm) CTCR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTCR 0x00000FA4 0xF8805FA4 8 bits rw 0x00000000 Claim Tag Clear Register

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Register CTCR Details

Field Name Bits 7:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

Register (itm) LAR

Name Relative Address Absolute Address Width Access Type Reset Value Description LAR 0x00000FB0 0xF8805FB0 32 bits wo 0x00000000 Lock Access Register

Register LAR Details

Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), ITM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): ITM is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

Register (itm) LSR

Name LSR

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Appendix B: Register Details

Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FB4 0xF8805FB4 3 bits ro 0x00000003 Lock Status Register

Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since ITM implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether ITM is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (itm) ASR

Name Relative Address Absolute Address Width Access Type Reset Value Description ASR 0x00000FB8 0xF8805FB8 8 bits ro 0x00000088 Authentication Status Register

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Register ASR Details

Field Name Bits 7:0 Type ro Reset Value 0x88 Description Value is 0b1S001N00 where S is secure non-invasive debug state and N is non-secure, non-invasive debug.

Register (itm) DEVID

Name Relative Address Absolute Address Width Access Type Reset Value Description DEVID 0x00000FC8 0xF8805FC8 13 bits ro 0x00000020 Device ID

Register DEVID Details

Field Name NumStimRegs Bits 12:0 Type ro Reset Value 0x20 Description Number of stimulus registers

Register (itm) DTIR

Name Relative Address Absolute Address Width Access Type Reset Value Description DTIR 0x00000FCC 0xF8805FCC 8 bits ro 0x00000043 Device Type Identifier Register

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x43 Description Indicates a Trace Source and the stimulus is devifed from bus activity

Register (itm) PERIPHID4

Name PERIPHID4

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FD0 0xF8805FD0 8 bits ro 0x00000004 Peripheral ID4

Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (itm) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 0xF8805FD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (itm) PERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID6 0x00000FD8 0xF8805FD8 8 bits ro 0x00000000 Peripheral ID6

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Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (itm) PERIPHID7

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID7 0x00000FDC 0xF8805FDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (itm) PERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID0 0x00000FE0 0xF8805FE0 8 bits ro 0x00000013 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x13 PartNumber0 Description

Register (itm) PERIPHID1

Name Relative Address PERIPHID1 0x00000FE4

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Absolute Address Width Access Type Reset Value Description

0xF8805FE4 8 bits ro 0x000000B9 Peripheral ID1

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (itm) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 0xF8805FE8 8 bits ro 0x0000002B Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x2 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (itm) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC 0xF8805FEC 8 bits ro 0x00000000 Peripheral ID3

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Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

Register (itm) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 0xF8805FF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (itm) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID1 0x00000FF4 0xF8805FF4 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (itm) COMPID2

Name COMPID2

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FF8 0xF8805FF8 8 bits ro 0x00000005 Component ID2

Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (itm) COMPID3

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID3 0x00000FFC 0xF8805FFC 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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Appendix B: Register Details

B.15 CoreSight Trace Packet Output (tpiu)

Module Name Base Address Description Vendor Info CoreSight Trace Packet Output (tpiu) 0xF8803000 debug_tpiu Trace Port Interface Unit

Register Summary
Register Name SuppSize CurrentSize SuppTrigMode TrigCount TrigMult SuppTest CurrentTest TestRepeatCount FFSR FFCR FormatSyncCount EXTCTLIn EXTCTLOut ITTRFLINACK ITTRFLIN ITATBDATA0 ITATBCTR2 Address 0x00000000 0x00000004 0x00000100 0x00000104 0x00000108 0x00000200 0x00000204 0x00000208 0x00000300 0x00000304 0x00000308 0x00000400 0x00000404 0x00000EE4 0x00000EE8 0x00000EEC 0x00000EF0 Width 32 32 18 8 5 18 18 8 3 14 12 8 8 2 2 5 2 Type rw rw ro rw rw ro mixed rw ro mixed rw ro rw wo ro ro wo Reset Value 0xFFFFFFFF 0x00000001 0x0000011F 0x00000000 0x00000000 0x0003000F 0x00000000 0x00000000 0x00000006 0x00000000 0x00000040 0x00000000 0x00000000 0x00000000 x x 0x00000000 Description Supported Port Size Register Current Port Size Register Supported Trigger Modes Register Trigger Counter Register Trigger Multiplier Register Supported Test Patterns/Modes Register Current Test Patterns/Modes Register TPIU Test Pattern Repeat Counter Register Formatter and Flush Status Register Formatter and Flush Control Register Formatter Synchronization Counter Register EXTCTL In Port EXTCTL Out Port Integration Test Trigger In and Flush In Acknowledge Register Integration Test Trigger In and Flush In Register Integration Test ATB Data Register 0 Integration Test ATB Control Register 2

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Register Name ITATBCTR1 ITATBCTR0 IMCR CTSR CTCR LAR LSR ASR DEVID DTIR PERIPHID4 PERIPHID5 PERIPHID6 PERIPHID7 PERIPHID0 PERIPHID1 PERIPHID2 PERIPHID3 COMPID0 COMPID1 COMPID2 COMPID3

Address 0x00000EF4 0x00000EF8 0x00000F00 0x00000FA0 0x00000FA4 0x00000FB0 0x00000FB4 0x00000FB8 0x00000FC8 0x00000FCC 0x00000FD0 0x00000FD4 0x00000FD8 0x00000FDC 0x00000FE0 0x00000FE4 0x00000FE8 0x00000FEC 0x00000FF0 0x00000FF4 0x00000FF8 0x00000FFC

Width 7 10 1 4 4 32 3 8 12 8 8 8 8 8 8 8 8 8 8 8 8 8

Type ro ro rw rw rw wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro x x

Reset Value

Description Integration Test ATB Control Register 1 Integration Test ATB Control Register 0 Integration Mode Control Register Claim Tag Set Register Claim Tag Clear Register Lock Access Register Lock Status Register Authentication Status Register Device ID Device Type Identifier Register Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

0x00000000 0x0000000F 0x00000000 0x00000000 0x00000003 0x00000000 0x000000A0 0x00000011 0x00000004 0x00000000 0x00000000 0x00000000 0x00000012 0x000000B9 0x0000004B 0x00000000 0x0000000D 0x00000090 0x00000005 0x000000B1

Register (tpiu) SuppSize

Name Relative Address Absolute Address Width Access Type Reset Value Description SuppSize 0x00000000 0xF8803000 32 bits rw 0xFFFFFFFF Supported Port Size Register

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Register SuppSize Details

Field Name Bits 31:0 Type rw Reset Value 0xFFFFFFFF Description Each bit location represents a single port size that is supported on the device, that is, 32-1 in bit locations [31:0].

Register (tpiu) CurrentSize

Name Relative Address Absolute Address Width Access Type Reset Value Description CurrentSize 0x00000004 0xF8803004 32 bits rw 0x00000001 Current Port Size Register

Register CurrentSize Details

Field Name Bits 31:0 Type rw Reset Value 0x1 Description The Current Port Size Register has the same format as the Supported Port Sizes register but only one bit is set, and all others must be zero. Writing values with more than one bit set or setting a bit that is not indicated as supported is not supported and causes unpredictable behavior.

Register (tpiu) SuppTrigMode

Name Relative Address Absolute Address Width Access Type Reset Value Description SuppTrigMode 0x00000100 0xF8803100 18 bits ro 0x0000011F Supported Trigger Modes Register

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Register SuppTrigMode Details

Field Name TrgRun Triggered reserved TCount8 reserved Mult64k Mult256 Mult16 Mult4 Mult2 Bits 17 16 15:9 8 7:5 4 3 2 1 0 Type ro ro ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x1 0x0 0x1 0x1 0x1 0x1 0x1 Description Trigger Counter running. A trigger has occurred but the counter is not at zero. A trigger has occurred and the counter has reached zero. Reserved 8-bit wide counter register implemented. Reserved Multiply the Trigger Counter by 65536 supported. Multiply the Trigger Counter by 256 supported. Multiply the Trigger Counter by 16 supported. Multiply the Trigger Counter by 4 supported. Multiply the Trigger Counter by 2 supported.

Register (tpiu) TrigCount

Name Relative Address Absolute Address Width Access Type Reset Value Description TrigCount 0x00000104 0xF8803104 8 bits rw 0x00000000 Trigger Counter Register

Register TrigCount Details

Field Name TrigCount Bits 7:0 Type rw Reset Value 0x0 Description 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted.

Register (tpiu) TrigMult

Name Relative Address Absolute Address Width TrigMult 0x00000108 0xF8803108 5 bits

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Access Type Reset Value Description

rw 0x00000000 Trigger Multiplier Register

Register TrigMult Details

Field Name Mult64k Mult256 Mult16 Mult4 Mult2 Bits 4 3 2 1 0 Type rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 Description Multiply the Trigger Counter by 65536. Multiply the Trigger Counter by 256. Multiply the Trigger Counter by 16. Multiply the Trigger Counter by 4. Multiply the Trigger Counter by 2.

Register (tpiu) SuppTest

Name Relative Address Absolute Address Width Access Type Reset Value Description SuppTest 0x00000200 0xF8803200 18 bits ro 0x0003000F Supported Test Patterns/Modes Register

Register SuppTest Details

Field Name PContEn PTimeEn reserved PatF0 PatA5 PatW0 PatW1 Bits 17 16 15:4 3 2 1 0 Type ro ro ro ro ro ro ro Reset Value 0x1 0x1 0x0 0x1 0x1 0x1 0x1 Description Continuous mode. Timed mode. Reserved FF/00 Pattern AA/55 Pattern Walking 0s Pattern Walking 1s Pattern

Register (tpiu) CurrentTest

Name Relative Address CurrentTest 0x00000204

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Absolute Address Width Access Type Reset Value Description

0xF8803204 18 bits mixed 0x00000000 Current Test Patterns/Modes Register

Register CurrentTest Details

Field Name PContEn PTimeEn reserved PatF0 PatA5 PatW0 PatW1 Bits 17 16 15:4 3 2 1 0 Type rw rw ro rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Continuous mode. Timed mode. Reserved FF/00 Pattern AA/55 Pattern Walking 0s Pattern Walking 1s Pattern

Register (tpiu) TestRepeatCount

Name Relative Address Absolute Address Width Access Type Reset Value Description TestRepeatCount 0x00000208 0xF8803208 8 bits rw 0x00000000 TPIU Test Pattern Repeat Counter Register

Register TestRepeatCount Details

Field Name PattCount Bits 7:0 Type rw Reset Value 0x0 Description 8-bit counter value to indicate the number of TRACECLKIN cycles that a pattern runs for before switching to the next pattern.

Register (tpiu) FFSR

Name Relative Address Absolute Address FFSR 0x00000300 0xF8803300

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Width Access Type Reset Value Description

3 bits ro 0x00000006 Formatter and Flush Status Register

Register FFSR Details

Field Name TCPresent FtStopped Bits 2 1 Type ro ro Reset Value 0x1 0x1 Description If this bit is set then TRACECTL is present. Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH. FlInProg 0 ro 0x0 Flush In Progress. This is an indication of the current state of AFVALIDS.

Register (tpiu) FFCR

Name Relative Address Absolute Address Width Access Type Reset Value Description FFCR 0x00000304 0xF8803304 14 bits mixed 0x00000000 Formatter and Flush Control Register

Register FFCR Details

Field Name StopTrig StopFl Bits 13 12 Type rw rw Reset Value 0x0 0x0 Description Stop the formatter after a Trigger Event is observed. Stop the formatter after a flush completes (return of AFREADYS). This forces the FIFO to drain off any part-completed packets. Reserved Indicates a trigger on Flush completion on AFREADYS being returned. Indicates a trigger on a Trigger Event. Indicates a trigger on TRIGIN being asserted. Reserved

reserved TrigFl TrigEvt TrigIn reserved

11 10 9 8 7

ro rw rw rw ro

0x0 0x0 0x0 0x0 0x0

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Field Name FOnMan

Bits 6

Type rw

Reset Value 0x0

Description Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. Generate a flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs.

FOnTrig

rw

0x0

FOnFlIn reserved EnFCont

4 3:2 1

rw ro rw

0x0 0x0 0x0

Generate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection. Reserved Continuous Formatting, no TRACECTL. Embed in trigger packets and indicate null cycles using Sync packets. Can only be changed when FtStopped is HIGH. Enable Formatting. Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH.

EnFTC

rw

0x0

Register (tpiu) FormatSyncCount

Name Relative Address Absolute Address Width Access Type Reset Value Description FormatSyncCount 0x00000308 0xF8803308 12 bits rw 0x00000040 Formatter Synchronization Counter Register

Register FormatSyncCount Details

Field Name CycCount Bits 11:0 Type rw Reset Value 0x40 Description 12-bit counter value to indicate the number of complete frames between full synchronization packets.

Register (tpiu) EXTCTLIn

Name Relative Address Absolute Address EXTCTLIn 0x00000400 0xF8803400

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Width Access Type Reset Value Description

8 bits ro 0x00000000 EXTCTL In Port

Register EXTCTLIn Details

Field Name Bits 7:0 Type ro Reset Value 0x0 Tied to 0 Description

Register (tpiu) EXTCTLOut

Name Relative Address Absolute Address Width Access Type Reset Value Description EXTCTLOut 0x00000404 0xF8803404 8 bits rw 0x00000000 EXTCTL Out Port

Register EXTCTLOut Details

Field Name Bits 7:0 Type rw Reset Value 0x0 Description Output not connected

Register (tpiu) ITTRFLINACK

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRFLINACK 0x00000EE4 0xF8803EE4 2 bits wo 0x00000000 Integration Test Trigger In and Flush In Acknowledge Register

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Register ITTRFLINACK Details

Field Name FLUSHINACK TRIGINACK Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of FLUSHINACK Set the value of TRIGINACK

Register (tpiu) ITTRFLIN

Name Relative Address Absolute Address Width Access Type Reset Value Description ITTRFLIN 0x00000EE8 0xF8803EE8 2 bits ro x Integration Test Trigger In and Flush In Register

Register ITTRFLIN Details

Field Name FLUSHIN TRIGIN Bits 1 0 Type ro ro Reset Value x x Description Read the value of FLUSHIN Read the value of TRIGIN

Register (tpiu) ITATBDATA0

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBDATA0 0x00000EEC 0xF8803EEC 5 bits ro x Integration Test ATB Data Register 0

Register ITATBDATA0 Details

Field Name ATDATA31 ATDATA23 ATDATA15 Bits 4 3 2 Type ro ro ro x x x Reset Value Description Read the value of ATDATAS[31] Read the value of ATDATAS[23] Read the value of ATDATAS[15]

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Appendix B: Register Details

Field Name ATDATA7 ATDATA0

Bits 1 0

Type ro ro

Reset Value x x

Description Read the value of ATDATAS[7] Read the value of ATDATAS[0]

Register (tpiu) ITATBCTR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR2 0x00000EF0 0xF8803EF0 2 bits wo 0x00000000 Integration Test ATB Control Register 2

Register ITATBCTR2 Details

Field Name AFVALID ATREADY Bits 1 0 Type wo wo Reset Value 0x0 0x0 Description Set the value of AFVALIDS Set the value of ATREADYS

Register (tpiu) ITATBCTR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ITATBCTR1 0x00000EF4 0xF8803EF4 7 bits ro x Integration Test ATB Control Register 1

Register ITATBCTR1 Details

Field Name ATID Bits 6:0 Type ro Reset Value x Description Read the value of ATIDS

Register (tpiu) ITATBCTR0

Name ITATBCTR0

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000EF8 0xF8803EF8 10 bits ro x Integration Test ATB Control Register 0

Register ITATBCTR0 Details

Field Name ATBYTES reserved AFREADY ATVALID Bits 9:8 7:2 1 0 Type ro ro ro ro Reset Value x x x x Description Read the value of ATBYTESS Reserved Read the value of AFREADYS Read the value of ATVALIDS

Register (tpiu) IMCR

Name Relative Address Absolute Address Width Access Type Reset Value Description IMCR 0x00000F00 0xF8803F00 1 bits rw 0x00000000 Integration Mode Control Register

Register IMCR Details

Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers

Register (tpiu) CTSR

Name Relative Address Absolute Address Width Access Type Reset Value CTSR 0x00000FA0 0xF8803FA0 4 bits rw 0x0000000F

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Description

Claim Tag Set Register

Register CTSR Details

Field Name Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: 1= Claim tag is implemented, 0 = Claim tag is not implemented Write: 1= Set claim tag bit, 0= No effect

Register (tpiu) CTCR

Name Relative Address Absolute Address Width Access Type Reset Value Description CTCR 0x00000FA4 0xF8803FA4 4 bits rw 0x00000000 Claim Tag Clear Register

Register CTCR Details

Field Name Bits 3:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag. Write: 1= Clear claim tag bit, 0= No effect

Register (tpiu) LAR

Name Relative Address Absolute Address Width Access Type Reset Value LAR 0x00000FB0 0xF8803FB0 32 bits wo 0x00000000

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Description

Lock Access Register

Register LAR Details

Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), TPIU is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): TPIU is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.

Register (tpiu) LSR

Name Relative Address Absolute Address Width Access Type Reset Value Description LSR 0x00000FB4 0xF8803FB4 3 bits ro 0x00000003 Lock Status Register

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Register LSR Details

Field Name 8BIT STATUS Bits 2 1 Type ro ro Reset Value 0x0 0x1 Description Set to 0 since TPIU implements a 32-bit lock access register Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether TPIU is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. IMP 0 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented.

Register (tpiu) ASR

Name Relative Address Absolute Address Width Access Type Reset Value Description ASR 0x00000FB8 0xF8803FB8 8 bits ro 0x00000000 Authentication Status Register

Register ASR Details

Field Name Bits 7:0 Type ro Reset Value 0x0 Description Indicates functionality not implemented

Register (tpiu) DEVID

Name Relative Address Absolute Address Width DEVID 0x00000FC8 0xF8803FC8 12 bits

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Appendix B: Register Details

Access Type Reset Value Description

ro 0x000000A0 Device ID

Register DEVID Details

Field Name UartNRZ Manchester ClockData FifoSize AsyncClock InputMux Bits 11 10 9 8:6 5 4:0 Type ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x2 0x1 0x0 Description UART/NRZ not supported Manchester not support Trace clock + data is supported FIFO size is 4 ATCLK and TRACECLKIN is asynchronous No input multiplexing

Register (tpiu) DTIR

Name Relative Address Absolute Address Width Access Type Reset Value Description DTIR 0x00000FCC 0xF8803FCC 8 bits ro 0x00000011 Device Type Identifier Register

Register DTIR Details

Field Name Bits 7:0 Type ro Reset Value 0x11 Description A trace sink and specifically a TPIU

Register (tpiu) PERIPHID4

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID4 0x00000FD0 0xF8803FD0 8 bits ro 0x00000004 Peripheral ID4

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Register PERIPHID4 Details

Field Name 4KB_count JEP106ID Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x4 Description 4KB Count, set to 0 JEP106 continuation code

Register (tpiu) PERIPHID5

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID5 0x00000FD4 0xF8803FD4 8 bits ro 0x00000000 Peripheral ID5

Register PERIPHID5 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (tpiu) PERIPHID6

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID6 0x00000FD8 0xF8803FD8 8 bits ro 0x00000000 Peripheral ID6

Register PERIPHID6 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (tpiu) PERIPHID7

Name PERIPHID7

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000FDC 0xF8803FDC 8 bits ro 0x00000000 Peripheral ID7

Register PERIPHID7 Details

Field Name Bits 7:0 Type ro Reset Value 0x0 reserved Description

Register (tpiu) PERIPHID0

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID0 0x00000FE0 0xF8803FE0 8 bits ro 0x00000012 Peripheral ID0

Register PERIPHID0 Details

Field Name Bits 7:0 Type ro Reset Value 0x12 PartNumber0 Description

Register (tpiu) PERIPHID1

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID1 0x00000FE4 0xF8803FE4 8 bits ro 0x000000B9 Peripheral ID1

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Appendix B: Register Details

Register PERIPHID1 Details

Field Name JEP106ID PartNumber1 Bits 7:4 3:0 Type ro ro Reset Value 0xB 0x9 Description JEP106 Identity Code [3:0] PartNumber1

Register (tpiu) PERIPHID2

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID2 0x00000FE8 0xF8803FE8 8 bits ro 0x0000004B Peripheral ID2

Register PERIPHID2 Details

Field Name RevNum JEDEC JEP106ID Bits 7:4 3 2:0 Type ro ro ro Reset Value 0x4 0x1 0x3 Description Revision number of Peripheral Indicates that a JEDEC assigned value is used JEP106 Identity Code [6:4]

Register (tpiu) PERIPHID3

Name Relative Address Absolute Address Width Access Type Reset Value Description PERIPHID3 0x00000FEC 0xF8803FEC 8 bits ro 0x00000000 Peripheral ID3

Register PERIPHID3 Details

Field Name RevAnd CustMod Bits 7:4 3:0 Type ro ro Reset Value 0x0 0x0 Description RevAnd, at top level Customer Modified

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Appendix B: Register Details

Register (tpiu) COMPID0

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID0 0x00000FF0 0xF8803FF0 8 bits ro 0x0000000D Component ID0

Register COMPID0 Details

Field Name Bits 7:0 Type ro Reset Value 0xD Preamble Description

Register (tpiu) COMPID1

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID1 0x00000FF4 0xF8803FF4 8 bits ro 0x00000090 Component ID1

Register COMPID1 Details

Field Name Bits 7:0 Type ro Reset Value 0x90 Preamble Description

Register (tpiu) COMPID2

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID2 0x00000FF8 0xF8803FF8 8 bits ro 0x00000005 Component ID2

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Register COMPID2 Details

Field Name Bits 7:0 Type ro Reset Value 0x5 Preamble Description

Register (tpiu) COMPID3

Name Relative Address Absolute Address Width Access Type Reset Value Description COMPID3 0x00000FFC 0xF8803FFC 8 bits ro 0x000000B1 Component ID3

Register COMPID3 Details

Field Name Bits 7:0 Type ro Reset Value 0xB1 Preamble Description

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B.16 Device Configuration Interface (devcfg)

Module Name Software Name Base Address Description Vendor Info Device Configuration Interface (devcfg) XDCFG 0xF8007000 devcfg Device configuraion Interface

Register Summary
Register Name CTRL Address 0x00000000 Width 32 Type mixed Reset Value 0x0C006000 Description Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. LOCK 0x00000004 32 mixed 0x00000000 This register defines LOCK register used to lock changes in the Control Register 0x000 after configuration. All those LOCK register is set only register. The only way to clear those registers is power on reset signal. Configuration Register : This register contains configuration information for the AXI transfers, and other general setup.

CFG

0x00000008

32

rw

0x00000508

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Register Name INT_STS

Address 0x0000000C

Width 32

Type mixed

Reset Value 0x00000000

Description Interrupt Status Register : This register contains interrupt status flags. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x010 is set. However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set

INT_MASK

0x00000010

32

rw

0xFFFFFFFF

Interrupt Mask Register: This register contains interrupt mask information. Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in Interrupt Status Register 0x00C.

STATUS DMA_SRC_ADDR

0x00000014 0x00000018

32 32

mixed rw

0x40000820 0x00000000

Status Register: This register contains miscellaneous status. DMA Source address Register: This register contains the source address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described

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Register Name DMA_DST_ADDR

Address 0x0000001C

Width 32

Type rw

Reset Value 0x00000000

Description DMA Destination address Register: This register contains the destination address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described.

DMA_SRC_LEN

0x00000020

32

rw

0x00000000

DMA Source transfer Length Register: This register contains the DMA source transfer length in unit of 4-byte word. A DMA command that consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described.

DMA_DEST_LEN

0x00000024

32

rw

0x00000000

DMA Destination transfer Length Register: This register contains the DMA destination transfer length in unit of 4-byte word. A DMA command that consists of source address, destination address, source transfer length, and destination transfer length is accepted when this register is written to. It is important that the parameters are programmed in the exact sequence as described.

ROM_SHADOW MULTIBOOT_ADDR

0x00000028 0x0000002C

32 32

wo rw

0x00000000 0x00000000

ROM Shadow Register: This register defines ROM shadow MULTI Boot Addr Pointer Register: This register defines multi-boot address pointer. This register is power on reset only used to remember multi-boot address pointer set by previous boot.

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Register Name SW_ID

Address 0x00000030

Width 32

Type mixed

Reset Value 0x00000000

Description Software ID Register: This register defines PS boot software ID. It will be used by firmware and software to perform consistent check for subsequent PS software and PL image loads. It is both readable and writeable after reset, and it becomes read only after system has entered user mode (bit 15 of reg 0x000 is set). Unlock Register: This register is used to protect the DEVCI configuration registers from ROM code corruption. The boot ROM will unlock the DEVCI by writing 0x757BDF0D to this register. Writing anything other than the unlock word to this register will cause an illegal access state and make the DEVCI inaccessible until a system reset occurs.

UNLOCK

0x00000034

32

rw

0x00000000

MCTRL

0x00000080

32

mixed

Miscellaneous control Register: This register contains miscellaneous controls. XADC Interface Configuration Register : This register configures the XADC Interface operation XADC Interface Interrupt Status Register : This register contains the interrupt status flags of the XADC interface block. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x108 is set. However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set

XADCIF_CFG

0x00000100

32

rw

0x00001114

XADCIF_INT_STS

0x00000104

32

mixed

0x00000200

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Register Name XADCIF_INT_MASK

Address 0x00000108

Width 32

Type rw

Reset Value 0xFFFFFFFF

Description XADC Interface Interrupt Mask Register : This register contains the interrupt mask information. Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in 0x104

XADCIF_MSTS

0x0000010C

32

ro

0x00000500

XADC Interface miscellaneous Status Register : This register contains miscellaneous status of the XADC Interface XADC Interface Command FIFO Register : This address is the entry point to the command FIFO. Commands get push into the FIFO when there is a write to this address

XADCIF_CMDFIFO

0x00000110

32

wo

0x00000000

XADCIF_RDFIFO

0x00000114

32

ro

0x00000000

XADC Interface Data FIFO Register : This address is the exit point of the read data FIFO. Read data is returned when there is a read from this address

XADCIF_MCTL

0x00000118

32

rw

0x00000010

XADC Interface Miscellaneous Control Register : This register provides miscellaneous control of the XADC Interface.

Register (devcfg) CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description CTRL 0x00000000 0xF8007000 32 bits mixed 0x0C006000 Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

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Register CTRL Details

Field Name FORCE_RST Bits 31 Type rw Reset Value 0x0 Description Force the PS into secure lockdown. The secure lockdown state can only be cleared by issuing a PS_POR_B reset PCFG_PROG_B PCFG_POR_CNT_4K 30 29 rw rw 0x0 0x0 Program Signal used to reset the PL. It acts as the PROG_B signal in the PL. This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer reserved PCAP_PR 28 27 rw rw 0x0 0x1 Reserved After the initial configuration of the PL, a partial reconfiguration can be performed using either the ICAP or PCAP interface. These interfaces are mutually exclusive and cannot be used simultaneously. Switching between ICAP and PCAP is possible but users should ensure that no commands or data are being transmitted or received before changing interfaces. Failure to do this could lead to unexpected behavior. This bit selects between ICAP and PCAP for PL reconfiguration. 0 - ICAP is selected for reconfiguration 1 - PCAP is selected for reconfiguration PCAP_MODE QUARTER_PCAP_RA TE_EN (PCAP_RATE_EN) 26 25 rw rw 0x1 0x0 This bit enables the PCAP interface This bit is used to reduce the PCAP data transmission to once every 4 clock cycles. This bit MUST be set when the AES engine is being used to decrypt configuration data for either the PS or PL. Setting this bit for non-encrypted PCAP data transmission is allowed but not recommended. 0 - PCAP data transmitted every clock cycle 1 - PCAP data transmitted every 4th clock cycle (must be used for encrypted data) MULTIBOOT_EN 24 rw 0x0 This bit enables multi-boot out of reset. This bit is only cleared by a PS_POR_B reset, 0 - Boot from default boot image base address 1 - Boot from multi-boot offset address

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Field Name JTAG_CHAIN_DIS

Bits 23

Type rw

Reset Value 0x0

Description This bit is used to disable the JTAG scan chain. The primary purpose is to protect the PL from unwanted JTAG accesses. The JTAG connection to the PS DAP and PL TAP will be disabled when this bit is set.

reserved reserved reserved reserved PCFG_AES_FUSE

22:16 15 14 13 12

rw wo rw rw rw

0x0 0x0 0x1 0x1 0x0

Reserved Reserved. Do not modify. Reserved - always write with 1 Reserved - always write with 1 (Lockable, see 0x004, bit 4) This bit is used to select the AES key source 0 - BBRAM key 1 - eFuse key User access to this bit is restricted. The boot ROM will make the key selection and lock this bit during the initial boot sequence. This bit is only cleared by PS_POR_B reset.

PCFG_AES_EN

11:9

rw

0x0

(Lockable, see 0x004, bit 3) This bit enables the AES engine within the PL. The three bits need to be either all 0's or 1's, any inconsistency will lead to security lockdown. 000 - Disable AES engine 111 - Enable AES engine All others - Secure lockdown User access to this bit is restricted. The boot ROM will enable the AES engine for secure boot and will always lock this bit before passing control to user code. This bit is only cleared by PS_POR_B reset.

SEU_EN

rw

0x0

(Lockable, see 0x004, bit 2) This bit enables an automatic lockdown of the PS when a PL SEU is detected. 0 - Ignore SEU signal from PL 1 - Initiate secure lockdown when SEU signal received from PL This bit is sticky, once set it can only be cleared with a PS_POR_B reset.

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Field Name SEC_EN

Bits 7

Type ro

Reset Value 0x0

Description (Lockable, see 0x004, bit 1) This bit is used to indicate if the PS has been booted securely. 0 - PS was not booted securely 1 - PS was booted securely User access to this bit is restricted. The boot ROM will set this bit when a secure boot is initiated and will always lock the bit before passing control to user code. This bit is only cleared by PS_POR_B reset.

SPNIDEN

rw

0x0

(Lockable, see 0x004, bit 0) Secure Non-Invasive Debug Enable 0 - Disable 1 - Enable

SPIDEN

rw

0x0

(Lockable, see 0x004, bit 0) Secure Invasive Debug Enable 0 - Disable 1 - Enable

NIDEN

rw

0x0

(Lockable, see 0x004, bit 0) Non-Invasive Debug Enable 0 - Disable 1 - Enable

DBGEN

rw

0x0

(Lockable, see 0x004, bit 0) Invasive Debug Enable 0 - Disable 1 - Enable

DAP_EN

2:0

rw

0x0

(Lockable, see 0x004, bit 0) These bits will enable the ARM DAP. 111 - ARM DAP Enabled Others - ARM DAP will be bypassed

Register (devcfg) LOCK

Name Relative Address Absolute Address Width Access Type Reset Value LOCK 0x00000004 0xF8007004 32 bits mixed 0x00000000

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Description

This register defines LOCK register used to lock changes in the Control Register 0x000 after configuration. All those LOCK register is set only register. The only way to clear those registers is power on reset signal.

Register LOCK Details

Field Name reserved AES_FUSE_LOCK Bits 31:5 4 Type rw rwso Reset Value 0x0 0x0 Reserved This bit locks the PCFG_AES_FUSE bit (CTRL[12]). 0 - Open 1 - Locked User access to this bit is restricted, the boot ROM will always set this bit prior to handing control over to user code. This bit is only cleared by a PS_POR_B reset. AES_EN_LOCK (AES_EN) 3 rwso 0x0 This bit locks the PCFG_AES_EN bits (CTRL[11:9]). 0 - Open 1 - Locked User access to this bit is restricted, the boot ROM will always set this bit prior to handing control over to user code. This bit is only cleared by a PS_POR_B reset. SEU_LOCK (SEU) 2 rwso 0x0 This bit locks the SEU_EN bit (CTRL[8]). 0 - Open 1 - Locked This bit is only cleared by a PS_POR_B reset. SEC_LOCK (SEC) 1 rwso 0x0 This bit locks the SEC_EN bit (CTRL[7]). 0 - Open 1 - Locked User access to this bit is restricted, the boot ROM will always set this bit prior to handing control over to user code. This bit is only cleared by a PS_POR_B reset. DBG_LOCK (DBG) 0 rwso 0x0 This bit locks the debug enable bits, SPNIDEN, SPIDEN, NIDEN, DBGEN, DAP_EN (CTRL[6:0]). 0 - Open 1 - Locked DBG_LOCK should only be used to prevent the debug access from being enabled. If DBG_LOCK is set and a soft-reset is issued, then the DAP_EN bits in the CTRL register (0x000) cannot be enabled until a power-on-reset is performed. This bit is only cleared by a PS_POR_B reset. Description

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Register (devcfg) CFG

Name Relative Address Absolute Address Width Access Type Reset Value Description CFG 0x00000008 0xF8007008 32 bits rw 0x00000508 Configuration Register : This register contains configuration information for the AXI transfers, and other general setup.

Register CFG Details

Field Name reserved RFIFO_TH Bits 31:12 11:10 Type rw rw Reset Value 0x0 0x1 Reserved These two bits define Rx FIFO level that sets interrupt flag 00 - One fourth full for read 01 - Half full for read 10 - Three fourth full for read 11 - Full for read(User could use this signal to trigger interrupt when read FIFO overflow) WFIFO_TH 9:8 rw 0x1 These two bits define Tx FIFO level that sets interrupt flag 00 - One fourth empty for write 01 - Half empty for write 10 - Three fourth empty for write 11 - Empty for write RCLK_EDGE 7 rw 0x0 Read data active clock edge 0 - Falling edge 1 - Rising edge WCLK_EDGE 6 rw 0x0 Write data active clock edge 0 - Falling edge 1 - Rising edge DISABLE_SRC_INC 5 rw 0x0 Disable automatic DMA AXI source address increment, if set, to allow AXI read from a keyhole address Disable automatic DMA AXI destination address increment, if set, to allow AXI read from a keyhole address Reserved. Do not modify. Description

DISABLE_DST_INC

rw

0x0

reserved

rw

0x1

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Field Name reserved reserved reserved

Bits 2 1 0

Type rw rw rw

Reset Value 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (devcfg) INT_STS

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_STS 0x0000000C 0xF800700C 32 bits mixed 0x00000000 Interrupt Status Register : This register contains interrupt status flags. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x010 is set. However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set

Register INT_STS Details

Field Name PSS_GTS_USR_B_INT PSS_FST_CFG_B_INT PSS_GPWRDWN_B_I NT PSS_GTS_CFG_B_INT PSS_CFG_RESET_B_I NT reserved AXI_WTO_INT (IXR_AXI_WTO) Bits 31 30 29 28 27 26:24 23 Type wtc wtc wtc wtc wtc rw wtc Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Tri-state PL IO during HIZ, both edges First configuration done, both edges Global power down, both edges Tri-state PL IO during configuration, both edges PL configuration reset, both edges Reserved AXI write address, data or response time out. AXI write is taking longer than expected (> 6144 cpu_1x clock cycles), this can be an indication of starvation 22 wtc 0x0 AXI write response error

AXI_WERR_INT (IXR_AXI_WERR)

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Field Name AXI_RTO_INT (IXR_AXI_RTO)

Bits 21

Type wtc

Reset Value 0x0

Description AXI read address or response time out. AXI read is taking longer than expected (> 2048 cpu_1x clock cycles), this can be an indication of starvation

AXI_RERR_INT (IXR_AXI_RERR) reserved RX_FIFO_OV_INT (IXR_RX_FIFO_OV)

20 19 18

wtc rw wtc

0x0 0x0 0x0

AXI read response error Reserved This bit is used to indicate that RX FIFO overflows. Incoming read data from PCAP will be dropped and the DEVCI DMA may enter an unrecoverable state . Tx FIFO level < threshold, see reg 0x008 Rx FIFO level >= threshold, see reg 0x008 Illegal DMA command

WR_FIFO_LVL_INT (IXR_WR_FIFO_LVL) RD_FIFO_LVL_INT (IXR_RD_FIFO_LVL) DMA_CMD_ERR_INT (IXR_DMA_CMD_ERR ) DMA_Q_OV_INT (IXR_DMA_Q_OV) DMA_DONE_INT (IXR_DMA_DONE)

17 16 15

wtc wtc wtc

0x0 0x0 0x0

14 13

wtc wtc

0x0 0x0

DMA command queue overflows This bit is used to indicate a DMA command is done. The bit is set either as soon as DMA is done (PCAP may not be finished) or both DMA and PCAP are done.

D_P_DONE_INT (IXR_D_P_DONE) P2D_LEN_ERR_INT (IXR_P2D_LEN_ERR) reserved PCFG_HMAC_ERR_I NT (IXR_PCFG_HMAC_E RR) PCFG_SEU_ERR_INT (IXR_PCFG_SEU_ERR) PCFG_POR_B_INT (IXR_PCFG_POR_B) PCFG_CFG_RST_INT (IXR_PCFG_CFG_RST)

12 11 10:7 6

wtc wtc rw wtc

0x0 0x0 0x0 0x0

Both DMA and PCAP transfers are done for intermediate and final transfers. Inconsistent PCAP to DMA transfer length error Reserved Triggers when an HMAC error is received from the PL

5 4 3

wtc wtc wtc

0x0 0x0 0x0

Triggers when an SEU error is received from the PL Triggers if the PL loses power, PL POR_B signal goes low Triggers if the PL configuration controller is under reset

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Field Name PCFG_DONE_INT (IXR_PCFG_DONE) PCFG_INIT_PE_INT (IXR_PCFG_INIT_PE) PCFG_INIT_NE_INT (IXR_PCFG_INIT_NE)

Bits 2 1 0

Type wtc wtc wtc

Reset Value 0x0 0x0 0x0

Description DONE signal from PL indicating that programming is complete and PL is in user mode. Triggered on the positive edge of the PL INIT signal Triggered on the negative edge of the PL INIT signal

Register (devcfg) INT_MASK

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_MASK 0x00000010 0xF8007010 32 bits rw 0xFFFFFFFF Interrupt Mask Register: This register contains interrupt mask information. Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in Interrupt Status Register 0x00C.

Register INT_MASK Details

Field Name M_PSS_GTS_USR_B_I NT M_PSS_FST_CFG_B_I NT M_PSS_GPWRDWN_B _INT M_PSS_GTS_CFG_B_I NT M_PSS_CFG_RESET_B _INT reserved M_AXI_WTO_INT (IXR_AXI_WTO) M_AXI_WERR_INT (IXR_AXI_WERR) M_AXI_RTO_INT (IXR_AXI_RTO) 21 rw 0x1 22 rw 0x1 Interrupt mask for AXI write response error interrupt Interrupt mask for AXI read time out interrupt Bits 31 30 29 28 27 26:24 23 Type rw rw rw rw rw rw rw Reset Value 0x1 0x1 0x1 0x1 0x1 0x7 0x1 Description Interrupt mask for tri-state IO during HIZ, both edges Interrupt mask for first config done, both edges Interrupt mask for global power down, both edges Interrupt mask for tri-state IO in config, both edges Interrupt mask for config reset, both edges Reserved Interrupt mask for AXI write time out interrupt

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Field Name M_AXI_RERR_INT (IXR_AXI_RERR) reserved M_RX_FIFO_OV_INT (IXR_RX_FIFO_OV) M_WR_FIFO_LVL_IN T (IXR_WR_FIFO_LVL) M_RD_FIFO_LVL_INT (IXR_RD_FIFO_LVL) M_DMA_CMD_ERR_I NT (IXR_DMA_CMD_ERR ) M_DMA_FIFO_OV_IN T (IXR_DMA_Q_OV) M_DMA_DONE_INT (IXR_DMA_DONE) M_D_P_DONE_INT (IXR_D_P_DONE) M_P2D_LEN_ERR_IN T (IXR_P2D_LEN_ERR) reserved M_PCFG_HMAC_ERR _INT (IXR_PCFG_HMAC_E RR) M_PCFG_SEU_ERR_I NT (IXR_PCFG_SEU_ERR) M_PCFG_POR_B_INT (IXR_PCFG_POR_B) M_PCFG_CFG_RST_I NT (IXR_PCFG_CFG_RST) M_PCFG_DONE_INT (IXR_PCFG_DONE)

Bits 20 19 18 17

Type rw rw rw rw

Reset Value 0x1 0x1 0x1 0x1

Description Interrupt mask for AXI read response error interrupt Reserved Interrupt mask for Rx FIFO overflow interrupt Interrupt mask for Tx FIFO level < threshold interrupt Interrupt mask for Rx FIFO level > threshold interrupt Interrupt mask for illegal DMA command interrupt

16 15

rw rw

0x1 0x1

14

rw

0x1

Interrupt mask for DMA command FIFO overflows Interrupt mask for DMA command done interrupt Interrupt mask for DMA and PCAP done interrupt Interrupt mask Inconsistent xfer length error interrupt Reserved Interrupt mask for HMAC error

13 12 11

rw rw rw

0x1 0x1 0x1

10:7 6

rw rw

0xF 0x1

rw

0x1

Interrupt mask for PCFG_SEU_ERR interrupt

4 3

rw rw

0x1 0x1

Interrupt mask for PCFG_POR_B Interrupt Interrupt mask for PCFG_CFG_RESET interrupt

rw

0x1

Interrupt mask for PCFG_DONE interrupt

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Field Name M_PCFG_INIT_PE_IN T (IXR_PCFG_INIT_PE) M_PCFG_INIT_NE_IN T (IXR_PCFG_INIT_NE)

Bits 1

Type rw

Reset Value 0x1

Description Interrupt mask for PCFG_INIT_PE interrupt

rw

0x1

Interrupt mask for PCFG_INIT_NE interrupt

Register (devcfg) STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description STATUS 0x00000014 0xF8007014 32 bits mixed 0x40000820 Status Register: This register contains miscellaneous status.

Register STATUS Details

Field Name DMA_CMD_Q_F DMA_CMD_Q_E DMA_DONE_CNT Bits 31 30 29:28 Type ro ro clron wr Reset Value 0x0 0x1 0x0 Description DMA command queue full, if set DMA command queue empty, if set Number of completed DMA transfers that have not been acknowledged by software: 00 - all finished transfers have been acknowledged 01 - one finished transfer outstanding 10 - two finished transfers outstanding 11 - three or more finished transfers outstanding A finished transfer is acknowledged by clearing the interrupt status flag, i.e., bit 9 of the interrupt status register 0x00C. This count is cleared by writing a 1 to either bit location. reserved RX_FIFO_LVL reserved TX_FIFO_LVL 27:25 24:20 19 18:12 rw ro rw ro 0x0 0x0 0x0 0x0 Reserved This register is used to indicate how many valid 32-Bit words in the Rx FIFO, max. is 31 Reserved This register is used to indicate how many valid 32-Bit words in the Tx FIFO, max. is 127

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Field Name PSS_GTS_USR_B PSS_FST_CFG_B PSS_GPWRDWN_B PSS_GTS_CFG_B SECURE_RST ILLEGAL_APB_ACCE SS

Bits 11 10 9 8 7 6

Type ro ro ro ro ro ro

Reset Value 0x1 0x0 0x0 0x0 0x0 0x0

Description Tri-state IO during HIZ, active low First PL configuration done, active low. Global power down, active low Tri-state IO during config, active low This bit is used to indicate a secure lockdown. Can only be cleared by a PS_POR_B reset. Indicates the UNLOCK register was not written with the correct unlock word. If set all secure boot features will be disabled, the DAP will be disabled and writing to the DEVCI registers will be disabled. The illegal access mode can only be cleared with a PS_POR_B reset.

PSS_CFG_RESET_B PCFG_INIT

5 4

ro ro

0x1 0x0

PL configuration reset, active low. PL INIT signal, indicates when housecleaning is done and the PL is ready to receive PCAP data. Positive and negative edges of the signal generate maskable interrupts in 0x00C.

EFUSE_BBRAM_KEY_ DISABLE (EFUSE_SW_RESERVE ) EFUSE_SEC_EN

ro

0x0

When this eFuse is blown, the BBRAM AES key is disabled. If the device is booted securely, the eFuse key must be used.

ro

0x0

When this eFuse is blown, the Zynq device must boot securely and use the eFuse as the AES key source. Non-secure boot will cause a security lockdown. When this eFuse is blown, the ARM DAP controller is permanently set in bypass mode. Any attempt to activate the DAP will cause a security lockdown.

EFUSE_JTAG_DIS

ro

0x0

reserved

ro

0x0

Reserved. Do not modify.

Register (devcfg) DMA_SRC_ADDR

Name Relative Address Absolute Address Width Access Type Reset Value DMA_SRC_ADDR 0x00000018 0xF8007018 32 bits rw 0x00000000

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Description

DMA Source address Register: This register contains the source address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described

Register DMA_SRC_ADDR Details

Field Name SRC_ADDR Bits 31:0 Type rw Reset Value 0x0 Description Source address for DMA transfer of AXI read. Setting SRC_ADDR[1:0] and DST_ADDR[1:0] to 2'b01 will cause the DMA engine to hold the DMA DONE interrupt until both the AXI and PCAP interfaces are done with the data transfer. Otherwise the interrupt will trigger as soon as the AXI interface is done.

Register (devcfg) DMA_DST_ADDR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DMA_DST_ADDR DMA_DEST_ADDR 0x0000001C 0xF800701C 32 bits rw 0x00000000 DMA Destination address Register: This register contains the destination address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described.

Register DMA_DST_ADDR Details

Field Name DST_ADDR Bits 31:0 Type rw Reset Value 0x0 Description Destination address for DMA transfer of AXI write. Setting SRC_ADDR[1:0] and DST_ADDR[1:0] to 2'b01 will cause the DMA engine to hold the DMA DONE interrupt until both the AXI and PCAP interfaces are done with the data transfer. Otherwise the interrupt will trigger as soon as the AXI interface is done.

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Register (devcfg) DMA_SRC_LEN

Name Relative Address Absolute Address Width Access Type Reset Value Description DMA_SRC_LEN 0x00000020 0xF8007020 32 bits rw 0x00000000 DMA Source transfer Length Register: This register contains the DMA source transfer length in unit of 4-byte word. A DMA command that consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described.

Register DMA_SRC_LEN Details

Field Name reserved LEN (DMA_LEN) Bits 31:27 26:0 Type rw rw Reset Value 0x0 0x0 Reserved Up to 512MB data Description

Register (devcfg) DMA_DEST_LEN

Name Relative Address Absolute Address Width Access Type Reset Value Description DMA_DEST_LEN 0x00000024 0xF8007024 32 bits rw 0x00000000 DMA Destination transfer Length Register: This register contains the DMA destination transfer length in unit of 4-byte word. A DMA command that consists of source address, destination address, source transfer length, and destination transfer length is accepted when this register is written to. It is important that the parameters are programmed in the exact sequence as described.

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Register DMA_DEST_LEN Details

Field Name reserved LEN (DMA_LEN) Bits 31:27 26:0 Type rw rw Reset Value 0x0 0x0 Reserved Up to 512MB data Description

Register (devcfg) ROM_SHADOW

Name Relative Address Absolute Address Width Access Type Reset Value Description ROM_SHADOW 0x00000028 0xF8007028 32 bits wo 0x00000000 ROM Shadow Register: This register defines ROM shadow

Register ROM_SHADOW Details

Field Name reserved Bits 31:0 Type wo Reset Value 0x0 Description Reserved. Do not modify.

Register (devcfg) MULTIBOOT_ADDR

Name Relative Address Absolute Address Width Access Type Reset Value Description MULTIBOOT_ADDR 0x0000002C 0xF800702C 32 bits rw 0x00000000 MULTI Boot Addr Pointer Register: This register defines multi-boot address pointer. This register is power on reset only used to remember multi-boot address pointer set by previous boot.

Register MULTIBOOT_ADDR Details

Field Name MULTIBOOT_ADDR Bits 31:0 Type rw Reset Value 0x0 Description Multi-Boot offset address

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Register (devcfg) SW_ID

Name Relative Address Absolute Address Width Access Type Reset Value Description SW_ID 0x00000030 0xF8007030 32 bits mixed 0x00000000 Software ID Register: This register defines PS boot software ID. It will be used by firmware and software to perform consistent check for subsequent PS software and PL image loads. It is both readable and writeable after reset, and it becomes read only after system has entered user mode (bit 15 of reg 0x000 is set).

Register SW_ID Details

Field Name SW_ID Bits 31:0 Type rw,ro Reset Value 0x0 Software ID Description

Register (devcfg) UNLOCK

Name Relative Address Absolute Address Width Access Type Reset Value Description UNLOCK 0x00000034 0xF8007034 32 bits rw 0x00000000 Unlock Register: This register is used to protect the DEVCI configuration registers from ROM code corruption. The boot ROM will unlock the DEVCI by writing 0x757BDF0D to this register. Writing anything other than the unlock word to this register will cause an illegal access state and make the DEVCI inaccessible until a system reset occurs.

Register UNLOCK Details

Field Name UNLOCK Bits 31:0 Type rw Reset Value 0x0 Unlock value. Description

Register (devcfg) MCTRL

Name Relative Address MCTRL 0x00000080

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Absolute Address Width Access Type Reset Value Description

0xF8007080 32 bits mixed x Miscellaneous control Register: This register contains miscellaneous controls.

Register MCTRL Details

Field Name PS_VERSION Bits 31:28 Type ro Reset Value x Description Version ID for silicon 0x0 = 1.0 Silicon 0x1 = 2.0 Silicon 0x2 = 3.0 Silicon 0x3 = 3.1 Silicon reserved reserved reserved reserved reserved reserved reserved reserved reserved PCFG_POR_B reserved INT_PCAP_LPBK (PCAP_LPBK) reserved reserved reserved 3:2 1 0 rw rw rw 0x0 0x0 0x0 Reserved Reserved - always write with 0 Reserved - always write with 0 27 26 25 24 23 22:14 13 12 11:9 8 7:5 4 ro ro ro ro rw rw rw rw rw ro rw rw 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved - always write with 1 Reserved Reserved. Do not modify. Reserved. Do not modify. Reserved PL POR_B signal used to determine power-up status of PL. Reserved Internal PCAP loopback, if set

Register (devcfg) XADCIF_CFG

Name Relative Address Absolute Address Width XADCIF_CFG 0x00000100 0xF8007100 32 bits

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Access Type Reset Value Description

rw 0x00001114 XADC Interface Configuration Register : This register configures the XADC Interface operation

Register XADCIF_CFG Details

Field Name ENABLE reserved CFIFOTH Bits 31 30:24 23:20 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Enable PS access of the XADC, if set Reserved Command FIFO level threshold. Interrupt status flag is set if the FIFO level is less than or equal to the threshold DFIFOTH 19:16 rw 0x0 Data FIFO level threshold. Interrupt status flag is set if FIFO level is greater than the threshold reserved WEDGE 15:14 13 rw rw 0x0 0x0 Reserved Write launch edge : 0 - Falling edge 1 - Rising edge REDGE 12 rw 0x1 Read capture edge : 0 - Falling edge 1 - Rising edge reserved TCKRATE 11:10 9:8 rw rw 0x0 0x1 Reserved XADC clock frequency control. The base frequency is pcap_2x clock which has a nominal frequency of 200 MHz. 00 - 1/2 of pcap_2x clock frequency 01 - 1/4 of pcap_2x clock frequency 10 - 1/8 of pcap_2x clock frequency 11 - 1/16 of pcap_2x clock frequency reserved IGAP 7:5 4:0 rw rw 0x0 0x14 Reserved Minimum idle gap between successive commands. Default is 20 cycles, the minimum required by the XADC is 10.

Register (devcfg) XADCIF_INT_STS

Name Relative Address XADCIF_INT_STS 0x00000104

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Absolute Address Width Access Type Reset Value Description

0xF8007104 32 bits mixed 0x00000200 XADC Interface Interrupt Status Register : This register contains the interrupt status flags of the XADC interface block. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x108 is set. However, external interrupt will only be generated if an interrupt status flag is set and the corresponding mask bit is not set

Register XADCIF_INT_STS Details

Field Name reserved CFIFO_LTH DFIFO_GTH OT Bits 31:10 9 8 7 Type rw wtc wtc wtc Reset Value 0x0 0x1 0x0 0x0 Reserved Command FIFO level less than or equal to the threshold (see register 0x100). Data FIFO level greater than threshold (see register 0x100). Over temperature alarm from XADC. This is a latched version of the raw signal which is also available in register 0x10C ALM 6:0 wtc 0x0 Alarm signals from XADC. These are latched version of the raw input alarm signals which are also available in register 0x10C Description

Register (devcfg) XADCIF_INT_MASK

Name Relative Address Absolute Address Width Access Type Reset Value Description XADCIF_INT_MASK 0x00000108 0xF8007108 32 bits rw 0xFFFFFFFF XADC Interface Interrupt Mask Register : This register contains the interrupt mask information. Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in 0x104

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Register XADCIF_INT_MASK Details

Field Name reserved M_CFIFO_LTH M_DFIFO_GTH M_OT M_ALM Bits 31:10 9 8 7 6:0 Type rw rw rw rw rw Reset Value 0x3FFFFF 0x1 0x1 0x1 0x7F Reserved Interrupt mask for command FIFO level threshold interrupt. Interrupt mask Data FIFO level greater than threshold interrupt. Interrupt mask for over temperature alarm interrupt Interrupt mask for alarm signals from XADC. Description

Register (devcfg) XADCIF_MSTS

Name Relative Address Absolute Address Width Access Type Reset Value Description XADCIF_MSTS 0x0000010C 0xF800710C 32 bits ro 0x00000500 XADC Interface miscellaneous Status Register : This register contains miscellaneous status of the XADC Interface

Register XADCIF_MSTS Details

Field Name reserved CFIFO_LVL DFIFO_LVL CFIFOF CFIFOE DFIFOF DFIFOE OT Bits 31:20 19:16 15:12 11 10 9 8 7 Type ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 Reserved Command FIFO level. Data FIFO level. Command FIFO full. Command FIFO empty. Data FIFO full. Data FIFO empty. Raw over temperature alarm from the XADC. Latched version of the signal is available in the interrupt status register. ALM 6:0 ro 0x0 Raw alarm signals from the XADC. Latched version of the signals are available in the interrupt status register. Description

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Register (devcfg) XADCIF_CMDFIFO

Name Relative Address Absolute Address Width Access Type Reset Value Description XADCIF_CMDFIFO 0x00000110 0xF8007110 32 bits wo 0x00000000 XADC Interface Command FIFO Register : This address is the entry point to the command FIFO. Commands get push into the FIFO when there is a write to this address

Register XADCIF_CMDFIFO Details

Field Name CMD Bits 31:0 Type wo Reset Value 0x0 32-bit command. Description

Register (devcfg) XADCIF_RDFIFO

Name Relative Address Absolute Address Width Access Type Reset Value Description XADCIF_RDFIFO 0x00000114 0xF8007114 32 bits ro 0x00000000 XADC Interface Data FIFO Register : This address is the exit point of the read data FIFO. Read data is returned when there is a read from this address

Register XADCIF_RDFIFO Details

Field Name RDDATA Bits 31:0 Type ro Reset Value 0x0 32-bit read data. Description

Register (devcfg) XADCIF_MCTL

Name Relative Address Absolute Address Width XADCIF_MCTL 0x00000118 0xF8007118 32 bits

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Access Type Reset Value Description

rw 0x00000010 XADC Interface Miscellaneous Control Register : This register provides miscellaneous control of the XADC Interface.

Register XADCIF_MCTL Details

Field Name reserved RESET Bits 31:5 4 Type rw rw Reset Value 0x0 0x1 Reserved This bit will reset the communication channel between the PS and XADC. If set, the PS-XADC communication channel will remain in reset until a 0 is written to this bit. reserved reserved 3:1 0 rw rw 0x0 0x0 Reserved Reserved - always write with 0 Description

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B.17 DMA Controller (dmac)

Module Name Software Name Base Address Description Vendor Info DMA Controller (dmac) XDMAPS 0xF8004000 dmac0_ns 0xF8003000 dmac0_s Direct Memory Access Controller, PL330 ARM PL330

Register Summary
Register Name DSR DPC INTEN INT_EVENT_RIS INTMIS INTCLR FSRD FSRC FTRD FTR0 FTR1 FTR2 FTR3 FTR4 FTR5 FTR6 FTR7 CSR0 CPC0 CSR1 CPC1 CSR2 Address 0x00000000 0x00000004 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000050 0x00000054 0x00000058 0x0000005C 0x00000100 0x00000104 0x00000108 0x0000010C 0x00000110 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description DMA Manager Status DMA Program Counter DMASEV Instruction Response Control Event Interrupt Raw Status Interrupt Status Interrupt Clear Fault Status DMA Manager Fault Status DMA Channel Fault Type DMA Manager Default Type DMA Channel 0 Default Type DMA Channel 1 Default Type DMA Channel 2 Default Type DMA Channel 3 Default Type DMA Channel 4 Default Type DMA Channel 5 Default Type DMA Channel 6 Default Type DMA Channel 7 Channel Status DMA Channel 0 Channel PC for DMA Channel 0 Channel Status DMA Channel 1 Channel PC for DMA Channel 1 Channel Status DMA Channel 2

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Register Name CPC2 CSR3 CPC3 CSR4 CPC4 CSR5 CPC5 CSR6 CPC6 CSR7 CPC7 SAR0 DAR0 CCR0

Address 0x00000114 0x00000118 0x0000011C 0x00000120 0x00000124 0x00000128 0x0000012C 0x00000130 0x00000134 0x00000138 0x0000013C 0x00000400 0x00000404 0x00000408

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Description Channel PC for DMA Channel 2 Channel Status DMA Channel 3 Channel PC for DMA Channel 3 Channel Status DMA Channel 4 Channel PC for DMA Channel 4 Channel Status DMA Channel 5 Channel PC for DMA Channel 5 Channel Status DMA Channel 6 Channel PC for DMA Channel 6 Channel Status DMA Channel 7 Channel PC for DMA Channel 7 Source Address DMA Channel 0 Destination Addr DMA Channel 0 Channel Control DMA Channel 0

LC0_0 LC1_0 SAR1 DAR1 CCR1

0x0000040C 0x00000410 0x00000420 0x00000424 0x00000428

32 32 32 32 32

mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Loop Counter 0 DMA Channel 0 Loop Counter 1 DMA Channel 0 Source address DMA Channel 1 Destination Addr DMA Channel 1 Channel Control DMA Channel 1

LC0_1 LC1_1 SAR2 DAR2 CCR2

0x0000042C 0x00000430 0x00000440 0x00000444 0x00000448

32 32 32 32 32

mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Loop Counter 0 DMA Channel 1 Loop Counter 1 DMA Channel 1 Source Address DMA Channel 2 Destination Addr DMA Channel 2 Channel Control DMA Channel 2

LC0_2 LC1_2

0x0000044C 0x00000450

32 32

mixed mixed

0x00000000 0x00000000

Loop Counter 0 DMA Channel 2 Loop Counter 1 DMA Channel 2

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Register Name SAR3 DAR3 CCR3

Address 0x00000460 0x00000464 0x00000468

Width 32 32 32

Type mixed mixed mixed

Reset Value 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Description Source Address DMA Channel 3 Destination Addr DMA Channel 3 Channel Control DMA Channel 3

LC0_3 LC1_3 SAR4 DAR4 CCR4

0x0000046C 0x00000470 0x00000480 0x00000484 0x00000488

32 32 32 32 32

mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Loop Counter 0 DMA Channel 3 Loop Counter 1 DMA Channel 3 Source Address DMA Channel 4 Destination Addr DMA Channel 4 Channel Control DMA Channel 4

LC0_4 LC1_4 SAR5 DAR5 CCR5

0x0000048C 0x00000490 0x000004A0 0x000004A4 0x000004A8

32 32 32 32 32

mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Loop Counter 0 DMA Channel 4 Loop Counter 1 DMA Channel 4 Source Address DMA Channel 5 Destination Addr DMA Channel 5 Channel Control DMA Channel 5

LC0_5 LC1_5 SAR6 DAR6 CCR6

0x000004AC 0x000004B0 0x000004C0 0x000004C4 0x000004C8

32 32 32 32 32

mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Loop Counter 0 DMA Channel 5 Loop Counter 1 DMA Channel 5 Source Address DMA Channel 6 Destination Addr DMA Channel 6 Channel Control DMA Channel 6

LC0_6 LC1_6 SAR7 DAR7

0x000004CC 0x000004D0 0x000004E0 0x000004E4

32 32 32 32

mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000

Loop Counter 0 DMA Channel 6 Loop Counter 1 DMA Channel 6 Source Address DMA Channel 7 Destination Addr DMA Channel 7

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Register Name CCR7

Address 0x000004E8

Width 32

Type mixed

Reset Value dmac0_ns: 0x00000000 dmac0_s: 0x00800200

Description Channel Control DMA Channel 7

LC0_7 LC1_7 DBGSTATUS DBGCMD DBGINST0 DBGINST1 CR0

0x000004EC 0x000004F0 0x00000D00 0x00000D04 0x00000D08 0x00000D0C 0x00000E00

32 32 32 32 32 32 32

mixed mixed mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x001E3071

Loop Counter 0 DMA Channel 7 Loop Counter 1 DMA Channel 7 DMA Manager Execution Status DMA Manager Instr. Command DMA Manager Instruction Part A DMA Manager Instruction Part B Config. 0: Events, Peripheral Interfaces, PC, Mode Config. 1: Instruction Cache

CR1

0x00000E04

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x00000074

CR2 CR3 CR4 CRD

0x00000E08 0x00000E0C 0x00000E10 0x00000E14

32 32 32 32

mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x07FF7F73

Config. 2: DMA Mgr Boot Addr Config. 3: Security state of IRQs Config 4, Security of Periph Interfaces DMA configuration

WD periph_id_0

0x00000E80 0x00000FE0

32 32

mixed mixed

0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x00000030

Watchdog Timer Peripheral Idenfication register 0

periph_id_1

0x00000FE4

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x00000013

Peripheral Idenfication register 1

periph_id_2

0x00000FE8

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x00000024

Peripheral Idenfication register 2

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Register Name periph_id_3 pcell_id_0

Address 0x00000FEC 0x00000FF0

Width 32 32

Type mixed mixed

Reset Value 0x00000000 dmac0_ns: 0x00000000 dmac0_s: 0x0000000D

Description Peripheral Idenfication register 3 Compontent Idenfication register 0

pcell_id_1

0x00000FF4

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x000000F0

Compontent Idenfication register 1

pcell_id_2

0x00000FF8

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x00000005

Compontent Idenfication register 2

pcell_id_3

0x00000FFC

32

mixed

dmac0_ns: 0x00000000 dmac0_s: 0x000000B1

Compontent Idenfication register 3

Register (dmac) DSR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DSR DS 0x00000000 dmac0_ns: 0xF8004000 dmac0_s: 0xF8003000 32 bits mixed 0x00000000 DMA Manager Status

Register DSR Details

Field Name reserved DNS Bits 31:10 9 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description Reserved, read undefined Provides the security status of the DMA manager thread: 0: Secure state 1: Non-secure state

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Field Name Wakeup_event

Bits 8:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA manager executes a DMAWFE instruction, it is waiting for one of the following events to occur from any of the DMA channel treads: 0 0000: event[0] 0 0001: event[1] ... 0 1111: event[15] 1 xxxx: reserved

DMA_status

3:0

sro,ns sraz,n snsro

0x0

The current operating state of the DMA manager: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101 to 1110: reserved 1111: Faulting.

Register (dmac) DPC

Name Relative Address Absolute Address Width Access Type Reset Value Description DPC 0x00000004 dmac0_ns: 0xF8004004 dmac0_s: 0xF8003004 32 bits mixed 0x00000000 DMA Program Counter

Register DPC Details

Field Name pc_mgr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter for the DMA manager thread

Register (dmac) INTEN

Name Relative Address INTEN 0x00000020

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Absolute Address Width Access Type Reset Value Description

dmac0_ns: 0xF8004020 dmac0_s: 0xF8003020 32 bits mixed 0x00000000 DMASEV Instruction Response Control

Register INTEN Details

Field Name event_irq_select Bits 31:0 Type Reset Value Description Control the respond of a DMA channel thread when it executes a DMASEV instruction. The channel thread will either signal the same DMASEV instruction to the other threads, or assert its interrupt signal. Bits [7:0] correspond to channels [7:0]. 0: The channel tread signals a DMASEV to the other threads (this typically selected when interrupts are not used) 1: Assert the channel's interrupt signal to the PS interrupt controller. Reserved

srw,ns 0x0 sraz,n snsrw

Register (dmac) INT_EVENT_RIS

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INT_EVENT_RIS ES 0x00000024 dmac0_ns: 0xF8004024 dmac0_s: 0xF8003024 32 bits mixed 0x00000000 Event Interrupt Raw Status

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Register INT_EVENT_RIS Details

Field Name DMASEV_active Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Raw status of the event or interrupt state. There are sixteen possible event settings [15:0] and eight possible interrupts [7:0]: 0: Inactive 1: Active Note: When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register controls whether the DMAC: signals an interrupt using the appropriate irq sends the event to all of the threads. Reserved

Register (dmac) INTMIS

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INTMIS INTSTATUS 0x00000028 dmac0_ns: 0xF8004028 dmac0_s: 0xF8003028 32 bits mixed 0x00000000 Interrupt Status

Register INTMIS Details

Field Name irq_status Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Interrupt signal state for DMA channel [7:0]: 0: inactive (IRQ signals is Low). 1: active (IRQ signals is HIgh). Reserved

Register (dmac) INTCLR

Name Relative Address Absolute Address INTCLR 0x0000002C dmac0_ns: 0xF800402C dmac0_s: 0xF800302C

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Width Access Type Reset Value Description

32 bits mixed 0x00000000 Interrupt Clear

Register INTCLR Details

Field Name irq_clr Bits 31:0 Type swo,n ssraz, nsns wo Reset Value 0x0 Description Clear interrupt(s) for DMA channel [7:0]: 0: no affect 1: clear the interrupt Reserved

Register (dmac) FSRD

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FSRD FSM 0x00000030 dmac0_ns: 0xF8004030 dmac0_s: 0xF8003030 32 bits mixed 0x00000000 Fault Status DMA Manager

Register FSRD Details

Field Name reserved fs_mgr Bits 31:1 0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the fault status of the DMA manager: 0: Not in the Faulting state 1: Faulting state

Register (dmac) FSRC

Name Software Name Relative Address Absolute Address FSRC FSC 0x00000034 dmac0_ns: 0xF8004034 dmac0_s: 0xF8003034

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Width Access Type Reset Value Description

32 bits mixed 0x00000000 Fault Status DMA Channel

Register FSRC Details

Field Name reserved fault_status Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Each bit provides the fault status of the corresponding DMA channel, Bits [7:0]: 0: No fault present 1: Fault or Fault completing state

Register (dmac) FTRD

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTRD FTM 0x00000038 dmac0_ns: 0xF8004038 dmac0_s: 0xF8003038 32 bits mixed 0x00000000 Fault Type DMA Manager

Register FTRD Details

Field Name reserved dbg_instr Bits 31 30 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 read undefined If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface reserved instr_fetch_err 29:17 16 rud sro,ns sraz,n snsro 0x0 0x0 read undefined Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response Description

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Appendix B: Register Details

Field Name reserved mgr_evnt_err

Bits 15:6 5

Type rud sro,ns sraz,n snsro

Reset Value 0x0 0x0 read undefined

Description

Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate security permissions: 0: the DMA manager has appropriate security to execute DMAWFE or DMASEV 1: a DMA manager thread in the Non-secure state attempted to execute either: DMAWFE to wait for a secure event H18DMASEV to create a secure event or secure interrupt.

dmago_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security permissions: 0: appropriate security to execute DMAGO 1: Non-secure state attempted to execute DMAGO to create a DMA channel thread operating in the Secure state

reserved operand_invalid

3:2 1

rud sro,ns sraz,n snsro

0x0 0x0

read undefined Indicates whether the DMA manager was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA manager was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction.

Register (dmac) FTR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR0 FTC0 0x00000040 dmac0_ns: 0xF8004040 dmac0_s: 0xF8003040 32 bits mixed 0x00000000 Default Type DMA Channel 0

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Register FTR0 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

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Field Name mfifo_err

Bits 12

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

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Field Name reserved

Bits 4:2

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) FTR1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR1 XDmaPs_FTCn_OFFSET(1) 0x00000044 dmac0_ns: 0xF8004044 dmac0_s: 0xF8003044 32 bits mixed 0x00000000 Default Type DMA Channel 1

Register FTR1 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface.

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Field Name reserved

Bits 29:19

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

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Field Name reserved

Bits 11:8

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

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Register (dmac) FTR2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR2 XDmaPs_FTCn_OFFSET(2) 0x00000048 dmac0_ns: 0xF8004048 dmac0_s: 0xF8003048 32 bits mixed 0x00000000 Default Type DMA Channel 2

Register FTR2 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

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Field Name instr_fetch_err

Bits 16

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

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Appendix B: Register Details

Field Name ch_periph_err

Bits 6

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) FTR3

Name Software Name Relative Address Absolute Address FTR3 XDmaPs_FTCn_OFFSET(3) 0x0000004C dmac0_ns: 0xF800404C dmac0_s: 0xF800304C

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Width Access Type Reset Value Description

32 bits mixed 0x00000000 Default Type DMA Channel 3

Register FTR3 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro

0x0

read undefined

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Field Name st_data_unavailable

Bits 13

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

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Appendix B: Register Details

Field Name ch_evnt_err

Bits 5

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) FTR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR4 XDmaPs_FTCn_OFFSET(4) 0x00000050 dmac0_ns: 0xF8004050 dmac0_s: 0xF8003050 32 bits mixed 0x00000000 Default Type DMA Channel 4

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Register FTR4 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

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Field Name mfifo_err

Bits 12

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

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Appendix B: Register Details

Field Name reserved

Bits 4:2

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) FTR5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR5 XDmaPs_FTCn_OFFSET(5) 0x00000054 dmac0_ns: 0xF8004054 dmac0_s: 0xF8003054 32 bits mixed 0x00000000 Default Type DMA Channel 5

Register FTR5 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface.

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Appendix B: Register Details

Field Name reserved

Bits 29:19

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

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Appendix B: Register Details

Field Name reserved

Bits 11:8

Type sro,ns sraz,n snsro sro,ns sraz,n snsro

Reset Value 0x0 read undefined

Description

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

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Register (dmac) FTR6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description FTR6 XDmaPs_FTCn_OFFSET(6) 0x00000058 dmac0_ns: 0xF8004058 dmac0_s: 0xF8003058 32 bits mixed 0x00000000 Default Type DMA Channel 6

Register FTR6 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

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Field Name instr_fetch_err

Bits 16

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

st_data_unavailable

13

0x0

Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

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Field Name ch_periph_err

Bits 6

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

ch_evnt_err

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) FTR7

Name Software Name Relative Address Absolute Address FTR7 XDmaPs_FTCn_OFFSET(7) 0x0000005C dmac0_ns: 0xF800405C dmac0_s: 0xF800305C

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Width Access Type Reset Value Description

32 bits mixed 0x00000000 Default Type DMA Channel 7

Register FTR7 Details

Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr 30 sro,ns sraz,n snsro 0x0 If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0: system memory 1: debug interface. reserved 29:19 sro,ns sraz,n snsro sro,ns sraz,n snsro 0x0 read undefined

data_read_err

18

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

data_write_err

17

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.

instr_fetch_err

16

sro,ns sraz,n snsro

0x0

Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.

reserved

15:14

sro,ns sraz,n snsro

0x0

read undefined

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Field Name st_data_unavailable

Bits 13

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.

mfifo_err

12

sro,ns sraz,n snsro

0x0

Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.

reserved

11:8

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

ch_rdwr_err

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort.

ch_periph_err

sro,ns sraz,n snsro

0x0

Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP to notify a secure peripheral, or c) DMAFLUSHP to flush a secure peripheral. This fault is a precise abort.

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Field Name ch_evnt_err

Bits 5

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt. This fault is a precise abort.

reserved

4:2

sro,ns sraz,n snsro sro,ns sraz,n snsro

0x0

read undefined

operand_invalid

0x0

Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.

undef_instr

sro,ns sraz,n snsro

0x0

Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0: defined instruction 1: undefined instruction. This fault is a precise abort.

Register (dmac) CSR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR0 CS0 0x00000100 dmac0_ns: 0xF8004100 dmac0_s: 0xF8003100 32 bits mixed 0x00000000 Channel Status DMA Channel 0

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Register CSR0 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 0x0 reserved,read undefined When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces. dmawfp_b_ns 14 sro,ns sraz,n snsro 0x0 When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set reserved 13:9 rud 0x0 reserved

reserved dmawfp_periph

20:16 15

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Field Name wakeup_num

Bits 8:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

Register (dmac) CPC0

Name Relative Address Absolute Address Width Access Type Reset Value Description CPC0 0x00000104 dmac0_ns: 0xF8004104 dmac0_s: 0xF8003104 32 bits mixed 0x00000000 Channel PC for DMA Channel 0

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Register CPC0 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR1 XDmaPs_CSn_OFFSET(1) 0x00000108 dmac0_ns: 0xF8004108 dmac0_s: 0xF8003108 32 bits mixed 0x00000000 Channel Status DMA Channel 1

Register CSR1 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 0x0 reserved,read undefined When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces. dmawfp_b_ns 14 sro,ns sraz,n snsro 0x0 When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set reserved 13:9 rud 0x0 reserved

reserved dmawfp_periph

20:16 15

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Field Name wakeup_num

Bits 8:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

Register (dmac) CPC1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value CPC1 XDmaPs_CPCn_OFFSET(1) 0x0000010C dmac0_ns: 0xF800410C dmac0_s: 0xF800310C 32 bits mixed 0x00000000

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Appendix B: Register Details

Description

Channel PC for DMA Channel 1

Register CPC1 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR2 XDmaPs_CSn_OFFSET(2) 0x00000110 dmac0_ns: 0xF8004110 dmac0_s: 0xF8003110 32 bits mixed 0x00000000 Channel Status DMA Channel 2

Register CSR2 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 0x0 reserved,read undefined When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces. dmawfp_b_ns 14 sro,ns sraz,n snsro 0x0 When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved dmawfp_periph

20:16 15

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Field Name reserved wakeup_num

Bits 13:9 8:4

Type rud sro,ns sraz,n snsro

Reset Value 0x0 0x0 reserved

Description

When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

Register (dmac) CPC2

Name Software Name Relative Address Absolute Address Width Access Type CPC2 XDmaPs_CPCn_OFFSET(2) 0x00000114 dmac0_ns: 0xF8004114 dmac0_s: 0xF8003114 32 bits mixed

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Reset Value Description

0x00000000 Channel PC for DMA Channel 2

Register CPC2 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR3 XDmaPs_CSn_OFFSET(3) 0x00000118 dmac0_ns: 0xF8004118 dmac0_s: 0xF8003118 32 bits mixed 0x00000000 Channel Status DMA Channel 3

Register CSR3 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 0x0 reserved,read undefined When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.

reserved dmawfp_periph

20:16 15

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Field Name dmawfp_b_ns

Bits 14

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved wakeup_num

13:9 8:4

rud sro,ns sraz,n snsro

0x0 0x0

reserved When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

Register (dmac) CPC3

Name Software Name Relative Address CPC3 XDmaPs_CPCn_OFFSET(3) 0x0000011C

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Absolute Address Width Access Type Reset Value Description

dmac0_ns: 0xF800411C dmac0_s: 0xF800311C 32 bits mixed 0x00000000 Channel PC for DMA Channel 3

Register CPC3 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR4 XDmaPs_CSn_OFFSET(4) 0x00000120 dmac0_ns: 0xF8004120 dmac0_s: 0xF8003120 32 bits mixed 0x00000000 Channel Status DMA Channel 4

Register CSR4 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 reserved,read undefined

reserved

20:16

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Field Name dmawfp_periph

Bits 15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.

dmawfp_b_ns

14

sro,ns sraz,n snsro

0x0

When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved wakeup_num

13:9 8:4

rud sro,ns sraz,n snsro

0x0 0x0

reserved When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

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Register (dmac) CPC4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CPC4 XDmaPs_CPCn_OFFSET(4) 0x00000124 dmac0_ns: 0xF8004124 dmac0_s: 0xF8003124 32 bits mixed 0x00000000 Channel PC for DMA Channel 4

Register CPC4 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR5 XDmaPs_CSn_OFFSET(5) 0x00000128 dmac0_ns: 0xF8004128 dmac0_s: 0xF8003128 32 bits mixed 0x00000000 Channel Status DMA Channel 5

Register CSR5 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 reserved,read undefined

reserved

20:16

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Field Name dmawfp_periph

Bits 15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.

dmawfp_b_ns

14

sro,ns sraz,n snsro

0x0

When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved wakeup_num

13:9 8:4

rud sro,ns sraz,n snsro

0x0 0x0

reserved When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

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Appendix B: Register Details

Register (dmac) CPC5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CPC5 XDmaPs_CPCn_OFFSET(5) 0x0000012C dmac0_ns: 0xF800412C dmac0_s: 0xF800312C 32 bits mixed 0x00000000 Channel PC for DMA Channel 5

Register CPC5 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR6 XDmaPs_CSn_OFFSET(6) 0x00000130 dmac0_ns: 0xF8004130 dmac0_s: 0xF8003130 32 bits mixed 0x00000000 Channel Status DMA Channel 6

Register CSR6 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 reserved,read undefined

reserved

20:16

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Field Name dmawfp_periph

Bits 15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.

dmawfp_b_ns

14

sro,ns sraz,n snsro

0x0

When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved wakeup_num

13:9 8:4

rud sro,ns sraz,n snsro

0x0 0x0

reserved When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

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Register (dmac) CPC6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CPC6 XDmaPs_CPCn_OFFSET(6) 0x00000134 dmac0_ns: 0xF8004134 dmac0_s: 0xF8003134 32 bits mixed 0x00000000 Channel PC for DMA Channel 6

Register CPC6 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) CSR7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CSR7 XDmaPs_CSn_OFFSET(7) 0x00000138 dmac0_ns: 0xF8004138 dmac0_s: 0xF8003138 32 bits mixed 0x00000000 Channel Status DMA Channel 7

Register CSR7 Details

Field Name reserved CNS Bits 31:22 21 Type rud sro,ns sraz,n snsro rud Reset Value 0x0 0x0 Description reserved,read undefined Security status of the DMA channel thread: 0: Secure state 1: Non-secure state. 0x0 reserved,read undefined

reserved

20:16

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Field Name dmawfp_periph

Bits 15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.

dmawfp_b_ns

14

sro,ns sraz,n snsro

0x0

When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set

reserved wakeup_num

13:9 8:4

rud sro,ns sraz,n snsro

0x0 0x0

reserved When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ... 0 1111: waiting for event 15 1 xxxx: reserved Waiting for Peripheral (WFP): 0 0000: waiting for peripheral 0 0 0001: waiting for peripheral 1 0 0010: waiting for peripheral 2 0 0011: waiting for peripheral 3 1 11xx: reserved

channel_status

3:0

sro,ns sraz,n snsro

0x0

The channel status encoding is: 0000: Stopped 0001: Executing 0010: Cache miss 0011: Updating PC 0100: Waiting for event 0101: At barrier 0110: reserved 0111: Waiting for peripheral 1000: Killing 1001: Completing 1010 to 1101: reserved 1110: Faulting completing 1111: Faulting.

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Register (dmac) CPC7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CPC7 XDmaPs_CPCn_OFFSET(7) 0x0000013C dmac0_ns: 0xF800413C dmac0_s: 0xF800313C 32 bits mixed 0x00000000 Channel PC for DMA Channel 7

Register CPC7 Details

Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.

Register (dmac) SAR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description SAR0 SA_0 0x00000400 dmac0_ns: 0xF8004400 dmac0_s: 0xF8003400 32 bits mixed 0x00000000 Source Address DMA Channel 0

Register SAR0 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR0

Name DAR0

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

DA_0 0x00000404 dmac0_ns: 0xF8004404 dmac0_s: 0xF8003404 32 bits mixed 0x00000000 Destination Addr DMA Channel 0

Register DAR0 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR0 CC_0 0x00000408 dmac0_ns: 0xF8004408 dmac0_s: 0xF8003408 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 0

Register CCR0 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved

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Field Name dst_cache_ctrl

Bits 27:25

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol.

dst_prot_ctrl

24:22

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts.

dst_burst_len

21:18

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

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Field Name dst_burst_size

Bits 17:15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

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Field Name src_burst_len

Bits 7:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_0

Name Relative Address Absolute Address Width Access Type Reset Value Description LC0_0 0x0000040C dmac0_ns: 0xF800440C dmac0_s: 0xF800340C 32 bits mixed 0x00000000 Loop Counter 0 DMA Channel 0

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Register LC0_0 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_0

Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_0 0x00000410 dmac0_ns: 0xF8004410 dmac0_s: 0xF8003410 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 0

Register LC1_0 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value SAR1 XDmaPs_SA_n_OFFSET(1) 0x00000420 dmac0_ns: 0xF8004420 dmac0_s: 0xF8003420 32 bits mixed 0x00000000

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Description

Source address DMA Channel 1

Register SAR1 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR1 XDmaPs_DA_n_OFFSET(1) 0x00000424 dmac0_ns: 0xF8004424 dmac0_s: 0xF8003424 32 bits mixed 0x00000000 Destination Addr DMA Channel 1

Register DAR1 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR1 XDmaPs_CC_n_OFFSET(1) 0x00000428 dmac0_ns: 0xF8004428 dmac0_s: 0xF8003428 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 1

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Register CCR1 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol. dst_prot_ctrl 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts. dst_burst_len 21:18 sro,ns sraz,n snsro 0x0 For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

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Field Name dst_burst_size

Bits 17:15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

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Field Name src_burst_len

Bits 7:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value LC0_1 XDmaPs_LC0_n_OFFSET(1) 0x0000042C dmac0_ns: 0xF800442C dmac0_s: 0xF800342C 32 bits mixed 0x00000000

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Description

Loop Counter 0 DMA Channel 1

Register LC0_1 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_1 XDmaPs_LC1_n_OFFSET(1) 0x00000430 dmac0_ns: 0xF8004430 dmac0_s: 0xF8003430 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 1

Register LC1_1 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR2

Name Software Name Relative Address Absolute Address Width SAR2 XDmaPs_SA_n_OFFSET(2) 0x00000440 dmac0_ns: 0xF8004440 dmac0_s: 0xF8003440 32 bits

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Access Type Reset Value Description

mixed 0x00000000 Source Address DMA Channel 2

Register SAR2 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR2 XDmaPs_DA_n_OFFSET(2) 0x00000444 dmac0_ns: 0xF8004444 dmac0_s: 0xF8003444 32 bits mixed 0x00000000 Destination Addr DMA Channel 2

Register DAR2 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR2

Name Software Name Relative Address Absolute Address Width Access Type CCR2 XDmaPs_CC_n_OFFSET(2) 0x00000448 dmac0_ns: 0xF8004448 dmac0_s: 0xF8003448 32 bits mixed

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Reset Value Description

dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 2

Register CCR2 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol. dst_prot_ctrl 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts.

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Field Name dst_burst_len

Bits 21:18

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

dst_burst_size

17:15

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

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Field Name src_prot_ctrl

Bits 10:8

Type sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x2

Description Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

src_burst_len

7:4

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

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Register (dmac) LC0_2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC0_2 XDmaPs_LC0_n_OFFSET(2) 0x0000044C dmac0_ns: 0xF800444C dmac0_s: 0xF800344C 32 bits mixed 0x00000000 Loop Counter 0 DMA Channel 2

Register LC0_2 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_2 XDmaPs_LC1_n_OFFSET(2) 0x00000450 dmac0_ns: 0xF8004450 dmac0_s: 0xF8003450 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 2

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Register LC1_2 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description SAR3 XDmaPs_SA_n_OFFSET(3) 0x00000460 dmac0_ns: 0xF8004460 dmac0_s: 0xF8003460 32 bits mixed 0x00000000 Source Address DMA Channel 3

Register SAR3 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR3 XDmaPs_DA_n_OFFSET(3) 0x00000464 dmac0_ns: 0xF8004464 dmac0_s: 0xF8003464 32 bits mixed 0x00000000 Destination Addr DMA Channel 3

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Register DAR3 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR3 XDmaPs_CC_n_OFFSET(3) 0x00000468 dmac0_ns: 0xF8004468 dmac0_s: 0xF8003468 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 3

Register CCR3 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol.

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Field Name dst_prot_ctrl

Bits 24:22

Type sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x2

Description Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts.

dst_burst_len

21:18

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

dst_burst_size

17:15

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

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Field Name src_cache_ctrl

Bits 13:11

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

src_burst_len

7:4

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

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Field Name src_burst_size

Bits 3:1

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC0_3 XDmaPs_LC0_n_OFFSET(3) 0x0000046C dmac0_ns: 0xF800446C dmac0_s: 0xF800346C 32 bits mixed 0x00000000 Loop Counter 0 DMA Channel 3

Register LC0_3 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

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Register (dmac) LC1_3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_3 XDmaPs_LC1_n_OFFSET(3) 0x00000470 dmac0_ns: 0xF8004470 dmac0_s: 0xF8003470 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 3

Register LC1_3 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description SAR4 XDmaPs_SA_n_OFFSET(4) 0x00000480 dmac0_ns: 0xF8004480 dmac0_s: 0xF8003480 32 bits mixed 0x00000000 Source Address DMA Channel 4

Register SAR4 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

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Register (dmac) DAR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR4 XDmaPs_DA_n_OFFSET(4) 0x00000484 dmac0_ns: 0xF8004484 dmac0_s: 0xF8003484 32 bits mixed 0x00000000 Destination Addr DMA Channel 4

Register DAR4 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR4 XDmaPs_CC_n_OFFSET(4) 0x00000488 dmac0_ns: 0xF8004488 dmac0_s: 0xF8003488 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 4

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Register CCR4 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol. dst_prot_ctrl 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts. dst_burst_len 21:18 sro,ns sraz,n snsro 0x0 For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

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Field Name dst_burst_size

Bits 17:15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

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Field Name src_burst_len

Bits 7:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value LC0_4 XDmaPs_LC0_n_OFFSET(4) 0x0000048C dmac0_ns: 0xF800448C dmac0_s: 0xF800348C 32 bits mixed 0x00000000

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Description

Loop Counter 0 DMA Channel 4

Register LC0_4 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_4 XDmaPs_LC1_n_OFFSET(4) 0x00000490 dmac0_ns: 0xF8004490 dmac0_s: 0xF8003490 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 4

Register LC1_4 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR5

Name Software Name Relative Address Absolute Address Width SAR5 XDmaPs_SA_n_OFFSET(5) 0x000004A0 dmac0_ns: 0xF80044A0 dmac0_s: 0xF80034A0 32 bits

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Access Type Reset Value Description

mixed 0x00000000 Source Address DMA Channel 5

Register SAR5 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR5 XDmaPs_DA_n_OFFSET(5) 0x000004A4 dmac0_ns: 0xF80044A4 dmac0_s: 0xF80034A4 32 bits mixed 0x00000000 Destination Addr DMA Channel 5

Register DAR5 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR5

Name Software Name Relative Address Absolute Address Width Access Type CCR5 XDmaPs_CC_n_OFFSET(5) 0x000004A8 dmac0_ns: 0xF80044A8 dmac0_s: 0xF80034A8 32 bits mixed

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Reset Value Description

dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 5

Register CCR5 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol. dst_prot_ctrl 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts.

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Field Name dst_burst_len

Bits 21:18

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

dst_burst_size

17:15

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

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Field Name src_prot_ctrl

Bits 10:8

Type sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x2

Description Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

src_burst_len

7:4

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

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Register (dmac) LC0_5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC0_5 XDmaPs_LC0_n_OFFSET(5) 0x000004AC dmac0_ns: 0xF80044AC dmac0_s: 0xF80034AC 32 bits mixed 0x00000000 Loop Counter 0 DMA Channel 5

Register LC0_5 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_5

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_5 XDmaPs_LC1_n_OFFSET(5) 0x000004B0 dmac0_ns: 0xF80044B0 dmac0_s: 0xF80034B0 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 5

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Register LC1_5 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description SAR6 XDmaPs_SA_n_OFFSET(6) 0x000004C0 dmac0_ns: 0xF80044C0 dmac0_s: 0xF80034C0 32 bits mixed 0x00000000 Source Address DMA Channel 6

Register SAR6 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

Register (dmac) DAR6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR6 XDmaPs_DA_n_OFFSET(6) 0x000004C4 dmac0_ns: 0xF80044C4 dmac0_s: 0xF80034C4 32 bits mixed 0x00000000 Destination Addr DMA Channel 6

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Register DAR6 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR6 XDmaPs_CC_n_OFFSET(6) 0x000004C8 dmac0_ns: 0xF80044C8 dmac0_s: 0xF80034C8 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 6

Register CCR6 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol.

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Field Name dst_prot_ctrl

Bits 24:22

Type sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x2

Description Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts.

dst_burst_len

21:18

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

dst_burst_size

17:15

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

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Field Name src_cache_ctrl

Bits 13:11

Type sro,ns sraz,n snsro

Reset Value 0x0

Description Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

src_burst_len

7:4

sro,ns sraz,n snsro

0x0

For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

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Field Name src_burst_size

Bits 3:1

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC0_6 XDmaPs_LC0_n_OFFSET(6) 0x000004CC dmac0_ns: 0xF80044CC dmac0_s: 0xF80034CC 32 bits mixed 0x00000000 Loop Counter 0 DMA Channel 6

Register LC0_6 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

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Register (dmac) LC1_6

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_6 XDmaPs_LC1_n_OFFSET(6) 0x000004D0 dmac0_ns: 0xF80044D0 dmac0_s: 0xF80034D0 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 6

Register LC1_6 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) SAR7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description SAR7 XDmaPs_SA_n_OFFSET(7) 0x000004E0 dmac0_ns: 0xF80044E0 dmac0_s: 0xF80034E0 32 bits mixed 0x00000000 Source Address DMA Channel 7

Register SAR7 Details

Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.

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Register (dmac) DAR7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DAR7 XDmaPs_DA_n_OFFSET(7) 0x000004E4 dmac0_ns: 0xF80044E4 dmac0_s: 0xF80034E4 32 bits mixed 0x00000000 Destination Addr DMA Channel 7

Register DAR7 Details

Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.

Register (dmac) CCR7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CCR7 XDmaPs_CC_n_OFFSET(7) 0x000004E8 dmac0_ns: 0xF80044E8 dmac0_s: 0xF80034E8 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Channel Control DMA Channel 7

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Register CCR7 Details

Field Name reserved endian_swap_size Bits 31 30:28 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Data swap: little-endian and byte-invariant big-endian (BE-8) formats. 000: No swap, 8-bit data 001: Swap bytes within 16-bit data 010: Swap bytes within 32-bit data 011: Swap bytes within 64-bit data 100: Swap bytes within 128-bit data 101 to 111: Reserved dst_cache_ctrl 27:25 sro,ns sraz,n snsro 0x0 Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol. dst_prot_ctrl 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] Low, then the DMA channel aborts. dst_burst_len 21:18 sro,ns sraz,n snsro 0x0 For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWLEN[3:0].

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Field Name dst_burst_size

Bits 17:15

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note: These bits control the state of AWSIZE[2:0].

dst_inc

14

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it writes the destination data: 0: Fixed-address burst. The DMAC signals AWBURST[0] Low. 1: Incrementing-address burst. The DMAC signals AWBURST[0] HIgh.

src_cache_ctrl

13:11

sro,ns sraz,n snsro

0x0

Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.

src_prot_ctrl

10:8

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x2

Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] Low, the DMA channel aborts.

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Field Name src_burst_len

Bits 7:4

Type sro,ns sraz,n snsro

Reset Value 0x0

Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARLEN[3:0].

src_burst_size

3:1

sro,ns sraz,n snsro

0x0

For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note: These bits control the state of ARSIZE[2:0].

src_inc

sro,ns sraz,n snsro

0x0

Programs the burst type that the DMAC performs when it reads the source data: 0: Fixed-address burst, DMAC signal ARBURST[0] driven Low. 1: Incrementing-address burst, DMAC signal ARBURST[0] driven High.

Register (dmac) LC0_7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value LC0_7 XDmaPs_LC0_n_OFFSET(7) 0x000004EC dmac0_ns: 0xF80044EC dmac0_s: 0xF80034EC 32 bits mixed 0x00000000

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Description

Loop Counter 0 DMA Channel 7

Register LC0_7 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.

Register (dmac) LC1_7

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description LC1_7 XDmaPs_LC1_n_OFFSET(7) 0x000004F0 dmac0_ns: 0xF80044F0 dmac0_s: 0xF80034F0 32 bits mixed 0x00000000 Loop Counter 1 DMA Channel 7

Register LC1_7 Details

Field Name reserved loop_counter_iteration Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.

Register (dmac) DBGSTATUS

Name Relative Address Absolute Address Width Access Type DBGSTATUS 0x00000D00 dmac0_ns: 0xF8004D00 dmac0_s: 0xF8003D00 32 bits mixed

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Reset Value Description

0x00000000 DMA Manager Execution Status

Register DBGSTATUS Details

Field Name reserved dbgstatus Bits 31:1 0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 Description reserved, read undefined The DMA manager Execution/Debug status: 0: Idle 1: Busy.

Register (dmac) DBGCMD

Name Relative Address Absolute Address Width Access Type Reset Value Description DBGCMD 0x00000D04 dmac0_ns: 0xF8004D04 dmac0_s: 0xF8003D04 32 bits mixed 0x00000000 DMA Manager Instr. Command

Register DBGCMD Details

Field Name reserved dbgcmd Bits 31:2 1:0 Type rud swo,n ssraz, nsns wo Reset Value 0x0 0x0 Description reserved, read undefined Command the DMA manager to execute the instruction defined in the two DBGINST registers. 00: execute the instruction. others: reserved.

Register (dmac) DBGINST0

Name Relative Address Absolute Address Width Access Type Reset Value DBGINST0 0x00000D08 dmac0_ns: 0xF8004D08 dmac0_s: 0xF8003D08 32 bits mixed 0x00000000

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Description

DMA Manager Instruction Part A

Register DBGINST0 Details

Field Name instruction_byte1 Bits 31:24 Type swo,n ssraz, nsns wo swo,n ssraz, nsns wo waz swo,n ssraz, nsns wo Reset Value 0x0 instruction byte 1 Description

instruction_byte0

23:16

0x0

instruction byte 0

reserved channel_num

15:11 10:8

0x0 0x0

reserved, write as 0 DMA channel number: 000: DMA channel 0 001: DMA channel 1 010: DMA channel 2 ... 111: DMA channel 7

reserved debug_thread

7:1 0

waz swo,n ssraz, nsns wo

0x0 0x0

reserved, write as 0 The debug thread encoding is as folLows: 0: DMA manager thread 1: DMA channel. Note: When set to 1, the Channel number field selects the DMA channel to debug.

Register (dmac) DBGINST1

Name Relative Address Absolute Address Width Access Type Reset Value Description DBGINST1 0x00000D0C dmac0_ns: 0xF8004D0C dmac0_s: 0xF8003D0C 32 bits mixed 0x00000000 DMA Manager Instruction Part B

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Register DBGINST1 Details

Field Name instruction_byte5 Bits 31:24 Type swo,n ssraz, nsns wo swo,n ssraz, nsns wo swo,n ssraz, nsns wo swo,n ssraz, nsns wo Reset Value 0x0 instruction byte 5 Description

instruction_byte4

23:16

0x0

instruction byte 4

instruction_byte3

15:8

0x0

instruction byte 3

instruction_byte2

7:0

0x0

instruction byte 2

Register (dmac) CR0

Name Relative Address Absolute Address Width Access Type Reset Value Description CR0 0x00000E00 dmac0_ns: 0xF8004E00 dmac0_s: 0xF8003E00 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x001E3071 Config. 0: Events, Peripheral Interfaces, PC, Mode

Register CR0 Details

Field Name reserved num_events Bits 31:22 21:17 Type rud sro,ns sraz,n snsro sro,ns sraz,n snsro rud Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0xF dmac0_ns: 0x0 dmac0_s: 0x3 0x0 read undefined The DMA Controller supports 16 events. This register always reads 01111 (15d). The DMA Controller supports four peripheral interfaces. This register always reads 00011 (3d). read undefined Description

num_periph_req

16:12

reserved

11:7

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Field Name num_chnls

Bits 6:4

Type sro,ns sraz,n snsro rud sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x7 0x0 0x0

Description The DMA Controller supports eight channel threads. This register always reads 00111 (7d). read undefined Indicates the status of the slcr.TZ_DMA_NS bit when the DMAC exits from reset: 0: TZ_DMA_NS was Low 1: TZ_DMA_NS was HIgh

reserved mgr_ns_at_rst

3 2

boot_en

sro,ns sraz,n snsro

0x0

Indicates the status of the boot_from_pc signal when the DMAC exited from reset: 0 = boot_from_pc was LOW 1 = boot_from_pc was HIGH.

periph_req

sro,ns sraz,n snsro

dmac0_ns: 0x0 dmac0_s: 0x1

The DMAC provides the peripheral request interfaces.

Register (dmac) CR1

Name Relative Address Absolute Address Width Access Type Reset Value Description CR1 0x00000E04 dmac0_ns: 0xF8004E04 dmac0_s: 0xF8003E04 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00000074 Config. 1: Instruction Cache

Register CR1 Details

Field Name reserved num_icache_lines Bits 31:8 7:4 Type rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x7 0x0 dmac0_ns: 0x0 dmac0_s: 0x4 read undefined The length of an i-cache line is sixteen bytes. read undefined The DMAC iCache has eight lines. Description

reserved icache_len

3 2:0

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Register (dmac) CR2

Name Relative Address Absolute Address Width Access Type Reset Value Description CR2 0x00000E08 dmac0_ns: 0xF8004E08 dmac0_s: 0xF8003E08 32 bits mixed 0x00000000 Config. 2: DMA Mgr Boot Addr

Register CR2 Details

Field Name boot_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description The boot address for the DMAC manager is hardwired to 0. This is a system memory address.

Register (dmac) CR3

Name Relative Address Absolute Address Width Access Type Reset Value Description CR3 0x00000E0C dmac0_ns: 0xF8004E0C dmac0_s: 0xF8003E0C 32 bits mixed 0x00000000 Config. 3: Security state of IRQs

Register CR3 Details

Field Name INS Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description The value of the slcr.TZ_DMA_IRQ_NS bits (boot_irq_ns signals) when the DMAC reset deasserts. Reserved

Register (dmac) CR4

Name Relative Address CR4 0x00000E10

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Absolute Address Width Access Type Reset Value Description

dmac0_ns: 0xF8004E10 dmac0_s: 0xF8003E10 32 bits mixed 0x00000000 Config 4, Security of Periph Interfaces

Register CR4 Details

Field Name PNS Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Reflects the slcr.TZ_DMA_PERIPH_NS register values for the four peripheral request interfaces when the DMAC is unreset. 0: Secure state 1: Non-secure state Reserved

Register (dmac) CRD

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CRD CRDN 0x00000E14 dmac0_ns: 0xF8004E14 dmac0_s: 0xF8003E14 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x07FF7F73 DMA configuration

Register CRD Details

Field Name reserved data_buffer_dep Bits 31:30 29:20 Type rud sro,ns sraz,n snsro sro,ns sraz,n snsro rud Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x7F dmac0_ns: 0x0 dmac0_s: 0xF 0x0 The depth of the Read Queue is hardwired at 16 lines. read undefined read undefined The MFIFO dept is 128 double words (64-bit). Description

rd_q_dep

19:16

reserved

15

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Field Name rd_cap

Bits 14:12

Type sro,ns sraz,n snsro sro,ns sraz,n snsro rud sro,ns sraz,n snsro rud sro,ns sraz,n snsro

Reset Value dmac0_ns: 0x0 dmac0_s: 0x7 dmac0_ns: 0x0 dmac0_s: 0xF 0x0 dmac0_ns: 0x0 dmac0_s: 0x7 0x0 dmac0_ns: 0x0 dmac0_s: 0x3

Description The number of possible outstanding Read Transactions is hardwired at 8. The depth of the Write Queue is hardwired at 16 lines. read undefined The number of outstanding Write Transactions is is hardwired at 8. read undefined The data width of the AXI master interface 64 bits.

wr_q_dep

11:8

reserved wr_cap

7 6:4

reserved data_width

3 2:0

Register (dmac) WD
Name Relative Address Absolute Address Width Access Type Reset Value Description WD 0x00000E80 dmac0_ns: 0xF8004E80 dmac0_s: 0xF8003E80 32 bits mixed 0x00000000 Watchdog Timer

Register WD Details
Field Name reserved wd_irq_only Bits 31:1 0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 read undefined When a lock-up is detected, the DMAC aborts the DMA channel thread and asserts the Abort interrupt. Description

Register (dmac) periph_id_0

Name Software Name Relative Address periph_id_0 PERIPH_ID_0 0x00000FE0

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Absolute Address Width Access Type Reset Value Description

dmac0_ns: 0xF8004FE0 dmac0_s: 0xF8003FE0 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00000030 Peripheral Idenfication register 0

Register periph_id_0 Details

Field Name reserved part_number_0 Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x30 read undefined returns 0x30 Description

Register (dmac) periph_id_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description periph_id_1 PERIPH_ID_1 0x00000FE4 dmac0_ns: 0xF8004FE4 dmac0_s: 0xF8003FE4 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00000013 Peripheral Idenfication register 1

Register periph_id_1 Details

Field Name reserved designer_0 Bits 31:8 7:4 Type rud sro,ns sraz,n snsro sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x1 dmac0_ns: 0x0 dmac0_s: 0x3 returns 0x3 read undefined returns 0x1 Description

part_number_1

3:0

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Register (dmac) periph_id_2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description periph_id_2 PERIPH_ID_2 0x00000FE8 dmac0_ns: 0xF8004FE8 dmac0_s: 0xF8003FE8 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00000024 Peripheral Idenfication register 2

Register periph_id_2 Details

Field Name reserved revision Bits 31:8 7:4 Type rud sro,ns sraz,n snsro sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x2 dmac0_ns: 0x0 dmac0_s: 0x4 returns 0x4 read undefined DMAC IP revision is r1p1. Description

designer_1

3:0

Register (dmac) periph_id_3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description periph_id_3 PERIPH_ID_3 0x00000FEC dmac0_ns: 0xF8004FEC dmac0_s: 0xF8003FEC 32 bits mixed 0x00000000 Peripheral Idenfication register 3

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Appendix B: Register Details

Register periph_id_3 Details

Field Name reserved integration_cfg Bits 31:1 0 Type rud sro,ns sraz,n snsro Reset Value 0x0 0x0 read undefined The DMAC does not contain integration test logic Description

Register (dmac) pcell_id_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description pcell_id_0 PCELL_ID_0 0x00000FF0 dmac0_ns: 0xF8004FF0 dmac0_s: 0xF8003FF0 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x0000000D Compontent Idenfication register 0

Register pcell_id_0 Details

Field Name reserved pcell_id_0 Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0xD read undefined returnx 0x0D Description

Register (dmac) pcell_id_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value pcell_id_1 PCELL_ID_1 0x00000FF4 dmac0_ns: 0xF8004FF4 dmac0_s: 0xF8003FF4 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x000000F0

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Appendix B: Register Details

Description

Compontent Idenfication register 1

Register pcell_id_1 Details

Field Name reserved pcell_id_1 Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0xF0 read undefined returns 0xF0 Description

Register (dmac) pcell_id_2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description pcell_id_2 PCELL_ID_2 0x00000FF8 dmac0_ns: 0xF8004FF8 dmac0_s: 0xF8003FF8 32 bits mixed dmac0_ns: 0x00000000 dmac0_s: 0x00000005 Compontent Idenfication register 2

Register pcell_id_2 Details

Field Name reserved pcell_id_2 Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0x5 read undefined returns 0x05 Description

Register (dmac) pcell_id_3

Name Software Name Relative Address Absolute Address Width Access Type pcell_id_3 PCELL_ID_3 0x00000FFC dmac0_ns: 0xF8004FFC dmac0_s: 0xF8003FFC 32 bits mixed

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Appendix B: Register Details

Reset Value Description

dmac0_ns: 0x00000000 dmac0_s: 0x000000B1 Compontent Idenfication register 3

Register pcell_id_3 Details

Field Name reserved pcell_id_3 Bits 31:8 7:0 Type rud sro,ns sraz,n snsro Reset Value 0x0 dmac0_ns: 0x0 dmac0_s: 0xB1 read undefined returns 0xB1 Description

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Appendix B: Register Details

B.18 Gigabit Ethernet Controller (GEM)

Module Name Base Address Description Vendor Info Gigabit Ethernet Controller (GEM) 0xE000B000 gem0 0xE000C000 gem1 Gigabit Ethernet Controller

Register Summary
Register Name net_ctrl net_cfg net_status user_io dma_cfg tx_status rx_qbar tx_qbar rx_status intr_status intr_en intr_dis intr_mask phy_maint rx_pauseq tx_pauseq hash_bot hash_top spec_addr1_bot spec_addr1_top spec_addr2_bot spec_addr2_top Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000080 0x00000084 0x00000088 0x0000008C 0x00000090 0x00000094 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type mixed rw ro mixed mixed mixed mixed mixed mixed mixed wo wo mixed rw ro rw rw rw rw mixed rw mixed Reset Value 0x00000000 0x00080000 x x 0x00020784 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 x x x 0x00000000 0x00000000 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description Network Control Network Configuration Network Status User Input/Output DMA Configuration Transmit Status Receive Buffer Queue Base Address Transmit Buffer Queue Base Address Receive Status Interrupt Status Interrupt Enable Interrupt Disable Interrupt Mask Status PHY Maintenance Received Pause Quantum Transmit Pause Quantum Hash Register Bottom [31:0] Hash Register Top [63:32] Specific Address 1 Bottom [31:0] Specific Address 1 Top [47:32] Specific Address 2 Bottom [31:0] Specific Address 2 Top [47:32]

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Register Name spec_addr3_bot spec_addr3_top spec_addr4_bot spec_addr4_top type_id_match1 type_id_match2 type_id_match3 type_id_match4 wake_on_lan ipg_stretch stacked_vlan tx_pfc_pause spec_addr1_mask_bot spec_addr1_mask_top module_id octets_tx_bot octets_tx_top frames_tx broadcast_frames_tx multi_frames_tx pause_frames_tx frames_64b_tx frames_65to127b_tx frames_128to255b_tx frames_256to511b_tx frames_512to1023b_tx frames_1024to1518b_tx tx_under_runs single_collisn_frames

Address 0x00000098 0x0000009C 0x000000A0 0x000000A4 0x000000A8 0x000000AC 0x000000B0 0x000000B4 0x000000B8 0x000000BC 0x000000C0 0x000000C4 0x000000C8 0x000000CC 0x000000FC 0x00000100 0x00000104 0x00000108 0x0000010C 0x00000110 0x00000114 0x00000118 0x0000011C 0x00000120 0x00000124 0x00000128 0x0000012C 0x00000134 0x00000138

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw mixed rw mixed mixed mixed mixed mixed mixed mixed mixed mixed rw mixed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00020118 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description Specific Address 3 Bottom [31:0] Specific Address 3 Top [47:32] Specific Address 4 Bottom [31:0] Specific Address 4 Top [47:32] Type ID Match 1 Type ID Match 2 Type ID Match 3 Type ID Match 4 Wake on LAN Register IPG stretch register Stacked VLAN Register Transmit PFC Pause Register Specific Address Mask 1 Bottom [31:0] Specific Address Mask 1 Top [47:32] Module ID Octets transmitted [31:0] (in frames without error) Octets transmitted [47:32] (in frames without error) Frames Transmitted Broadcast frames Tx Multicast frames Tx Pause frames Tx Frames Tx, 64-byte length Frames Tx, 65 to 127-byte length Frames Tx, 128 to 255-byte length Frames Tx, 256 to 511-byte length Frames Tx, 512 to 1023-byte length Frame Tx, 1024 to 1518-byte length Transmit under runs Single Collision Frames

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Appendix B: Register Details

Register Name multi_collisn_frames excessive_collisns late_collisns deferred_tx_frames carrier_sense_errs octets_rx_bot octets_rx_top frames_rx bdcast_fames_rx multi_frames_rx pause_rx frames_64b_rx frames_65to127b_rx frames_128to255b_rx frames_256to511b_rx frames_512to1023b_rx frames_1024to1518b_rx undersz_rx oversz_rx jab_rx fcs_errors length_field_errors rx_symbol_errors align_errors rx_resource_errors rx_overrun_errors ip_hdr_csum_errors tcp_csum_errors udp_csum_errors timer_strobe_s

Address 0x0000013C 0x00000140 0x00000144 0x00000148 0x0000014C 0x00000150 0x00000154 0x00000158 0x0000015C 0x00000160 0x00000164 0x00000168 0x0000016C 0x00000170 0x00000174 0x00000178 0x0000017C 0x00000184 0x00000188 0x0000018C 0x00000190 0x00000194 0x00000198 0x0000019C 0x000001A0 0x000001A4 0x000001A8 0x000001AC 0x000001B0 0x000001C8

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro rw

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description Multiple Collision Frames Excessive Collisions Late Collisions Deferred Transmission Frames Carrier Sense Errors. Octets Received [31:0] Octets Received [47:32] Frames Received Broadcast Frames Rx Multicast Frames Rx Pause Frames Rx Frames Rx, 64-byte length Frames Rx, 65 to 127-byte length Frames Rx, 128 to 255-byte length Frames Rx, 256 to 511-byte length Frames Rx, 512 to 1023-byte length Frames Rx, 1024 to 1518-byte length Undersize frames received Oversize frames received Jabbers received Frame check sequence errors Length field frame errors Receive symbol errors Alignment errors Receive resource errors Receive overrun errors IP header checksum errors TCP checksum errors UDP checksum error 1588 timer sync strobe seconds

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Register Name timer_strobe_ns timer_s timer_ns timer_adjust timer_incr ptp_tx_s ptp_tx_ns ptp_rx_s ptp_rx_ns ptp_peer_tx_s ptp_peer_tx_ns ptp_peer_rx_s ptp_peer_rx_ns design_cfg2 design_cfg3 design_cfg4 design_cfg5

Address 0x000001CC 0x000001D0 0x000001D4 0x000001D8 0x000001DC 0x000001E0 0x000001E4 0x000001E8 0x000001EC 0x000001F0 0x000001F4 0x000001F8 0x000001FC 0x00000284 0x00000288 0x0000028C 0x00000290

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type mixed rw mixed mixed mixed ro ro ro ro ro ro ro ro ro ro ro ro

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 x 0x00000000 0x00000000 x

Description 1588 timer sync strobe nanoseconds 1588 timer seconds 1588 timer nanoseconds 1588 timer adjust 1588 timer increment PTP event frame transmitted seconds PTP event frame transmitted nanoseconds PTP event frame received seconds PTP event frame received nanoseconds. PTP peer event frame transmitted seconds PTP peer event frame transmitted nanoseconds PTP peer event frame received seconds PTP peer event frame received nanoseconds. Design Configuration 2 Design Configuration 3 Design Configuration 4 Design Configuration 5

Register (GEM) net_ctrl

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description net_ctrl XEMACPS_NWCTRL 0x00000000 gem0: 0xE000B000 gem1: 0xE000C000 32 bits mixed 0x00000000 Network Control

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Register net_ctrl Details

The network control register contains general MAC control functions for both receiver and transmitter.
Field Name reserved flush_next_rx_dpram_ pkt Bits 31:19 18 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. tx_pfc_pri_pri_pause_f rame en_pfc_pri_pause_rx 17 wo 0x0 Transmit PFC Priority Based Pause Frame. Takes the values stored in the Transmit PFC Pause Register Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. str_rx_timestamp 15 rw 0x0 Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation. Reserved. Do not modify. Reserved. Do not modify. Transmit zero quantum pause frame. Writing one to this bit causes a pause frame with zero quantum to be transmitted. Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends. Start transmission - writing one to this bit starts transmission. Back pressure - if set in 10M or 100M half duplex mode will force collisions on all received frames. Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes.

16

wo

0x0

reserved reserved tx_zeroq_pause_frame (ZEROPAUSETX) tx_pause_frame (PAUSETX) tx_halt (HALTTX) start_tx (STARTTX) back_pressure wren_stat_regs (STATWEN) incr_stat_regs (STATINC)

14 13 12

rw wo wo

0x0 0x0 0x0

11 10

wo wo

0x0 0x0

9 8 7

wo rw rw

0x0 0x0 0x0

wo

0x0

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Appendix B: Register Details

Field Name clear_stat_regs (STATCLR) mgmt_port_en (MDEN) tx_en (TXEN)

Bits 5 4

Type wo rw

Reset Value 0x0 0x0

Description Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. Loop back local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. Local loopback functionality isn't available in the EP107 Zynq Emulation Platform, because the clocking doesn't map well into an FPGA. Reserved. Do not modify.

rw

0x0

rx_en (RXEN)

rw

0x0

loopback_local (LOOPEN)

rw

0x0

reserved

rw

0x0

Register (GEM) net_cfg

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description net_cfg XEMACPS_NWCFG 0x00000004 gem0: 0xE000B004 gem1: 0xE000C004 32 bits rw 0x00080000 Network Configuration

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Appendix B: Register Details

Register net_cfg Details

The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC
Field Name unidir_en Bits 31 Type rw Reset Value 0x0 Description Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down. Ignore IPG rx_er. When set rx_er has no effect on the GEM's operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. Receive bad preamble. When set frames with non-standard preamble are not rejected. IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. SGMII mode enable - changes behavior of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. rx_hd_while_tx (HDRXEN) rx_chksum_offld_en (RXCHKSUMEN) dis_cp_pause_frame (PAUSECOPYDI) 23 rw 0x0 24 rw 0x0 25 rw 0x0 Enable frames to be received in half-duplex mode while transmitting. Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found or whether a type ID match is identified. If a destination address match is found the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.

ignore_ipg_rx_er

30

rw

0x0

rx_bad_preamble (BADPREAMBEN) ipg_stretch_en (IPDSTRETCH)

29 28

rw rw

0x0 0x0

sgmii_en

27

rw

0x0

ignore_rx_fcs (FCSIGNORE)

26

rw

0x0

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Appendix B: Register Details

Field Name dbus_width

Bits 22:21

Type rw

Reset Value 0x0

Description Data bus width. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. Zynq defines gem_dma_bus_width_def as 2'b00. 00: 32 bit AMBA AHB data bus width 01: 64 bit AMBA AHB data bus width 10: 128 bit AMBA AHB data bus width 11: 128 bit AMBA AHB data bus width

mdc_clk_div (MDCCLKDIV)

20:18

rw

0x2

MDC clock division - set according to cpu_1xclk speed. These three bits determine the number cpu_1xclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). 000: divide cpu_1xclk by 8 (cpu_1xclk up to 20 MHz) 001: divide cpu_1xclk by 16 (cpu_1xclk up to 40 MHz) 010: divide cpu_1xclk by 32 (cpu_1xclk up to 80 MHz) 011: divide cpu_1xclk by 48 (cpu_1xclk up to 120MHz) 100: divide cpu_1xclk by 64 (cpu_1xclk up to 160 MHz) 101: divide cpu_1xclk by 96 (cpu_1xclk up to 240 MHz) 110: divide cpu_1xclk by 128 (cpu_1xclk up to 320 MHz) 111: divide cpu_1xclk by 224 (cpu_1xclk up to 540 MHz)

fcs_remove (FCSREM)

17

rw

0x0

FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer.

len_err_frame_disc (LENGTHERRDSCRD)

16

rw

0x0

rx_buf_offset (RXOFFS)

15:14

rw

0x0

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Appendix B: Register Details

Field Name pause_en (PAUSEEN) retry_test (RETRYTESTEN)

Bits 13

Type rw

Reset Value 0x0

Description Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle.

12

rw

0x0

pcs_sel

11

rw

0x0

PCS select - selects between MII/GMII and TBI. Must be set for SGMII operation. 0: GMII/MII interface enabled, TBI disabled 1: TBI enabled, GMII/MII disabled

gige_en (1000)

10

rw

0x0

Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII or TBI interface 1: Gigabit operation using GMII or TBI interface

ext_addr_match_en (EXTADDRMATCHEN ) rx_1536_byte_frames (1536RXEN)

rw

0x0

External address match enable - when set the external address match interface can be used to copy frames to memory. Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. Copy all frames - when set to logic one, all valid frames will be accepted. Reserved. Do not modify. Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic.

rw

0x0

uni_hash_en (UCASTHASHEN)

rw

0x0

multi_hash_en (MCASTHASHEN)

rw

0x0

no_broadcast (BCASTDI) copy_all (COPYALLEN) reserved disc_non_vlan (NVLANDISC)

rw

0x0

4 3 2

rw rw rw

0x0 0x0 0x0

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Appendix B: Register Details

Field Name full_duplex (FDEN)

Bits 1

Type rw

Reset Value 0x0

Description Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half-duplex pin. Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin.

speed (100)

rw

0x0

Register (GEM) net_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description net_status XEMACPS_NWSR 0x00000008 gem0: 0xE000B008 gem1: 0xE000C008 32 bits ro x Network Status

Register net_status Details

The network status register returns status information with respect to the PHY management interface.
Field Name reserved pfc_pri_pause_neg pcs_autoneg_pause_tx _res pcs_autoneg_pause_rx _res pcs_autoneg_dup_res Bits 31:7 6 5 4 3 Type ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 Description Reserved, read as zero, ignored on write. Set when PFC Priority Based Pause has been negotiated. PCS auto-negotiation pause transmit resolution. PCS auto-negotiation pause receive resolution PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one. The PHY management logic is idle (i.e. has completed).

phy_mgmt_idle

ro

0x1

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Appendix B: Register Details

Field Name mdio_in_pin_status (MDIO) pcs_link_state

Bits 1 0

Type ro ro

Reset Value x 0x0

Description Returns status of the mdio_in pin Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronization status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved, it is always set in the LINK_OK state in SGMII mode.

Register (GEM) user_io

Name Relative Address Absolute Address Width Access Type Reset Value Description user_io 0x0000000C gem0: 0xE000B00C gem1: 0xE000C00C 32 bits mixed x User Input/Output

Register user_io Details

The GEM design provides up to 16 inputs and 16 outputs so that the I/O can be read or set under the control of the processor interface. If the user I/O is disabled as a configuration option, this address space is defined as reserved, and hence will be a read-only register of the value 0x0. If enabled, the number of inputs and outputs can be configured separately. The first output will be represented in bit 0 of the user I/O register, the second output will use bit 1 and so on. The first input will be represented in bit 16 of the user I/O register, the second input will use bit 17 and so on.

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Appendix B: Register Details

Field Name user_in

Bits 31:16

Type ro x

Reset Value

Description User programmable inputs - the upper 16 bits of this register are used to monitor the state of the user inputs. A logic one read from a bit in this range will correspond to the input being in a high state. A logic zero read from a bit in this range will correspond to the input being in a low state. Any unused bits will be read as zero. Writing to any bits in this range will have no functional effect. User programmable outputs - the lower 16 bits of this register are used to control the state of the user outputs. A logic one written to a bit in this range will cause the corresponding output to be set high. A logic zero written to a bit in this range shall cause the corresponding output to be forced low. Any unused bits will be read as logic zero. Writing to any unused bits in this range will have no functional effect.

user_out

15:0

rw

0x0

Register (GEM) dma_cfg

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description dma_cfg XEMACPS_DMACR 0x00000010 gem0: 0xE000B010 gem1: 0xE000C010 32 bits mixed 0x00020784 DMA Configuration

Register dma_cfg Details

Field Name reserved disc_when_no_ahb Bits 31:25 24 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AHB resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AHB buffer resource next becomes available.

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Appendix B: Register Details

Field Name ahb_mem_rx_buf_size (RXBUF)

Bits 23:16

Type rw

Reset Value 0x2

Description DMA receive buffer size in AHB system memory. The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data. The value is defined in multiples of 64 bytes such that a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte 0x18: 1536 byte (1*max length frame/buffer) 0xA0: 10240 byte (1*10k jumbo frame/buffer) Note that this value should never be written as zero.

reserved csum_gen_offload_en (TCPCKSUM)

15:12 11

ro rw

0x0 0x0

Reserved, read as zero, ignored on write. Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Zynq uses packet buffer.

tx_pktbuf_memsz_sel (TXSIZE)

10

rw

0x1

Transmitter packet buffer memory size select Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 kB. 1: Use full configured addressable space (4 kB) 0: Do not use top address bit (2 kB) If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Zynq uses packet buffer.

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Appendix B: Register Details

Field Name rx_pktbuf_memsz_sel (RXSIZE)

Bits 9:8

Type rw

Reset Value 0x3

Description Receiver packet buffer memory size select Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 kBs. 00: Do not use top three address bits (1 kB) 01: Do not use top two address bits (2 kB) 10: Do not use top address bit (4 kB) 11: Use full configured addressable space (8 kB) If the controller is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as zero, ignored on write. Zynq uses packet buffer.

ahb_endian_swp_pkt_ en (ENDIAN) ahb_endian_swp_mgm t_en

rw

0x1

AHB endian swap mode enable for packet data accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode. AHB endian swap mode enable for management descriptor accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode. Reserved, read as zero, ignored on write AHB fixed burst length for DMA data operations - Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used. Upper bits become non-writeable if the configured DMA TX and RX FIFO sizes are smaller than required to support the selected burst size. One-hot priority encoding enforced automatically on register writes as follows, where 'x' represents don't care: 00001: Always use SINGLE AHB bursts 0001x: Always use SINGLE AHB bursts 001xx: Attempt to use INCR4 AHB bursts (default) 01xxx: Attempt to use INCR8 AHB bursts 1xxxx: Attempt to use INCR16 AHB bursts others: reserved

rw

0x0

reserved ahb_fixed_burst_len (BLENGTH)

5 4:0

rw rw

0x0 0x4

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Register (GEM) tx_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description tx_status XEMACPS_TXSR 0x00000014 gem0: 0xE000B014 gem1: 0xE000C014 32 bits mixed 0x00000000 Transmit Status

Register tx_status Details

This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Field Name reserved hresp_not_ok (HRESPNOK) late_collision 7 wtc 0x0 Bits 31:9 8 Type ro wtc Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit. Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. tx_under_run (URUN) 6 wtc 0x0 Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1. tx_complete (TXCOMPL) 5 wtc 0x0 Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.

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Appendix B: Register Details

Field Name tx_corr_ahb_err (BUFEXH)

Bits 4

Type wtc

Reset Value 0x0

Description Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit.

tx_go (TXGO)

ro

0x0

Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description.

retry_limit_exceeded (RXOVR) collision (FRAMERX)

2 1

wtc wtc

0x0 0x0

Retry limit exceeded - cleared by writing a one to this bit. Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.

used_bit_read (USEDREAD)

wtc

0x0

Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.

Register (GEM) rx_qbar

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description rx_qbar XEMACPS_RXQBASE 0x00000018 gem0: 0xE000B018 gem1: 0xE000C018 32 bits mixed 0x00000000 Receive Buffer Queue Base Address

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Appendix B: Register Details

Register rx_qbar Details

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the 'used' bits. The descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses.
Field Name rx_q_baseaddr Bits 31:2 Type rw Reset Value 0x0 Description Receive buffer queue base address - written with the address of the start of the receive queue. reserved 1:0 ro 0x0 Reserved, read as 0, ignored on write.

Register (GEM) tx_qbar

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description tx_qbar XEMACPS_TXQBASE 0x0000001C gem0: 0xE000B01C gem1: 0xE000C01C 32 bits mixed 0x00000000 Transmit Buffer Queue Base Address

Register tx_qbar Details

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. The descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses.

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Appendix B: Register Details

Field Name tx_q_base_addr reserved

Bits 31:2 1:0

Type rw ro

Reset Value 0x0 0x0

Description Transmit buffer queue base address - written with the address of the start of the transmit queue. Reserved, read as 0, ignored on write.

Register (GEM) rx_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description rx_status XEMACPS_RXSR 0x00000020 gem0: 0xE000B020 gem1: 0xE000C020 32 bits mixed 0x00000000 Receive Status

Register rx_status Details

When read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Field Name reserved hresp_not_ok (HRESPNOK) rx_overrun (RXOVR) 2 wtc 0x0 Bits 31:4 3 Type ro wtc Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit. Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it.

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Appendix B: Register Details

Field Name frame_recd (FRAMERX) buffer_not_avail (BUFFNA)

Bits 1

Type wtc

Reset Value 0x0

Description Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit.

wtc

0x0

Register (GEM) intr_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description intr_status XEMACPS_ISR 0x00000024 gem0: 0xE000B024 gem1: 0xE000C024 32 bits mixed 0x00000000 Interrupt Status

Register intr_status Details

Indicates an interrupt is asserted by the controller and is enabled (unmasked). 0: not asserted 1: asserted (if any bit reads as a 1, then the ethernet_int signal will be asserted to the interrupt controller)
Field Name reserved tsu_sec_incr pdelay_resp_tx (XEMACPS_IXR_PTPP STX) pdelay_req_tx (XEMACPS_IXR_PTPP DRTX) 24 wtc 0x0 Bits 31:27 26 25 Type ro wtc wtc Reset Value 0x0 0x0 0x0 Description Reserved, read as 0, ignored on write. TSU seconds register increment - indicates the register has incremented. PTP pdelay_resp frame transmitted - indicates a PTP pdelay_resp frame has been transmitted. PTP pdelay_req frame transmitted - indicates a PTP pdelay_req frame has been transmitted.

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Appendix B: Register Details

Field Name pdelay_resp_rx (XEMACPS_IXR_PTPS TX) pdelay_req_rx (XEMACPS_IXR_PTP DRTX) sync_tx (XEMACPS_IXR_PTPP SRX) delay_req_tx (XEMACPS_IXR_PTPP DRRX) sync_rx (XEMACPS_IXR_PTPS RX) delay_req_rx (XEMACPS_IXR_PTP DRRX) partner_pg_rx

Bits 23

Type wtc

Reset Value 0x0

Description PTP pdelay_resp frame received - indicates a PTP pdelay_resp frame has been received. PTP pdelay_req frame received - indicates a PTP pdelay_req frame has been received. PTP sync frame transmitted - indicates a PTP sync frame has been transmitted. PTP delay_req frame transmitted - indicates a PTP delay_req frame has been transmitted. PTP sync frame received - indicates a PTP sync frame has been received. PTP delay_req frame received - indicates a PTP delay_req frame has been received. PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signaled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001). PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation. External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin. Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Pause time zero - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.

22

wtc

0x0

21

wtc

0x0

20

wtc

0x0

19

wtc

0x0

18

wtc

0x0

17

wtc

0x0

autoneg_complete

16

wtc

0x0

ext_intr pause_tx (XEMACPS_IXR_PAU SETX) pause_zero (XEMACPS_IXR_PAU SEZERO)

15 14

wtc wtc

0x0 0x0

13

wtc

0x0

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Appendix B: Register Details

Field Name pause_nonzeroq_rx (XEMACPS_IXR_PAU SENZERO) hresp_not_ok (XEMACPS_IXR_HRE SPNOK) rx_overrun (XEMACPS_IXR_RXO VR) link_chng reserved tx_complete (XEMACPS_IXR_TXC OMPL) tx_corrupt_ahb_err (XEMACPS_IXR_TXEX H)

Bits 12

Type wtc

Reset Value 0x0

Description Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. Hresp not OK - set when the DMA block sees hresp not OK. Receive overrun - set when the receive overrun status bit gets set. Link change - set when the state of the link detected by the internal PCS changes state. Reserved Transmit complete - set when a frame has been transmitted. Transmit frame corruption due to AHB error - set if an error occurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read.

11

wtc

0x0

10

wtc

0x0

9 8 7

wtc ro wtc

0x0 0x0 0x0

clronr d

0x0

retry_ex_late_collisn (XEMACPS_IXR_RETR Y) reserved tx_used_read (XEMACPS_IXR_TXUS ED) rx_used_read (XEMACPS_IXR_RXU SED) rx_complete (XEMACPS_IXR_FRA MERX) mgmt_sent (XEMACPS_IXR_MG MNT)

wtc

0x0

Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted).

4 3

wtc wtc

0x0 0x0

Reserved. Do not modify. TX used bit read - set when a transmit buffer descriptor is read with its used bit set. RX used bit read - set when a receive buffer descriptor is read with its used bit set. Receive complete - a frame has been stored in memory. Management frame sent - the PHY maintenance register has completed its operation.

wtc

0x0

wtc

0x0

wtc

0x0

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Appendix B: Register Details

Register (GEM) intr_en

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description intr_en XEMACPS_IER 0x00000028 gem0: 0xE000B028 gem1: 0xE000C028 32 bits wo x Interrupt Enable

Register intr_en Details

Enable interrupts by writing a 1 to one or more bits. Write a 1 to enable (unmask) the interrupt. Writing 0 has no affect on the mask bit. When read, this register returns zero. To control interrupt masks and read status, use the interrupt status, enable, disable and mask registers together. At reset, all interrupts are disabled (masked).
Field Name reserved tsu_sec_incr pdelay_resp_tx (XEMACPS_IXR_PTPP STX) pdelay_req_tx (XEMACPS_IXR_PTPP DRTX) pdelay_resp_rx (XEMACPS_IXR_PTPS TX) pdelay_req_rx (XEMACPS_IXR_PTP DRTX) sync_tx (XEMACPS_IXR_PTPP SRX) delay_req_tx (XEMACPS_IXR_PTPP DRRX) 20 wo x Enable PTP delay_req frame transmitted interrupt 21 wo x Enable PTP sync frame transmitted interrupt 22 wo x Enable PTP pdelay_req frame received interrupt 23 wo x 24 wo x Bits 31:27 26 25 Type wo wo wo Reset Value x x x Reserved Enable TSU seconds register increment interrupt Enable PTP pdelay_resp frame transmitted interrupt Enable PTP pdelay_req frame transmitted interrupt Enable PTP pdelay_resp frame received interrupt Description

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Field Name sync_rx (XEMACPS_IXR_PTPS RX) delay_req_rx (XEMACPS_IXR_PTP DRRX) partner_pg_rx autoneg_complete ext_intr pause_tx (XEMACPS_IXR_PAU SETX) pause_zero (XEMACPS_IXR_PAU SEZERO) pause_nonzeroq (XEMACPS_IXR_PAU SENZERO) hresp_not_ok (XEMACPS_IXR_HRE SPNOK) rx_overrun (XEMACPS_IXR_RXO VR) link_chng reserved tx_complete (XEMACPS_IXR_TXC OMPL) tx_corrupt_ahb_err (XEMACPS_IXR_TXEX H) retry_ex_late_collisn (XEMACPS_IXR_RETR Y) tx_underrun (XEMACPS_IXR_URU N) tx_used_read (XEMACPS_IXR_TXUS ED)

Bits 19

Type wo

Reset Value x

Description Enable PTP sync frame received interrupt

18

wo

Enable PTP delay_req frame received interrupt

17 16 15 14

wo wo wo wo

x x x x

Enable PCS link partner page received interrupt Enable PCS auto-negotiation complete interrupt Enable external interrupt Enable pause frame transmitted interrupt

13

wo

Enable pause time zero interrupt

12

wo

Enable pause frame with non-zero pause quantum interrupt Enable hresp not OK interrupt

11

wo

10

wo

Enable receive overrun interrupt

9 8 7

wo wo wo

x x x

Enable link change interrupt Not used Enable transmit complete interrupt

wo

Enable transmit frame corruption due to AHB error interrupt Enable retry limit exceeded or late collision interrupt Enable transmit buffer under run interrupt

wo

wo

wo

Enable transmit used bit read interrupt

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Appendix B: Register Details

Field Name rx_used_read (XEMACPS_IXR_RXU SED) rx_complete (XEMACPS_IXR_FRA MERX) mgmt_done (XEMACPS_IXR_MG MNT)

Bits 2

Type wo

Reset Value x

Description Enable receive used bit read interrupt

wo

Enable receive complete interrupt

wo

Enable management done interrupt

Register (GEM) intr_dis

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description intr_dis XEMACPS_IDR 0x0000002C gem0: 0xE000B02C gem1: 0xE000C02C 32 bits wo x Interrupt Disable

Register intr_dis Details

Disable interrupts by applying a mask to one or more bits. Write 1 to disable (mask) the interrupt. Writing 0 has no affect on the mask bit. When read, this register returns zero.
Field Name reserved tsu_sec_incr pdelay_resp_tx (XEMACPS_IXR_PTPP STX) pdelay_req_tx (XEMACPS_IXR_PTPP DRTX) 24 wo x Bits 31:27 26 25 Type wo wo wo Reset Value x x x Reserved Disable TSU seconds register increment interrupt Disable PTP pdelay_resp frame transmitted interrupt Disable PTP pdelay_req frame transmitted interrupt Description

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Appendix B: Register Details

Field Name pdelay_resp_rx (XEMACPS_IXR_PTPS TX) pdelay_req_rx (XEMACPS_IXR_PTP DRTX) sync_tx (XEMACPS_IXR_PTPP SRX) delay_req_tx (XEMACPS_IXR_PTPP DRRX) sync_rx (XEMACPS_IXR_PTPS RX) delay_req_rx (XEMACPS_IXR_PTP DRRX) partner_pg_rx autoneg_complete ext_intr pause_tx (XEMACPS_IXR_PAU SETX) pause_zero (XEMACPS_IXR_PAU SEZERO) pause_nonzeroq (XEMACPS_IXR_PAU SENZERO) hresp_not_ok (XEMACPS_IXR_HRE SPNOK) rx_overrun (XEMACPS_IXR_RXO VR) link_chng reserved tx_complete (XEMACPS_IXR_TXC OMPL)

Bits 23

Type wo

Reset Value x

Description Disable PTP pdelay_resp frame received interrupt

22

wo

Disable PTP pdelay_req frame received interrupt

21

wo

Disable PTP sync frame transmitted interrupt

20

wo

Disable PTP delay_req frame transmitted interrupt Disable PTP sync frame received interrupt

19

wo

18

wo

Disable PTP delay_req frame received interrupt

17 16 15 14

wo wo wo wo

x x x x

Disable PCS link partner page received interrupt Disable PCS auto-negotiation complete interrupt Disable external interrupt Disable pause frame transmitted interrupt

13

wo

Disable pause time zero interrupt

12

wo

Disable pause frame with non-zero pause quantum interrupt Disable hresp not OK interrupt

11

wo

10

wo

Disable receive overrun interrupt

9 8 7

wo wo wo

x x x

Disable link change interrupt Not used Disable transmit complete interrupt

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Appendix B: Register Details

Field Name tx_corrupt_ahb_err (XEMACPS_IXR_TXEX H) retry_ex_late_collisn (XEMACPS_IXR_RETR Y) tx_underrun (XEMACPS_IXR_URU N) tx_used_read (XEMACPS_IXR_TXUS ED) rx_used_read (XEMACPS_IXR_RXU SED) rx_complete (XEMACPS_IXR_FRA MERX) mgmt_done (XEMACPS_IXR_MG MNT)

Bits 6

Type wo

Reset Value x

Description Disable transmit frame corruption due to AHB error interrupt Disable retry limit exceeded or late collision interrupt Disable transmit buffer under run interrupt

wo

wo

wo

Disable transmit used bit read interrupt

wo

Disable receive used bit read interrupt

wo

Disable receive complete interrupt

wo

Disable management done interrupt

Register (GEM) intr_mask

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description intr_mask XEMACPS_IMR 0x00000030 gem0: 0xE000B030 gem1: 0xE000C030 32 bits mixed x Interrupt Mask Status

Register intr_mask Details

Indicates the mask state of each interrupt. 0: interrupt non masked (enabled) 1: interrupt masked (disabled), reset default All interrupts are disabled after a module reset. The interrupt masks are individually controlled using the write-only interrupt enable and disable registers.

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Appendix B: Register Details

For test purposes there is a write-only function to the interrupt mask register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Field Name reserved pdelay_resp_tx (XEMACPS_IXR_PTPP STX) pdelay_req_tx (XEMACPS_IXR_PTPP DRTX) pdelay_resp_rx (XEMACPS_IXR_PTPS TX) pdelay_req_rx (XEMACPS_IXR_PTP DRTX) sync_tx (XEMACPS_IXR_PTPP SRX) delay_req_tx (XEMACPS_IXR_PTPP DRRX) sync_rx (XEMACPS_IXR_PTPS RX) delay_req_rx (XEMACPS_IXR_PTP DRRX) partner_pg_rx autoneg_complete ext_intr pause_tx (XEMACPS_IXR_PAU SETX) pause_zero (XEMACPS_IXR_PAU SEZERO) pause_nonzeroq (XEMACPS_IXR_PAU SENZERO) 12 ro,wo 0x1 Pause frame with non-zero pause quantum interrupt mask. 13 ro,wo 0x1 Pause time zero interrupt mask. 17 16 15 14 ro,wo ro,wo ro,wo ro,wo x 0x1 0x1 0x1 PCS link partner page mask. PCS auto-negotiation complete interrupt mask. External interrupt mask. Pause frame transmitted interrupt mask. 18 ro,wo x PTP delay_req frame received mask. 19 ro,wo x PTP sync frame received mask. 20 ro,wo x PTP delay_req frame transmitted mask. 21 ro,wo x PTP sync frame transmitted mask. 22 ro,wo x PTP pdelay_req frame received mask. 23 ro,wo x PTP pdelay_resp frame received mask. 24 ro,wo x PTP pdelay_req frame transmitted mask. Bits 31:26 25 Type ro ro,wo Reset Value 0x0 x Reserved PTP pdelay_resp frame transmitted mask. Description

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Appendix B: Register Details

Field Name hresp_not_ok (XEMACPS_IXR_HRE SPNOK) rx_overrun (XEMACPS_IXR_RXO VR) link_chng reserved tx_complete (XEMACPS_IXR_TXC OMPL) tx_corrupt_ahb_err (XEMACPS_IXR_TXEX H) retry_ex_late_collisn (XEMACPS_IXR_RETR Y) tx_underrun (XEMACPS_IXR_URU N) tx_used_read (XEMACPS_IXR_TXUS ED) rx_used_read (XEMACPS_IXR_RXU SED) rx_complete (XEMACPS_IXR_FRA MERX) mgmt_done (XEMACPS_IXR_MG MNT)

Bits 11

Type ro,wo

Reset Value 0x1

Description Hresp not OK interrupt mask.

10

ro,wo

0x1

Receive overrun interrupt mask.

9 8 7

ro,wo ro,wo ro,wo

0x1 0x1 0x1

Link change interrupt mask. Not used Transmit complete interrupt mask.

ro,wo

0x1

Transmit frame corruption due to AHB error interrupt Retry limit exceeded or late collision (gigabit mode only) Transmit buffer under run interrupt mask.

ro,wo

0x1

ro,wo

0x1

ro,wo

0x1

Transmit used bit read interrupt mask.

ro,wo

0x1

Receive used bit read interrupt mask.

ro,wo

0x1

Receive complete interrupt mask.

ro,wo

0x1

Management done interrupt mask.

Register (GEM) phy_maint

Name Software Name Relative Address Absolute Address phy_maint XEMACPS_PHYMNTNC 0x00000034 gem0: 0xE000B034 gem1: 0xE000C034

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Appendix B: Register Details

Width Access Type Reset Value Description

32 bits rw 0x00000000 PHY Maintenance

Register phy_maint Details

The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation, which is signaled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
Field Name reserved clause_22 Bits 31 30 Type rw rw Reset Value 0x0 0x0 Description Must be written with 0. Must be written to 1 for Clause 22 operation. Check your PHY's spec to see if it is clause 22 or clause 45 compliant. operation (OP) phy_addr (ADDR) reg_addr (REG) must_10 data (DATA) 17:16 15:0 rw rw 0x0 0x0 22:18 rw 0x0 Register address - specifies the register in the PHY to access. Must be written to 10. For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. 27:23 rw 0x0 PHY address. 29:28 rw 0x0 Operation. 10 is read. 01 is write.

Register (GEM) rx_pauseq

Name Software Name Relative Address Absolute Address Width Access Type rx_pauseq XEMACPS_RXPAUSE 0x00000038 gem0: 0xE000B038 gem1: 0xE000C038 32 bits ro

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Reset Value Description

0x00000000 Received Pause Quantum

Register rx_pauseq Details

Field Name reserved rx_pauseq Bits 31:16 15:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times.

Register (GEM) tx_pauseq

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description tx_pauseq XEMACPS_TXPAUSE 0x0000003C gem0: 0xE000B03C gem1: 0xE000C03C 32 bits rw 0x0000FFFF Transmit Pause Quantum

Register tx_pauseq Details

Field Name reserved tx_pauseq Bits 31:16 15:0 Type rw rw Reset Value 0x0 0xFFFF Description Reserved, read as 0, ignored on write. Transmit pause quantum - written with the pause quantum value for pause frame transmission.

Register (GEM) hash_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value hash_bot XEMACPS_HASHL 0x00000080 gem0: 0xE000B080 gem1: 0xE000C080 32 bits rw 0x00000000

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Description

Hash Register Bottom [31:0]

Register hash_bot Details

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.
Field Name Bits 31:0 Type rw Reset Value 0x0 Description The first 32 bits of the hash address register.

Register (GEM) hash_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description hash_top XEMACPS_HASHH 0x00000084 gem0: 0xE000B084 gem1: 0xE000C084 32 bits rw 0x00000000 Hash Register Top [63:32]

Register hash_top Details

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.
Field Name Bits 31:0 Type rw Reset Value 0x0 Description The remaining 32 bits of the hash address register.

Register (GEM) spec_addr1_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr1_bot XEMACPS_LADDR1L 0x00000088 gem0: 0xE000B088 gem1: 0xE000C088 32 bits rw 0x00000000 Specific Address 1 Bottom [31:0]

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Register spec_addr1_bot Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

Register (GEM) spec_addr1_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr1_top XEMACPS_LADDR1H 0x0000008C gem0: 0xE000B08C gem1: 0xE000C08C 32 bits mixed 0x00000000 Specific Address 1 Top [47:32]

Register spec_addr1_top Details

Field Name reserved addr_msbs Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write Specific address 1. The most significant bits of the destination address, that is bits 47:32.

Register (GEM) spec_addr2_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr2_bot XEMACPS_LADDR2L 0x00000090 gem0: 0xE000B090 gem1: 0xE000C090 32 bits rw 0x00000000 Specific Address 2 Bottom [31:0]

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Register spec_addr2_bot Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

Register (GEM) spec_addr2_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr2_top XEMACPS_LADDR2H 0x00000094 gem0: 0xE000B094 gem1: 0xE000C094 32 bits mixed 0x00000000 Specific Address 2 Top [47:32]

Register spec_addr2_top Details

Field Name reserved addr_msbs Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write Specific address 2. The most significant bits of the destination address, that is bits 47:32.

Register (GEM) spec_addr3_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr3_bot XEMACPS_LADDR3L 0x00000098 gem0: 0xE000B098 gem1: 0xE000C098 32 bits rw 0x00000000 Specific Address 3 Bottom [31:0]

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Register spec_addr3_bot Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

Register (GEM) spec_addr3_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr3_top XEMACPS_LADDR3H 0x0000009C gem0: 0xE000B09C gem1: 0xE000C09C 32 bits mixed 0x00000000 Specific Address 3 Top [47:32]

Register spec_addr3_top Details

Field Name reserved addr_msbs Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write Specific address 3. The most significant bits of the destination address, that is bits 47:32.

Register (GEM) spec_addr4_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr4_bot XEMACPS_LADDR4L 0x000000A0 gem0: 0xE000B0A0 gem1: 0xE000C0A0 32 bits rw 0x00000000 Specific Address 4 Bottom [31:0]

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Register spec_addr4_bot Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

Register (GEM) spec_addr4_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr4_top XEMACPS_LADDR4H 0x000000A4 gem0: 0xE000B0A4 gem1: 0xE000C0A4 32 bits mixed 0x00000000 Specific Address 4 Top [47:32]

Register spec_addr4_top Details

Field Name reserved addr_msbs Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write Specific address 4. The most significant bits of the destination address, that is bits 47:32.

Register (GEM) type_id_match1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description type_id_match1 XEMACPS_MATCH1 0x000000A8 gem0: 0xE000B0A8 gem1: 0xE000C0A8 32 bits mixed 0x00000000 Type ID Match 1

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Register type_id_match1 Details

Field Name copy_en reserved type_id_match1 Bits 31 30:16 15:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Enable copying of type ID match 1 matched frames Reserved, read as 0, ignored on write Type ID match 1. For use in comparisons with received frames type ID/length field.

Register (GEM) type_id_match2

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description type_id_match2 XEMACPS_MATCH2 0x000000AC gem0: 0xE000B0AC gem1: 0xE000C0AC 32 bits mixed 0x00000000 Type ID Match 2

Register type_id_match2 Details

Field Name copy_en reserved type_id_match2 Bits 31 30:16 15:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Enable copying of type ID match 2 matched frames Reserved, read as 0, ignored on write Type ID match 2. For use in comparisons with received frames type ID/length field.

Register (GEM) type_id_match3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value type_id_match3 XEMACPS_MATCH3 0x000000B0 gem0: 0xE000B0B0 gem1: 0xE000C0B0 32 bits mixed 0x00000000

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Description

Type ID Match 3

Register type_id_match3 Details

Field Name copy_en reserved type_id_match3 Bits 31 30:16 15:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Enable copying of type ID match 3 matched frames Reserved, read as 0, ignored on write Type ID match 3. For use in comparisons with received frames type ID/length field.

Register (GEM) type_id_match4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description type_id_match4 XEMACPS_MATCH4 0x000000B4 gem0: 0xE000B0B4 gem1: 0xE000C0B4 32 bits mixed 0x00000000 Type ID Match 4

Register type_id_match4 Details

Field Name copy_en reserved type_id_match4 Bits 31 30:16 15:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Enable copying of type ID match 4 matched frames Reserved, read as 0, ignored on write Type ID match 4. For use in comparisons with received frames type ID/length field.

Register (GEM) wake_on_lan

Name Relative Address Absolute Address Width Access Type wake_on_lan 0x000000B8 gem0: 0xE000B0B8 gem1: 0xE000C0B8 32 bits mixed

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Reset Value Description

0x00000000 Wake on LAN Register

Register wake_on_lan Details

Field Name reserved multi_hash_en Bits 31:20 19 Type ro rw Reset Value 0x0 0x0 Description Reserved - read 0, ignored when written Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted. Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted. Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted. Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted. Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.

spec_addr_reg1_en

18

rw

0x0

arp_req_en

17

rw

0x0

magic_pkt_en

16

rw

0x0

arp_req_ip_addr

15:0

rw

0x0

Register (GEM) ipg_stretch

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ipg_stretch XEMACPS_STRETCH 0x000000BC gem0: 0xE000B0BC gem1: 0xE000C0BC 32 bits mixed 0x00000000 IPG stretch register

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Register ipg_stretch Details

Field Name reserved ipg_stretch Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero.

Register (GEM) stacked_vlan

Name Relative Address Absolute Address Width Access Type Reset Value Description stacked_vlan 0x000000C0 gem0: 0xE000B0C0 gem1: 0xE000C0C0 32 bits mixed 0x00000000 Stacked VLAN Register

Register stacked_vlan Details

Field Name stacked_vlan_en reserved user_def_vlan_type Bits 31 30:16 15:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Enable Stacked VLAN processing mode Reserved, read as 0, ignored on write. User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100.

Register (GEM) tx_pfc_pause

Name Relative Address tx_pfc_pause 0x000000C4

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Absolute Address Width Access Type Reset Value Description

gem0: 0xE000B0C4 gem1: 0xE000C0C4 32 bits mixed 0x00000000 Transmit PFC Pause Register

Register tx_pfc_pause Details

Field Name reserved pauseq_sel Bits 31:16 15:8 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].

pri_en_vec_val

7:0

rw

0x0

Register (GEM) spec_addr1_mask_bot

Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr1_mask_bot 0x000000C8 gem0: 0xE000B0C8 gem1: 0xE000C0C8 32 bits rw 0x00000000 Specific Address Mask 1 Bottom [31:0]

Register spec_addr1_mask_bot Details

Field Name mask_bits_bot Bits 31:0 Type rw Reset Value 0x0 Description Setting a bit to one masks the corresponding bit in the specific address 1 register

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Register (GEM) spec_addr1_mask_top

Name Relative Address Absolute Address Width Access Type Reset Value Description spec_addr1_mask_top 0x000000CC gem0: 0xE000B0CC gem1: 0xE000C0CC 32 bits mixed 0x00000000 Specific Address Mask 1 Top [47:32]

Register spec_addr1_mask_top Details

Field Name reserved mask_bits_top Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Setting a bit to one masks the corresponding bit in the specific address 1 register

Register (GEM) module_id

Name Relative Address Absolute Address Width Access Type Reset Value Description module_id 0x000000FC gem0: 0xE000B0FC gem1: 0xE000C0FC 32 bits ro 0x00020118 Module ID

Register module_id Details

This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value. With GEM p23, it is 0x00020118.
Field Name module_id module_rev Bits 31:16 15:0 Type ro ro Reset Value 0x2 0x118 Description Module identification number - for the GEM, this value is fixed at 0x0002. Module revision - fixed byte value specific to the revision of the design which is incremented after each release of the IP. Corresponds to Zynq having GEM p23.

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Register (GEM) octets_tx_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description octets_tx_bot XEMACPS_OCTTXL 0x00000100 gem0: 0xE000B100 gem1: 0xE000C100 32 bits ro 0x00000000 Octets transmitted [31:0] (in frames without error)

Register octets_tx_bot Details

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name octets_tx_bot Bits 31:0 Type ro Reset Value 0x0 Description Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.

Register (GEM) octets_tx_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description octets_tx_top XEMACPS_OCTTXH 0x00000104 gem0: 0xE000B104 gem1: 0xE000C104 32 bits ro 0x00000000 Octets transmitted [47:32] (in frames without error)

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Register octets_tx_top Details

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved octets_tx_top Bits 31:16 15:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.

Register (GEM) frames_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_tx XEMACPS_TXCNT 0x00000108 gem0: 0xE000B108 gem1: 0xE000C108 32 bits ro 0x00000000 Frames Transmitted

Register frames_tx Details

Statistical counter for Frames transmitted without an error and exclude pause frames. NOTES for ALL Statistical registers for Frames Transferred: The a statistical counter is read by software, it is cleared to zero by the hardware. When a counter reaches its maximum value, it stops counting and is read with all 1s. The statistical counters must be read frequently enough if data loss is to be prevented. For test purposes, all of the statistical counters may be written to (not just read) by setting bit 7 (wren_stat_regs) in the network control register. Also for test purposes, all of the statistical counters can be incremented (by one) by writing a 1 to bit 6 (incr_stat_regs) of the network control register.

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Field Name

Bits 31:0

Type ro

Reset Value 0x0

Description Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e., no under run and not too many retries. Excludes pause frames.

Register (GEM) broadcast_frames_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description broadcast_frames_tx XEMACPS_TXBCCNT 0x0000010C gem0: 0xE000B10C gem1: 0xE000C10C 32 bits ro 0x00000000 Broadcast frames Tx

Register broadcast_frames_tx Details

Statistical counter for Broadcast Frames transmitted without an error and exclude pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

Register (GEM) multi_frames_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description multi_frames_tx XEMACPS_TXMCCNT 0x00000110 gem0: 0xE000B110 gem1: 0xE000C110 32 bits ro 0x00000000 Multicast frames Tx

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Register multi_frames_tx Details

Statistical counter for Multicast Frames transmitted without an error and exclude pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

Register (GEM) pause_frames_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description pause_frames_tx XEMACPS_TXPAUSECNT 0x00000114 gem0: 0xE000B114 gem1: 0xE000C114 32 bits ro 0x00000000 Pause frames Tx

Register pause_frames_tx Details

Statistical counter for Pause Frames transmitted without an error and not sent through the FIFO interface. Refer to the FRAMES_TX register for additional information.
Field Name reserved pause_frames_tx Bits 31:16 15:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter.

Register (GEM) frames_64b_tx

Name Software Name Relative Address frames_64b_tx XEMACPS_TX64CNT 0x00000118

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Absolute Address Width Access Type Reset Value Description

gem0: 0xE000B118 gem1: 0xE000C118 32 bits ro 0x00000000 Frames Tx, 64-byte length

Register frames_64b_tx Details

Statistical counter of frames of 64 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

Register (GEM) frames_65to127b_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_65to127b_tx XEMACPS_TX65CNT 0x0000011C gem0: 0xE000B11C gem1: 0xE000C11C 32 bits ro 0x00000000 Frames Tx, 65 to 127-byte length

Register frames_65to127b_tx Details

Statistical counter of frames of 65 to 127 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

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Register (GEM) frames_128to255b_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_128to255b_tx XEMACPS_TX128CNT 0x00000120 gem0: 0xE000B120 gem1: 0xE000C120 32 bits ro 0x00000000 Frames Tx, 128 to 255-byte length

Register frames_128to255b_tx Details

Statistical counter of frames of 128 to 255 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

Register (GEM) frames_256to511b_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_256to511b_tx XEMACPS_TX256CNT 0x00000124 gem0: 0xE000B124 gem1: 0xE000C124 32 bits ro 0x00000000 Frames Tx, 256 to 511-byte length

Register frames_256to511b_tx Details

Statistical counter of frames of 256 to 511 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

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Appendix B: Register Details

Field Name

Bits 31:0

Type ro

Reset Value 0x0

Description 256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

Register (GEM) frames_512to1023b_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_512to1023b_tx XEMACPS_TX512CNT 0x00000128 gem0: 0xE000B128 gem1: 0xE000C128 32 bits ro 0x00000000 Frames Tx, 512 to 1023-byte length

Register frames_512to1023b_tx Details

Statistical counter of frames of 512 to 1023 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

Register (GEM) frames_1024to1518b_tx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_1024to1518b_tx XEMACPS_TX1024CNT 0x0000012C gem0: 0xE000B12C gem1: 0xE000C12C 32 bits ro 0x00000000 Frame Tx, 1024 to 1518-byte length

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Register frames_1024to1518b_tx Details

Statistical counter of frames of1024 to 1518 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

Register (GEM) tx_under_runs

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description tx_under_runs XEMACPS_TXURUNCNT 0x00000134 gem0: 0xE000B134 gem1: 0xE000C134 32 bits ro 0x00000000 Transmit under runs

Register tx_under_runs Details

In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved tx_under_runs Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented.

Register (GEM) single_collisn_frames

Name Software Name single_collisn_frames XEMACPS_SNGLCOLLCNT

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000138 gem0: 0xE000B138 gem1: 0xE000C138 32 bits ro 0x00000000 Single Collision Frames

Register single_collisn_frames Details

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved single_collisn Bits 31:18 17:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run.

Register (GEM) multi_collisn_frames

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description multi_collisn_frames XEMACPS_MULTICOLLCNT 0x0000013C gem0: 0xE000B13C gem1: 0xE000C13C 32 bits ro 0x00000000 Multiple Collision Frames

Register multi_collisn_frames Details

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.

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Once a statistics register has been read, it is automatically cleared.

Field Name reserved multi_collisn Bits 31:18 17:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no under run and not too many retries.

Register (GEM) excessive_collisns

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description excessive_collisns XEMACPS_EXCESSCOLLCNT 0x00000140 gem0: 0xE000B140 gem1: 0xE000C140 32 bits ro 0x00000000 Excessive Collisions

Register excessive_collisns Details

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved excessive_collisns Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.

Register (GEM) late_collisns

Name Software Name Relative Address late_collisns XEMACPS_LATECOLLCNT 0x00000144

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Absolute Address Width Access Type Reset Value Description

gem0: 0xE000B144 gem1: 0xE000C144 32 bits ro 0x00000000 Late Collisions

Register late_collisns Details

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved late_collisns Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e., both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated.

Register (GEM) deferred_tx_frames

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description deferred_tx_frames XEMACPS_TXDEFERCNT 0x00000148 gem0: 0xE000B148 gem1: 0xE000C148 32 bits ro 0x00000000 Deferred Transmission Frames

Register deferred_tx_frames Details

In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

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For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved deferred_tx Bits 31:18 17:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run.

Register (GEM) carrier_sense_errs

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description carrier_sense_errs XEMACPS_TXCSENSECNT 0x0000014C gem0: 0xE000B14C gem1: 0xE000C14C 32 bits ro 0x00000000 Carrier Sense Errors.

Register carrier_sense_errs Details

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.

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Field Name reserved carrier_sense_errs

Bits 31:10 9:0

Type ro ro

Reset Value 0x0 0x0

Description Reserved, read as 0, ignored on write. Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.

Register (GEM) octets_rx_bot

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description octets_rx_bot XEMACPS_OCTRXL 0x00000150 gem0: 0xE000B150 gem1: 0xE000C150 32 bits ro 0x00000000 Octets Received [31:0]

Register octets_rx_bot Details

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name octets_rx_bot Bits 31:0 Type ro Reset Value 0x0 Description Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

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Register (GEM) octets_rx_top

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description octets_rx_top XEMACPS_OCTRXH 0x00000154 gem0: 0xE000B154 gem1: 0xE000C154 32 bits ro 0x00000000 Octets Received [47:32]

Register octets_rx_top Details

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared.
Field Name reserved octets_rx_top Bits 31:16 15:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) frames_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value frames_rx XEMACPS_RXCNT 0x00000158 gem0: 0xE000B158 gem1: 0xE000C158 32 bits ro 0x00000000

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Description

Frames Received

Register frames_rx Details

Statistical counter for Frames received without an error and exclude pause frames. NOTES for ALL Statistical registers for Frames Transferred: The a statistical counter is read by software, it is cleared to zero by the hardware. When a counter reaches its maximum value, it stops counting and is read with all 1s. The statistical counters must be read frequently enough if data loss is to be prevented. For test purposes, all of the statistical counters may be written to (not just read) by setting bit 7 (wren_stat_regs) in the network control register. Also for test purposes, all of the statistical counters can be incremented (by one) by writing a 1 to bit 6 (incr_stat_regs) of the network control register.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) bdcast_fames_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description bdcast_fames_rx XEMACPS_RXBROADCNT 0x0000015C gem0: 0xE000B15C gem1: 0xE000C15C 32 bits ro 0x00000000 Broadcast Frames Rx

Register bdcast_fames_rx Details

Statistical counter for Broadcast Frames received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

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Register (GEM) multi_frames_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description multi_frames_rx XEMACPS_RXMULTICNT 0x00000160 gem0: 0xE000B160 gem1: 0xE000C160 32 bits ro 0x00000000 Multicast Frames Rx

Register multi_frames_rx Details

Statistical counter for Multicast Frames received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) pause_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description pause_rx XEMACPS_RXPAUSECNT 0x00000164 gem0: 0xE000B164 gem1: 0xE000C164 32 bits ro 0x00000000 Pause Frames Rx

Register pause_rx Details

Statistical counter for Pause Frames received without an error. Refer to the FRAMES_RX register for additional information.

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Field Name reserved pause_rx

Bits 31:16 15:0

Type ro ro

Reset Value 0x0 0x0

Description Reserved, read as 0, ignored on write. Received pause frames - a 16 bit register counting the number of pause frames received without error.

Register (GEM) frames_64b_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_64b_rx XEMACPS_RX64CNT 0x00000168 gem0: 0xE000B168 gem1: 0xE000C168 32 bits ro 0x00000000 Frames Rx, 64-byte length

Register frames_64b_rx Details

Statistical counter for frames of 64 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) frames_65to127b_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value frames_65to127b_rx XEMACPS_RX65CNT 0x0000016C gem0: 0xE000B16C gem1: 0xE000C16C 32 bits ro 0x00000000

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Description

Frames Rx, 65 to 127-byte length

Register frames_65to127b_rx Details

Statistical counter for frames of 65 to 127 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) frames_128to255b_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_128to255b_rx XEMACPS_RX128CNT 0x00000170 gem0: 0xE000B170 gem1: 0xE000C170 32 bits ro 0x00000000 Frames Rx, 128 to 255-byte length

Register frames_128to255b_rx Details

Statistical counter for frames of 128 to 255 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) frames_256to511b_rx

Name Software Name Relative Address frames_256to511b_rx XEMACPS_RX256CNT 0x00000174

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Absolute Address Width Access Type Reset Value Description

gem0: 0xE000B174 gem1: 0xE000C174 32 bits ro 0x00000000 Frames Rx, 256 to 511-byte length

Register frames_256to511b_rx Details

Statistical counter for frames of 256 to 511 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) frames_512to1023b_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_512to1023b_rx XEMACPS_RX512CNT 0x00000178 gem0: 0xE000B178 gem1: 0xE000C178 32 bits ro 0x00000000 Frames Rx, 512 to 1023-byte length

Register frames_512to1023b_rx Details

Statistical counter for frames of 512 to 1023 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

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Register (GEM) frames_1024to1518b_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description frames_1024to1518b_rx XEMACPS_RX1024CNT 0x0000017C gem0: 0xE000B17C gem1: 0xE000C17C 32 bits ro 0x00000000 Frames Rx, 1024 to 1518-byte length

Register frames_1024to1518b_rx Details

Statistical counter for frames of 1024 to 1518 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.
Field Name Bits 31:0 Type ro Reset Value 0x0 Description 1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

Register (GEM) undersz_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description undersz_rx XEMACPS_RXUNDRCNT 0x00000184 gem0: 0xE000B184 gem1: 0xE000C184 32 bits ro 0x00000000 Undersize frames received

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Register undersz_rx Details

Field Name reserved undersz_rx Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error.

Register (GEM) oversz_rx

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description oversz_rx XEMACPS_RXOVRCNT 0x00000188 gem0: 0xE000B188 gem1: 0xE000C188 32 bits ro 0x00000000 Oversize frames received

Register oversz_rx Details

Field Name reserved oversz_rx Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.

Register (GEM) jab_rx

Name Software Name Relative Address Absolute Address Width Access Type jab_rx XEMACPS_RXJABCNT 0x0000018C gem0: 0xE000B18C gem1: 0xE000C18C 32 bits ro

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Reset Value Description

0x00000000 Jabbers received

Register jab_rx Details

Field Name reserved jab_rx Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.

Register (GEM) fcs_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description fcs_errors XEMACPS_RXFCSCNT 0x00000190 gem0: 0xE000B190 gem1: 0xE000C190 32 bits ro 0x00000000 Frame check sequence errors

Register fcs_errors Details

Field Name reserved fcs_errors Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length. This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register.H524

Register (GEM) length_field_errors

Name length_field_errors

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

XEMACPS_RXLENGTHCNT 0x00000194 gem0: 0xE000B194 gem1: 0xE000C194 32 bits ro 0x00000000 Length field frame errors

Register length_field_errors Details

Field Name reserved length_field_errors Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register.

Register (GEM) rx_symbol_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description rx_symbol_errors XEMACPS_RXSYMBCNT 0x00000198 gem0: 0xE000B198 gem1: 0xE000C198 32 bits ro 0x00000000 Receive symbol errors

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Register rx_symbol_errors Details

Field Name reserved rx_symbol_errors Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error.

Register (GEM) align_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description align_errors XEMACPS_RXALIGNCNT 0x0000019C gem0: 0xE000B19C gem1: 0xE000C19C 32 bits ro 0x00000000 Alignment errors

Register align_errors Details

Field Name reserved align_errors Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length. This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes.

Register (GEM) rx_resource_errors

Name Software Name Relative Address Absolute Address rx_resource_errors XEMACPS_RXRESERRCNT 0x000001A0 gem0: 0xE000B1A0 gem1: 0xE000C1A0

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Width Access Type Reset Value Description

32 bits ro 0x00000000 Receive resource errors

Register rx_resource_errors Details

Field Name reserved rx_resource_errors Bits 31:18 17:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer was available. This will be either because the AHB bus was not granted in time or because a hresp not OK was returned.

Register (GEM) rx_overrun_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description rx_overrun_errors XEMACPS_RXORCNT 0x000001A4 gem0: 0xE000B1A4 gem1: 0xE000C1A4 32 bits ro 0x00000000 Receive overrun errors

Register rx_overrun_errors Details

Field Name reserved rx_overrun_errors Bits 31:10 9:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun.

Register (GEM) ip_hdr_csum_errors

Name ip_hdr_csum_errors

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

XEMACPS_RXIPCCNT 0x000001A8 gem0: 0xE000B1A8 gem1: 0xE000C1A8 32 bits ro 0x00000000 IP header checksum errors

Register ip_hdr_csum_errors Details

Field Name reserved ip_hdr_csum_errors Bits 31:8 7:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. 0 IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

Register (GEM) tcp_csum_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description tcp_csum_errors XEMACPS_RXTCPCCNT 0x000001AC gem0: 0xE000B1AC gem1: 0xE000C1AC 32 bits ro 0x00000000 TCP checksum errors

Register tcp_csum_errors Details

Field Name reserved tcp_csum_errors Bits 31:8 7:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

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Register (GEM) udp_csum_errors

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description udp_csum_errors XEMACPS_RXUDPCCNT 0x000001B0 gem0: 0xE000B1B0 gem1: 0xE000C1B0 32 bits ro 0x00000000 UDP checksum error

Register udp_csum_errors Details

Field Name reserved udp_csum_errors Bits 31:8 7:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

Register (GEM) timer_strobe_s

Name Relative Address Absolute Address Width Access Type Reset Value Description timer_strobe_s 0x000001C8 gem0: 0xE000B1C8 gem1: 0xE000C1C8 32 bits rw 0x00000000 1588 timer sync strobe seconds

Register timer_strobe_s Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description The value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero.

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Register (GEM) timer_strobe_ns

Name Relative Address Absolute Address Width Access Type Reset Value Description timer_strobe_ns 0x000001CC gem0: 0xE000B1CC gem1: 0xE000C1CC 32 bits mixed 0x00000000 1588 timer sync strobe nanoseconds

Register timer_strobe_ns Details

Field Name reserved ns_reg_val Bits 31:30 29:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero.

Register (GEM) timer_s

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description timer_s XEMACPS_1588_SEC 0x000001D0 gem0: 0xE000B1D0 gem1: 0xE000C1D0 32 bits rw 0x00000000 1588 timer seconds

Register timer_s Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Timer count in seconds. This register is writeable. It increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented when the timer adjust register is written.

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Register (GEM) timer_ns

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description timer_ns XEMACPS_1588_NANOSEC 0x000001D4 gem0: 0xE000B1D4 gem1: 0xE000C1D4 32 bits mixed 0x00000000 1588 timer nanoseconds

Register timer_ns Details

Field Name reserved timer_ct_ns Bits 31:30 29:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle.

Register (GEM) timer_adjust

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description timer_adjust XEMACPS_1588_ADJ 0x000001D8 gem0: 0xE000B1D8 gem1: 0xE000C1D8 32 bits mixed 0x00000000 1588 timer adjust

Register timer_adjust Details

Field Name add_subn Bits 31 Type wo Reset Value 0x0 Description Write as one to subtract from the 1588 timer. Write as zero to add to it.

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Field Name reserved ns_delta

Bits 30 29:0

Type ro wo

Reset Value 0x0 0x0

Description Reserved, read as 0, ignored on write. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary, the 1588 seconds register will be incremented or decremented.

Register (GEM) timer_incr

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description timer_incr XEMACPS_1588_INC 0x000001DC gem0: 0xE000B1DC gem1: 0xE000C1DC 32 bits mixed 0x00000000 1588 timer increment

Register timer_incr Details

Field Name reserved incr_b4_alt alt_ct_ns_delta Bits 31:24 23:16 15:8 Type ro rw rw Reset Value 0x0 0x0 0x0 Description Reserved, read as 0, ignored on write. The number of increments after which the alternative increment is used. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle.

ns_delta

7:0

rw

0x0

Register (GEM) ptp_tx_s

Name Software Name Relative Address Absolute Address Width ptp_tx_s XEMACPS_PTP_TXSEC 0x000001E0 gem0: 0xE000B1E0 gem1: 0xE000C1E0 32 bits

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Access Type Reset Value Description

ro 0x00000000 PTP event frame transmitted seconds

Register ptp_tx_s Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_tx_ns

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ptp_tx_ns XEMACPS_PTP_TXNANOSEC 0x000001E4 gem0: 0xE000B1E4 gem1: 0xE000C1E4 32 bits ro 0x00000000 PTP event frame transmitted nanoseconds

Register ptp_tx_ns Details

Field Name reserved ns_reg_val Bits 31:30 29:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_rx_s

Name Software Name ptp_rx_s XEMACPS_PTP_RXSEC

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Relative Address Absolute Address Width Access Type Reset Value Description

0x000001E8 gem0: 0xE000B1E8 gem1: 0xE000C1E8 32 bits ro 0x00000000 PTP event frame received seconds

Register ptp_rx_s Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_rx_ns

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ptp_rx_ns XEMACPS_PTP_RXNANOSEC 0x000001EC gem0: 0xE000B1EC gem1: 0xE000C1EC 32 bits ro 0x00000000 PTP event frame received nanoseconds.

Register ptp_rx_ns Details

Field Name reserved ns_reg_val Bits 31:30 29:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.

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Register (GEM) ptp_peer_tx_s

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ptp_peer_tx_s XEMACPS_PTPP_TXSEC 0x000001F0 gem0: 0xE000B1F0 gem1: 0xE000C1F0 32 bits ro 0x00000000 PTP peer event frame transmitted seconds

Register ptp_peer_tx_s Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdealy_req or pdelay_resp frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_peer_tx_ns

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ptp_peer_tx_ns XEMACPS_PTPP_TXNANOSEC 0x000001F4 gem0: 0xE000B1F4 gem1: 0xE000C1F4 32 bits ro 0x00000000 PTP peer event frame transmitted nanoseconds

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Register ptp_peer_tx_ns Details

Field Name reserved ns_reg_val Bits 31:30 29:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_peer_rx_s

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ptp_peer_rx_s XEMACPS_PTPP_RXSEC 0x000001F8 gem0: 0xE000B1F8 gem1: 0xE000C1F8 32 bits ro 0x00000000 PTP peer event frame received seconds

Register ptp_peer_rx_s Details

Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated.

Register (GEM) ptp_peer_rx_ns

Name Software Name Relative Address Absolute Address Width ptp_peer_rx_ns XEMACPS_PTPP_RXNANOSEC 0x000001FC gem0: 0xE000B1FC gem1: 0xE000C1FC 32 bits

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Access Type Reset Value Description

ro 0x00000000 PTP peer event frame received nanoseconds.

Register ptp_peer_rx_ns Details

Field Name reserved ns_reg_val Bits 31:30 29:0 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as 0, ignored on write. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated.

Register (GEM) design_cfg2

Name Relative Address Absolute Address Width Access Type Reset Value Description design_cfg2 0x00000284 gem0: 0xE000B284 gem1: 0xE000C284 32 bits ro x Design Configuration 2

Register design_cfg2 Details

Field Name reserved gem_tx_pbuf_addr Bits 31:30 29:26 Type ro ro x 0xA Reset Value Description Reserved. Set to zero. Takes the value of the `gem_tx_pbuf_addr DEFINE. Max address bits for Tx packet buffer (10-bits for maximum 4 kB buffer). Buffer size for Tx packet buffer mode will be 4kB. This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.

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Field Name gem_rx_pbuf_addr

Bits 25:22

Type ro

Reset Value 0xA

Description Takes the value of the `gem_rx_pbuf_addr DEFINE. Max address bits for Rx packet buffer (10-bits for maximum 4 kB buffer). Buffer size for Rx packet buffer mode will be 4kB. This will allow one standard packet to be received while another is transferred to system memory by the DMA interface.

gem_tx_pkt_buffer

21

ro

Takes the value of the `gem_tx_pkt_buffer DEFINE. Defined for Zynq. Includes the transmitter packet buffer Takes the value of the `gem_rx_pkt_buffer DEFINE. Defined for Zynq. Includes the receiver packet buffer. Takes the value of the `gem_hprot_value DEFINE. For Zynq, set the fixed AHB HPROT value used during transfers. Takes the value of the `gem_jumbo_max_length DEFINE. Maximum length of jumbo frames accepted by receiver. This is set to the size of the smallest of the two packet buffer, minus a margin for packet headers. However, Zynq will not support jumbo frames.

gem_rx_pkt_buffer

20

ro

gem_hprot_value

19:16

ro

0x1

gem_jumbo_max_lengt h

15:0

ro

0x3FFF

Register (GEM) design_cfg3

Name Relative Address Absolute Address Width Access Type Reset Value Description design_cfg3 0x00000288 gem0: 0xE000B288 gem1: 0xE000C288 32 bits ro 0x00000000 Design Configuration 3

Register design_cfg3 Details

Field Name gem_rx_base2_fifo_siz e gem_rx_fifo_size Bits 31:16 15:0 Type ro ro Reset Value 0x0 0x0 Description Takes the value of the `gem_rx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_rx_fifo_size Takes the value of the `gem_rx_fifo_size DEFINE. Set the size of the small Rx FIFO for grant latency. Extended to 16 deep to allow buffering of 64 byte maximum AHB burst size in Zynq.

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Register (GEM) design_cfg4

Name Relative Address Absolute Address Width Access Type Reset Value Description design_cfg4 0x0000028C gem0: 0xE000B28C gem1: 0xE000C28C 32 bits ro 0x00000000 Design Configuration 4

Register design_cfg4 Details

Field Name Bits Type ro ro Reset Value 0x0 0x0 Description Takes the value of the `gem_tx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_tx_fifo_size. Takes the value of the `gem_tx_fifo_size DEFINE. Set the size of the small TX FIFO for grant latency

gem_tx_base2_fifo_size 31:16 gem_tx_fifo_size 15:0

Register (GEM) design_cfg5

Name Relative Address Absolute Address Width Access Type Reset Value Description design_cfg5 0x00000290 gem0: 0xE000B290 gem1: 0xE000C290 32 bits ro x Design Configuration 5

Register design_cfg5 Details

Field Name reserved gem_tsu_clk Bits 31:29 28 Type ro ro x x Reset Value Description Reserved. Set to zero. Takes the value of the `gem_tsu_clk DEFINE. Undefined in Zynq. 1588 Time Stamp Unit clock sourced from pclk rather than independent tsu_clk. Takes the value of the `gem_rx_buffer_length_def DEFINE. Set the default buffer length used by Rx DMA to 128 bytes.

gem_rx_buffer_length_ def

27:20

ro

0x2

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Field Name gem_tx_pbuf_size_def

Bits 19

Type ro

Reset Value 0x1

Description Takes the value of the `gem_tx_pbuf_size_def DEFINE. Full 4 kB Tx packet buffer size dedicated memory resource in Zynq. Takes the value of the `gem_rx_pbuf_size_def DEFINE. Full 4 kB Rx packet buffer size - dedicated memory resource in Zynq.

gem_rx_pbuf_size_def

18:17

ro

0x3

gem_endian_swap_def

16:15

ro

0x2

Takes the value of the `gem_endian_swap_def DEFINE. Set to big endian data, little endian management descriptors in Zynq. Takes the value of the `gem_mdc_clock_div DEFINE. Set default MDC clock divisor (can still be programmed) in Zynq. Takes the value of the `gem_dma_bus_width_def DEFINE. Limit to 32-bit AHB bus in Zynq. Takes the value of the `gem_phy_ident DEFINE. Undefined in Zynq. Only used in PCS. Takes the value of the `gem_tsu DEFINE. Defined in Zynq. Include support for 1588 Time Stamp Unit. Takes the value of the `gem_tx_fifo_cnt_width DEFINE. Width for `gem_tx_fifo_size Takes the value of the `gem_rx_fifo_cnt_width DEFINE. Width for `gem_rx_fifo_size.

gem_mdc_clock_div

14:12

ro

0x2

gem_dma_bus_width gem_phy_ident gem_tsu

11:10 9 8

ro ro ro

0x0 x x

gem_tx_fifo_cnt_width gem_rx_fifo_cnt_width

7:4 3:0

ro ro

0x4 0x5

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B.19 General Purpose I/O (gpio)

Module Name Software Name Base Address Description Vendor Info General Purpose I/O (gpio) XGPIOPS 0xE000A000 gpio General Purpose Input / Output

Register Summary
Register Name MASK_DATA_0_LSW MASK_DATA_0_MSW MASK_DATA_1_LSW MASK_DATA_1_MSW MASK_DATA_2_LSW MASK_DATA_2_MSW MASK_DATA_3_LSW MASK_DATA_3_MSW DATA_0 DATA_1 DATA_2 DATA_3 DATA_0_RO DATA_1_RO DATA_2_RO DATA_3_RO Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000060 0x00000064 0x00000068 0x0000006C Width 32 32 32 22 32 32 32 32 32 22 32 32 32 22 32 32 Type mixed mixed mixed mixed mixed mixed mixed mixed rw rw rw rw ro ro ro ro Reset Value x x x x 0x00000000 0x00000000 0x00000000 0x00000000 x x 0x00000000 0x00000000 x x 0x00000000 0x00000000 Description Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) Maskable Output Data (GPIO Bank0, MIO, Upper 16bits) Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) Maskable Output Data (GPIO Bank2, EMIO, Lower 16bits) Maskable Output Data (GPIO Bank2, EMIO, Upper 16bits) Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits) Maskable Output Data (GPIO Bank3, EMIO, Upper 16bits) Output Data (GPIO Bank0, MIO) Output Data (GPIO Bank1, MIO) Output Data (GPIO Bank2, EMIO) Output Data (GPIO Bank3, EMIO) Input Data (GPIO Bank0, MIO) Input Data (GPIO Bank1, MIO) Input Data (GPIO Bank2, EMIO) Input Data (GPIO Bank3, EMIO)

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Register Name DIRM_0 OEN_0 INT_MASK_0 INT_EN_0 INT_DIS_0 INT_STAT_0 INT_TYPE_0 INT_POLARITY_0 INT_ANY_0 DIRM_1 OEN_1 INT_MASK_1 INT_EN_1 INT_DIS_1 INT_STAT_1 INT_TYPE_1 INT_POLARITY_1 INT_ANY_1 DIRM_2 OEN_2

Address 0x00000204 0x00000208 0x0000020C 0x00000210 0x00000214 0x00000218 0x0000021C 0x00000220 0x00000224 0x00000244 0x00000248 0x0000024C 0x00000250 0x00000254 0x00000258 0x0000025C 0x00000260 0x00000264 0x00000284 0x00000288

Width 32 32 32 32 32 32 32 32 32 22 22 22 22 22 22 22 22 22 32 32

Type rw rw ro wo wo wtc rw rw rw rw rw ro wo wo wtc rw rw rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x003FFFFF 0x00000000 0x00000000 0x00000000 0x00000000

Description Direction mode (GPIO Bank0, MIO) Output enable (GPIO Bank0, MIO) Interrupt Mask Status (GPIO Bank0, MIO) Interrupt Enable/Unmask (GPIO Bank0, MIO) Interrupt Disable/Mask (GPIO Bank0, MIO) Interrupt Status (GPIO Bank0, MIO) Interrupt Type (GPIO Bank0, MIO) Interrupt Polarity (GPIO Bank0, MIO) Interrupt Any Edge Sensitive (GPIO Bank0, MIO) Direction mode (GPIO Bank1, MIO) Output enable (GPIO Bank1, MIO) Interrupt Mask Status (GPIO Bank1, MIO) Interrupt Enable/Unmask (GPIO Bank1, MIO) Interrupt Disable/Mask (GPIO Bank1, MIO) Interrupt Status (GPIO Bank1, MIO) Interrupt Type (GPIO Bank1, MIO) Interrupt Polarity (GPIO Bank1, MIO) Interrupt Any Edge Sensitive (GPIO Bank1, MIO) Direction mode (GPIO Bank2, EMIO) Output enable (GPIO Bank2, EMIO)

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Register Name INT_MASK_2 INT_EN_2 INT_DIS_2 INT_STAT_2 INT_TYPE_2 INT_POLARITY_2 INT_ANY_2 DIRM_3 OEN_3 INT_MASK_3 INT_EN_3 INT_DIS_3 INT_STAT_3 INT_TYPE_3 INT_POLARITY_3 INT_ANY_3

Address 0x0000028C 0x00000290 0x00000294 0x00000298 0x0000029C 0x000002A0 0x000002A4 0x000002C4 0x000002C8 0x000002CC 0x000002D0 0x000002D4 0x000002D8 0x000002DC 0x000002E0 0x000002E4

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type ro wo wo wtc rw rw rw rw rw ro wo wo wtc rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0x00000000 0x00000000

Description Interrupt Mask Status (GPIO Bank2, EMIO) Interrupt Enable/Unmask (GPIO Bank2, EMIO) Interrupt Disable/Mask (GPIO Bank2, EMIO) Interrupt Status (GPIO Bank2, EMIO) Interrupt Type (GPIO Bank2, EMIO) Interrupt Polarity (GPIO Bank2, EMIO) Interrupt Any Edge Sensitive (GPIO Bank2, EMIO) Direction mode (GPIO Bank3, EMIO) Output enable (GPIO Bank3, EMIO) Interrupt Mask Status (GPIO Bank3, EMIO) Interrupt Enable/Unmask (GPIO Bank3, EMIO) Interrupt Disable/Mask (GPIO Bank3, EMIO) Interrupt Status (GPIO Bank3, EMIO) Interrupt Type (GPIO Bank3, EMIO) Interrupt Polarity (GPIO Bank3, EMIO) Interrupt Any Edge Sensitive (GPIO Bank3, EMIO)

Register (gpio) MASK_DATA_0_LSW

Name Software Name Relative Address Absolute Address Width MASK_DATA_0_LSW DATA_LSW 0x00000000 0xE000A000 32 bits

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Access Type Reset Value Description

mixed x Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)

Register MASK_DATA_0_LSW Details

This register enables software to change the value being output on up to 16bits at one time selectively. Only data values with a corresponding deasserted mask bit will be changed. Output data values are unchanged and hold their previous value for bits which are masked. This register avoids the need for a read-modify-write sequence for unchanged bits. NOTE: This register does not affect the enabling of the output driver. See the DIRM_0 and OEN_0 registers. This register controls the output values for the lower 16bits of bank0, which corresponds to MIO[15:0].
Field Name MASK_0_LSW Bits 31:16 Type wo Reset Value 0x0 Description On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. DATA_0_LSW 15:0 rw x On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.

Register (gpio) MASK_DATA_0_MSW

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_0_MSW DATA_MSW 0x00000004 0xE000A004 32 bits mixed x Maskable Output Data (GPIO Bank0, MIO, Upper 16bits)

Register MASK_DATA_0_MSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 16bits of bank0, which corresponds to MIO[31:16].

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Field Name MASK_0_MSW DATA_0_MSW

Bits 31:16 15:0

Type wo rw

Reset Value 0x0 x

Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_1_LSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_1_LSW 0x00000008 0xE000A008 32 bits mixed x Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)

Register MASK_DATA_1_LSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16bits of bank1, which corresponds to MIO[47:32].
Field Name MASK_1_LSW DATA_1_LSW Bits 31:16 15:0 Type wo rw Reset Value 0x0 x Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_1_MSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_1_MSW 0x0000000C 0xE000A00C 22 bits mixed x Maskable Output Data (GPIO Bank1, MIO, Upper 6bits)

Register MASK_DATA_1_MSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 6bits of bank1, which corresponds to MIO[53:48]. NOTE: This register does not control a full 16bits because the MIO unit itself is limited to 54 pins.

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Field Name MASK_1_MSW reserved DATA_1_MSW

Bits 21:16 15:6 5:0

Type wo rw rw

Reset Value 0x0 0x0 x

Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Not used, read back as zero Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_2_LSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_2_LSW 0x00000010 0xE000A010 32 bits mixed 0x00000000 Maskable Output Data (GPIO Bank2, EMIO, Lower 16bits)

Register MASK_DATA_2_LSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16bits of bank2, which corresponds to EMIO[15:0].
Field Name MASK_2_LSW DATA_2_LSW Bits 31:16 15:0 Type wo rw Reset Value 0x0 0x0 Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_2_MSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_2_MSW 0x00000014 0xE000A014 32 bits mixed 0x00000000 Maskable Output Data (GPIO Bank2, EMIO, Upper 16bits)

Register MASK_DATA_2_MSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 16bits of bank2, which corresponds to EMIO[31:16].

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Field Name MASK_2_MSW DATA_2_MSW

Bits 31:16 15:0

Type wo rw

Reset Value 0x0 0x0

Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_3_LSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_3_LSW 0x00000018 0xE000A018 32 bits mixed 0x00000000 Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits)

Register MASK_DATA_3_LSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16bits of bank3, which corresponds to EMIO[47:32].
Field Name MASK_3_LSW DATA_3_LSW Bits 31:16 15:0 Type wo rw Reset Value 0x0 0x0 Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) MASK_DATA_3_MSW

Name Relative Address Absolute Address Width Access Type Reset Value Description MASK_DATA_3_MSW 0x0000001C 0xE000A01C 32 bits mixed 0x00000000 Maskable Output Data (GPIO Bank3, EMIO, Upper 16bits)

Register MASK_DATA_3_MSW Details

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 16bits of bank3, which corresponds to EMIO[63:48].

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Field Name MASK_3_MSW DATA_3_MSW

Bits 31:16 15:0

Type wo rw

Reset Value 0x0 0x0

Description Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]

Register (gpio) DATA_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_0 DATA 0x00000040 0xE000A040 32 bits rw x Output Data (GPIO Bank0, MIO)

Register DATA_0 Details

This register controls the value being output when the GPIO signal is configured as an output. All 32bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the value on the device pin. NOTE: This register does not affect the enabling of the output driver. See the DIRM_0 and OEN_0 registers. This register controls the output values for bank0, which corresponds to MIO[31:0].
Field Name DATA_0 Bits 31:0 Type rw Reset Value x Output Data Description

Register (gpio) DATA_1

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_1 0x00000044 0xE000A044 22 bits rw x Output Data (GPIO Bank1, MIO)

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Register DATA_1 Details

This register operates in exactly the same manner as DATA_0, except that it controls bank1, which corresponds to MIO[53:32].
Field Name DATA_1 Bits 21:0 Type rw Reset Value x Output Data Description

Register (gpio) DATA_2

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_2 0x00000048 0xE000A048 32 bits rw 0x00000000 Output Data (GPIO Bank2, EMIO)

Register DATA_2 Details

This register operates in exactly the same manner as DATA_0, except that it controls bank2, which corresponds to EMIO[31:0].
Field Name DATA_2 Bits 31:0 Type rw Reset Value 0x0 Output Data Description

Register (gpio) DATA_3

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_3 0x0000004C 0xE000A04C 32 bits rw 0x00000000 Output Data (GPIO Bank3, EMIO)

Register DATA_3 Details

This register operates in exactly the same manner as DATA_0, except that it controls bank3, which corresponds to EMIO[63:32].
Field Name DATA_3 Bits 31:0 Type rw Reset Value 0x0 Output Data Description

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Register (gpio) DATA_0_RO

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_0_RO 0x00000060 0xE000A060 32 bits ro x Input Data (GPIO Bank0, MIO)

Register DATA_0_RO Details

This register enables software to observe the value on the device pin. If the GPIO signal is configured as an output, then this would normally reflect the value being driven on the output. Writes to this register are ignored. This register reflects the input values for bank0, which corresponds to MIO[31:0]. NOTE: If the MIO is not configured to enable this pin as a GPIO pin, then DATA_RO is unpredictable. In other words, software cannot observe values on non-GPIO pins through the GPIO registers.
Field Name DATA_0_RO Bits 31:0 Type ro Reset Value x Input Data NOTE: bits[8:7] of bank0 cannot be used as inputs and will always return 0 when read. See the GPIO chapter for more information. Description

Register (gpio) DATA_1_RO

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_1_RO 0x00000064 0xE000A064 22 bits ro x Input Data (GPIO Bank1, MIO)

Register DATA_1_RO Details

This register operates in exactly the same manner as DATA_0_RO, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name DATA_1_RO Bits 21:0 Type ro Reset Value x Input Data Description

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Register (gpio) DATA_2_RO

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_2_RO 0x00000068 0xE000A068 32 bits ro 0x00000000 Input Data (GPIO Bank2, EMIO)

Register DATA_2_RO Details

This register operates in exactly the same manner as DATA_0_RO, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name DATA_2_RO Bits 31:0 Type ro Reset Value 0x0 Input Data Description

Register (gpio) DATA_3_RO

Name Relative Address Absolute Address Width Access Type Reset Value Description DATA_3_RO 0x0000006C 0xE000A06C 32 bits ro 0x00000000 Input Data (GPIO Bank3, EMIO)

Register DATA_3_RO Details

This register operates in exactly the same manner as DATA_0_RO, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name DATA_3_RO Bits 31:0 Type ro Reset Value 0x0 Input Data Description

Register (gpio) DIRM_0

Name Software Name Relative Address Absolute Address DIRM_0 DIRM 0x00000204 0xE000A204

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Width Access Type Reset Value Description

32 bits rw 0x00000000 Direction mode (GPIO Bank0, MIO)

Register DIRM_0 Details

This register controls whether the IO pin is acting as an input or an output. Since the input logic is always enabled, this effectively enables/disables the output driver. Each bit of the bank is independently controlled. This register controls bank0, which corresponds to MIO[31:0].
Field Name DIRECTION_0 Bits 31:0 Type rw Reset Value 0x0 Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information. Description

Register (gpio) OEN_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description OEN_0 OUTEN 0x00000208 0xE000A208 32 bits rw 0x00000000 Output enable (GPIO Bank0, MIO)

Register OEN_0 Details

When the IO is configured as an output, this controls whether the output is enabled or not. When the output is disabled, the pin is tri-stated. NOTE: The MIO driver setting (slcr.MIO_PIN_xx.TRI_ENABLE field) must be disabled (i.e. set to 0) for this field to be operational. When the MIO tri-state is enabled, the driver is disabled regardless of this GPIO setting. This register controls bank0, which corresponds to MIO[31:0].

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Field Name OP_ENABLE_0

Bits 31:0

Type rw

Reset Value 0x0 Output enables 0: disabled 1: enabled

Description

Each bit configures the corresponding pin within the 32-bit bank

Register (gpio) INT_MASK_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INT_MASK_0 INTMASK 0x0000020C 0xE000A20C 32 bits ro 0x00000000 Interrupt Mask Status (GPIO Bank0, MIO)

Register INT_MASK_0 Details

This register shows which bits are currently masked and which are un-masked/enabled. This register is read only, so masks cannot be changed here. Use INT_EN and INT_DIS to change the mask value. This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_MASK_0 Bits 31:0 Type ro Reset Value 0x0 Interrupt mask 0: interrupt source enabled 1: interrupt source masked Each bit reports the status for the corresponding pin within the 32-bit bank Description

Register (gpio) INT_EN_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value INT_EN_0 INTEN 0x00000210 0xE000A210 32 bits wo 0x00000000

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Description

Interrupt Enable/Unmask (GPIO Bank0, MIO)

Register INT_EN_0 Details

This register is used to enable or unmask a GPIO input for use as an interrupt source. Writing a 1 to any bit of this register enables/unmasks that signal for interrupts. Reading from this register returns an unpredictable value. This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_ENABLE_0 Bits 31:0 Type wo Reset Value 0x0 Interrupt enable 0: no change 1: clear interrupt mask Each bit configures the corresponding pin within the 32-bit bank Description

Register (gpio) INT_DIS_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INT_DIS_0 INTDIS 0x00000214 0xE000A214 32 bits wo 0x00000000 Interrupt Disable/Mask (GPIO Bank0, MIO)

Register INT_DIS_0 Details

This register is used to disable or mask a GPIO input for use as an interrupt source. Writing a 1 to any bit of this register disables/masks that signal for interrupts. Reading from this register returns an unpredictable value. This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_DISABLE_0 Bits 31:0 Type wo Reset Value 0x0 Interrupt disable 0: no change 1: set interrupt mask Each bit configures the corresponding pin within the 32-bit bank Description

Register (gpio) INT_STAT_0

Name INT_STAT_0

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

INTSTS 0x00000218 0xE000A218 32 bits wtc 0x00000000 Interrupt Status (GPIO Bank0, MIO)

Register INT_STAT_0 Details

This registers shows if an interrupt event has occurred or not. Writing a 1 to a bit in this register clears the interrupt status for that bit. Writing a 0 to a bit in this register is ignored. This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_STATUS_0 Bits 31:0 Type wtc Reset Value 0x0 Interrupt status Upon read: 0: no interrupt 1: interrupt event has occurred Upon write: 0: no action 1: clear interrupt status bit Each bit configures the corresponding pin within the 32-bit bank Description

Register (gpio) INT_TYPE_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INT_TYPE_0 INTTYPE 0x0000021C 0xE000A21C 32 bits rw 0xFFFFFFFF Interrupt Type (GPIO Bank0, MIO)

Register INT_TYPE_0 Details

This register controls whether the interrupt is edge sensitive or level sensitive. This register controls bank0, which corresponds to MIO[31:0].

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Field Name INT_TYPE_0

Bits 31:0

Type rw

Reset Value 0xFFFFFFFF Interrupt type 0: level-sensitive 1: edge-sensitive

Description

Each bit configures the corresponding pin within the 32-bit bank

Register (gpio) INT_POLARITY_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description INT_POLARITY_0 INTPOL 0x00000220 0xE000A220 32 bits rw 0x00000000 Interrupt Polarity (GPIO Bank0, MIO)

Register INT_POLARITY_0 Details

This register controls whether the interrupt is active-low or active high (or falling-edge sensitive or rising-edge sensitive). This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_POL_0 Bits 31:0 Type rw Reset Value 0x0 Interrupt polarity 0: active low or falling edge 1: active high or rising edge Each bit configures the corresponding pin within the 32-bit bank Description

Register (gpio) INT_ANY_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value INT_ANY_0 INTANY 0x00000224 0xE000A224 32 bits rw 0x00000000

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Description

Interrupt Any Edge Sensitive (GPIO Bank0, MIO)

Register INT_ANY_0 Details

If INT_TYPE is set to edge sensitive, then this register enables an interrupt event on both rising and falling edges. This register is ignored if INT_TYPE is set to level sensitive. This register controls bank0, which corresponds to MIO[31:0].
Field Name INT_ON_ANY_0 Bits 31:0 Type rw Reset Value 0x0 Description Interrupt edge triggering mode 0: trigger on single edge, using configured interrupt polarity 1: trigger on both edges Each bit configures the corresponding pin within the 32-bit bank

Register (gpio) DIRM_1

Name Relative Address Absolute Address Width Access Type Reset Value Description DIRM_1 0x00000244 0xE000A244 22 bits rw 0x00000000 Direction mode (GPIO Bank1, MIO)

Register DIRM_1 Details

This register operates in exactly the same manner as DIRM_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name DIRECTION_1 Bits 21:0 Type rw Reset Value 0x0 Description Operation is the same as DIRM_0[DIRECTION_0]

Register (gpio) OEN_1

Name Relative Address Absolute Address Width Access Type Reset Value OEN_1 0x00000248 0xE000A248 22 bits rw 0x00000000

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Description

Output enable (GPIO Bank1, MIO)

Register OEN_1 Details

This register operates in exactly the same manner as OEN_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name OP_ENABLE_1 Bits 21:0 Type rw Reset Value 0x0 Description Operation is the same as OEN_0[OP_ENABLE_0]

Register (gpio) INT_MASK_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_MASK_1 0x0000024C 0xE000A24C 22 bits ro 0x00000000 Interrupt Mask Status (GPIO Bank1, MIO)

Register INT_MASK_1 Details

This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_MASK_1 Bits 21:0 Type ro Reset Value 0x0 Description Operation is the same as INT_MASK_0[INT_MASK_0]

Register (gpio) INT_EN_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_EN_1 0x00000250 0xE000A250 22 bits wo 0x00000000 Interrupt Enable/Unmask (GPIO Bank1, MIO)

Register INT_EN_1 Details

This register operates in exactly the same manner as INT_EN_0, except that it reflects bank1, which corresponds to MIO[53:32].

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Field Name INT_ENABLE_1

Bits 21:0

Type wo

Reset Value 0x0

Description Operation is the same as INT_EN_0[INT_ENABLE_0]

Register (gpio) INT_DIS_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_DIS_1 0x00000254 0xE000A254 22 bits wo 0x00000000 Interrupt Disable/Mask (GPIO Bank1, MIO)

Register INT_DIS_1 Details

This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_DISABLE_1 Bits 21:0 Type wo Reset Value 0x0 Description Operation is the same as INT_DIS_0[INT_DISABLE_0]

Register (gpio) INT_STAT_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_STAT_1 0x00000258 0xE000A258 22 bits wtc 0x00000000 Interrupt Status (GPIO Bank1, MIO)

Register INT_STAT_1 Details

This register operates in exactly the same manner as INT_STAT_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_STATUS_1 Bits 21:0 Type wtc Reset Value 0x0 Description Operation is the same as INT_STAT_0[INT_STATUS_0]

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Register (gpio) INT_TYPE_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_TYPE_1 0x0000025C 0xE000A25C 22 bits rw 0x003FFFFF Interrupt Type (GPIO Bank1, MIO)

Register INT_TYPE_1 Details

This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_TYPE_1 Bits 21:0 Type rw Reset Value 0x3FFFFF Description Operation is the same as INT_TYPE_0[INT_TYPE_0]

Register (gpio) INT_POLARITY_1

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_POLARITY_1 0x00000260 0xE000A260 22 bits rw 0x00000000 Interrupt Polarity (GPIO Bank1, MIO)

Register INT_POLARITY_1 Details

This register operates in exactly the same manner as INT_POLARITY_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_POL_1 Bits 21:0 Type rw Reset Value 0x0 Description Operation is the same as INT_POLARITY_0[INT_POL_0]

Register (gpio) INT_ANY_1

Name Relative Address INT_ANY_1 0x00000264

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Absolute Address Width Access Type Reset Value Description

0xE000A264 22 bits rw 0x00000000 Interrupt Any Edge Sensitive (GPIO Bank1, MIO)

Register INT_ANY_1 Details

This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank1, which corresponds to MIO[53:32].
Field Name INT_ON_ANY_1 Bits 21:0 Type rw Reset Value 0x0 Description Operation is the same as INT_ANY_0[INT_ON_ANY_0]

Register (gpio) DIRM_2

Name Relative Address Absolute Address Width Access Type Reset Value Description DIRM_2 0x00000284 0xE000A284 32 bits rw 0x00000000 Direction mode (GPIO Bank2, EMIO)

Register DIRM_2 Details

This register operates in exactly the same manner as DIRM_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name DIRECTION_2 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as DIRM_0[DIRECTION_0]

Register (gpio) OEN_2

Name Relative Address Absolute Address Width Access Type Reset Value OEN_2 0x00000288 0xE000A288 32 bits rw 0x00000000

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Description

Output enable (GPIO Bank2, EMIO)

Register OEN_2 Details

This register operates in exactly the same manner as OEN_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name OP_ENABLE_2 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as OEN_0[OP_ENABLE_0]

Register (gpio) INT_MASK_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_MASK_2 0x0000028C 0xE000A28C 32 bits ro 0x00000000 Interrupt Mask Status (GPIO Bank2, EMIO)

Register INT_MASK_2 Details

This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_MASK_2 Bits 31:0 Type ro Reset Value 0x0 Description Operation is the same as INT_MASK_0[INT_MASK_0]

Register (gpio) INT_EN_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_EN_2 0x00000290 0xE000A290 32 bits wo 0x00000000 Interrupt Enable/Unmask (GPIO Bank2, EMIO)

Register INT_EN_2 Details

This register operates in exactly the same manner as INT_EN_0, except that it reflects bank2, which corresponds to EMIO[31:0].

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Field Name INT_ENABLE_2

Bits 31:0

Type wo

Reset Value 0x0

Description Operation is the same as INT_EN_0[INT_ENABLE_0]

Register (gpio) INT_DIS_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_DIS_2 0x00000294 0xE000A294 32 bits wo 0x00000000 Interrupt Disable/Mask (GPIO Bank2, EMIO)

Register INT_DIS_2 Details

This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_DISABLE_2 Bits 31:0 Type wo Reset Value 0x0 Description Operation is the same as INT_DIS_0[INT_DISABLE_0]

Register (gpio) INT_STAT_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_STAT_2 0x00000298 0xE000A298 32 bits wtc 0x00000000 Interrupt Status (GPIO Bank2, EMIO)

Register INT_STAT_2 Details

This register operates in exactly the same manner as INT_STAT_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_STATUS_2 Bits 31:0 Type wtc Reset Value 0x0 Description Operation is the same as INT_STAT_0[INT_STATUS_0]

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Register (gpio) INT_TYPE_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_TYPE_2 0x0000029C 0xE000A29C 32 bits rw 0xFFFFFFFF Interrupt Type (GPIO Bank2, EMIO)

Register INT_TYPE_2 Details

This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_TYPE_2 Bits 31:0 Type rw Reset Value 0xFFFFFFFF Description Operation is the same as INT_TYPE_0[INT_TYPE_0]

Register (gpio) INT_POLARITY_2

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_POLARITY_2 0x000002A0 0xE000A2A0 32 bits rw 0x00000000 Interrupt Polarity (GPIO Bank2, EMIO)

Register INT_POLARITY_2 Details

This register operates in exactly the same manner as INT_POLARITY_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_POL_2 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as INT_POLARITY_0[INT_POL_0]

Register (gpio) INT_ANY_2

Name Relative Address INT_ANY_2 0x000002A4

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Absolute Address Width Access Type Reset Value Description

0xE000A2A4 32 bits rw 0x00000000 Interrupt Any Edge Sensitive (GPIO Bank2, EMIO)

Register INT_ANY_2 Details

This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Field Name INT_ON_ANY_2 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as INT_ANY_0[INT_ON_ANY_0]

Register (gpio) DIRM_3

Name Relative Address Absolute Address Width Access Type Reset Value Description DIRM_3 0x000002C4 0xE000A2C4 32 bits rw 0x00000000 Direction mode (GPIO Bank3, EMIO)

Register DIRM_3 Details

This register operates in exactly the same manner as DIRM_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name DIRECTION_3 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as DIRM_0[DIRECTION_0]

Register (gpio) OEN_3

Name Relative Address Absolute Address Width Access Type Reset Value OEN_3 0x000002C8 0xE000A2C8 32 bits rw 0x00000000

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Description

Output enable (GPIO Bank3, EMIO)

Register OEN_3 Details

This register operates in exactly the same manner as OEN_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name OP_ENABLE_3 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as OEN_0[OP_ENABLE_0]

Register (gpio) INT_MASK_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_MASK_3 0x000002CC 0xE000A2CC 32 bits ro 0x00000000 Interrupt Mask Status (GPIO Bank3, EMIO)

Register INT_MASK_3 Details

This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_MASK_3 Bits 31:0 Type ro Reset Value 0x0 Description Operation is the same as INT_MASK_0[INT_MASK_0]

Register (gpio) INT_EN_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_EN_3 0x000002D0 0xE000A2D0 32 bits wo 0x00000000 Interrupt Enable/Unmask (GPIO Bank3, EMIO)

Register INT_EN_3 Details

This register operates in exactly the same manner as INT_EN_0, except that it reflects bank3, which corresponds to EMIO[63:32].

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Field Name INT_ENABLE_3

Bits 31:0

Type wo

Reset Value 0x0

Description Operation is the same as INT_EN_0[INT_ENABLE_0]

Register (gpio) INT_DIS_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_DIS_3 0x000002D4 0xE000A2D4 32 bits wo 0x00000000 Interrupt Disable/Mask (GPIO Bank3, EMIO)

Register INT_DIS_3 Details

This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_DISABLE_3 Bits 31:0 Type wo Reset Value 0x0 Description Operation is the same as INT_DIS_0[INT_DISABLE_0]

Register (gpio) INT_STAT_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_STAT_3 0x000002D8 0xE000A2D8 32 bits wtc 0x00000000 Interrupt Status (GPIO Bank3, EMIO)

Register INT_STAT_3 Details

This register operates in exactly the same manner as INT_STAT_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_STATUS_3 Bits 31:0 Type wtc Reset Value 0x0 Description Operation is the same as INT_STAT_0[INT_STATUS_0]

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Register (gpio) INT_TYPE_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_TYPE_3 0x000002DC 0xE000A2DC 32 bits rw 0xFFFFFFFF Interrupt Type (GPIO Bank3, EMIO)

Register INT_TYPE_3 Details

This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_TYPE_3 Bits 31:0 Type rw Reset Value 0xFFFFFFFF Description Operation is the same as INT_TYPE_0[INT_TYPE_0]

Register (gpio) INT_POLARITY_3

Name Relative Address Absolute Address Width Access Type Reset Value Description INT_POLARITY_3 0x000002E0 0xE000A2E0 32 bits rw 0x00000000 Interrupt Polarity (GPIO Bank3, EMIO)

Register INT_POLARITY_3 Details

This register operates in exactly the same manner as INT_POLARITY_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_POL_3 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as INT_POLARITY_0[INT_POL_0]

Register (gpio) INT_ANY_3

Name Relative Address INT_ANY_3 0x000002E4

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Absolute Address Width Access Type Reset Value Description

0xE000A2E4 32 bits rw 0x00000000 Interrupt Any Edge Sensitive (GPIO Bank3, EMIO)

Register INT_ANY_3 Details

This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Field Name INT_ON_ANY_3 Bits 31:0 Type rw Reset Value 0x0 Description Operation is the same as INT_ANY_0[INT_ON_ANY_0]

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B.20 Interconnect QoS (qos301)

Module Name Base Address Interconnect QoS (qos301) 0xF8946000 gpv_qos301_cpu 0xF8947000 gpv_qos301_dmac 0xF8948000 gpv_qos301_iou Description Vendor Info AMBA Network Interconnect Advanced Quality of Service (QoS-301) ARM QoS-301

Register Summary
Register Name qos_cntl Address 0x0000010C Width 32 Type rw Reset Value 0x00000000 Description The QoS control register contains the enable bits for all the regulators. Maximum number of outstanding transactions Maximum number of combined outstanding transactions AW channel peak rate AW channel burstiness allowance AW channel average rate AR channel peak rate AR channel burstiness allowance AR channel average rate

max_ot max_comb_ot aw_p aw_b aw_r ar_p ar_b ar_r

0x00000110 0x00000114 0x00000118 0x0000011C 0x00000120 0x00000124 0x00000128 0x0000012C

32 32 32 32 32 32 32 32

rw rw rw rw rw rw rw rw

0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Register (qos301) qos_cntl

Name Relative Address Absolute Address qos_cntl 0x0000010C gpv_qos301_cpu: 0xF894610C gpv_qos301_dmac: 0xF894710C gpv_qos301_iou: 0xF894810C Width Access Type Reset Value 32 bits rw 0x00000000

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Description

The QoS control register contains the enable bits for all the regulators.

Register qos_cntl Details

By default, all of the bits are set to 0, and no regulation is enabled. Regulation only takes place when both the enable bit is set, and its corresponding regulation value is non-zero. The QoS regulators are reset whenever they are re-enabled.
Field Name en_awar_ot en_ar_ot en_aw_ot reserved en_awar_rate en_ar_rate en_aw_rate Bits 7 6 5 4:3 2 1 0 Type rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Enable combined regulation of outstanding transactions. Enable regulation of outstanding read transactions. Enable regulation of outstanding write transactions. Reserved Enable combined AW/AR rate regulation. Enable AR rate regulation. Enable AW rate regulation.

Register (qos301) max_ot

Name Relative Address Absolute Address max_ot 0x00000110 gpv_qos301_cpu: 0xF8946110 gpv_qos301_dmac: 0xF8947110 gpv_qos301_iou: 0xF8948110 Width Access Type Reset Value Description 32 bits rw 0x00000000 Maximum number of outstanding transactions

Register max_ot Details

The maximum number of outstanding transactions register enables you to program the maximum number of address requests for the AR and AW channels. The outstanding transaction limits have an integer part and a fractional part.
Field Name ar_max_oti ar_max_otf aw_max_oti aw_max_otf Bits 29:24 23:16 13:8 7:0 Type rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 Description Integer part of max outstanding AR addresses. Fraction part of max outstanding AR addresses. Integer part of max outstanding AW addresses. Fraction part of max outstanding AW addresses.

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A value of 0 for both the integer and fractional parts disables the programmable regulation so that the NIC-301 base product configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The AW and AR outstanding transaction limits are enabled when you set the corresponding en_aw_ot or en_ar_ot control bits of the QoS control register.

Register (qos301) max_comb_ot

Name Relative Address Absolute Address max_comb_ot 0x00000114 gpv_qos301_cpu: 0xF8946114 gpv_qos301_dmac: 0xF8947114 gpv_qos301_iou: 0xF8948114 Width Access Type Reset Value Description 32 bits rw 0x00000000 Maximum number of combined outstanding transactions

Register max_comb_ot Details

The maximum combined outstanding transactions register enables you to program the maximum number of address requests for the AR and AW channels. The combined limit is applied after any individual channel limits.
Field Name awar_max_oti awar_max_otf Bits 14:8 7:0 Type rw rw Reset Value 0x0 0x0 Description Integer part of max combined outstanding AW/AR addresses. Fraction part of max combined outstanding AW/AR addresses.

A value of 0 for both the integer and fractional parts disables the programmable regulation so that the configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The regulation of the combined outstanding transaction limit also requires that you set the en_awar_ot control bit of the QoS control register.

Register (qos301) aw_p

Name Relative Address Absolute Address aw_p 0x00000118 gpv_qos301_cpu: 0xF8946118 gpv_qos301_dmac: 0xF8947118 gpv_qos301_iou: 0xF8948118

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Width Access Type Reset Value Description

32 bits rw 0x00000000 AW channel peak rate

Register aw_p Details

Field Name Bits 31:24 Type rw Reset Value 0x0 Description channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.

Register (qos301) aw_b

Name Relative Address Absolute Address aw_b 0x0000011C gpv_qos301_cpu: 0xF894611C gpv_qos301_dmac: 0xF894711C gpv_qos301_iou: 0xF894811C Width Access Type Reset Value Description 32 bits rw 0x00000000 AW channel burstiness allowance

Register aw_b Details

Field Name Bits 15:0 Type rw Reset Value 0x0 Description channel burstiness (integer number of transfers)

Register (qos301) aw_r

Name Relative Address Absolute Address aw_r 0x00000120 gpv_qos301_cpu: 0xF8946120 gpv_qos301_dmac: 0xF8947120 gpv_qos301_iou: 0xF8948120 Width Access Type 32 bits rw

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Reset Value Description

0x00000000 AW channel average rate

Register aw_r Details

Field Name Bits 31:20 Type rw Reset Value 0x0 Description channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.

Register (qos301) ar_p

Name Relative Address Absolute Address ar_p 0x00000124 gpv_qos301_cpu: 0xF8946124 gpv_qos301_dmac: 0xF8947124 gpv_qos301_iou: 0xF8948124 Width Access Type Reset Value Description 32 bits rw 0x00000000 AR channel peak rate

Register ar_p Details

Field Name Bits 31:24 Type rw Reset Value 0x0 Description channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.

Register (qos301) ar_b

Name Relative Address Absolute Address ar_b 0x00000128 gpv_qos301_cpu: 0xF8946128 gpv_qos301_dmac: 0xF8947128 gpv_qos301_iou: 0xF8948128 Width Access Type 32 bits rw

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Reset Value Description

0x00000000 AR channel burstiness allowance

Register ar_b Details

Field Name Bits 15:0 Type rw Reset Value 0x0 Description channel burstiness (integer number of transfers)

Register (qos301) ar_r

Name Relative Address Absolute Address ar_r 0x0000012C gpv_qos301_cpu: 0xF894612C gpv_qos301_dmac: 0xF894712C gpv_qos301_iou: 0xF894812C Width Access Type Reset Value Description 32 bits rw 0x00000000 AR channel average rate

Register ar_r Details

Field Name Bits 31:20 Type rw Reset Value 0x0 Description channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.

Usage Example: Peak = 2 (or 1 in 128) Burstiness = 5 Average = 10 (or 1 in 409) This allows an issuing rate of 1 in 128 until the burstiness allowance of 5 outstanding transactions is reached. Then the average issuing rate of 1 in 409 takes effect until the number of outstanding transactions drops below 5.

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B.21 NIC301 Address Region Control (nic301_addr_region_ctrl_registers)

Module Name Software Name Base Address Description Vendor Info NIC301 Address Region Control (nic301_addr_region_ctrl_registers) XARC 0xF8900000 gpv_trustzone AMBA NIC301 TrustZone. ARM

Register Summary
Register Name security_gp0_axi security_gp1_axi Address 0x0000001C 0x00000020 Width 1 1 Type wo wo Reset Value 0x00000000 0x00000000 Description M_AXI_GP0 security setting M_AXI_GP1 security setting

Register (nic301_addr_region_ctrl_registers) security_gp0_axi

Name Relative Address Absolute Address Width Access Type Reset Value Description security_gp0_axi 0x0000001C 0xF890001C 1 bits wo 0x00000000 M_AXI_GP0 security setting

Register security_gp0_axi Details

Field Name gp0_axi Bits 0 Type wo Reset Value 0x0 Description Controls the transactions from M_AXI_GP0 to PL: 0 - Always secure 1 - Always non-secure.

Register (nic301_addr_region_ctrl_registers) security_gp1_axi

Name Relative Address Absolute Address security_gp1_axi 0x00000020 0xF8900020

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Width Access Type Reset Value Description

1 bits wo 0x00000000 M_AXI_GP1 security setting

Register security_gp1_axi Details

Field Name gp1_axi Bits 0 Type wo Reset Value 0x0 Description Controls the transactions from M_AXI_GP1 to PL: 0 - Always secure 1 - Always non-secure.

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B.22 I2C Controller (IIC)

Module Name Software Name Base Address Description Vendor Info I2C Controller (IIC) XIICPS 0xE0004000 i2c0 0xE0005000 i2c1 Inter Integrated Circuit (I2C) Cadence IIC

Register Summary
Register Name Control_reg0 Status_reg0 I2C_address_reg0 I2C_data_reg0 Interrupt_status_reg0 Transfer_size_reg0 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 Width 16 16 16 16 16 8 8 8 16 16 16 Type mixed ro mixed mixed mixed rw mixed rw ro mixed mixed Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000001F 0x000002FF 0x00000000 0x00000000 Description Control Register Status register IIC Address register IIC data register IIC interrupt status register Transfer Size Register Slave Monitor Pause Register Time out register Interrupt mask register Interrupt Enable Register Interrupt Disable Register

Slave_mon_pause_reg0 0x00000018 Time_out_reg0 Intrpt_mask_reg0 Intrpt_enable_reg0 Intrpt_disable_reg0 0x0000001C 0x00000020 0x00000024 0x00000028

Register (IIC) Control_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Control_reg0 CR 0x00000000 i2c0: 0xE0004000 i2c1: 0xE0005000 16 bits mixed 0x00000000 Control Register

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Register Control_reg0 Details

Field Name divisor_a (DIV_A) divisor_b (DIV_B) reserved CLR_FIFO 7 6 ro rw 0x0 0x0 13:8 rw 0x0 Bits 15:14 Type rw Reset Value 0x0 Description Divisor for stage A clock divider. 0 - 3: Divides the input pclk frequency by divisor_a + 1. Divisor for stage B clock divider. 0 - 63 : Divides the output frequency from divisor_a by divisor_b + 1. Reserved, read as zero, ignored on write. 1 - initializes the FIFO to all zeros and clears the transfer size register. Automatically gets cleared on the next APB clock after being set. SLVMON 5 rw 0x0 Slave monitor mode 1 - monitor mode. 0 - normal operation. HOLD 4 rw 0x0 hold_bus 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. ACK_EN (ACKEN) NEA 2 rw 0x0 3 rw 0x0 This bit needs to be set to 1 1 - acknowledge enabled, ACK transmitted 0 - acknowledge disabled, NACK transmitted. Addressing mode: This bit is used in master mode only. 1 - normal (7-bit) address 0 - reserved MS 1 rw 0x0 Overall interface mode: 1 - master 0 - slave RW (RD_WR) 0 rw 0x0 Direction of transfer: This bit is used in master mode only. 1 - master receiver 0 - master transmitter.

Register (IIC) Status_reg0

Name Software Name Status_reg0 SR

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000004 i2c0: 0xE0004004 i2c1: 0xE0005004 16 bits ro 0x00000000 Status register

Register Status_reg0 Details

Field Name reserved BA RXOVF Bits 15:9 8 7 Type ro ro ro Reset Value 0x0 0x0 0x0 Description Reserved, read as zero, ignored on write. Bus Active 1 - ongoing transfer on the I2C bus. Receiver Overflow 1 - This bit is set whenever FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged. TXDV 6 ro 0x0 Transmit Data Valid - SW should not use this to determine data completion, it is the RAW value on the interface. Please use COMP in the ISR. 1 - still a byte of data to be transmitted by the interface. RXDV reserved RXRW 5 4 3 ro ro ro 0x0 0x0 0x0 Receiver Data Valid 1 -valid, new data to be read from the interface. Reserved, read as zero, ignored on write. RX read_write 1 - mode of the transmission received from a master. reserved 2:0 ro 0x0 Reserved, read as zero, ignored on write.

Register (IIC) I2C_address_reg0

Name Software Name Relative Address Absolute Address Width I2C_address_reg0 ADDR 0x00000008 i2c0: 0xE0004008 i2c1: 0xE0005008 16 bits

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Access Type Reset Value Description

mixed 0x00000000 IIC Address register

Register I2C_address_reg0 Details

Field Name reserved ADD (MASK) Bits 15:10 9:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Address 0 - 1024: Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].

Register (IIC) I2C_data_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description I2C_data_reg0 DATA 0x0000000C i2c0: 0xE000400C i2c1: 0xE000500C 16 bits mixed 0x00000000 IIC data register

Register I2C_data_reg0 Details

Field Name reserved DATA (MASK) Bits 15:8 7:0 Type ro rw Reset Value 0x0 0x0 data 0 -255: When written to, the data register sets data to transmit. When read from, the data register reads the last received byte of data. Description

Register (IIC) Interrupt_status_reg0

Name Software Name Relative Address Absolute Address Interrupt_status_reg0 ISR 0x00000010 i2c0: 0xE0004010 i2c1: 0xE0005010

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Width Access Type Reset Value Description

16 bits mixed 0x00000000 IIC interrupt status register

Register Interrupt_status_reg0 Details

Field Name reserved ARB_LOST (IXR_ARB_LOST) reserved RX_UNF (IXR_RX_UNF) 8 7 ro wtc 0x0 0x0 Bits 15:10 9 Type ro wtc Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. arbitration lost 1 = master loses bus ownership during a transfer due to ongoing arbitration Reserved, read as zero, ignored on write. FIFO receive underflow 1 = host attempts to read from the I2C data register more times than the value of the transfer size register plus one 6 wtc 0x0 FIFO transmit overflow 1 = host attempts to write to the I2C data register more times than the FIFO depth 5 wtc 0x0 Receive overflow 1 = This bit is set whenever FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged. 4 wtc 0x0 Monitored slave ready 1= addressed slave returns ACK. TO (IXR_TO) NACK (IXR_NACK) DATA (IXR_DATA) COMP (IXR_COMP) 0 wtc 0x0 1 wtc 0x0 2 wtc 0x0 3 wtc 0x0 Transfer time out 1= I2C sclk line is kept low for longer time Transfer not acknowledged 1 = slave responds with a NACK or master terminates the transfer before all data is supplied More data 1= Data being sent or received Transfer complete 1= transfer is complete

TX_OVF (IXR_TX_OVR) RX_OVF (IXR_RX_OVR)

SLV_RDY (IXR_SLV_RDY)

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Register (IIC) Transfer_size_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Transfer_size_reg0 TRANS_SIZE 0x00000014 i2c0: 0xE0004014 i2c1: 0xE0005014 8 bits rw 0x00000000 Transfer Size Register

Register Transfer_size_reg0 Details

This register's meaning varies according to the operating mode as follows: * Master transmitter mode: number of data bytes still not transmitted minus one * Master receiver mode: number of data bytes that are still expected to be received * Slave transmitter mode: number of bytes remaining in the FIFO after the master terminates the transfer * Slave receiver mode: number of valid data bytes in the FIFO This register is cleared if CLR_FIFO bit in the control register is set.
Field Name Transfer_Size (MASK) Bits 7:0 Type rw Reset Value 0x0 Transfer Size 0-255 Description

Register (IIC) Slave_mon_pause_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Slave_mon_pause_reg0 SLV_PAUSE 0x00000018 i2c0: 0xE0004018 i2c1: 0xE0005018 8 bits mixed 0x00000000 Slave Monitor Pause Register

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Register Slave_mon_pause_reg0 Details

Field Name reserved Pause (MASK) Bits 7:4 3:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. pause interval 0 - 7: pause interval

Register (IIC) Time_out_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Time_out_reg0 TIME_OUT 0x0000001C i2c0: 0xE000401C i2c1: 0xE000501C 8 bits rw 0x0000001F Time out register

Register Time_out_reg0 Details

Field Name TO (MASK) Bits 7:0 Type rw Reset Value 0x1F Time Out 127 - 32 : value of time out register Description

Register (IIC) Intrpt_mask_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_mask_reg0 IMR 0x00000020 i2c0: 0xE0004020 i2c1: 0xE0005020 16 bits ro 0x000002FF Interrupt mask register

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Register Intrpt_mask_reg0 Details

Each bit in this register corresponds to a bit in the interrupt status register. If bit i in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit i in the interrupt status register is set. Bits in this register are set through a write to the interrupt disable register and are cleared through a write to the interrupt enable register. All mask bits are set and all interrupts are disabled after reset. Interrupt mask register has the same format as the interrupt status register.
Field Name reserved ARB_LOST (IXR_ARB_LOST) reserved RX_UNF (IXR_RX_UNF) TX_OVF (IXR_TX_OVR) RX_OVF (IXR_RX_OVR) SLV_RDY (IXR_SLV_RDY) TO (IXR_TO) NACK (IXR_NACK) DATA (IXR_DATA) COMP (IXR_COMP) 0 ro 0x1 1 ro 0x1 2 ro 0x1 3 ro 0x1 4 ro 0x1 5 ro 0x1 6 ro 0x1 8 7 ro ro 0x0 0x1 Bits 15:10 9 Type ro ro Reset Value 0x0 0x1 Description Reserved, read as zero, ignored on write. arbitration lost 1 = Mask this interrupt 0 = unmask this interrupt Reserved, read as zero, ignored on write. FIFO receive underflow 1 = Mask this interrupt 0 = unmask this interrupt FIFO transmit overflow 1 = Mask this interrupt 0 = unmask this interrupt Receive overflow 1 = Mask this interrupt 0 = unmask this interrupt Monitored slave ready 1 = Mask this interrupt 0 = unmask this interrupt Transfer time out 1 = Mask this interrupt 0 = unmask this interrupt Transfer not acknowledged 1 = Mask this interrupt 0 = unmask this interrupt More data 1 = Mask this interrupt 0 = unmask this interrupt Transfer complete 1 = Mask this interrupt 0 = unmask this interrupt

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Register (IIC) Intrpt_enable_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_enable_reg0 IER 0x00000024 i2c0: 0xE0004024 i2c1: 0xE0005024 16 bits mixed 0x00000000 Interrupt Enable Register

Register Intrpt_enable_reg0 Details

This register has the same format as the interrupt status register. Setting a bit in the interrupt enable register clears the corresponding mask bit in the interrupt mask register, effectively enabling corresponding interrupt to be generated.
Field Name reserved ARB_LOST (IXR_ARB_LOST) reserved RX_UNF (IXR_RX_UNF) TX_OVF (IXR_TX_OVR) RX_OVF (IXR_RX_OVR) SLV_RDY (IXR_SLV_RDY) TO (IXR_TO) NACK (IXR_NACK) DATA (IXR_DATA) COMP (IXR_COMP) 0 wo 0x0 1 wo 0x0 2 wo 0x0 3 wo 0x0 4 wo 0x0 5 wo 0x0 6 wo 0x0 8 7 ro wo 0x0 0x0 Bits 15:10 9 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. arbitration lost 1 = enable this interrupt Reserved, read as zero, ignored on write. FIFO receive underflow 1 = enable this interrupt FIFO transmit overflow 1 = enable this interrupt Receive overflow 1 = enable this interrupt Monitored slave ready 1 = enable this interrupt Transfer time out 1 = enable this interrupt Transfer not acknowledged 1 = enable this interrupt More data 1 = enable this interrupt Transfer complete Will be set when transfer is complete 1 = enable this interrupt

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Register (IIC) Intrpt_disable_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_disable_reg0 IDR 0x00000028 i2c0: 0xE0004028 i2c1: 0xE0005028 16 bits mixed 0x00000000 Interrupt Disable Register

Register Intrpt_disable_reg0 Details

This register has the same format as the interrupt status register. Setting a bit in the interrupt disable register sets the corresponding mask bit in the interrupt mask register, effectively disabling corresponding interrupt to be generated.
Field Name reserved ARB_LOST (IXR_ARB_LOST) reserved RX_UNF (IXR_RX_UNF) TX_OVF (IXR_TX_OVR) RX_OVF (IXR_RX_OVR) SLV_RDY (IXR_SLV_RDY) TO (IXR_TO) NACK (IXR_NACK) 2 wo 0x0 3 wo 0x0 4 wo 0x0 5 wo 0x0 6 wo 0x0 8 7 ro wo 0x0 0x0 Bits 15:10 9 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. arbitration lost 1 = disable this interrupt Reserved, read as zero, ignored on write. FIFO receive underflow 1 = disable this interrupt FIFO transmit overflow 1 = disable this interrupt Receive overflow 1 = disable this interrupt Monitored slave ready 1 = disable this interrupt Transfer time out 1 = disable this interrupt Transfer not acknowledged 1 = disable this interrupt

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Field Name DATA (IXR_DATA) COMP (IXR_COMP)

Bits 1

Type wo

Reset Value 0x0

Description Master Write or Slave Transmitter Master Read or Slave Receiver 1 = disable this interrupt

wo

0x0

Transfer complete Will be set when transfer is complete 1 = disable this interrupt

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B.23 L2 Cache (L2Cpl310)

Module Name Base Address Description Vendor Info L2 Cache (L2Cpl310) 0xF8F02000 l2cache L2 cache PL310 ARM

Register Summary
Register Name reg0_cache_id Address 0x00000000 Width 32 Type mixed Reset Value 0x410000C8 Description cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator. Reset value: 0x410000c8 reg0_cache_type 0x00000004 32 mixed 0x9E300300 cache type register, Returns the 32-bit cache type. Reset value: 0x1c100100 control register, reset value: 0x0 auxilary control register, reset value: 0x02020000+H273 Configures Tag RAM latencies configures data RAM latencies Permits the event counters to be enabled and reset. Enables event counter 1 to be driven by a specific event. Counter 1 increments when the event occurs. reg2_ev_counter0_cfg 0x00000208 32 mixed 0x00000000 Enables event counter 0 to be driven by a specific event. Counter 0 increments when the event occurs.

reg1_control reg1_aux_control reg1_tag_ram_control reg1_data_ram_control reg2_ev_counter_ctrl reg2_ev_counter1_cfg

0x00000100 0x00000104 0x00000108 0x0000010C 0x00000200 0x00000204

32 32 32 32 32 32

mixed mixed mixed mixed mixed mixed

0x00000000 0x02050000 0x00000777 0x00000777 0x00000000 0x00000000

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Register Name reg2_ev_counter1

Address 0x0000020C

Width 32

Type rw

Reset Value 0x00000000

Description Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register.

reg2_ev_counter0

0x00000210

32

rw

0x00000000

Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register.

reg2_int_mask

0x00000214

32

mixed

0x00000000

This register enables or masks interrupts from being triggered on the external pins of the cache controller. Figure 3-8 on page 3-17 shows the register bit assignments. The bit assignments enables the masking of the interrupts on both their individual outputs and the combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on that pin. All bits are cleared by a reset. You must write to the register bits with a 1 to enable the generation of interrupts. 1 = Enabled. 0 = Masked. This is the default.

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Register Name reg2_int_mask_status

Address 0x00000218

Width 32

Type mixed

Reset Value 0x00000000

Description This register is a read-only.It returns the masked interrupt status. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW If the bits read LOW, either no interrupt has been generated, or the interrupt is masked.

reg2_int_raw_status

0x0000021C

32

mixed

0x00000000

The Raw Interrupt Status Register enables the interrupt status that excludes the masking logic. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW If the bits read LOW, no interrupt has been generated.

reg2_int_clear

0x00000220

32

mixed

0x00000000

Clears the Raw Interrupt Status Register bits. When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect

reg7_cache_sync

0x00000730

32

mixed

0x00000000

Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty Invalidate Line by PA: Specific L2 cache line is marked as not valid

reg7_inv_pa

0x00000770

32

mixed

0x00000000

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Register Name reg7_inv_way

Address 0x0000077C

Width 32

Type mixed

Reset Value 0x00000000

Description Invalidate by Way Invalidate all data in specified ways, including dirty data. An Invalidate by way while selecting all cache ways is equivalent to invalidating all cache entries. Completes as a background task with the way, or ways, locked, preventing allocation.

reg7_clean_pa

0x000007B0

32

mixed

0x00000000

Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged

reg7_clean_index

0x000007B8

32

mixed

0x00000000

Clean Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged

reg7_clean_way

0x000007BC

32

mixed

0x00000000

Clean by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged. Completes as a background task with the way, or ways, locked, preventing allocation.

reg7_clean_inv_pa

0x000007F0

32

mixed

0x00000000

Clean and Invalidate Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid Clean and Invalidate Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid

reg7_clean_inv_index

0x000007F8

32

mixed

0x00000000

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Register Name reg7_clean_inv_way

Address 0x000007FC

Width 32

Type mixed

Reset Value 0x00000000

Description Clean and Invalidate by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not valid. Completes as a background task with the way, or ways, locked, preventing allocation.

reg9_d_lockdown0

0x00000900

32

mixed

0x00000000

These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following meaning: 0 allocation can occur in the corresponding way. 1 there is no allocation in the corresponding way.

reg9_i_lockdown0 reg9_d_lockdown1 reg9_i_lockdown1 reg9_d_lockdown2 reg9_i_lockdown2 reg9_d_lockdown3 reg9_i_lockdown3 reg9_d_lockdown4 reg9_i_lockdown4 reg9_d_lockdown5 reg9_i_lockdown5 reg9_d_lockdown6 reg9_i_lockdown6 reg9_d_lockdown7

0x00000904 0x00000908 0x0000090C 0x00000910 0x00000914 0x00000918 0x0000091C 0x00000920 0x00000924 0x00000928 0x0000092C 0x00000930 0x00000934 0x00000938

32 32 32 32 32 32 32 32 32 32 32 32 32 32

mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed mixed

0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

instruction lock down 0 data lock down 1 instruction lock down 1 data lock down 2 instruction lock down 2 data lock down 3 instruction lock down 3 data lock down 4 instruction lock down 4 data lock down 5 instruction lock down 5 data lock down 6 instruction lock down 6 data lock down 7

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Appendix B: Register Details

Register Name reg9_i_lockdown7 reg9_lock_line_en reg9_unlock_way

Address 0x0000093C 0x00000950 0x00000954

Width 32 32 32

Type mixed mixed mixed

Reset Value 0x00000000 0x00000000 0x00000000

Description instruction lock down 7 Lockdown by Line Enable Register. Cache lockdown by way To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following meaning: 0 allocation can occur in the corresponding way. 1 there is no allocation in the corresponding way.

reg12_addr_filtering_st art

0x00000C00

32

mixed

0x40000001

When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and <address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers.

reg12_addr_filtering_e nd

0x00000C04

32

mixed

0xFFF00000

When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and <address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers.

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Register Name reg15_debug_ctrl

Address 0x00000F40

Width 32

Type mixed

Reset Value 0x00000000

Description The Debug Control Register forces specific cache behavior required for debug. This register has read-only, non-secure, or read and write, secure, permission. Any secure access and non-secure access can read this register. Only a secure access can write to this register. If a non-secure access tries to write to this register the register issues a DECERR response and does not update.

reg15_prefetch_ctrl

0x00000F60

32

mixed

0x00000000

Purpose Enables prefetch-related features that can improve system performance. Usage constraints This register has both read-only, non-secure, and read and write, secure, permissions. Any secure or non-secure access can read this register. Only a secure access can write to this register. If a non-secure access attempts to write to this register, the register

reg15_power_ctrl

0x00000F80

32

mixed

0x00000000

Purpose Controls the operating mode clock and power modes. Usage constraints There are no usage constraints.

Register (L2Cpl310) reg0_cache_id

Name Relative Address Absolute Address Width Access Type Reset Value reg0_cache_id 0x00000000 0xF8F02000 32 bits mixed 0x410000C8

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Description

cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator. Reset value: 0x410000c8

Register reg0_cache_id Details

Field Name implementer reserved cache_id part_num rtl_release Bits 31:24 23:16 15:10 9:6 5:0 Type ro waz ro ro ro Reset Value 0x41 0x0 0x0 0x3 0x8 0x41, ARM reserved cache id part number RTL release R3p2 Description

Register (L2Cpl310) reg0_cache_type

Name Relative Address Absolute Address Width Access Type Reset Value Description reg0_cache_type 0x00000004 0xF8F02004 32 bits mixed 0x9E300300 cache type register, Returns the 32-bit cache type. Reset value: 0x1c100100

Register reg0_cache_type Details

Field Name data_banking reserved ctype Bits 31 30:29 28:25 Type ro waz ro Reset Value 0x1 0x0 0xF Description 0 = Data banking not implemented. 1 = Data banking implemented. reserved 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. H Dsize_23 Dsize_mid Dsize_19 24 23 22:20 19 ro waz,r az ro waz,r az 0x0 0x0 0x3 0x0 unified fixed to 0 L2 cache way size Read from Auxiliary Control Register 19 through 17 fixed to 0

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Field Name L2_assoc_D reserved l2cache_line_len_D Isize_11 Isize_mid Isize_7 L2_assoc_I reserved l2cache_line_len_I

Bits 18 17:14 13:12 11 10:8 7 6 5:2 1:0

Type ro waz ro waz,r az ro waz,r az ro waz ro

Reset Value 0x0 0x0 0x0 0x0 0x3 0x0 0x0 0x0 0x0

Description Read from Auxiliary Control Register bit 16 reserved L2 cache line length - 00-32 bytes fixed to 0 L2 cache way size Read from Auxiliary Control Register[19:17] fixed to 0 Read from Auxiliary Control Register bit 16 reserved L2 cache line length - 00-32 bytes

Register (L2Cpl310) reg1_control

Name Relative Address Absolute Address Width Access Type Reset Value Description reg1_control 0x00000100 0xF8F02100 32 bits mixed 0x00000000 control register, reset value: 0x0

Register reg1_control Details

Field Name reserved l2_enable Bits 30:1 0 Type waz,r az rw Reset Value 0x0 0x0 reserved, reserved 0 = L2 Cache is disabled. This is the default value. 1 = L2 Cache is enabled. Description

Register (L2Cpl310) reg1_aux_control

Name Relative Address Absolute Address Width reg1_aux_control 0x00000104 0xF8F02104 32 bits

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Access Type Reset Value Description

mixed 0x02050000 auxilary control register, reset value: 0x02020000+H273

Register reg1_aux_control Details

Field Name reserved early_bresp_en Bits 31 30 Type waz,r az rw Reset Value 0x0 0x0 reserved, reserved Early BRESP enable 0 = Early BRESP disabled. This is the default. 1 = Early BRESP enabled. instr_prefetch_en 29 rw 0x0 Instruction prefetch enable 0 = Instruction prefetching disabled. This is the default. 1 = Instruction prefetching enabled. data_prefetch_en 28 rw 0x0 Data prefetch enable 0 = Data prefetching disabled. This is the default. 1 = Data prefetching enabled. nonsec_inte_access_ctrl 27 rw 0x0 Non-secure interrupt access control 0 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can only be modified or read with secure accesses. This is the default. 1 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can be modified or read with secure or non-secure accesses. nonsec_lockdown_en 26 rw 0x0 Non-secure lockdown enable 0 = Lockdown registers cannot be modified using non-secure accesses. This is the default. 1 = Non-secure accesses can write to the lockdown registers. cache_replace_policy 25 rw 0x1 Cache replacement policy 0 = pseudo-random replacement using lfsr. 1 = round-robin replacement. This is the default. Description

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Field Name force_write_alloc

Bits 24:23

Type rw

Reset Value 0x0

Description Force write allocate b00 = Use AWCACHE attributes for WA. This is the default. b01 = Force no allocate, set WA bit always 0. b10 = Override AWCACHE attributes, set WA bit always 1, all cacheable write misses become write allocated. b11 = Internally mapped to 00. See Cache operation on page 2-11 for more information.

shared_attr_override_e n

22

rw

0x0

Shared attribute override enable 0 = Treats shared accesses as specified in Shareable attribute on page 2-15. This is the default. 1 = Shared attribute internally ignored.

parity_en

21

rw

0x0

Parity enable 0 = Disabled. This is the default. 1 = Enabled

event_mon_bus_en

20

rw

0x0

Event monitor bus enable 0 = Disabled. This is the default. 1 = Enabled

way_size

19:17

rw

0x2

Way-size b000 = Reserved, internally mapped to 16KB. b001 = 16KB. b010 = 32KB. b011 = 64KB. b100 = 128KB. b101 = 256KB. b110 = 512KB. b111 = Reserved, internally mapped to 512 KB.

associativity

16

rw

0x1

Associativity 0 = 8-way. 1 = 16-way.

reserved shared_attr_inva_en

15:14 13

waz,r az rw

0x0 0x0

reserved, reserved Shared Attribute Invalidate Enable 0 = Shared invalidate behavior disabled. This is the default. 1 = Shared invalidate behavior enabled, if Shared Attribute Override Enable bit not set. See Shareable attribute on page 2-15.

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Field Name ex_cache_config

Bits 12

Type rw

Reset Value 0x0

Description Exclusive cache configuration 0 = Disabled. This is the default. 1 = Enabled,

store_buff_dev_lim_en

11

rw

0x0

Store buffer device limitation Enable 0 = Store buffer device limitation disabled. Device writes can take all slots in store buffer. This is the default. 1= Store buffer device limitation enabled. Device writes cannot take all slots in store buffer when connected to the Cortex-A9 MPCore processor. There is always one available slot to service Normal Memory

high_pr_so_dev_rd_en

10

rw

0x0

High Priority for SO and Dev Reads Enable 0 = Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC (L2C-310) master ports. This is the default. 1 = Strongly Ordered and Device reads get the highest priority when arbitrated in the L2CC (L2C-310) master ports.

reserved full_line_zero_enable

9:1 0

waz,r az rw

0x0 0x0

reserved, reserved Full Line of Zero Enable 0 = Full line of write zero behavior disabled. This is the default. 1 = Full line of write zero behavior Enabled.

Register (L2Cpl310) reg1_tag_ram_control

Name Relative Address Absolute Address Width Access Type Reset Value Description reg1_tag_ram_control 0x00000108 0xF8F02108 32 bits mixed 0x00000777 Configures Tag RAM latencies

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Register reg1_tag_ram_control Details

Field Name reserved ram_wr_access_lat Bits 31:11 10:8 Type waz,r az rw Reset Value 0x0 0x7 reserved, reserved RAM write access latency Default value depends on the value of pl310_TAG_WRITE_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency reserved ram_rd_access_lat 7 6:4 waz,r az rw 0x0 0x7 reserved, reserved RAM read access latency Default value depends on the value of pl310_TAG_READ_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency. reserved ram_setup_lat 3 2:0 waz,r az rw 0x0 0x7 reserved, reserved RAM setup latency Default value depends on the value of pl310_TAG_SETUP_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency. Description

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Register (L2Cpl310) reg1_data_ram_control

Name Relative Address Absolute Address Width Access Type Reset Value Description reg1_data_ram_control 0x0000010C 0xF8F0210C 32 bits mixed 0x00000777 configures data RAM latencies

Register reg1_data_ram_control Details

Field Name reserved ram_wr_access_lat Bits 31:11 10:8 Type waz,r az rw Reset Value 0x0 0x7 reserved, reserved RAM write access latency Default value depends on the value of pl310_DATA_WRITE_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency reserved ram_rd_access_lat 7 6:4 waz,r az rw 0x0 0x7 reserved, reserved RAM read access latency Default value depends on the value of pl310_DATA_READ_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency. Description

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Field Name reserved ran_setup_lat

Bits 3 2:0

Type waz,r az rw

Reset Value 0x0 0x7 reserved, reserved

Description

RAM setup latency Default value depends on the value of pl310_DATA_SETUP_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency.

Register (L2Cpl310) reg2_ev_counter_ctrl

Name Relative Address Absolute Address Width Access Type Reset Value Description reg2_ev_counter_ctrl 0x00000200 0xF8F02200 32 bits mixed 0x00000000 Permits the event counters to be enabled and reset.

Register reg2_ev_counter_ctrl Details

Field Name reserved counter_reset Bits 31:3 2:1 Type waz,r az raz,r w Reset Value 0x0 0x0 reserved, reserved Always Read as zero. The following counters are reset when a 1 is written to the following bits: bit[2] = Event Counter1 reset bit[1] = Event Counter0 reset. ev_ctr_en 0 rw 0x0 Event counter enable 0 = Event Counting Disable. This is the default. 1 = Event Counting Enable. Description

Register (L2Cpl310) reg2_ev_counter1_cfg

Name reg2_ev_counter1_cfg

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000204 0xF8F02204 32 bits mixed 0x00000000 Enables event counter 1 to be driven by a specific event. Counter 1 increments when the event occurs.

Register reg2_ev_counter1_cfg Details

Field Name reserved ctr_ev_src Bits 31:6 5:2 Type waz,r az rw Reset Value 0x0 0x0 reserved, reserved Counter event source Event Encoding Counter Disabled b0000 CO b0001 DRHIT b0010 DRREQ b0011 DWHIT b0100 DWREQ b0101 DWTREQ b0110 IRHIT b0111 IRREQ b1000 WA b1001 IPFALLOC b1010 EPFHIT b1011 EPFALLOC b1100 SRRCVD b1101 SRCONF b1110 EPFRCVD b1111 ev_ctr_intr_gen 1:0 rw 0x0 Event counter interrupt generation b00 = Disabled. This is the default. b01 = Enabled: Increment condition. b10 = Enabled: Overflow condition. b11 = Interrupt generation is disabled. Description

Register (L2Cpl310) reg2_ev_counter0_cfg

Name Relative Address Absolute Address reg2_ev_counter0_cfg 0x00000208 0xF8F02208

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Width Access Type Reset Value Description

32 bits mixed 0x00000000 Enables event counter 0 to be driven by a specific event. Counter 0 increments when the event occurs.

Register reg2_ev_counter0_cfg Details

Field Name reserved ctr_ev_src Bits 31:6 5:2 Type waz,r az rw Reset Value 0x0 0x0 reserved, reserved Counter event source Event Encoding Counter Disabled b0000 CO b0001 DRHIT b0010 DRREQ b0011 DWHIT b0100 DWREQ b0101 DWTREQ b0110 IRHIT b0111 IRREQ b1000 WA b1001 IPFALLOC b1010 EPFHIT b1011 EPFALLOC b1100 SRRCVD b1101 SRCONF b1110 EPFRCVD b1111 ev_ctr_intr_gen 1:0 rw 0x0 Event counter interrupt generation b00 = Disabled. This is the default. b01 = Enabled: Increment condition. b10 = Enabled: Overflow condition. b11 = Interrupt generation is disabled. Description

Register (L2Cpl310) reg2_ev_counter1

Name Relative Address Absolute Address Width Access Type Reset Value reg2_ev_counter1 0x0000020C 0xF8F0220C 32 bits rw 0x00000000

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Description

Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register.

Register reg2_ev_counter1 Details

Field Name counter_val Bits 31:0 Type rw Reset Value 0x0 Description Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset.

Register (L2Cpl310) reg2_ev_counter0

Name Relative Address Absolute Address Width Access Type Reset Value Description reg2_ev_counter0 0x00000210 0xF8F02210 32 bits rw 0x00000000 Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register.

Register reg2_ev_counter0 Details

Field Name counter_val Bits 31:0 Type rw Reset Value 0x0 Description Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset.

Register (L2Cpl310) reg2_int_mask

Name Relative Address Absolute Address Width Access Type Reset Value reg2_int_mask 0x00000214 0xF8F02214 32 bits mixed 0x00000000

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Description

This register enables or masks interrupts from being triggered on the external pins of the cache controller. Figure 3-8 on page 3-17 shows the register bit assignments. The bit assignments enables the masking of the interrupts on both their individual outputs and the combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on that pin. All bits are cleared by a reset. You must write to the register bits with a 1 to enable the generation of interrupts. 1 = Enabled. 0 = Masked. This is the default.

Register reg2_int_mask Details

Field Name reserved DECERR SLVERR ERRRD ERRRT ERRWD ERRWT PARRD PARRT ECNTR Bits 31:9 8 7 6 5 4 3 2 1 0 Type waz,r az rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 reserved, reserved DECERR: DECERR from L3 SLVERR: SLVERR from L3 ERRRD: Error on L2 data RAM, Read ERRRT: Error on L2 tag RAM, Read ERRWD: Error on L2 data RAM, Write ERRWT: Error on L2 tag RAM, Write PARRD: Parity Error on L2 data RAM, Read PARRT: Parity Error on L2 tag RAM, Read ECNTR: Event Counter1/0 Overflow Increment Description

Register (L2Cpl310) reg2_int_mask_status

Name Relative Address Absolute Address Width Access Type Reset Value reg2_int_mask_status 0x00000218 0xF8F02218 32 bits mixed 0x00000000

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Description

This register is a read-only.It returns the masked interrupt status. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW If the bits read LOW, either no interrupt has been generated, or the interrupt is masked.

Register reg2_int_mask_status Details

Field Name reserved DECERR SLVERR ERRRD ERRRT ERRWD ERRWT PARRD PARRT ECNTR Bits 31:9 8 7 6 5 4 3 2 1 0 Type raz ro ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 reserved DECERR: DECERR from L3 SLVERR: SLVERR from L3 ERRRD: Error on L2 data RAM, Read ERRRT: Error on L2 tag RAM, Read ERRWD: Error on L2 data RAM, Write ERRWT: Error on L2 tag RAM, Write PARRD: Parity Error on L2 data RAM, Read PARRT: Parity Error on L2 tag RAM, Read ECNTR: Event Counter1/0 Overflow Increment Description

Register (L2Cpl310) reg2_int_raw_status

Name Relative Address Absolute Address Width Access Type Reset Value Description reg2_int_raw_status 0x0000021C 0xF8F0221C 32 bits mixed 0x00000000 The Raw Interrupt Status Register enables the interrupt status that excludes the masking logic. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW If the bits read LOW, no interrupt has been generated.

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Register reg2_int_raw_status Details

Field Name reserved DECERR SLVERR ERRRD ERRRT ERRWD ERRWT PARRD PARRT ECNTR Bits 31:9 8 7 6 5 4 3 2 1 0 Type raz ro ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 reserved DECERR: DECERR from L3 SLVERR: SLVERR from L3 ERRRD: Error on L2 data RAM, Read ERRRT: Error on L2 tag RAM, Read ERRWD: Error on L2 data RAM, Write ERRWT: Error on L2 tag RAM, Write PARRD: Parity Error on L2 data RAM, Read PARRT: Parity Error on L2 tag RAM, Read ECNTR: Event Counter1/0 Overflow Increment Description

Register (L2Cpl310) reg2_int_clear

Name Relative Address Absolute Address Width Access Type Reset Value Description reg2_int_clear 0x00000220 0xF8F02220 32 bits mixed 0x00000000 Clears the Raw Interrupt Status Register bits. When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect

Register reg2_int_clear Details

Field Name reserved DECERR SLVERR ERRRD ERRRT ERRWD ERRWT PARRD Bits 31:9 8 7 6 5 4 3 2 Type raz wtc wtc wtc wtc wtc wtc wtc Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 reserved DECERR: DECERR from L3 SLVERR: SLVERR from L3 ERRRD: Error on L2 data RAM, Read ERRRT: Error on L2 tag RAM, Read ERRWD: Error on L2 data RAM, Write ERRWT: Error on L2 tag RAM, Write PARRD: Parity Error on L2 data RAM, Read Description

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Appendix B: Register Details

Field Name PARRT ECNTR

Bits 1 0

Type wtc wtc

Reset Value 0x0 0x0

Description PARRT: Parity Error on L2 tag RAM, Read ECNTR: Event Counter1/0 Overflow Increment

Register (L2Cpl310) reg7_cache_sync

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_cache_sync 0x00000730 0xF8F02730 32 bits mixed 0x00000000 Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty

Register reg7_cache_sync Details

Field Name reserved c Bits 31:1 0 Type waz rw Reset Value 0x0 0x0 reserved Cache Sync: Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty. Description

Register (L2Cpl310) reg7_inv_pa

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_inv_pa 0x00000770 0xF8F02770 32 bits mixed 0x00000000 Invalidate Line by PA: Specific L2 cache line is marked as not valid

Register reg7_inv_pa Details

Field Name tag index Bits 31:12 11:5 Type rw rw Reset Value 0x0 0x0 tag index Description

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Field Name reserved c

Bits 4:1 0

Type waz rw

Reset Value 0x0 0x0 reserved C Flag

Description

When written must be 0. When read, indicates that a background operation is in progress

Register (L2Cpl310) reg7_inv_way

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_inv_way 0x0000077C 0xF8F0277C 32 bits mixed 0x00000000 Invalidate by Way Invalidate all data in specified ways, including dirty data. An Invalidate by way while selecting all cache ways is equivalent to invalidating all cache entries. Completes as a background task with the way, or ways, locked, preventing allocation.

Register reg7_inv_way Details

Field Name reserved way_bits Bits 31:8 7:0 Type waz rw Reset Value 0x0 0x0 reserved way bits: You can select multiple ways at the same time, by setting the Way bits to 1 Description

Register (L2Cpl310) reg7_clean_pa

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_clean_pa 0x000007B0 0xF8F027B0 32 bits mixed 0x00000000 Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged

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Register reg7_clean_pa Details

Field Name tag index reserved c Bits 31:12 11:5 4:1 0 Type rw rw waz rw Reset Value 0x0 0x0 0x0 0x0 tag index reserved C Flag When written must be 0. When read, indicates that a background operation is in progress Description

Register (L2Cpl310) reg7_clean_index

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_clean_index 0x000007B8 0xF8F027B8 32 bits mixed 0x00000000 Clean Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged

Register reg7_clean_index Details

Field Name reserved way reserved index reserved c Bits 31 30:28 27:12 11:5 4:1 0 Type waz rw waz rw waz rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 reserved way reserved index reserved c Description

Register (L2Cpl310) reg7_clean_way

Name Relative Address Absolute Address Width reg7_clean_way 0x000007BC 0xF8F027BC 32 bits

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Access Type Reset Value Description

mixed 0x00000000 Clean by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged. Completes as a background task with the way, or ways, locked, preventing allocation.

Register reg7_clean_way Details

Field Name reserved way_bits Bits 31:8 7:0 Type waz rw Reset Value 0x0 0x0 reserved way bits: You can select multiple ways at the same time, by setting the Way bits to 1 Description

Register (L2Cpl310) reg7_clean_inv_pa

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_clean_inv_pa 0x000007F0 0xF8F027F0 32 bits mixed 0x00000000 Clean and Invalidate Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid

Register reg7_clean_inv_pa Details

Field Name tag index reserved c Bits 31:12 11:5 4:1 0 Type rw rw waz rw Reset Value 0x0 0x0 0x0 0x0 tag index reserved C Flag When written must be 0. When read, indicates that a background operation is in progress Description

Register (L2Cpl310) reg7_clean_inv_index

Name reg7_clean_inv_index

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Relative Address Absolute Address Width Access Type Reset Value Description

0x000007F8 0xF8F027F8 32 bits mixed 0x00000000 Clean and Invalidate Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid

Register reg7_clean_inv_index Details

Field Name reserved way reserved index reserved c Bits 31 30:28 27:12 11:5 4:1 0 Type waz rw waz rw waz rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 reserved way reserved index reserved c Description

Register (L2Cpl310) reg7_clean_inv_way

Name Relative Address Absolute Address Width Access Type Reset Value Description reg7_clean_inv_way 0x000007FC 0xF8F027FC 32 bits mixed 0x00000000 Clean and Invalidate by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not valid. Completes as a background task with the way, or ways, locked, preventing allocation.

Register reg7_clean_inv_way Details

Field Name reserved way_bits Bits 31:8 7:0 Type waz rw Reset Value 0x0 0x0 reserved way bits: You can select multiple ways at the same time, by setting the Way bits to 1 Description

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Register (L2Cpl310) reg9_d_lockdown0

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown0 0x00000900 0xF8F02900 32 bits mixed 0x00000000 These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following meaning: 0 allocation can occur in the corresponding way. 1 there is no allocation in the corresponding way.

Register reg9_d_lockdown0 Details

Field Name reserved DATALOCK000 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 000 Description

Register (L2Cpl310) reg9_i_lockdown0

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown0 0x00000904 0xF8F02904 32 bits mixed 0x00000000 instruction lock down 0

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Register reg9_i_lockdown0 Details

Field Name reserved INSTRLOCK000 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 000 Description

Register (L2Cpl310) reg9_d_lockdown1

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown1 0x00000908 0xF8F02908 32 bits mixed 0x00000000 data lock down 1

Register reg9_d_lockdown1 Details

Field Name reserved DATALOCK001 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 001 Description

Register (L2Cpl310) reg9_i_lockdown1

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown1 0x0000090C 0xF8F0290C 32 bits mixed 0x00000000 instruction lock down 1

Register reg9_i_lockdown1 Details

Field Name reserved INSTRLOCK001 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 001 Description

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Register (L2Cpl310) reg9_d_lockdown2

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown2 0x00000910 0xF8F02910 32 bits mixed 0x00000000 data lock down 2

Register reg9_d_lockdown2 Details

Field Name reserved DATALOCK010 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 010 Description

Register (L2Cpl310) reg9_i_lockdown2

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown2 0x00000914 0xF8F02914 32 bits mixed 0x00000000 instruction lock down 2

Register reg9_i_lockdown2 Details

Field Name reserved INSTRLOCK010 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 010 Description

Register (L2Cpl310) reg9_d_lockdown3

Name Relative Address Absolute Address Width reg9_d_lockdown3 0x00000918 0xF8F02918 32 bits

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Access Type Reset Value Description

mixed 0x00000000 data lock down 3

Register reg9_d_lockdown3 Details

Field Name reserved DATALOCK011 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 011 Description

Register (L2Cpl310) reg9_i_lockdown3

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown3 0x0000091C 0xF8F0291C 32 bits mixed 0x00000000 instruction lock down 3

Register reg9_i_lockdown3 Details

Field Name reserved INSTRLOCK011 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 011 Description

Register (L2Cpl310) reg9_d_lockdown4

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown4 0x00000920 0xF8F02920 32 bits mixed 0x00000000 data lock down 4

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Register reg9_d_lockdown4 Details

Field Name reserved DATALOCK100 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 100 Description

Register (L2Cpl310) reg9_i_lockdown4

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown4 0x00000924 0xF8F02924 32 bits mixed 0x00000000 instruction lock down 4

Register reg9_i_lockdown4 Details

Field Name reserved INSTRLOCK100 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 100 Description

Register (L2Cpl310) reg9_d_lockdown5

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown5 0x00000928 0xF8F02928 32 bits mixed 0x00000000 data lock down 5

Register reg9_d_lockdown5 Details

Field Name reserved DATALOCK101 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 101 Description

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Register (L2Cpl310) reg9_i_lockdown5

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown5 0x0000092C 0xF8F0292C 32 bits mixed 0x00000000 instruction lock down 5

Register reg9_i_lockdown5 Details

Field Name reserved INSTRLOCK101 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 101 Description

Register (L2Cpl310) reg9_d_lockdown6

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown6 0x00000930 0xF8F02930 32 bits mixed 0x00000000 data lock down 6

Register reg9_d_lockdown6 Details

Field Name reserved DATALOCK110 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 110 Description

Register (L2Cpl310) reg9_i_lockdown6

Name Relative Address Absolute Address Width reg9_i_lockdown6 0x00000934 0xF8F02934 32 bits

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Access Type Reset Value Description

mixed 0x00000000 instruction lock down 6

Register reg9_i_lockdown6 Details

Field Name reserved INSTRLOCK110 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 110 Description

Register (L2Cpl310) reg9_d_lockdown7

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_d_lockdown7 0x00000938 0xF8F02938 32 bits mixed 0x00000000 data lock down 7

Register reg9_d_lockdown7 Details

Field Name reserved DATALOCK111 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 111 Description

Register (L2Cpl310) reg9_i_lockdown7

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_i_lockdown7 0x0000093C 0xF8F0293C 32 bits mixed 0x00000000 instruction lock down 7

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Register reg9_i_lockdown7 Details

Field Name reserved INSTRLOCK111 Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved Use when AR/WUSERSx[7:5] = 111 Description

Register (L2Cpl310) reg9_lock_line_en

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_lock_line_en 0x00000950 0xF8F02950 32 bits mixed 0x00000000 Lockdown by Line Enable Register.

Register reg9_lock_line_en Details

Field Name reserved lock_down_by_line_en able Bits 31:1 0 Type waz,r az rw Reset Value 0x0 0x0 reserved 0 = Lockdown by line disabled. This is the default. 1 = Lockdown by line enabled. Description

Register (L2Cpl310) reg9_unlock_way

Name Relative Address Absolute Address Width Access Type Reset Value Description reg9_unlock_way 0x00000954 0xF8F02954 32 bits mixed 0x00000000 Cache lockdown by way To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following meaning: 0 allocation can occur in the corresponding way. 1 there is no allocation in the corresponding way.

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Register reg9_unlock_way Details

Field Name reserved unlock_all_lines_by_w ay_operation Bits 31:16 15:0 Type waz,r az rw Reset Value 0x0 0x0 reserved For all bits: 0 = Unlock all lines disabled. This is the default. 1 = Unlock all lines operation in progress for the corresponding way. Description

Register (L2Cpl310) reg12_addr_filtering_start

Name Relative Address Absolute Address Width Access Type Reset Value Description reg12_addr_filtering_start 0x00000C00 0xF8F02C00 32 bits mixed 0x40000001 When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and <address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers.

Register reg12_addr_filtering_start Details

Field Name addr_filtering_start reserved addr_filtering_enable Bits 31:20 19:1 0 Type rw waz,r az rw Reset Value 0x400 0x0 0x1 Description Address filtering start address. reserved 0 = Address filtering disabled. 1 = Address filtering enabled

Register (L2Cpl310) reg12_addr_filtering_end

Name Relative Address Absolute Address Width Access Type reg12_addr_filtering_end 0x00000C04 0xF8F02C04 32 bits mixed

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Reset Value Description

0xFFF00000 When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and <address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers.

Register reg12_addr_filtering_end Details

Field Name addr_filtering_end reserved Bits 31:20 19:0 Type rw waz,r az Reset Value 0xFFF 0x0 Description Address filtering end address. reserved

Register (L2Cpl310) reg15_debug_ctrl

Name Relative Address Absolute Address Width Access Type Reset Value Description reg15_debug_ctrl 0x00000F40 0xF8F02F40 32 bits mixed 0x00000000 The Debug Control Register forces specific cache behavior required for debug. This register has read-only, non-secure, or read and write, secure, permission. Any secure access and non-secure access can read this register. Only a secure access can write to this register. If a non-secure access tries to write to this register the register issues a DECERR response and does not update.

Register reg15_debug_ctrl Details

Field Name reserved SPNIDEN Bits 31:3 2 Type waz,r az rw Reset Value 0x0 0x0 reserved Reads value of SPNIDEN input. Description

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Field Name DWB

Bits 1

Type rw

Reset Value 0x0

Description DWB: Disable write-back, force WT 0 = Enable write-back behavior. This is the default. 1 = Force write-through behavior DCL: Disable cache linefill 0 = Enable cache linefills. This is the default. 1 = Disable cache linefills.

DCL

rw

0x0

Register (L2Cpl310) reg15_prefetch_ctrl

Name Relative Address Absolute Address Width Access Type Reset Value Description reg15_prefetch_ctrl 0x00000F60 0xF8F02F60 32 bits mixed 0x00000000 Purpose Enables prefetch-related features that can improve system performance. Usage constraints This register has both read-only, non-secure, and read and write, secure, permissions. Any secure or non-secure access can read this register. Only a secure access can write to this register. If a non-secure access attempts to write to this register, the register

Register reg15_prefetch_ctrl Details

Field Name reserved double_linefill_en Bits 31 30 Type waz,r az rw Reset Value 0x0 0x0 reserved Double linefill enable: You can set the following options for this register bit: 0 The L2CC always issues 4x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default. 1 The L2CC issues 8x64-bit read bursts to L3 on reads that miss in the L2 cache. inst_pref_en 29 rw 0x0 Instruction prefetch enable: You can set the following options for this register bit: 0 Instruction prefetching disabled. This is the default. 1 Instruction prefetching enabled Description

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Field Name data_pref_en

Bits 28

Type rw

Reset Value 0x0

Description Data prefetch enable: You can set the following options for this register bit: 0 Data prefetching disabled. This is the default. 1 Data prefetching enabled.

double_linefill_on_wra pread_en

27

rw

0x0

Double linefill on WRAP read disable: You can set the following options for this register bit: 0 Double linefill on WRAP read enabled. This is the default. 1 Double linefill on WRAP read disabled

reserved pref_drop_en

26:25 24

waz,r az rw

0x0 0x0

reserved Prefetch drop enable: You can set the following options for this register bit: 0 The L2CC does not discard prefetch reads issued to L3. This is the default. 1 The L2CC discards prefetch reads issued to L3 when there is a resource conflict with explicit reads.

incr_double_linefill_en

23

rw

0x0

Incr double Linefill enable: You can set the following options for this register bit: 0 The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default. 1 The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache.

reserved

22

waz,r az rw

0x0 0x0

reserved Not same ID on exclusive sequence enable: You can set the following options for this register bit: 0 Read and write portions of a non-cacheable exclusive sequence have the same AXI ID when issued to L3. This is the default. 1 Read and write portions of a non-cacheable exclusive sequence do not have the same AXI ID when issued to L3.

not_same_id_on_excl_s 21 eq_en

reserved prefetch_offset

20:5 4:0

waz,r az rw

0x0 0x0

reserved Default = b00000.

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Register (L2Cpl310) reg15_power_ctrl

Name Relative Address Absolute Address Width Access Type Reset Value Description reg15_power_ctrl 0x00000F80 0xF8F02F80 32 bits mixed 0x00000000 Purpose Controls the operating mode clock and power modes. Usage constraints There are no usage constraints.

Register reg15_power_ctrl Details

Field Name reserved dynamic_clk_gating_e n Bits 31:2 1 Type waz,r az rw Reset Value 0x0 0x0 reserved Dynamic clock gating enable. 1 = Enabled. 0 = Masked. This is the default. standby_mode_en 0 rw 0x0 Standby mode enable. 1 = Enabled. 0 = Masked. This is the default Description

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B.24 Application Processing Unit (mpcore)

Module Name Software Name Base Address Description Vendor Info Application Processing Unit (mpcore) XSCU 0xF8F00000 mpcore Mpcore - SCU, Interrupt controller, Counters and Timers ARM

Register Summary
Register Name Address Width 32 32 32 32 Type rw ro rw rw Reset Value 0x00000002 0x00000501 0x00000000 0x00000000 Description SCU Control Register SCU Configuration Register SCU CPU Power Status Register SCU Invalidate All Registers in Secure State 0x00000040 0x00000044 0x00000050 32 32 32 32 rw rw rw ro 0x00100000 0x00000000 0x0000000F 0x00000000 Filtering Start Address Register Defined by FILTEREND input SCU Access Control (SAC) Register SCU Non-secure Access Control Register SNSAC ICCICR ICCPMR ICCBPR ICCIAR ICCEOIR ICCRPR ICCHPIR ICCABPR 0x00000100 0x00000104 0x00000108 0x0000010C 0x00000110 0x00000114 0x00000118 0x0000011C 32 32 32 32 32 32 32 32 rw rw rw rw rw rw rw rw 0x00000000 0x00000000 0x00000002 0x000003FF 0x00000000 0x000000FF 0x000003FF 0x00000003 CPU Interface Control Register Interrupt Priority Mask Register Binary Point Register Interrupt Acknowledge Register End Of Interrupt Register Running Priority Register Highest Pending Interrupt Register Aliased Non-secure Binary Point Register

SCU_CONTROL_REGI 0x00000000 STER SCU_CONFIGURATIO N_REGISTER SCU_CPU_Power_Stat us_Register SCU_Invalidate_All_R egisters_in_Secure_Stat e Filtering_Start_Addres s_Register Filtering_End_Address _Register SCU_Access_Control_ Register_SAC 0x00000004 0x00000008 0x0000000C

SCU_Non_secure_Acce 0x00000054 ss_Control_Register

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Register Name ICCIDR Global_Timer_Counter _Register0 Global_Timer_Counter _Register1

Address 0x000001FC 0x00000200 0x00000204

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro ro

Reset Value 0x3901243B 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000C22 0x0102043B

Description CPU Interface Implementer Identification Register Global Timer Counter Register 0 Global Timer Counter Register 1 Global Timer Control Register Global Timer Interrupt Status Register Comparator Value Register_0 Comparator Value Register_1 Auto-increment Register Private Timer Load Register Private Timer Counter Register Private Timer Control Register Private Timer Interrupt Status Register Watchdog Load Register Watchdog Counter Register Watchdog Control Register Watchdog Interrupt Status Register Watchdog Reset Status Register Watchdog Disable Register Distributor Control Register Interrupt Controller Type Register Distributor Implementer Identification Register

Global_Timer_Control_ 0x00000208 Register Global_Timer_Interrup t_Status_Register Comparator_Value_Re gister0 Comparator_Value_Re gister1 Auto_increment_Regis ter Private_Timer_Load_R egister 0x0000020C 0x00000210 0x00000214 0x00000218 0x00000600

Private_Timer_Counter 0x00000604 _Register Private_Timer_Control _Register Private_Timer_Interru pt_Status_Register Watchdog_Load_Regis ter Watchdog_Counter_Re gister Watchdog_Control_Re gister Watchdog_Interrupt_St atus_Register Watchdog_Reset_Statu s_Register Watchdog_Disable_Re gister ICDDCR ICDICTR ICDIIDR 0x00000608 0x0000060C 0x00000620 0x00000624 0x00000628 0x0000062C 0x00000630 0x00000634 0x00001000 0x00001004 0x00001008

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Register Name ICDISR0 ICDISR1 ICDISR2 ICDISER0 ICDISER1 ICDISER2 ICDICER0 ICDICER1 ICDICER2 ICDISPR0 ICDISPR1 ICDISPR2 ICDICPR0 ICDICPR1 ICDICPR2 ICDABR0 ICDABR1 ICDABR2 ICDIPR0 ICDIPR1 ICDIPR2 ICDIPR3 ICDIPR4 ICDIPR5 ICDIPR6 ICDIPR7 ICDIPR8 ICDIPR9

Address 0x00001080 0x00001084 0x00001088 0x00001100 0x00001104 0x00001108 0x00001180 0x00001184 0x00001188 0x00001200 0x00001204 0x00001208 0x00001280 0x00001284 0x00001288 0x00001300 0x00001304 0x00001308 0x00001400 0x00001404 0x00001408 0x0000140C 0x00001410 0x00001414 0x00001418 0x0000141C 0x00001420 0x00001424

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 0x0000FFFF 0x00000000 0x00000000 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description Interrupt Security Register_0 Interrupt Security Register_1 Interrupt Security Register_2 Interrupt Set-enable Register 0 Interrupt Set-enable Register 1 Interrupt Set-enable Register 2 Interrupt Clear-Enable Register 0 Interrupt Clear-Enable Register 1 Interrupt Clear-Enable Register 2 Interrupt Set-pending Register_0 Interrupt Set-pending Register_1 Interrupt Set-pending Register_2 Interrupt Clear-Pending Register_0 Interrupt Clear-Pending Register_1 Interrupt Clear-Pending Register_2 Active Bit register_0 Active Bit register_1 Active Bit register_2 Interrupt Priority Register_0 Interrupt Priority Register_1 Interrupt Priority Register_2 Interrupt Priority Register_3 Interrupt Priority Register_4 Interrupt Priority Register_5 Interrupt Priority Register_6 Interrupt Priority Register_7 Interrupt Priority Register_8 Interrupt Priority Register_9

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Appendix B: Register Details

Register Name ICDIPR10 ICDIPR11 ICDIPR12 ICDIPR13 ICDIPR14 ICDIPR15 ICDIPR16 ICDIPR17 ICDIPR18 ICDIPR19 ICDIPR20 ICDIPR21 ICDIPR22 ICDIPR23 ICDIPTR0 ICDIPTR1 ICDIPTR2 ICDIPTR3 ICDIPTR4 ICDIPTR5 ICDIPTR6 ICDIPTR7 ICDIPTR8 ICDIPTR9 ICDIPTR10 ICDIPTR11

Address 0x00001428 0x0000142C 0x00001430 0x00001434 0x00001438 0x0000143C 0x00001440 0x00001444 0x00001448 0x0000144C 0x00001450 0x00001454 0x00001458 0x0000145C 0x00001800 0x00001804 0x00001808 0x0000180C 0x00001810 0x00001814 0x00001818 0x0000181C 0x00001820 0x00001824 0x00001828 0x0000182C

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101

Description Interrupt Priority Register_10 Interrupt Priority Register_11 Interrupt Priority Register_12 Interrupt Priority Register_13 Interrupt Priority Register_14 Interrupt Priority Register_15 Interrupt Priority Register_16 Interrupt Priority Register_17 Interrupt Priority Register_18 Interrupt Priority Register_19 Interrupt Priority Register_20 Interrupt Priority Register_21 Interrupt Priority Register_22 Interrupt Priority Register_23 Interrupt Processor Targets Register_0 Interrupt Processor Targets Register_1 Interrupt Processor Targets Register_2 Interrupt Processor Targets Register_3 Interrupt Processor Targets Register_4 Interrupt Processor Targets Register_5 Interrupt Processor Targets Register_6 Interrupt Processor Targets Register_7 Interrupt Processor Targets Register_8 Interrupt Processor Targets Register_9 Interrupt Processor Targets Register_10 Interrupt Processor Targets Register_11

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Register Name ICDIPTR12 ICDIPTR13 ICDIPTR14 ICDIPTR15 ICDIPTR16 ICDIPTR17 ICDIPTR18 ICDIPTR19 ICDIPTR20 ICDIPTR21 ICDIPTR22 ICDIPTR23 ICDICFR0 ICDICFR1 ICDICFR2 ICDICFR3 ICDICFR4 ICDICFR5 ppi_status spi_status_0 spi_status_1 ICDSGIR

Address 0x00001830 0x00001834 0x00001838 0x0000183C 0x00001840 0x00001844 0x00001848 0x0000184C 0x00001850 0x00001854 0x00001858 0x0000185C 0x00001C00 0x00001C04 0x00001C08 0x00001C0C 0x00001C10 0x00001C14 0x00001D00 0x00001D04 0x00001D08 0x00001F00

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro ro ro rw

Reset Value 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0x01010101 0xAAAAAAA A 0x7DC00000 0x55555555 0x55555555 0x55555555 0x55555555 0x00000000 0x00000000 0x00000000 0x00000000

Description Interrupt Processor Targets Register_12 Interrupt Processor Targets Register_13 Interrupt Processor Targets Register_14 Interrupt Processor Targets Register_15 Interrupt Processor Targets Register_16 Interrupt Processor Targets Register_17 Interrupt Processor Targets Register_18 Interrupt Processor Targets Register_19 Interrupt Processor Targets Register_20 Interrupt Processor Targets Register_21 Interrupt Processor Targets Register_22 Interrupt Processor Targets Register_23 Interrupt Configuration Register 0 Interrupt Configuration Register 1 Interrupt Configuration Register 2 Interrupt Configuration Register 3 Interrupt Configuration Register 4 Interrupt Configuration Register 5 PPI Status Register SPI Status Register 0 SPI Status Register 1 Software Generated Interrupt Register

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Register Name ICPIDR4 ICPIDR5 ICPIDR6 ICPIDR7 ICPIDR0 ICPIDR1 ICPIDR2 ICPIDR3 ICCIDR0 ICCIDR1 ICCIDR2 ICCIDR3

Address 0x00001FD0 0x00001FD4 0x00001FD8 0x00001FDC 0x00001FE0 0x00001FE4 0x00001FE8 0x00001FEC 0x00001FF0 0x00001FF4 0x00001FF8 0x00001FFC

Width 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000004 0x00000000 0x00000000 0x00000000 0x00000090 0x000000B3 0x0000001B 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1

Description Peripheral ID4 Peripheral ID5 Peripheral ID6 Peripheral ID7 Peripheral ID0 Peripheral ID1 Peripheral ID2 Peripheral ID3 Component ID0 Component ID1 Component ID2 Component ID3

Register (mpcore) SCU_CONTROL_REGISTER

Name Relative Address Absolute Address Width Access Type Reset Value Description SCU_CONTROL_REGISTER 0x00000000 0xF8F00000 32 bits rw 0x00000002 SCU Control Register

Register SCU_CONTROL_REGISTER Details

Field Name reserved IC_standby_enable Bits 31:7 6 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is always zero. When set, this stops the Interrupt Controller clock when no interrupts are pending, and no CPU is performing a read/write request.

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Field Name SCU_standby_enable

Bits 5

Type rw

Reset Value 0x0

Description When set, SCU CLK is turned off when all processors are in WFI mode, there is no pending request on the ACP (if implemented), and there is no remaining activity in the SCU. When SCU CLK is off, ARREADYS, AWREADYS and WREADYS on the ACP are forced LOW. The clock is turned on when any processor leaves WFI mode, or if there is a new request on the ACP.

Force_all_Device_to_p ort0_enable

rw

0x0

When set, all requests from the ACP or processors with AxCACHE = NonCacheable Bufferable are forced to be issued on the AXI Master port M0.

SCU_Speculative_linefi lls_enable

rw

0x0

When set, coherent linefill requests are sent speculatively to the L2C-310 in parallel with the tag look-up. If the tag look-up misses, the confirmed linefill is sent to the L2C-310 and gets RDATA earlier because the data request was already initiated by the speculative request. This feature works only if the L2C-310 is present in the design.

SCU_RAMs_Parity_en able

rw

0x0

1 = Parity on. 0 = Parity off. This is the default setting. This bit is always zero if support for parity is not implemented.

Address_filtering_enab le

rw

0x1

1 = Addressing filtering on. 0 = Addressing filtering off. The default value is the value of FILTEREN sampled when nSCURESET is deasserted. This bit is always zero if the SCU is implemented in the single master port configuration.

SCU_enable

rw

0x0

1 = SCU enable. 0 = SCU disable. This is the default setting

Register (mpcore) SCU_CONFIGURATION_REGISTER

Name SCU_CONFIGURATION_REGISTER

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000004 0xF8F00004 32 bits ro 0x00000501 SCU Configuration Register

Register SCU_CONFIGURATION_REGISTER Details

Field Name reserved Tag_RAM_sizes Bits 31:16 15:8 Type ro ro Reset Value 0x0 0x5 Description Should Be Zero (SBZ) Bits [15:14] indicate Cortex-A9 processor CPU3 tag RAM size if present. Bits [13:12] indicate Cortex-A9 processor CPU2 tag RAM size if present. Bits [11:10] indicate Cortex-A9 processor CPU1 tag RAM size if present. Bits [9:8] indicate Cortex-A9 processor CPU0 tag RAM size. The encoding is as follows: b11 = reserved b10 = 64KB cache, 256 indexes per tag RAM b01 = 32KB cache, 128 indexes per tag RAM b00 = 16KB cache, 64 indexes per tag RAM. CPUs_SMP 7:4 ro 0x0 Shows the Cortex-A9 processors that are in Symmetric Multi-processing (SMP) or Asymmetric Multi-processing (AMP) mode. 0 = this Cortex-A9 processor is in AMP mode not taking part in coherency or not present. 1 = this Cortex-A9 processor is in SMP mode taking part in coherency. Bit 7 is for CPU3 Bit 6 is for CPU2 Bit 5 is for CPU1 Bit 4 is for CPU0. reserved CPU_number 3:2 1:0 ro ro 0x0 0x1 Should Be Zero (SBZ) Number of CPUs present in the Cortex-A9 MPCore processor b11 = four Cortex-A9 processors, CPU0, CPU1, CPU2, and CPU3 b10 = three Cortex-A9 processors, CPU0, CPU1, and CPU2 b01 = two Cortex-A9 processors, CPU0 and CPU1 b00 = one Cortex-A9 processor, CPU0.

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Register (mpcore) SCU_CPU_Power_Status_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description SCU_CPU_Power_Status_Register 0x00000008 0xF8F00008 32 bits rw 0x00000000 SCU CPU Power Status Register

Register SCU_CPU_Power_Status_Register Details

Field Name reserved CPU3_status Bits 31:26 25:24 Type rw rw Reset Value 0x0 0x0 Description Should Be Zero (SBZ) Power status of the Cortex-A9 processor: b00: Normal mode. b01: Reserved. b10: the Cortex-A9 processor is about to enter (or is in) dormant mode. No coherency request is sent to the Cortex-A9 processor. b11: the Cortex-A9 processor is about to enter (or is in) powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor. reserved CPU2_status reserved CPU1_status reserved CPU0_status 23:18 17:16 15:10 9:8 7:2 1:0 rw rw rw rw rw rw 0x0 0x0 0x0 0x0 0x0 0x0 Should Be Zero (SBZ) Power status of the Cortex-A9 processor Should Be Zero (SBZ) Power status of the Cortex-A9 processor Should Be Zero (SBZ) Power status of the Cortex-A9 processor

Register (mpcore) SCU_Invalidate_All_Registers_in_Secure_State

Name Relative Address Absolute Address Width Access Type Reset Value SCU_Invalidate_All_Registers_in_Secure_State 0x0000000C 0xF8F0000C 32 bits rw 0x00000000

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Description

SCU Invalidate All Registers in Secure State

Register SCU_Invalidate_All_Registers_in_Secure_State Details

Field Name NA CPU3_ways Bits 31:16 15:12 Type rw rw Reset Value 0x0 0x0 NA Specifies the ways that must be invalidated for CPU3. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than four processors. CPU2_ways 11:8 rw 0x0 Specifies the ways that must be invalidated for CPU2. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than three processors CPU1_ways 7:4 rw 0x0 Specifies the ways that must be invalidated for CPU1. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than two processors. CPU0_ways 3:0 rw 0x0 Specifies the ways that must be invalidated for CPU0 Description

Register (mpcore) Filtering_Start_Address_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description Filtering_Start_Address_Register 0x00000040 0xF8F00040 32 bits rw 0x00100000 Filtering Start Address Register

Register Filtering_Start_Address_Register Details

Field Name Filtering_start_address Bits 31:20 Type rw Reset Value 0x1 Description Start address for use with master port 1 in a two-master port configuration when address filtering is enabled. The default value is the value of FILTERSTART sampled on exit from reset. The value on the pin gives the upper address bits with 1MB granularity. SBZ 19:0 rw 0x0 SBZ

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Register (mpcore) Filtering_End_Address_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description Filtering_End_Address_Register 0x00000044 0xF8F00044 32 bits rw 0x00000000 Defined by FILTEREND input

Register Filtering_End_Address_Register Details

Field Name Filtering_end_address Bits 31:20 Type rw Reset Value 0x0 Description End address for use with master port 1 in a two-master port configuration, when address filtering is enabled. The default value is the value of FILTEREND sampled on exit from reset. The value on the pin gives the upper address bits with 1MB granularity. SBZ 19:0 rw 0x0 SBZ

Register (mpcore) SCU_Access_Control_Register_SAC

Name Relative Address Absolute Address Width Access Type Reset Value Description SCU_Access_Control_Register_SAC 0x00000050 0xF8F00050 32 bits rw 0x0000000F SCU Access Control (SAC) Register

Register SCU_Access_Control_Register_SAC Details

Field Name Bits 31:4 CPU3 3 Type rw rw Reset Value 0x0 0x1 SBZ 0 = CPU3 cannot access the components. 1 = CPU3 can access the components. This is the default. Description

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Field Name CPU2

Bits 2

Type rw

Reset Value 0x1

Description 0 = CPU2 cannot access the components. 1 = CPU2 can access the components. This is the default.

CPU1

rw

0x1

0 = CPU1 cannot access the components. 1 = CPU1 can access the components. This is the default.

CPU0

rw

0x1

0 = CPU0 cannot access the components. 1 = CPU0 can access the components. This is the default.

Register (mpcore) SCU_Non_secure_Access_Control_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description SCU_Non_secure_Access_Control_Register 0x00000054 0xF8F00054 32 bits ro 0x00000000 SCU Non-secure Access Control Register SNSAC

Register SCU_Non_secure_Access_Control_Register Details

Field Name SBZ CPU3_global_timer CPU2_global_timer CPU1_global_timer CPU0_global_timer Bits 31:12 11 10 9 8 Type ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 SBZ same as above same as above same as above Non-secure access to the global timer for CPU<n>. * <n> is 3 for bit[11] * <n> is 2 for bit[10] * <n> is 1 for bit[9] * <n> is 0 for bit[8]. 0 = Secure accesses only. This is the default value. 1 = Secure accesses and Non-Secure accesses. Private_timers_for_CP U3 Private_timers_for_CP U2 7 6 ro ro 0x0 0x0 same as above same as above Description

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Field Name Private_timers_for_CP U1 Private_timers_for_CP U0

Bits 5 4

Type ro ro

Reset Value 0x0 0x0 same as above

Description

Non-secure access to the private timer and watchdog for CPU<n>. * <n> is 3 for bit[7] * <n> is 2 for bit[6]] * <n> is 1 for bit[5] * <n> is 0 for bit[4]. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses.

Component_access_for _CPU3 Component_access_for _CPU2 Component_access_for _CPU1 Component_access_for _CPU0

3 2 1 0

ro ro ro ro

0x0 0x0 0x0 0x0

same as above same as above same as above Non-secure access to the components for CPU<n>. * <n> is 3 for bit[3] * <n> is 2 for bit[2]] * <n> is 1 for bit[1] * <n> is 0 for bit[0]. 0 = CPU cannot write the components 1 = CPU can access the components.

Register (mpcore) ICCICR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCICR GIC_CONTROL 0x00000100 0xF8F00100 32 bits rw 0x00000000 CPU Interface Control Register

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Register ICCICR Details

Field Name reserved SBPR (GIC_CNTR_SBPR) Bits 31:5 4 Type rw rw Reset Value 0x0 0x0 reserved Controls whether the CPU interface uses the Secure or Non-secure Binary Point Register for preemption. 0: use the Secure Binary Point Register for Secure interrupts, and use the Non-secure Binary Point Register for Non-secure interrupts. 1: use the Secure Binary Point Register for both Secure and Non-secure interrupts. FIQEn (GIC_CNTR_FIQEN) 3 rw 0x0 Controls whether the GIC signals Secure interrupts to a target processor using the FIQ or the IRQ signal. 0: using IRQ, 1: using FIQ. The GIC always signals Non-secure interrupts using IRQ. AckCtl (GIC_CNTR_ACKCTL ) EnableNS (GIC_CNTR_EN_NS) 1 rw 0x0 2 rw 0x0 Controls whether a Secure read of the ICCIAR, when the highest priority pending interrupt is Non-secure, causes the CPU interface to acknowledge the interrupt. An alias of the Enable bit in the Non-secure ICCICR. This alias bit means Secure software can enable the signal of Non-secure interrupts. EnableS (GIC_CNTR_EN_S) 0 rw 0x0 Global enable for the signaling of Secure interrupts by the CPU interfaces to the connected processors. Description

Register (mpcore) ICCPMR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCPMR GIC_CPU_PRIOR 0x00000104 0xF8F00104 32 bits rw 0x00000000 Interrupt Priority Mask Register

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Register ICCPMR Details

Field Name reserved Priority (GIC_PRIORITY) Bits 31:8 7:0 Type rw rw Reset Value 0x0 0x0 reserved The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor. Description

Register (mpcore) ICCBPR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCBPR GIC_BIN_PT 0x00000108 0xF8F00108 32 bits rw 0x00000002 Binary Point Register

Register ICCBPR Details

Field Name reserved (GIC_CPUID) Binary_point (MASK) 2:0 rw 0x2 The value of this field controls the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field. Bits 31:3 Type rw Reset Value 0x0 reserved Description

Register (mpcore) ICCIAR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIAR GIC_INT_ACK 0x0000010C 0xF8F0010C 32 bits rw 0x000003FF Interrupt Acknowledge Register

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Register ICCIAR Details

Field Name reserved CPUID Bits 31:13 12:10 Type rw rw Reset Value 0x0 0x0 reserved Identifies the processor that requested the interrupt. Returns the number of the CPU interface that made the request. ACKINTID (GIC_ACK_INTID) 9:0 rw 0x3FF The interrupt ID. This read acts as an acknowledge for the interrupt. Description

Register (mpcore) ICCEOIR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCEOIR GIC_EOI 0x00000110 0xF8F00110 32 bits rw 0x00000000 End Of Interrupt Register

Register ICCEOIR Details

Field Name reserved CPUID Bits 31:13 12:10 Type rw rw Reset Value 0x0 0x0 reserved On completion of the processing of an SGI, this field contains the CPUID value from the corresponding ICCIAR access. The ACKINTID value from the corresponding ICCIAR access. Description

EOIINTID (INTID)

9:0

rw

0x0

Register (mpcore) ICCRPR

Name Software Name Relative Address Absolute Address Width ICCRPR GIC_RUN_PRIOR 0x00000114 0xF8F00114 32 bits

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Access Type Reset Value Description

rw 0x000000FF Running Priority Register

Register ICCRPR Details

Field Name reserved Priority (GIC_RUN_PRIORITY ) Bits 31:8 7:0 Type rw rw Reset Value 0x0 0xFF reserved The priority value of the highest priority interrupt that is active on the CPU interface. Description

Register (mpcore) ICCHPIR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCHPIR GIC_HI_PEND 0x00000118 0xF8F00118 32 bits rw 0x000003FF Highest Pending Interrupt Register

Register ICCHPIR Details

Field Name reserved CPUID (GIC_CPUID) Bits 31:13 12:10 Type rw rw Reset Value 0x0 0x0 reserved If the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. The identifies the processor that generated the interrupt. PENDINTID (GIC_PEND_INTID) 9:0 rw 0x3FF The interrupt ID of the highest priority pending interrupt. Description

Register (mpcore) ICCABPR

Name Software Name Relative Address ICCABPR GIC_ALIAS_BIN_PT 0x0000011C

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Absolute Address Width Access Type Reset Value Description

0xF8F0011C 32 bits rw 0x00000003 Aliased Non-secure Binary Point Register

Register ICCABPR Details

Field Name reserved Binary_point Bits 31:3 2:0 Type rw rw Reset Value 0x0 0x3 reserved Provides an alias of the Non-secure ICCBPR. Description

Register (mpcore) ICCIDR

Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIDR 0x000001FC 0xF8F001FC 32 bits ro 0x3901243B CPU Interface Implementer Identification Register

Register ICCIDR Details

Field Name Part_number Architecture_version Revision_number Bits 31:20 19:16 15:12 Type ro ro ro Reset Value 0x390 0x1 0x2 Description Identifies the peripheral Identifies the architecture version Returns the revision number of the Interrupt Controller. The implementer defines the format of this field. Implementer 11:0 ro 0x43B Returns the JEP106 code of the company that implemented the Cortex-A9 processor interface RTL. It uses the following construct: [11:8] the JEP106 continuation code of the implementer [7] 0 [6:0] the JEP106 code [6:0] of the implementer

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Register (mpcore) Global_Timer_Counter_Register0

Name Relative Address Absolute Address Width Access Type Reset Value Description Global_Timer_Counter_Register0 0x00000200 0xF8F00200 32 bits rw 0x00000000 Global Timer Counter Register 0

Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name Global_Timer_Counter _Register0 Global_Timer_Counter _Register1 Address 0xf8f00200 0xf8f00204

Register Global_Timer_Counter_Register0 to Global_Timer_Counter_Register1 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and the upper 32-bit timer counter at offset 0x04. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. To modify the register proceed as follows: 1. Clear the timer enable bit in the Global Timer Control Register 2. Write the lower 32-bit timer counter register 3. Write the upper 32-bit timer counter register 4. Set the timer enable bit. To get the value from the Global Timer Counter register proceed as follows: 1. Read the upper 32-bit timer counter register 2. Read the lower 32-bit timer counter register 3. Read the upper 32-bit timer counter register again. If the value is different to the 32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer counter value is correct.

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Register (mpcore) Global_Timer_Control_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description Global_Timer_Control_Register 0x00000208 0xF8F00208 32 bits rw 0x00000000 Global Timer Control Register

Register Global_Timer_Control_Register Details

Field Name reserved Prescaler Bits 31:16 15:8 Type rw rw Reset Value 0x0 0x0 Reserved The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals on page 4-2 for the equation reserved 7:4 3 rw rw 0x0 0x0 Reserved This bit is banked per Cortex-A9 processor. 1'b0: single shot mode. When the counter reaches the comparator value, sets the event flag. It is the responsibility of software to update the comparator value to get further events. 1'b1: auto increment mode. Each time the counter reaches the comparator value, the comparator register is incremented with the auto-increment register, so that further events can be set periodically without any software updates. IRQ_Enable 2 rw 0x0 This bit is banked per Cortex-A9 processor. If set, the interrupt ID 27 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. Description

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Field Name Comp_Enablea

Bits 1

Type rw

Reset Value 0x0

Description This bit is banked per Cortex-A9 processor. If set, it allows the comparison between the 64-bit Timer Counter and the related 64-bit Comparator Register.

Timer_Enable

rw

0x0

Timer enable 1'b0 = Timer is disabled and the counter does not increment. All registers can still be read and written 1'b1 = Timer is enabled and the counter increments normally

Register (mpcore) Global_Timer_Interrupt_Status_Register

Name Relative Address Absolute Address Width Access Type Reset Value Description Global_Timer_Interrupt_Status_Register 0x0000020C 0xF8F0020C 32 bits rw 0x00000000 Global Timer Interrupt Status Register

Register Global_Timer_Interrupt_Status_Register Details

Field Name reserved Event_flag Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 UNK/SBZP This is a banked register for all Cortex-A9 processors present. The event flag is a sticky bit that is automatically set when the Counter Register reaches the Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. Figure 4-7 shows the Global Timer Interrupt Status Register bit assignment. Description

Register (mpcore) Comparator_Value_Register0

Name Relative Address Comparator_Value_Register0 0x00000210

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Absolute Address Width Access Type Reset Value Description

0xF8F00210 32 bits rw 0x00000000 Comparator Value Register_0

Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name Comparator_Value_Re gister0 Comparator_Value_Re gister1 Address 0xf8f00210 0xf8f00214

Register Comparator_Value_Register0 to Comparator_Value_Register1 Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10 and the upper 32-bit comparator value register at offset 0x14. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There is a Comparator Value Register for each Cortex-A9 processor. To ensure that updates to this register do not set the Interrupt Status Register proceed as follows: 1. Clear the Comp Enable bit in the Timer Control Register. 2. Write the lower 32-bit Comparator Value Register. 3. Write the upper 32-bit Comparator Value Register. 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.

Register (mpcore) Auto_increment_Register

Name Relative Address Absolute Address Width Auto_increment_Register 0x00000218 0xF8F00218 32 bits

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Access Type Reset Value Description

rw 0x00000000 Auto-increment Register

Register Auto_increment_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Auto-increment Register This 32-bit register gives the increment value of the Comparator Register when the Auto-increment bit is set in the Timer Control Register. Each Cortex-A9 processor present has its own Auto-increment Register If the comp enable and auto-increment bits are set when the global counter reaches the Comparator Register value, the comparator is incremented by the auto-increment value, so that a new event can be set periodically. The global timer is not affected and goes on incrementing

Register (mpcore) Private_Timer_Load_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Private_Timer_Load_Register TIMER_LOAD 0x00000600 0xF8F00600 32 bits rw 0x00000000 Private Timer Load Register

Register Private_Timer_Load_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register.

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Register (mpcore) Private_Timer_Counter_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Private_Timer_Counter_Register TIMER_COUNTER 0x00000604 0xF8F00604 32 bits rw 0x00000000 Private Timer Counter Register

Register Private_Timer_Counter_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description The Timer Counter Register is a decrementing counter. The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register. If a Cortex-A9 processor timer is in debug state, the counter only decrements when the Cortex-A9 processor returns to non debug state. When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops. When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register. Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.

Register (mpcore) Private_Timer_Control_Register

Name Software Name Private_Timer_Control_Register TIMER_CONTROL

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000608 0xF8F00608 32 bits rw 0x00000000 Private Timer Control Register

Register Private_Timer_Control_Register Details

Field Name SBZP Prescaler (PRESCALER) Bits 31:16 15:8 Type rw rw Reset Value 0x0 0x0 UNK/SBZP. The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals on page 4-2 for the equation.\ UNK_SBZP IRQ_Enable (IRQ_ENABLE) Auto_reload (AUTO_RELOAD) 1 rw 0x0 7:3 2 rw rw 0x0 0x0 UNK/SBZP. If set, the interrupt ID 29 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. 1'b0 = Single shot mode. Counter decrements down to zero, sets the event flag and stops. 1'b1 = Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. Timer_Enable (ENABLE) 0 rw 0x0 Timer enable 1'b0 = Timer is disabled and the counter does not decrement. All registers can still be read and written 1'b1 = Timer is enabled and the counter decrements normally Description

Register (mpcore) Private_Timer_Interrupt_Status_Register

Name Software Name Relative Address Absolute Address Width Access Type Private_Timer_Interrupt_Status_Register TIMER_ISR 0x0000060C 0xF8F0060C 32 bits rw

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Reset Value Description

0x00000000 Private Timer Interrupt Status Register

Register Private_Timer_Interrupt_Status_Register Details

Field Name UNK_SBZP Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 UNK/SBZP This is a banked register for all Cortex-A9 processors present. The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. Description

Register (mpcore) Watchdog_Load_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Watchdog_Load_Register WDT_LOAD 0x00000620 0xF8F00620 32 bits rw 0x00000000 Watchdog Load Register

Register Watchdog_Load_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Watchdog Load Register The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register

Register (mpcore) Watchdog_Counter_Register

Name Watchdog_Counter_Register

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

WDT_COUNTER 0x00000624 0xF8F00624 32 bits rw 0x00000000 Watchdog Counter Register

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Register Watchdog_Counter_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Watchdog Counter Register The Watchdog Counter Register is a down counter. It decrements if the Watchdog is enabled using the Watchdog enable bit in the Watchdog Control Register. If the Cortex-A9 processor associated with the Watchdog is in debug state, the counter does not decrement until the Cortex-A9 processor returns to non debug state. When the Watchdog Counter Register reaches zero and auto reload mode is enabled, and in timer mode, it reloads the value in the Watchdog Load Register and then decrements from that value. If auto reload mode is not enabled or the watchdog is not in timer mode, the Watchdog Counter Register decrements down to zero and stops. When in watchdog mode the only way to update the Watchdog Counter Register is to write to the Watchdog Load Register. When in timer mode the Watchdog Counter Register is write accessible. The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode: Timer mode When the Watchdog Counter Register reaches zero, the watchdog interrupt status event flag is set and the interrupt ID 30 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Watchdog Control Register. Watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed, the Watchdog Counter Register reaches zero, the Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted. The external reset source is then responsible for resetting all or part of the Cortex-A9 MPCore design.

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Register (mpcore) Watchdog_Control_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Watchdog_Control_Register WDT_CONTROL 0x00000628 0xF8F00628 32 bits rw 0x00000000 Watchdog Control Register

Register Watchdog_Control_Register Details

Field Name reserved Prescaler (PRESCALER) 7:4 Watchdog_mode (WD_MODE) 3 rw rw 0x0 0x0 Bits 31:16 15:8 Type rw rw Reset Value 0x0 0x0 Reserved. The prescaler modifies the clock period for the decrementing event for the Counter Register. Reserved. 1'b0 = Timer mode, default Writing a zero to this bit has no effect. You must use the Watchdog Disable Register to put the watchdog into timer mode. See Watchdog Disable Register on page 4-9. 1'b1 = Watchdog mode. IT_Enable (IT_ENABLE) 2 rw 0x0 If set, the interrupt ID 30 is set as pending in the Interrupt Distributor when the event flag is set in the watchdog Status Register. In watchdog mode this bit is ignored Auto_reload (AUTO_RELOAD) 1 rw 0x0 1'b0 = Single shot mode. Counter decrements down to zero, sets the event flag and stops. 1'b1 = Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Load Register and then continues decrementing. Watchdog_Enable (WD_ENABLE) 0 rw 0x0 Global watchdog enable 1'b0 = Watchdog is disabled and the counter does not decrement. All registers can still be read and /or written 1'b1 = Watchdog is enabled and the counter decrements normally. Description

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Register (mpcore) Watchdog_Interrupt_Status_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Watchdog_Interrupt_Status_Register WDT_ISR 0x0000062C 0xF8F0062C 32 bits rw 0x00000000 Watchdog Interrupt Status Register

Register Watchdog_Interrupt_Status_Register Details

Field Name reserved Event_flag (EVENT_FLAG) Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Reserved The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. If the watchdog interrupt is enabled, Interrupt ID 30 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written with a value of 1. Trying to write a zero to the event flag or a one when it is not set has no effect. Description

Register (mpcore) Watchdog_Reset_Status_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Watchdog_Reset_Status_Register WDT_RST_STS 0x00000630 0xF8F00630 32 bits rw 0x00000000 Watchdog Reset Status Register

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Register Watchdog_Reset_Status_Register Details

Field Name reserved Reset_flag (RESET_FLAG) Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is always zero. The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) The reset flag is cleared when written with a value of 1. Trying to write a zero to the reset flag or a one when it is not set has no effect. This flag is not reset by normal Cortex-A9 processor resets but has its own reset line, nWDRESET. nWDRESET must not be asserted when the Cortex-A9 processor reset assertion is the result of a watchdog reset request with WDRESETREQ. This distinction enables software to differentiate between a normal boot sequence, reset flag is zero, and one caused by a previous watchdog time-out, reset flag set to one.

Register (mpcore) Watchdog_Disable_Register

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Watchdog_Disable_Register WDT_DISABLE 0x00000634 0xF8F00634 32 bits rw 0x00000000 Watchdog Disable Register

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Register Watchdog_Disable_Register Details

Field Name Bits 31:0 Type rw Reset Value 0x0 Description Watchdog Disable Register Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero. If one of the values written to the Watchdog Disable Register is incorrect or if any other write occurs in between the two word writes, the watchdog remains in its current state. To reactivate the Watchdog, the software must write 1 to the watchdog mode bit of the Watchdog Control Register.

Register (mpcore) ICDDCR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDDCR GIC_DIST_EN 0x00001000 0xF8F01000 32 bits rw 0x00000000 Distributor Control Register

Register ICDDCR Details

Field Name reserved Bits 31:2 Type rw Reset Value 0x0 Description Reserved. Writes are ignored, read data is always zero.

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Field Name Enable_Non_secure

Bits 1

Type rw

Reset Value 0x0

Description 0 = disables all Non-secure interrupts control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals 1 = enables the distributor to update register locations for Non-secure interrupts FOR: ICDDCR_for_Non_secure_mode 31,1 --> Reserved. Writes are ignored, read data is always zero.

Enable_secure (GIC_EN_INT)

rw

0x0

0 = disables all Secure interrupt control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals. 1 = enables the distributor to update register locations for Secure interrupts. FOR: ICDDCR_for_Non_secure_mode 0 --> Enable_Non_secure --> 0 = disables all Non-secure interrupts control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals 1 = enables the distributor to update register locations for Non-secure interrupts

Register (mpcore) ICDICTR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICTR GIC_IC_TYPE 0x00001004 0xF8F01004 32 bits ro 0x00000C22 Interrupt Controller Type Register

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Register ICDICTR Details

Field Name reserved LSPI (GIC_LSPI) Bits 31:29 15:11 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is always zero. Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the controller contains. The encoding is: b11111 = 31 LSPIs, which are the interrupts of IDs 32-62. When CFGSDISABLE is HIGH then the interrupt controller prevents writes to any register locations that control the operating state of an LSPI. SecurityExtn (GIC_DOMAIN) 10 ro 0x1 Returns the number of security domains that the controller contains: 1 = the controller contains two security domains. This bit always returns the value one. SBZ CPU_Number (GIC_CPU_NUM) 9:8 7:5 ro ro 0x0 0x1 Reserved The encoding is: b000 the Cortex-A9 MPCore configuration contains one Cortex-A9 processor. b001 the Cortex-A9 MPCore configuration contains two Cortex-A9 processors. b010 the Cortex-A9 MPCore configuration contains three Cortex-A9 processors. b011 the Cortex-A9 MPCore configuration contains four Cortex-A9 processors. b1xx: Unused values. IT_Lines_Number (GIC_NUM_INT) 4:0 ro 0x2 The encoding is: b00000 = the distributor provides 32 interrupts, no external interrupt lines. b00001 = the distributor provides 64 interrupts, 32 external interrupt lines. b00010 = the distributor provides 96 interrupts, 64 external interrupt lines. b00011 = the distributor provide 128 interrupts, 96 external interrupt lines. b00100 = the distributor provides 160 interrupts, 128 external interrupt lines. b00101 = the distributor provides 192 interrupts, 160 external interrupt lines. b00110 = the distributor provides 224 interrupts, 192 external interrupt lines. b00111 = the distributor provides 256 interrupts, 224 external interrupt lines. All other values not used.

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Register (mpcore) ICDIIDR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDIIDR GIC_DIST_IDENT 0x00001008 0xF8F01008 32 bits ro 0x0102043B Distributor Implementer Identification Register

Register ICDIIDR Details

Field Name Implementation_Versio n Revision_Number (GIC_REV) Implementer (GIC_IMPL) 11:0 ro 0x43B Implementer Number Bits 31:24 23:12 Type ro ro Reset Value 0x1 0x20 Description Gives implementation version number Return the revision number of the controller

Register (mpcore) ICDISR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDISR0 GIC_SECURITY0 0x00001080 0xF8F01080 32 bits rw 0x00000000 Interrupt Security Register_0

Note: This register is the first in an array of 3 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDISR0 ICDISR1 ICDISR2 Address 0xf8f01080 0xf8f01084 0xf8f01088

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Register ICDISR0 to ICDISR2 Details

Field Name Security_Status (GIC_INT_NS) Bits 31:0 Type rw Reset Value 0x0 Description The ICDISRn provide a Security status bit for each interrupt supported by the GIC. Each bit controls the security status of the corresponding interrupt. Accessible by Secure accesses only. The register addresses are RAZ/WI to Non-secure accesses. ICDISR0 is banked for each connected processor.

Register (mpcore) ICDISER0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDISER0 GIC_ENABLE_SET 0x00001100 0xF8F01100 32 bits rw 0x0000FFFF Interrupt Set-enable Register 0

Register ICDISER0 Details

Field Name Set (GIC_INT_EN) Bits 31:0 Type rw Reset Value 0xFFFF Description The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access. ICDISER0 is banked for each connected processor.

Register (mpcore) ICDISER1

Name Relative Address Absolute Address Width Access Type ICDISER1 0x00001104 0xF8F01104 32 bits rw

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Reset Value Description

0x00000000 Interrupt Set-enable Register 1

Register ICDISER1 Details

Field Name Set Bits 31:0 Type rw Reset Value 0x0 Description The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.

Register (mpcore) ICDISER2

Name Relative Address Absolute Address Width Access Type Reset Value Description ICDISER2 0x00001108 0xF8F01108 32 bits rw 0x00000000 Interrupt Set-enable Register 2

Register ICDISER2 Details

Field Name Set Bits 31:0 Type rw Reset Value 0x0 Description The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.

Register (mpcore) ICDICER0

Name Software Name Relative Address Absolute Address Width Access Type ICDICER0 GIC_DISABLE 0x00001180 0xF8F01180 32 bits rw

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Reset Value Description

0x0000FFFF Interrupt Clear-Enable Register 0

Register ICDICER0 Details

Field Name Clear (GIC_INT_CLR) Bits 31:0 Type rw Reset Value 0xFFFF Description The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC. Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDICER0 is banked for each connected processor.

Register (mpcore) ICDICER1

Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICER1 0x00001184 0xF8F01184 32 bits rw 0x00000000 Interrupt Clear-Enable Register 1

Register ICDICER1 Details

Field Name Clear Bits 31:0 Type rw Reset Value 0x0 Description The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC. Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.

Register (mpcore) ICDICER2

Name Relative Address Absolute Address Width ICDICER2 0x00001188 0xF8F01188 32 bits

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Access Type Reset Value Description

rw 0x00000000 Interrupt Clear-Enable Register 2

Register ICDICER2 Details

Field Name Clear Bits 31:0 Type rw Reset Value 0x0 Description The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC. Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.

Register (mpcore) ICDISPR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDISPR0 GIC_PENDING_SET0 0x00001200 0xF8F01200 32 bits rw 0x00000000 Interrupt Set-pending Register_0

Note: This register is the first in an array of 3 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDISPR0 ICDISPR1 ICDISPR2 Address 0xf8f01200 0xf8f01204 0xf8f01208

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Register ICDISPR0 to ICDISPR2 Details

Field Name Set (GIC_PEND_SET) Bits 31:0 Type rw Reset Value 0x0 Description The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC. Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDISPR0 is banked for each connected processor.

Register (mpcore) ICDICPR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICPR0 GIC_PENDING_CLR0 0x00001280 0xF8F01280 32 bits rw 0x00000000 Interrupt Clear-Pending Register_0

Note: This register is the first in an array of 3 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDICPR0 ICDICPR1 ICDICPR2 Address 0xf8f01280 0xf8f01284 0xf8f01288

Register ICDICPR0 to ICDICPR2 Details

Field Name Clear (GIC_PEND_CLR) Bits 31:0 Type rw Reset Value 0x0 Description The ICDICPRs provide a Clear-pending bit for each interrupt supported by the GIC. Writing 1 to a Clear-pending bit clears the status of the corresponding peripheral interrupt to pending. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDICPR0 is banked for each connected processor.

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Register (mpcore) ICDABR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDABR0 GIC_ACTIVE0 0x00001300 0xF8F01300 32 bits rw 0x00000000 Active Bit register_0

Note: This register is the first in an array of 3 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDABR0 ICDABR1 ICDABR2 Address 0xf8f01300 0xf8f01304 0xf8f01308

Register ICDABR0 to ICDABR2 Details

Field Name Active (MASK) Bits 31:0 Type rw Reset Value 0x0 Description The ICDABRs provide an Active bit for each interrupt supported by the GIC. The bit reads as one if the status of the interrupt is active or active and pending. Read the ICDSPR or ICDCPR to find the pending status of the interrupt. ICDABR0 is banked for each connected processor.

Register (mpcore) ICDIPR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDIPR0 GIC_PRIORITY0 0x00001400 0xF8F01400 32 bits rw 0x00000000 Interrupt Priority Register_0

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Note: This register is the first in an array of 24 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDIPR0 ICDIPR1 ICDIPR2 ICDIPR3 ICDIPR4 ICDIPR5 ICDIPR6 ICDIPR7 ICDIPR8 ICDIPR9 ICDIPR10 ICDIPR11 ICDIPR12 ICDIPR13 ICDIPR14 ICDIPR15 ICDIPR16 ICDIPR17 ICDIPR18 ICDIPR19 ICDIPR20 ICDIPR21 ICDIPR22 ICDIPR23 Address 0xf8f01400 0xf8f01404 0xf8f01408 0xf8f0140c 0xf8f01410 0xf8f01414 0xf8f01418 0xf8f0141c 0xf8f01420 0xf8f01424 0xf8f01428 0xf8f0142c 0xf8f01430 0xf8f01434 0xf8f01438 0xf8f0143c 0xf8f01440 0xf8f01444 0xf8f01448 0xf8f0144c 0xf8f01450 0xf8f01454 0xf8f01458 0xf8f0145c

Register ICDIPR0 to ICDIPR23 Details

Field Name Priority (MASK) Bits 31:0 Type rw Reset Value 0x0 Description The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC. These registers are byte accessible. A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDIPR0 to ICDIPR7 are banked for each connected processor

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Register (mpcore) ICDIPTR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDIPTR0 GIC_SPI_TARGET0 0x00001800 0xF8F01800 32 bits rw 0x01010101 Interrupt Processor Targets Register_0

Note: This register is the first in an array of 24 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ICDIPTR0 ICDIPTR1 ICDIPTR2 ICDIPTR3 ICDIPTR4 ICDIPTR5 ICDIPTR6 ICDIPTR7 ICDIPTR8 ICDIPTR9 ICDIPTR10 ICDIPTR11 ICDIPTR12 ICDIPTR13 ICDIPTR14 ICDIPTR15 ICDIPTR16 ICDIPTR17 ICDIPTR18 ICDIPTR19 ICDIPTR20 ICDIPTR21 Address 0xf8f01800 0xf8f01804 0xf8f01808 0xf8f0180c 0xf8f01810 0xf8f01814 0xf8f01818 0xf8f0181c 0xf8f01820 0xf8f01824 0xf8f01828 0xf8f0182c 0xf8f01830 0xf8f01834 0xf8f01838 0xf8f0183c 0xf8f01840 0xf8f01844 0xf8f01848 0xf8f0184c 0xf8f01850 0xf8f01854

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Name ICDIPTR22 ICDIPTR23

Address 0xf8f01858 0xf8f0185c

Register ICDIPTR0 to ICDIPTR23 Details

Field Name Target (GIC_SPI_CPUn) Bits 31:0 Type rw Reset Value 0x1010101 Description The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the lists of processors that the interrupt is sent to if it is asserted. These registers are byte accessible. A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDIPTR0 to ICDIPTR7 are read-only, and each field returns a value corresponding only to the processor reading the register. Meaning of CPU targets field bit values: 0bxxxxxxx1: CPU interface 0 0bxxxxxx1x: CPU interface 1

Register (mpcore) ICDICFR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICFR0 GIC_INT_CFG 0x00001C00 0xF8F01C00 32 bits rw 0xAAAAAAAA Interrupt Configuration Register 0

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Register ICDICFR0 Details

Field Name Config (MASK) Bits 31:0 Type rw Reset Value 0xAAAAAAA A Description The ICDICFRs provide a 2-bit Int_config field for each interrupt supported by the GIC. A register field that corresponds to Secure interrupt is RAZ/WI to Non-secure accesses. ICDICFR0 is read-only. Meaning of each 2-bit Int_config: SGI: both bits are read-only; always 0b10 PPI: both bits are read-only; always 0b01 (active LOW level sensitive) for PPI[1], and [4]; always 0b11(rising-edge sensitive) for PPI[0], [2], and [3]. SPI: LSB is read-only, and is always 1; 0b01=active HIGH level sensitive; 0b11=rising-edge sensitive.

Register (mpcore) ICDICFR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICFR1 0x00001C04 0xF8F01C04 32 bits rw 0x7DC00000 Interrupt Configuration Register 1

Register ICDICFR1 Details

Field Name Config Bits 31:0 Type rw Reset Value 0x7DC00000 (ditto) ICDICFR1 is banked for each connected processor. Description

Register (mpcore) ICDICFR2

Name Relative Address Absolute Address Width Access Type Reset Value ICDICFR2 0x00001C08 0xF8F01C08 32 bits rw 0x55555555

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Description

Interrupt Configuration Register 2

Register ICDICFR2 Details

Field Name Config Bits 31:0 Type rw Reset Value 0x55555555 (ditto) Description

Register (mpcore) ICDICFR3

Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICFR3 0x00001C0C 0xF8F01C0C 32 bits rw 0x55555555 Interrupt Configuration Register 3

Register ICDICFR3 Details

Field Name Config Bits 31:0 Type rw Reset Value 0x55555555 (ditto) Description

Register (mpcore) ICDICFR4

Name Relative Address Absolute Address Width Access Type Reset Value Description ICDICFR4 0x00001C10 0xF8F01C10 32 bits rw 0x55555555 Interrupt Configuration Register 4

Register ICDICFR4 Details

Field Name Config Bits 31:0 Type rw Reset Value 0x55555555 (ditto) Description

Register (mpcore) ICDICFR5

Name ICDICFR5

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00001C14 0xF8F01C14 32 bits rw 0x55555555 Interrupt Configuration Register 5

Register ICDICFR5 Details

Field Name Config Bits 31:0 Type rw Reset Value 0x55555555 (ditto) Description

Register (mpcore) ppi_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ppi_status GIC_PPI_STAT 0x00001D00 0xF8F01D00 32 bits ro 0x00000000 PPI Status Register

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Register ppi_status Details

Field Name reserved ppi_status Bits 31:16 15:11 Type ro ro Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is always zero Returns the status of the PPI(4:0) inputs on the distributor: * PPI[4] is nIRQ * PPI[3] is the private watchdog * PPI[2] is the private timer * PPI[1] is nFIQ * PPI[0] is the global timer. PPI[1] and PPI[4] are active LOW PPI[0], PPI[2] and PPI[3] are active HIGH. Note These bits return the actual status of the PPI(4:0) signals. The ICDISPRn and ICDICPRn registers can also provide the PPI(4:0) status but because you can write to these registers then they might not contain the actual status of the PPI(4:0) signals. SBZ 10:0 ro 0x0 SBZ

Register (mpcore) spi_status_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description spi_status_0 GIC_SPI_STAT 0x00001D04 0xF8F01D04 32 bits ro 0x00000000 SPI Status Register 0

Register spi_status_0 Details

Field Name spi_status (GIC_SPI_N) Bits 31:0 Type ro Reset Value 0x0 Description Returns the status of the IRQ ID32 to ID63 inputs on the distributor. These bits return the actual status of the IRQ signals. Note: The ICDISPR1 and ICDICPR1 registers can also provide the IRQ status but because you can write to these registers then they might not contain the actual status of the IRQ signals.

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Register (mpcore) spi_status_1

Name Relative Address Absolute Address Width Access Type Reset Value Description spi_status_1 0x00001D08 0xF8F01D08 32 bits ro 0x00000000 SPI Status Register 1

Register spi_status_1 Details

Field Name spi_status (GIC_SPI_N) Bits 31:0 Type ro Reset Value 0x0 Description Returns the status of the IRQ ID64 to ID95 inputs on the distributor. These bits return the actual status of the IRQ signals. Note: The ICDISPR2 and ICDICPR2 registers can also provide the IRQ status but because you can write to these registers then they might not contain the actual status of the IRQ signals.

Register (mpcore) ICDSGIR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICDSGIR GIC_SFI_TRIG 0x00001F00 0xF8F01F00 32 bits rw 0x00000000 Software Generated Interrupt Register

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Register ICDSGIR Details

Field Name reserved TargetListFilter (TRGFILT) Bits 31:26 25:24 Type rw rw Reset Value 0x0 0x0 reserved 0b00: send the interrupt to the CPU interfaces specified in the CPUTargetList field 0b01: send the interrupt to all CPU interfaces except the CPU interface that requested the interrupt 0b10: send the interrupt on only to the CPU interface that requested the interrupt 0b11: reserved CPUTargetList (CPU) 23:16 rw 0x0 When TargetListFilter is 0b00, defines the CPU interfaces the Distributor must send the interrupt to. Each bit refers to the corresponding CPU interface. SATT 15 rw 0x0 Determines the condition for sending the SGI specified in the SGIINTID field to a specified CPU interfaces: 0: only if the SGI is configured as Secure on that interface. 1: only if the SGI is configured as Non-secure on that interface. SBZ SGIINTID (INTID) 14:4 3:0 rw rw 0x0 0x0 SBZ The Interrupt ID of the SGI to send to the specified CPU interfaces. Description

Register (mpcore) ICPIDR4

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR4 GIC_PERPHID 0x00001FD0 0xF8F01FD0 32 bits rw 0x00000004 Peripheral ID4

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Register ICPIDR4 Details

Field Name reserved ContinuationCode Bits 31:4 3:0 Type rw rw Reset Value 0x0 0x4 reserved ARM-defined ContinuationCode field Description

Register (mpcore) ICPIDR5

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR5 0x00001FD4 0xF8F01FD4 32 bits rw 0x00000000 Peripheral ID5

Register ICPIDR5 Details

Field Name reserved Bits 31:0 Type rw Reset Value 0x0 Reserved Description

Register (mpcore) ICPIDR6

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR6 0x00001FD8 0xF8F01FD8 32 bits rw 0x00000000 Peripheral ID6

Register ICPIDR6 Details

Field Name reserved Bits 31:0 Type rw Reset Value 0x0 Reserved Description

Register (mpcore) ICPIDR7

Name ICPIDR7

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00001FDC 0xF8F01FDC 32 bits rw 0x00000000 Peripheral ID7

Register ICPIDR7 Details

Field Name reserved Bits 31:0 Type rw Reset Value 0x0 Reserved Description

Register (mpcore) ICPIDR0

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR0 0x00001FE0 0xF8F01FE0 32 bits rw 0x00000090 Peripheral ID0

Register ICPIDR0 Details

Field Name reserved DevID_low Bits 31:8 7:0 Type rw rw Reset Value 0x0 0x90 reserved ARM-defined DevID[7:0] field Description

Register (mpcore) ICPIDR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR1 0x00001FE4 0xF8F01FE4 32 bits rw 0x000000B3 Peripheral ID1

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Register ICPIDR1 Details

Field Name reserved ARchID_low DevID_high Bits 31:8 7:4 3:0 Type rw rw rw Reset Value 0x0 0xB 0x3 reserved ARM-defined ArchID[3:0] field ARM-defined DevID[11:8] field Description

Register (mpcore) ICPIDR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR2 0x00001FE8 0xF8F01FE8 32 bits rw 0x0000001B Peripheral ID2

Register ICPIDR2 Details

Field Name reserved ArchRev UsesJEPcode ArchID_high Bits 31:8 7:4 3 2:0 Type rw rw rw rw Reset Value 0x0 0x1 0x1 0x3 reserved ARM-defined ArchRev field ARM-defined ContinuationCode field ARM-defined ArchID[6:4] field Description

Register (mpcore) ICPIDR3

Name Relative Address Absolute Address Width Access Type Reset Value Description ICPIDR3 0x00001FEC 0xF8F01FEC 32 bits rw 0x00000000 Peripheral ID3

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Register ICPIDR3 Details

Field Name reserved Revision reserved Bits 31:8 7:4 3:0 Type rw rw rw Reset Value 0x0 0x0 0x0 reserved ARM-defined Revision field reserved Description

Register (mpcore) ICCIDR0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIDR0 GIC_PCELLID 0x00001FF0 0xF8F01FF0 32 bits rw 0x0000000D Component ID0

Register ICCIDR0 Details

Field Name Bits 31:0 Type rw Reset Value 0xD Description ARM-defined fixed values for the preamble for component discovery

Register (mpcore) ICCIDR1

Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIDR1 0x00001FF4 0xF8F01FF4 32 bits rw 0x000000F0 Component ID1

Register ICCIDR1 Details

Field Name Bits 31:0 Type rw Reset Value 0xF0 Description ARM-defined fixed values for the preamble for component discovery

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Register (mpcore) ICCIDR2

Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIDR2 0x00001FF8 0xF8F01FF8 32 bits rw 0x00000005 Component ID2

Register ICCIDR2 Details

Field Name Bits 31:0 Type rw Reset Value 0x5 Description ARM-defined fixed values for the preamble for component discovery

Register (mpcore) ICCIDR3

Name Relative Address Absolute Address Width Access Type Reset Value Description ICCIDR3 0x00001FFC 0xF8F01FFC 32 bits rw 0x000000B1 Component ID3

Register ICCIDR3 Details

Field Name Bits 31:0 Type rw Reset Value 0xB1 Description ARM-defined fixed values for the preamble for component discovery

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B.25 On-Chip Memory (ocm)

Module Name Base Address Description Vendor Info On-Chip Memory (ocm) 0xF800C000 ocm On-Chip Memory Registers Xilinx

Register Summary
Register Name OCM_PARITY_CTRL OCM_PARITY_ERRA DDRESS Address 0x00000000 0x00000004 Width 32 32 Type mixed mixed Reset Value 0x00000000 0x00000000 Description Control fields for RAM parity operation Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged. Status of OCM Interrupt Control fields for OCM

OCM_IRQ_STS OCM_CONTROL

0x00000008 0x0000000C

32 32

mixed mixed

0x00000000 0x00000000

Register (ocm) OCM_PARITY_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description OCM_PARITY_CTRL 0x00000000 0xF800C000 32 bits mixed 0x00000000 Control fields for RAM parity operation

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Register OCM_PARITY_CTRL Details

Field Name reserved OddParityEn Bits 31:21 20:5 Type ro rw Reset Value 0x0 0x0 Description Returns 0 when read Enable RAM Odd Parity Generation. One control bit per data byte (OddParity[0] controls Data[7:0] e.t.c) 0: Even Parity generated 1: Odd Parity generated LockFailErrIrqEn 4 rw 0x0 Enable interrupt when an AXI LOCK ("locked access") command is detected. MultipleParityErrIrqEn 3 rw 0x0 Same as SingleParityErrIrqEn, but enables IRQ on multiple parity errors detected. 0: IRQ is not generated when parity error detected and ParityCheckDis=0 1: IRQ is generated when parity error detected and ParityCheckDis=0. SingleParityErrIrqEn 2 rw 0x0 Enable interrupt when a single parity error is detected. Note that even if this field is 0, the OCM_IRQ_STS register will still log the error if ParityCheckDis=0. This allows software the option of polling if an error occurred. 0: IRQ is not generated when parity error detected and ParityCheckDis=0 1: IRQ is generated when parity error detected and ParityCheckDis=0. RdRespParityErrEn 1 rw 0x0 Enable AXI read 'SLVERR' response for parity error detection. 0: Error will not be sent on AXI read channel when parity error detected 1: Error will be sent on AXI read channel when parity error detected and ParityCheckDis=0 ParityCheckDis 0 rw 0x0 Disable RAM Parity Checking. No checking or logging of status will occur when 1. 0: RAM Parity checking is enabled 1: RAM Parity checking is disabled

Register (ocm) OCM_PARITY_ERRADDRESS

Name Relative Address Absolute Address Width OCM_PARITY_ERRADDRESS 0x00000004 0xF800C004 32 bits

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Access Type Reset Value Description

mixed 0x00000000 Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged.

Register OCM_PARITY_ERRADDRESS Details

Field Name reserved ParityErrAddress Bits 31:14 13:0 Type ro wtc Reset Value 0x0 0x0 Description Return 0 when read When a parity Error occurs, the access address associated with the error is logged here. The first error address will be held if multiple parity errors occur. Need an explicit write of all '1's' to reset/clear this field.

Register (ocm) OCM_IRQ_STS

Name Relative Address Absolute Address Width Access Type Reset Value Description OCM_IRQ_STS 0x00000008 0xF800C008 32 bits mixed 0x00000000 Status of OCM Interrupt

Register OCM_IRQ_STS Details

Field Name reserved LockFailErr Bits 31:3 2 Type ro wtc Reset Value 0x0 0x0 Description Return 0 when read When set (1), indicates that an AXI LOCK has been attempted (not supported by OCM). This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin. (Associated irq enable bit must be set)

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Field Name MultipleParityErr

Bits 1

Type wtc

Reset Value 0x0

Description Status of OCM multiple parity error. This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin. (Associated irq enable bit must be set) 0: Multiple OCM parity Errors have not occurred 1: Multiple OCM parity Errors have occurred

SingleParityErr

wtc

0x0

Status of OCM single parity error. This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin (Associated irq enable bit must be set) 0: Single OCM parity Error has not occurred 1: Single OCM parity Error has occurred

Register (ocm) OCM_CONTROL

Name Relative Address Absolute Address Width Access Type Reset Value Description OCM_CONTROL 0x0000000C 0xF800C00C 32 bits mixed 0x00000000 Control fields for OCM

Register OCM_CONTROL Details

Field Name reserved ArbShareTopSwScuWr DIs Bits 31:3 2 Type ro rw Reset Value 0x0 0x0 Description Return 0 when read Controls the arbitration to memory between the topswitch port and the scuwr port. 0: The topsw and the scuWr porst share the memory bandwith - 50% each. 1: The scuWr takes higher priority over the topswitch port (unless the ScuWrPriorityLo bit is set) reserved ScuWrPriorityLo 1 0 rw rw 0x0 0x0 Reserved. Do not modify. When set (1), changes the priority of the SCU write port to LOW from Medium

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B.26 Quad-SPI Flash Controller (qspi)

Module Name Software Name Base Address Description Vendor Info Quad-SPI Flash Controller (qspi) XQSPIPS 0xE000D000 qspi LQSPI module Registers Xilinx lqspi

Register Summary
Register Name Config_reg Intr_status_REG Intrpt_en_REG Intrpt_dis_REG Intrpt_mask_REG En_REG Delay_REG TXD0 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Width 32 32 32 32 32 32 32 32 Type mixed mixed mixed mixed ro mixed rw wo Reset Value x 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description SPI configuration register SPI interrupt status register Interrupt Enable register. Interrupt disable register. Interrupt mask register SPI_Enable Register Delay Register Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3. Receive Data Register Slave Idle Count Register TX_FIFO Threshold Register RX FIFO Threshold Register General Purpose Inputs and Outputs Register for the Quad-SPI Controller core Loopback Master Clock Delay Adjustment Register Transmit Data Register. Keyhole addresses for the Transmit data FIFO. Transmit Data Register. Keyhole addresses for the Transmit data FIFO.

Rx_data_REG Slave_Idle_count_REG TX_thres_REG RX_thres_REG GPIO

0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030

32 32 32 32 32

ro mixed rw rw rw

0x00000000 0x000000FF 0x00000001 0x00000001 0x00000001

LPBK_DLY_ADJ TXD1

0x00000038 0x00000080

32 32

rw wo

0x00000033 0x00000000

TXD2

0x00000084

32

wo

0x00000000

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Register Name TXD3

Address 0x00000088

Width 32

Type wo

Reset Value 0x00000000

Description Transmit Data Register. Keyhole addresses for the Transmit data FIFO. Configuration Register specifically for the Linear Quad-SPI Controller Status Register specifically for the Linear Quad-SPI Controller Module Identification register

LQSPI_CFG

0x000000A0

32

rw

LQSPI_STS MOD_ID

0x000000A4 0x000000FC

9 32

rw rw

0x00000000 0x01090101

Register (qspi) Config_reg

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Config_reg CR 0x00000000 0xE000D000 32 bits mixed x SPI configuration register

Register Config_reg Details

Field Name leg_flsh (IFMODE) Bits 31 Type rw Reset Value 0x1 Description Flash memory interface mode control: 0: legacy SPI mode 1: Flash memory interface mode This control is required to enable or disable automatic recognition of instruction bytes in the first byte of a transfer. If this mode is disabled, the core will operate in standard SPI mode, with no dual- or quad-bit input or output capability; the extended bits will be configured as inputs to prevent any driver contention on these pins. If enabled, flash memory interface instructions are automatically recognized and the I/O configured accordingly. reserved 30:27 ro 0x0 Reserved, read as zero, ignored on write.

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Field Name endian (ENDIAN)

Bits 26

Type rw

Reset Value 0x0

Description 0 for little endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20. 1 for big endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20.

reserved Holdb_dr

25:20 19

ro rw

0x0 0x0

Reserved, read as zero, ignored on write. If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI

reserved reserved Man_start_com (MANSTRT) Man_start_en (MANSTRTEN) Manual_CS (SSFORCE) reserved PCS reserved REF_CLK FIFO_WIDTH

18 17 16

rw rw wo

0x0 x 0x0

Reserved Reserved, do not modify Manual Start Command 1: start transmission of data 0: don't care

15

rw

0x0

Manual Start Enable 1: enables manual start 0: auto mode

14

rw

0x0

Manual CS 1: manual CS mode 0: auto mode

13:11 10 9 8 7:6

rw rw rw rw rw

0x0 0x0 0x0 0x0 0x0

Reserved Peripheral chip select line, directly drive n_ss_out if Manual_C is set Reserved Reserved. Must be 0 FIFO width Must be set to 2'b11 (32bits). All other settings are not supported.

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Field Name BAUD_RATE_DIV

Bits 5:3

Type rw

Reset Value 0x0

Description Master mode baud rate divisor 000: divide by 2. This is the only baud rate setting that can be used if the loopback clock is enabled (USE_LPBK). This setting also works in non-loopback mode. 001: divide by 4 010: divide by 8 011: divide by 16 100: divide by 32 101: divide by 64 110: divide by 128 111: divide by 256

CLK_PH (CPHA)

rw

0x0

Clock phase 1: the SPI clock is inactive outside the word 0: the SPI clock is active outside the word Note : For {CLK_PH, CLK_POL}, only 2'b11 and 2'b00 are supported.

CLK_POL (CPOL)

rw

0x0

Clock polarity outside SPI word 1: The SPI clock is quiescent high 0: The SPI clock is quiescent low Note : For {CLK_PH, CLK_POL}, only 2'b11 and 2'b00 are supported.

MODE_SEL (MSTREN)

rw

0x0

Mode select 1: The SPI is in master mode 0: RESERVED In QSPI boot mode, ROM code will set this bit. In other boot modes, this bit must be set before using QSPI.

Register (qspi) Intr_status_REG

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intr_status_REG SR 0x00000004 0xE000D004 32 bits mixed 0x00000004 SPI interrupt status register

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Register Intr_status_REG Details

This register is set when the described event occurs and the interrupt is enabled in the mask register. When any of these bits are set the interrupt output is asserted high. In the default configuration, these bits are all cleared simultaneously by reading this register, though this may be configured for an individual write-one-to-clear scheme.
Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wtc Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow, write one to this bit location to clear. 1: underflow is detected 0: no underflow has been detected Write 1 to this bit location to clear RX_FIFO_full (IXR_RXFULL) RX_FIFO_not_empty (IXR_RXNEMPTY) 4 ro 0x0 5 ro 0x0 RX FIFO full (current FIFO status) 1: FIFO is full 0: FIFO is not full RX FIFO not empty (current FIFO status) 1: FIFO has more than or equal to THRESHOLD entries 0: FIFO has less than RX THRESHOLD entries TX_FIFO_full (IXR_TXFULL) TX_FIFO_not_full (IXR_TXOW) 2 ro 0x1 3 ro 0x0 TX FIFO full (current FIFO status) 1: FIFO is full 0: FIFO is not full TX FIFO not full (current FIFO status) 1: FIFO has less than THRESHOLD entries 0: FIFO has more than or equal toTHRESHOLD entries reserved RX_OVERFLOW (IXR_RXOVR) 1 0 ro wtc 0x0 0x0 Reserved, read as zero, ignored on write. Receive Overflow interrupt, write one to this bit location to clear. 1: overflow occurred 0: no overflow occurred Write 1 to this bit location to clear

Register (qspi) Intrpt_en_REG

Name Software Name Relative Address Absolute Address Width Access Type Intrpt_en_REG IER 0x00000008 0xE000D008 32 bits mixed

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Reset Value Description

0x00000000 Interrupt Enable register.

Register Intrpt_en_REG Details

Writing a 1 to this register sets the corresponding bits of the interrupt mask register.
Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: enable the interrupt 0: no effect RX_FIFO_full (IXR_RXFULL) 5 wo 0x0 RX FIFO full enable 1: enable the interrupt 0: no effect RX_FIFO_not_empty (IXR_RXNEMPTY) 4 wo 0x0 RX FIFO not empty enable 1: enable the interrupt 0: no effect TX_FIFO_full (IXR_TXFULL) 3 wo 0x0 TX FIFO full enable 1: enable the interrupt 0: no effect TX_FIFO_not_full (IXR_TXOW) 2 wo 0x0 TX FIFO not full enable 1: enable the interrupt 0: no effect reserved RX_OVERFLOW (IXR_RXOVR) 1 0 wo wo 0x0 0x0 Reserved, read as zero, ignored on write. Receive Overflow interrupt enable 1: enable the interrupt 0: no effect

Register (qspi) Intrpt_dis_REG

Name Software Name Relative Address Absolute Address Width Intrpt_dis_REG IDR 0x0000000C 0xE000D00C 32 bits

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Access Type Reset Value Description

mixed 0x00000000 Interrupt disable register.

Register Intrpt_dis_REG Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: disables the interrupt 0: no effect RX_FIFO_full (IXR_RXFULL) 5 wo 0x0 RX FIFO full enable 1: disables the interrupt 0: no effect RX_FIFO_not_empty (IXR_RXNEMPTY) 4 wo 0x0 RX FIFO not empty enable 1: disables the interrupt 0: no effect TX_FIFO_full (IXR_TXFULL) 3 wo 0x0 TX FIFO full enable 1: disables the interrupt 0: no effect TX_FIFO_not_full (IXR_TXOW) 2 wo 0x0 TX FIFO not full enable 1: disables the interrupt 0: no effect reserved RX_OVERFLOW (IXR_RXOVR) 1 0 wo wo 0x0 0x0 Reserved Receive Overflow interrupt enable 1: disables the interrupt 0: no effect

Register (qspi) Intrpt_mask_REG

Name Software Name Relative Address Absolute Address Width Intrpt_mask_REG IMR 0x00000010 0xE000D010 32 bits

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Access Type Reset Value Description

ro 0x00000000 Interrupt mask register

Register Intrpt_mask_REG Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: interrupt is disabled 0: interrupt is enabled RX_FIFO_full (IXR_RXFULL) 5 ro 0x0 RX FIFO full enable 1: interrupt is disabled 0: interrupt is enabled RX_FIFO_not_empty (IXR_RXNEMPTY) 4 ro 0x0 RX FIFO not empty enable 1: interrupt is disabled 0: interrupt is enabled TX_FIFO_full (IXR_TXFULL) 3 ro 0x0 TX FIFO full enable 1: interrupt is disabled 0: interrupt is enabled TX_FIFO_not_full (IXR_TXOW) 2 ro 0x0 TX FIFO not full enable 1: interrupt is disabled 0: interrupt is enabled reserved RX_OVERFLOW (IXR_RXOVR) 1 0 ro ro 0x0 0x0 Reserved Receive Overflow interrupt enable 1: interrupt is disabled 0: interrupt is enabled

Register (qspi) En_REG

Name Software Name Relative Address Absolute Address Width En_REG ER 0x00000014 0xE000D014 32 bits

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Access Type Reset Value Description

mixed 0x00000000 SPI_Enable Register

Register En_REG Details

Field Name reserved SPI_EN (ENABLE) Bits 31:1 0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. SPI_Enable 1: enable the SPI 0: disable the SPI

Register (qspi) Delay_REG

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Delay_REG DR 0x00000018 0xE000D018 32 bits rw 0x00000000 Delay Register

Register Delay_REG Details

This register is only used in master mode to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.
Field Name d_nss Bits 31:24 Type rw Reset Value 0x0 Description Delay in SPI REFERENCE CLOCK or ext_clk cycles for the length that the master mode chip select outputs are de-asserted between words when cpha=0. Delay in SPI REFERENCE CLOCK or ext_clk cycles between one chip select being de-activated and the activation of another Delay in SPI REFERENCE CLOCK or ext_clk cycles between last bit of current word and the first bit of the next word. Added delay in SPI REFERENCE CLOCK or ext_clk cycles between setting n_ss_out low and first bit transfer.

d_btwn (BTWN) d_after (AFTER) d_int (INIT)

23:16

rw

0x0

15:8

rw

0x0

7:0

rw

0x0

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Register (qspi) TXD0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXD0 TXD_00 0x0000001C 0xE000D01C 32 bits wo 0x00000000 Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3.

Register TXD0 Details

Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 4-byte instruction for normal read/write data transfer.

Register (qspi) Rx_data_REG

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Rx_data_REG RXD 0x00000020 0xE000D020 32 bits ro 0x00000000 Receive Data Register

Register Rx_data_REG Details

Field Name RX_FIFO_data Bits 31:0 Type ro Reset Value 0x0 Description Data from TX FIFO

Register (qspi) Slave_Idle_count_REG

Name Software Name Relative Address Absolute Address Slave_Idle_count_REG SICR 0x00000024 0xE000D024

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Width Access Type Reset Value Description

32 bits mixed 0x000000FF Slave Idle Count Register

Register Slave_Idle_count_REG Details

Field Name reserved Slave_Idle_coun (MASK) Bits 31:8 7:0 Type ro rw Reset Value 0x0 0xFF Description Reserved, read as zero, ignored on write. SPI in slave mode detects a start only when the external SPI master serial clock (sclk_in) is stable (quiescent state) for SPI REFERENCE CLOCK cycles specified by slave idle count register or when the SPI is deselected.

Register (qspi) TX_thres_REG

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TX_thres_REG TXWR 0x00000028 0xE000D028 32 bits rw 0x00000001 TX_FIFO Threshold Register

Register TX_thres_REG Details

Field Name Bits Type rw Reset Value 0x1 Description Defines the level at which the TX FIFO not full interrupt is generated

Threshold_of_TX_FIFO 31:0

Register (qspi) RX_thres_REG

Name Relative Address Absolute Address Width Access Type RX_thres_REG 0x0000002C 0xE000D02C 32 bits rw

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Reset Value Description

0x00000001 RX FIFO Threshold Register

Register RX_thres_REG Details

Field Name Threshold_of_RX_FIF O Bits 31:0 Type rw Reset Value 0x1 Description Defines the level at which the RX FIFO not empty interrupt is generated

Register (qspi) GPIO

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIO 0x00000030 0xE000D030 32 bits rw 0x00000001 General Purpose Inputs and Outputs Register for the Quad-SPI Controller core

Register GPIO Details

Field Name reserved WP_N Bits 31:1 0 Type rw rw Reset Value 0x0 0x1 Description Reserved for future GPIO. Write Protect. Write Protect output for flash devices supporting this function. Active low (may be inverted externally to the core if required for flash devices requiring active high write protect signal.)

Register (qspi) LPBK_DLY_ADJ

Name Relative Address Absolute Address Width Access Type Reset Value Description LPBK_DLY_ADJ 0x00000038 0xE000D038 32 bits rw 0x00000033 Loopback Master Clock Delay Adjustment Register

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Register LPBK_DLY_ADJ Details

Register for adjusting the internal loopback clock delay for read data capturing. This feature is only active if bit 5 is set AND if the baud rate divisor in reg 0x00 is programmed to 2 (i.e., 000).
Field Name reserved LPBK_SEL LPBK_PH reserved USE_LPBK DLY1 DLY0 Bits 31:9 8 7 6 5 4:3 2:0 Type rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x1 0x2 0x3 Reserved. Set to 0, do not modify Set to 0, do not modify Set to 0, do not modify Use internal loopback master clock for read data capturing when baud rate divisor (reg 0x00) is 2 Must be set to 00 if Loopback clk used Must be set to 00 if Loopback clk used Description

Register (qspi) TXD1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXD1 TXD_01 0x00000080 0xE000D080 32 bits wo 0x00000000 Transmit Data Register. Keyhole addresses for the Transmit data FIFO.

Register TXD1 Details

Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 1-byte instruction, not for normal data transfer. In little endian mode (default), only bits 7:0 are valid, bits 31:8 are ignored. In big endian mode, only the 8 MS bits are valid.

Register (qspi) TXD2

Name Software Name Relative Address TXD2 TXD_10 0x00000084

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Absolute Address Width Access Type Reset Value Description

0xE000D084 32 bits wo 0x00000000 Transmit Data Register. Keyhole addresses for the Transmit data FIFO.

Register TXD2 Details

Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 2-byte instruction, not for normal data transfer. In little endian mode (default), only bits 15:0 are valid, bits 31:16 are ignored. In big endian mode, only the 16 MS bits are valid.

Register (qspi) TXD3

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXD3 TXD_11 0x00000088 0xE000D088 32 bits wo 0x00000000 Transmit Data Register. Keyhole addresses for the Transmit data FIFO.

Register TXD3 Details

Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 3-byte instruction, not for normal data transfer. In little endian mode (default), only bits 23:0 are valid, bits 31:24 are ignored. In big endian mode, only the 24 MS bits are valid.

Register (qspi) LQSPI_CFG

Name Software Name Relative Address LQSPI_CFG LQSPI_CR 0x000000A0

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Absolute Address Width Access Type Reset Value Description

0xE000D0A0 32 bits rw x Configuration Register specifically for the Linear Quad-SPI Controller

Register LQSPI_CFG Details

Field Name LQ_MODE (LINEAR) TWO_MEM SEP_BUS U_PAGE 30 29 28 rw rw rw 0x0 0x0 0x0 Both upper and lower memories are active, if set Separate memory bus, if set. Only has meaning if bit 30 is set Upper memory page, if set. Only has meaning if bit 30 is set AND bit 29 is clear AND bit 31 is clear. In LQSPI mode, address bit 25 will indicate lower (0) or upper (1) page. In IO mode, this bit is used to select the lower or upper memory for configuration or read/write operations. reserved reserved 27 26 rw rw 0x0 x Reserved Reserved. Write to this location may lead to unpredictable behavior. MODE_EN 25 rw 0x1 Enable MODE_BITS[23:16] to be sent, if set. This bit MUST BE SET for dual I/O or quad I/O read (specified through [7:0]). This bit MUST BE CLEAR for all other read modes as they do not have mode bits. If this bit is 0, bits 24, and [23:16] are ignored. Here is a summary of how bits 25, 24 and 23:16 are related: if ( [ Bit25 == 0 ] && [ Bit24 == x ] ) then [ Bits23:16 =x] if ( [ Bit25 == 1 ] && [ Bit24 == 0 ] ) then [ Bits23:16 = ~(8'bxx10xxxx) ] if ( [ Bit25 == 1 ] && [ Bit24 == 1 ] ) then [ Bits23:16 = 8'bxx10xxxx ] Bits 31 Type rw Reset Value 0x0 Description Linear quad SPI mode, if set, else quad SPI mode

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Field Name MODE_ON

Bits 24

Type rw

Reset Value 0x1

Description This bit is only relevant if bit 25 is set, else it is ignored. If this bit is set, instruction code is only sent for the very first read transfer. If this bit is clear, instruction code will be sent for all read transfers. This bit is configured in association with the MODE_BITS. For Winbond devices, this bit MUST BE SET if the MODE_BITS are 8'bxx10xxxx, else this bit MUST BE CLEAR.

MODE_BITS

23:16

rw

0xA0

These bits are only relevant if bit 25 is set, else it is ignored. If bit 25 is set, this value is required for both dual I/O read and quad I/O read. See vendor's datasheet for more information. For Winbond's device, the continuous read mode value is 8'bxx10xxxx to skip the instruction code for the next read transfer, else instruction code is sent for all read transfers. Bit 24 has to be configured accordingly with this value.

reserved DUMMY_BYTE (DUMMY) INST_CODE (INST)

15:11 10:8 7:0

rw rw rw

x 0x2 0xEB

Reserved, value is undefined when read. Number of dummy bytes between address and return read data Read instruction code. The known read instruction codes are: 8'h03 - Read 8'h0B - Fast read 8'h3B - Fast read dual output 8'h6B - Fast read quad output 8'hBB - Fast read dual I/O 8'hEB - Fast read quad I/O

Register (qspi) LQSPI_STS

Name Software Name Relative Address Absolute Address Width Access Type LQSPI_STS LQSPI_SR 0x000000A4 0xE000D0A4 9 bits rw

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Reset Value Description

0x00000000 Status Register specifically for the Linear Quad-SPI Controller

Register LQSPI_STS Details

Field Name reserved D_FSM_ERR (FB_RECVD) WR_RECVD reserved 1 0 rw rw 0x0 0x0 AXI write command received, if set Reserved Bits 8:3 2 Type rw rw Reset Value 0x0 0x0 Reserved Data FSM error, if set Description

Register (qspi) MOD_ID

Name Relative Address Absolute Address Width Access Type Reset Value Description MOD_ID 0x000000FC 0xE000D0FC 32 bits rw 0x01090101 Module Identification register

Register MOD_ID Details

Field Name Bits 31:0 Type rw Reset Value 0x1090101 Module ID value. Description

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B.27 SD Controller (sdio)

Module Name Base Address Description Vendor Info SD Controller (sdio) 0xE0100000 sd0 0xE0101000 sd1 SD2.0/ SDIO2.0/ MMC3.31 AHB Host ControllerRegisters

Register Summary
Register Name SDMA_system_addres s_register Block_Size_Block_Cou nt Argument Transfer_Mode_Comm and Response0 Response1 Response2 Response3 Buffer_Data_Port Present_State Host_control_Power_c ontrol_Block_Gap_Con trol_Wakeup_control Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 Width 32 32 32 32 32 32 32 32 32 25 32 Type rw mixed rw mixed ro ro ro ro rw ro mixed Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01F20000 0x00000000 Description System DMA Address Register Block size register Block count register Argument register Transfer mode register Command register Response register Response register Response register Response register Buffer data port register Present State register Host control register Power control register Block gap control register Wake-up control register Clock_Control_Timeou t_control_Software_res et 0x0000002C 27 mixed 0x00000000 Clock Control register Timeout control register Software reset register 30 mixed 0x00000000 Normal interrupt status register Error interrupt status register 30 mixed 0x00000000 Normal interrupt status enable register Error interrupt status enable register

Normal_interrupt_stat 0x00000030 us_Error_interrupt_stat us Normal_interrupt_stat us_enable_Error_interr upt_status_enable 0x00000034

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Register Name Normal_interrupt_sign al_enable_Error_interr upt_signal_enable Auto_CMD12_error_st atus Capabilities Maximum_current_cap abilities Force_event_for_Auto Cmd12_Error_Status_F orce_event_register_for _error_interrupt_status ADMA_error_status ADMA_system_addres s Boot_Timeout_control Debug_Selection SPI_interrupt_support Slot_interrupt_status_ Host_controller_versio n

Address 0x00000038

Width 30

Type mixed

Reset Value 0x00000000

Description Normal interrupt signal enable register Error interrupt signal enable register

0x0000003C 0x00000040 0x00000048 0x00000050

8 31 24 32

ro ro ro mixed

0x00000000 0x69EC0080 0x00000001 0x00000000

Auto CMD12 error status register Capabilities register Maximum current capabilities register Force event register for Auto CMD12 error status register Force event register for error interrupt status

0x00000054 0x00000058 0x00000060 0x00000064 0x000000F0 0x000000FC

3 32 32 1 8 32

mixed rw rw wo rw ro

0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x89010000

ADMA error status register ADMA system address register Boot Timeout control register Debug Selection Register SPI interrupt support register Slot interrupt status register and Host controller version register

Register (sdio) SDMA_system_address_register

Name Relative Address Absolute Address Width Access Type Reset Value Description SDMA_system_address_register 0x00000000 sd0: 0xE0100000 sd1: 0xE0101000 32 bits rw 0x00000000 System DMA Address Register

Register SDMA_system_address_register Details

This register contains the system memory address for a DMA transfer. When the Host Controller (HC) stops a DMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations during transfer return an invalid value. The Host Driver (HD) shall initialize this register before starting a DMA transaction. After DMA has stopped, the next system address of the next contiguous data position can be read from this register. The DMA transfer waits at every boundary specified by the Host DMA

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Buffer Size in the Block Size register. The Host Controller generates DMA Interrupt to request to update this register. The HD sets the next system address of the next data position to this register. When most upper byte of this register (003h) is written, the HC restart the DMA transfer. When restarting DMA by the resume command or by setting Continue Request in the Block Gap Control register, the HC shall start at the next contiguous address stored here in the System Address register
Field Name SDMA_System_Addre ss Bits 31:0 Type rw Reset Value 0x0 Description Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.

Register (sdio) Block_Size_Block_Count

Name Relative Address Absolute Address Width Access Type Reset Value Description Block_Size_Block_Count 0x00000004 sd0: 0xE0100004 sd1: 0xE0101004 32 bits mixed 0x00000000 Block size register Block count register

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Register Block_Size_Block_Count Details

Field Name Blocks_Count_for_Cur rent_Transfer Bits 31:16 Type rw Reset Value 0x0 Description This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. When saving transfer context as a result of Suspend command, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, the HD shall restore the previously save block count. 0000h - Stop Count 0001h - 1 block 0002h - 2 blocks --- --FFFFh - 65535 blocks reserved 15 ro 0x0 Reserved

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Field Name Host_SDMA_Buffer_Si ze

Bits 14:12

Type rw

Reset Value 0x0

Description To perform long DMA transfer, the System Address register shall be updated at every system boundary during a DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System Address register. These bits shall support when the DMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the Transfer Mode register is set to 1. 000b - 4KB(Detects A11 Carry out) 001b - 8KB(Detects A12 Carry out) 010b - 16KB(Detects A13 Carry out) 011b - 32KB(Detects A14 Carry out) 100b - 64KB(Detects A15 Carry out) 101b -128KB(Detects A16 Carry out) 110b - 256KB(Detects A17 Carry out) 111b - 512KB(Detects A18 Carry out)

Transfer_Block_Size

11:0

rw

0x0

This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. 0000h - No Data Transfer 0001h - 1 Byte 0002h - 2 Bytes 0003h - 3 Bytes 0004h - 4 Bytes --- --01FFh - 511 Bytes 0200h - 512 Bytes --- --0800h - 2048 Bytes

Register (sdio) Argument

Name Relative Address Absolute Address Argument 0x00000008 sd0: 0xE0100008 sd1: 0xE0101008

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Width Access Type Reset Value Description

32 bits rw 0x00000000 Argument register

Register Argument Details

Field Name Command_Argument Bits 31:0 Type rw Reset Value 0x0 Description The SD Command Argument is specified as bit 39-8 of Command-Format.

Register (sdio) Transfer_Mode_Command

Name Relative Address Absolute Address Width Access Type Reset Value Description Transfer_Mode_Command 0x0000000C sd0: 0xE010000C sd1: 0xE010100C 32 bits mixed 0x00000000 Transfer mode register Command register

Register Transfer_Mode_Command Details

Field Name reserved Command_Index Bits 31:30 29:24 Type ro rw Reset Value 0x0 0x0 Reserved This bit shall be set to the command number (CMD0-63, ACMD0-63). Description

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Field Name Command_Type

Bits 23:22

Type rw

Reset Value 0x0

Description There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register. Resume Command The HD re-starts the data transfer by restoring the registers in the range of 000-00Dh. The HC shall check for busy before starting write transfers. Abort Command If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset 00b - Normal 01b - Suspend 10b - Resume 11b - Abort

Data_Present_Select

21

rw

0x0

This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line (ex. CMD52) 2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b ex. CMD38) 3. Resume Command 0 - No Data Present 1 - Data Present

Command_Index_Che ck_Enable

20

rw

0x0

If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked. 0 - Disable 1 - Enable

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Field Name Command_CRC_Chec k_Enable

Bits 19

Type rw

Reset Value 0x0

Description If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. 0 - Disable 1 - Enable

reserved Response_Type_Select

18 17:16

ro rw

0x0 0x0

Reserved Response Type Select 00 - No Response 01 - Response length 136 10 - Response length 48 11 - Response length 48 check Busy after response

reserved

15:6

ro rw

0x0 0x0

Reserved This bit enables multiple block DAT line data transfers. 0 - Single Block 1 - Multiple Block

Multi_Single_Block_Sel 5 ect

Data_Transfer_Directio n_Select

rw

0x0

This bit defines the direction of DAT line data transfers. 0 - Write (Host to Card) 1 - Read (Card to Host)

reserved Auto_CMD12_Enable

3 2

ro rw

0x0 0x0

Reserved Multiple block transfers for memory require CMD12 to stop the transaction. When this bit is set to 1, the HC shall issue CMD12 automatically when last block transfer is completed. The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer. 0 - Disable 1 - Enable

Block_Count_Enable

rw

0x0

This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer. 0 - Disable 1 - Enable

DMA_Enable

rw

0x0

DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh). 0 - Disable 1 - Enable

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Register (sdio) Response0

Name Relative Address Absolute Address Width Access Type Reset Value Description Response0 0x00000010 sd0: 0xE0100010 sd1: 0xE0101010 32 bits ro 0x00000000 Response register

Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name Response0 Response1 Response2 Response3 Address 0xe0100010 0xe0100014 0xe0100018 0xe010001c

Register Response0 to Response3 Details

Field Name Command_Response Bits 31:0 Type ro Reset Value 0x0 Description command responses registers

Register (sdio) Buffer_Data_Port

Name Relative Address Absolute Address Width Access Type Reset Value Description Buffer_Data_Port 0x00000020 sd0: 0xE0100020 sd1: 0xE0101020 32 bits rw 0x00000000 Buffer data port register

Register Buffer_Data_Port Details

Field Name Buffer_Data Bits 31:0 Type rw Reset Value 0x0 Description The Host Controller Buffer can be accessed through this 32-bit Data Port Register.

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Register (sdio) Present_State

Name Relative Address Absolute Address Width Access Type Reset Value Description Present_State 0x00000024 sd0: 0xE0100024 sd1: 0xE0101024 25 bits ro 0x01F20000 Present State register

Register Present_State Details

Field Name CMD_Line_Signal_Lev el DAT_Bit3_Bit0_Line_Si gnal_Level Bits 24 23:20 Type ro ro Reset Value 0x1 0xF Description This status is used to check CMD line level to recover from errors, and for debugging. This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D23 - DAT[3] D22 - DAT[2] D21 - DAT[1] D20 - DAT[0] Write_Protect_Switch_ Pin_Level 19 ro 0x0 The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin. 0 - Write protected (SDWP# = 1) 1 - Write enabled (SDWP# = 0) Card_Detect_Pin_Level 18 ro 0x0 This bit reflects the inverse value of the SDCD# pin. 0 - No Card present (SDCD# = 1) 1 - Card present (SDCD# = 0) Card_State_Stable 17 ro 0x1 This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit. 0 - Reset of Debouncing 1 - No Card or Inserted

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Field Name Card_Inserted

Bits 16

Type ro

Reset Value 0x0

Description This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power. 0 - Reset or Debouncing or No Card 1 - Card Inserted

reserved Buffer_Read_Enable

15:12 11

ro ro

0x0 0x0

Reserved This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0 - Read Disable 1 - Read Enable.

Buffer_Write_Enable

10

ro

0x0

This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt. 0 - Write Disable 1 - Write Enable.

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Field Name Read_Transfer_Active

Bits 9

Type ro

Reset Value 0x0

Description This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: 1. After the end bit of the read command 2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: 1. When the last data block as specified by block length is transferred to the system. 2. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 1 - Transferring data 0 - No valid data

Write_Transfer_Active

ro

0x0

This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: 1. After the end bit of the write command. 2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: 1. After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) 2. After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 1 - transferring data 0 - No valid data

reserved DAT_Line_Active

7:3 2

ro ro

0x0 0x0

Reserved This bit indicates whether one of the DAT line on SD bus is in use. 1 - DAT line active 0 - DAT line inactive

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Field Name Command_Inhibit_DA T

Bits 1

Type ro

Reset Value 0x0

Description This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0. 1 - cannot issue command which uses the DAT line 0 - Can issue command which uses the DAT line

Command_Inhibit_CM D

ro

0x0

If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Note: The SD host controller requires couple of clocks to update this register bit after the command is posted to command register.

Register (sdio) Host_control_Power_control_Block_Gap_Control_Wakeup_control

Name Relative Address Absolute Address Width Access Type Reset Value Host_control_Power_control_Block_Gap_Control_Wakeup_control 0x00000028 sd0: 0xE0100028 sd1: 0xE0101028 32 bits mixed 0x00000000

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Description

Host control register Power control register Block gap control register Wake-up control register

Register Host_control_Power_control_Block_Gap_Control_Wakeup_control Details

Field Name reserved Wakeup_Event_Enable _On_SD_Card_Remov al Bits 31:27 26 Type ro rw Reset Value 0x0 0x0 Reserved This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit. 1 - Enable 0 - Disable Wakeup_Event_Enable _On_SD_Card_Insertio n 25 rw 0x0 This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake up Support) in CIS does not affect this bit. 1 - Enable 0 - Disable Wakeup_Event_Enable _On_Card_Interrupt 24 rw 0x0 This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. 1 - Enable 0 - Disable reserved Interrupt_At_Block_Ga p 23:20 19 ro rw 0x0 0x0 Reserved This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. Description

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Field Name Read_Wait_Control

Bits 18

Type rw

Reset Value 0x0

Description The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported 1 - Enable Read Wait Control 0 - Disable Read Wait Control

Continue_Request

17

rw

0x0

This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer. The HC automatically clears this bit in either of the following cases: 1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts. 2) In the case of a write transaction, the Write transfer active changes from 0 to 1 as the write transaction restarts. Therefore it is not necessary for Host driver to set this bit to 0. If Stop At Block Gap Request is set to 1, any write to this bit is ignored. 1 - Restart 0 - Ignored

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Appendix B: Register Details

Field Name Stop_At_Block_Gap_R equest

Bits 16

Type rw

Reset Value 0x0

Description This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The HC shall honor Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1. In case of write transfers in which the HD writes data to the Buffer Data Port register, the HD shall set this bit after all block data is written. If this bit is set to 1, the HD shall not write data to Buffer data port register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the Present State register. 1 - Stop 0 - Transfer

reserved SD_Bus_Voltage_Select

15:12 11:9

ro rw

0x0 0x0

Reserved By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected, the Host System shall not supply SD bus voltage 111b - 3.3 Flattop.) 110b - 3.0 V(Typ.) 101b - 1.8 V(Typ.) 100b - 000b - Reserved

SD_Bus_Power

rw

0x0

Before setting this bit, the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be cleared. 1 - Power on 0 - Power off

Card_detect_signal_det 7 etction

rw

0x0

This bit selects source for card detection. 1- The card detect test level is selected 0 -SDCD# is selected (for normal use)

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Appendix B: Register Details

Field Name

Bits

Type rw

Reset Value 0x0

Description This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set. 1 - Card Inserted 0 - No Card

Card_Detect_Test_Leve 6 l

reserved DMA_Select

5 4:3

ro rw

0x0 0x0

Reserved One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. 00 - SDMA is selected 01 - 32-bit Address ADMA1 is selected 10 -32-bit Address ADMA2 is selected 11 - 64-bit Address ADMA2 is selected

High_Speed_Enable

rw

0x0

This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20 MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52 MHz for MMC) 1 - High Speed Mode 0 - Normal Speed Mode

Data_Transfer_Width_ SD1_or_SD4

rw

0x0

This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. 1 - 4 bit mode 0 - 1 bit mode

LED_Control

rw

0x0

This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction. 1 - LED on 0 - LED off

Register (sdio) Clock_Control_Timeout_control_Software_reset

Name Relative Address Clock_Control_Timeout_control_Software_reset 0x0000002C

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Appendix B: Register Details

Absolute Address Width Access Type Reset Value Description

sd0: 0xE010002C sd1: 0xE010102C 27 bits mixed 0x00000000 Clock Control register Timeout control register Software reset register

Register Clock_Control_Timeout_control_Software_reset Details

Field Name Software_Reset_for_D AT_Line Bits 26 Type rw Reset Value 0x0 Description Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register Buffer is cleared and Initialized. Present State register Buffer read Enable Buffer write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit (DAT) Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write Ready Block Gap Event Transfer Complete 1 - Reset 0 - Work Software_Reset_for_C MD_Line 25 rw 0x0 Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register Command Inhibit (CMD) Normal Interrupt Status register Command Complete 1 - Reset 0 - Work

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Appendix B: Register Details

Field Name

Bits

Type rw

Reset Value 0x0

Description This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD. 1 - Reset 0 - Work

Software_Reset_for_All 24

reserved

23:20

ro rw

0x0 0x0

Reserved This value determines the interval by which DAT line time-outs are detected. Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate Timeout generation. Timeout clock frequency will be generated by dividing the sdclockTMCLK by this value. When setting this register, prevent inadvertent Timeout events by clearing the Data Time-out Error Status Enable (in the Error Interrupt Status Enable register) 1111 - Reserved 1110 - TMCLK * 2^27 ----------------------------------------------------------0001 - TMCLK * 2^14 0000 - TMCLK * 2^13

Data_Timeout_Counter 19:16 _Value_

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Appendix B: Register Details

Field Name SDCLK_Frequency_Sel ect

Bits 15:8

Type rw

Reset Value 0x0

Description This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed. 80h - base clock divided by 256 40h - base clock divided by 128 20h - base clock divided by 64 10h - base clock divided by 32 08h - base clock divided by 16 04h - base clock divided by 8 02h - base clock divided by 4 01h - base clock divided by 2 00h - base clock(10MHz-63MHz) Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register. 1) 25 MHz divider value 2) 400 KHz divider value The frequency of the SDCLK is set by the following formula: Clock Frequency = (Baseclock) / divisor. Thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency. Maximum Frequency for SD = 50Mhz (base clock) Maximum Frequency for MMC = 52Mhz (base clock) Minimum Frequency = 195.3125Khz (50Mhz / 256), same calc for MMC also

reserved SD_Clock_Enable

7:3 2

ro rw

0x0 0x0

Reserved The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared. 1 - Enable 0 - Disable

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Appendix B: Register Details

Field Name Internal_Clock_Stable

Bits 1

Type ro

Reset Value 0x0

Description This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock oscillator that requires setup time. 1 - Ready 0 - Not Ready

Internal_Clock_Enable

rw

0x0

This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection. 1 - Oscillate 0 - Stop

Register (sdio) Normal_interrupt_status_Error_interrupt_status

Name Relative Address Absolute Address Width Access Type Reset Value Description Normal_interrupt_status_Error_interrupt_status 0x00000030 sd0: 0xE0100030 sd1: 0xE0101030 30 bits mixed 0x00000000 Normal interrupt status register Error interrupt status register

Register Normal_interrupt_status_Error_interrupt_status Details

Field Name Ceata_Error_Status Bits 29 Type wtc Reset Value 0x0 Description Occurs when ATA command termination has occurred due to an error condition the device has encountered. 0 - no error 1 - error Target_Response_error 28 wtc 0x0 Occurs when detecting ERROR in m_hresp(dma transaction) 0 - no error 1 - error

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Field Name reserved ADMA_Error

Bits 27:26 25

Type ro wtc

Reset Value 0x0 0x0 Reserved

Description

This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register. 1- Error 0 -No error

Auto_CMD12_Error

24

wtc

0x0

Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error. 0 - No Error 1 - Error

Current_Limit_Error

23

wtc

0x0

By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function. 0 - No Error 1 - Power Fail

Data_End_Bit_Error

22

wtc

0x0

Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. 0 - No Error 1 - Error

Data_CRC_Error

21

wtc

0x0

Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than '010'. 0 - No Error 1 - Error

Data_Timeout_Error

20

wtc

0x0

Occurs when detecting one of following timeout conditions. 1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout 0 - No Error 1 - Timeout

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Appendix B: Register Details

Field Name Command_Index_Erro r

Bits 19

Type wtc

Reset Value 0x0

Description Occurs if a Command Index error occurs in the Command Response. 0 - No Error 1 - Error

Command_End_Bit_Er ror

18

wtc

0x0

Occurs when detecting that the end bit of a command response is 0. 0 - No Error 1 - End Bit Error Generated

Command_CRC_Error

17

wtc

0x0

Command CRC Error is generated in two cases. 1. If a response is returned and the Command Timeout Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict. 0 - No Error 1 - CRC Error Generated

Command_Timeout_Er 16 ror

wtc

0x0

Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC. 0 - No Error 1 - Timeout

Error_Interrupt

15

ro

0x0

If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first. 0 - No Error. 1 - Error.

reserved

14:11

ro wtc

0x0 0x0

Reserved This status is set if the boot operation get terminated 0 - Boot operation is not terminated. 1 - Boot operation is terminated

Boot_terminate_Interru 10 pt

Boot_ack_rcv

wtc

0x0

This status is set if the boot acknowledge is received from device. 0 - Boot ack is not received. 1 - Boot ack is received.

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Appendix B: Register Details

Field Name Card_Interrupt

Bits 8

Type ro

Reset Value 0x0

Description Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again. 0 - No Card Interrupt 1 - Generate Card Interrupt

Card_Removal

wtc

0x0

This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated. 0 - Card State Stable or Debouncing 1 - Card Removed

Card_Insertion

wtc

0x0

This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated. 0 - Card State Stable or Debouncing 1 - Card Inserted

Buffer_Read_Ready

wtc

0x0

This status is set if the Buffer Read Enable changes from 0 to 1. 0 - Not Ready to read Buffer. 1 - Ready to read Buffer.

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Appendix B: Register Details

Field Name Buffer_Write_Ready

Bits 4

Type wtc

Reset Value 0x0

Description This status is set if the Buffer Write Enable changes from 0 to 1. 0 - Not Ready to Write Buffer. 1 - Ready to Write Buffer.

DMA_Interrupt

wtc

0x0

This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size register. 0 - No DMA Interrupt 1 - DMA Interrupt is Generated

Block_Gap_Event

wtc

0x0

If the Stop At Block Gap Request in the Block Gap Control Register is set, this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The Read Wait must be supported in order to use this function). Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at SD Bus timing). 0 - No Block Gap Event 1 - Transaction stopped at Block Gap

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Appendix B: Register Details

Field Name Transfer_Complete

Bits 1

Type wtc

Reset Value 0x0

Description This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid data has been read to the Host System). Write Transaction: This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released). Note: Transfer Complete has higher priority than Data Timeout Error. If both bits are set to 1, the data transfer can be considered complete 0 - No Data Transfer Complete 1 - Data Transfer Complete

Command_Complete

wtc

0x0

This bit is set when get the end bit of the command response (Except Auto CMD12). Note: Command Timeout Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly. 0 - No Command Complete 1 - Command Complete

Register (sdio) Normal_interrupt_status_enable_Error_interrupt_status_enable

Name Relative Address Normal_interrupt_status_enable_Error_interrupt_status_enable 0x00000034

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Absolute Address Width Access Type Reset Value Description

sd0: 0xE0100034 sd1: 0xE0101034 30 bits mixed 0x00000000 Normal interrupt status enable register Error interrupt status enable register

Register Normal_interrupt_status_enable_Error_interrupt_status_enable Details

Field Name Ceata_Error_Status_En able Target_Response_Error _Status_Enable reserved Bits 29 28 27:26 Type rw rw ro rw rw rw rw rw rw rw rw rw rw ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled Reserved 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 23 22 21 20 19 18 17 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled The HC shall control error Interrupts using the Error Interrupt Status Enable register. Reserved Description

ADMA_Error_Status_E 25 nable Auto_CMD12_Error_St atus_Enable Current_Limit_Error_S tatus_Enable Data_End_Bit_Error_St atus_Enable Data_CRC_Error_Statu s_Enable Data_Timeout_Error_S tatus_Enable Command_Index_Erro r_Status_Enable Command_End_Bit_Er ror_Status_Enable Command_CRC_Error _Status_Enable 24

Command_Timeout_Er 16 ror_Status_Enable Fixed_to_0 reserved 15 14:11

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Appendix B: Register Details

Field Name

Bits

Type rw rw rw

Reset Value 0x0 0x0 0x0 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled

Description

Boot_terminate_Interru 10 pt_enable Boot_ack_rcv_enable Card_Interrupt_Status _Enable 9 8

If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD should clear the Card Interrupt Status Enable before servicing the Card Interrupt and should set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts. 0 - Masked 1 - Enabled

Card_Removal_Status_ Enable Card_Insertion_Status_ Enable Buffer_Read_Ready_St atus_Enable Buffer_Write_Ready_St atus_Enable DMA_Interrupt_Status _Enable Block_Gap_Event_Stat us_Enable Transfer_Complete_Sta tus_Enable Command_Complete_ Status_Enable

7 6 5 4 3 2 1 0

rw rw rw rw rw rw rw rw

0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled

Register (sdio) Normal_interrupt_signal_enable_Error_interrupt_signal_enable

Name Relative Address Absolute Address Width Access Type Normal_interrupt_signal_enable_Error_interrupt_signal_enable 0x00000038 sd0: 0xE0100038 sd1: 0xE0101038 30 bits mixed

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Appendix B: Register Details

Reset Value Description

0x00000000 Normal interrupt signal enable register Error interrupt signal enable register

Register Normal_interrupt_signal_enable_Error_interrupt_signal_enable Details

Field Name Ceata_Error_Signal_En able Target_Response_Error _Signal_Enable reserved ADMA_Error_Signal_ Enable Auto_CMD12_Error_Si gnal_Enable Current_Limit_Error_S ignal_Enable Data_End_Bit_Error_Si gnal_Enable Data_CRC_Error_Sign al_Enable Bits 29 28 27:26 25 24 23 22 21 Type rw rw ro rw rw rw rw rw rw rw rw rw rw ro ro rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled Reserved 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 18 17 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled The HD shall control error Interrupts using the Error Interrupt Signal Enable register. Reserved 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled Description

Data_Timeout_Error_Si 20 gnal_Enable Command_Index_Erro r_Signal_Enable Command_End_Bit_Er ror_Signal_Enable Command_CRC_Error _Signal_Enable 19

Command_Timeout_Er 16 ror_Signal_Enable Fixed_to_0 reserved 15 14:11

Boot_terminate_Interru 10 pt_signal_enable Boot_ack_rcv_signal_e nable 9

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Appendix B: Register Details

Field Name Card_Interrupt_Signal _Enable Card_Removal_Signal_ Enable

Bits 8 7

Type rw rw rw rw rw rw rw rw rw

Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled 0 - Masked 1 - Enabled

Description

Card_Insertion_Signal_ 6 Enable Buffer_Read_Ready_Si gnal_Enable Buffer_Write_Ready_Si gnal_Enable DMA_Interrupt_Signal _Enable Block_Gap_Event_Sign al_Enable Transfer_Complete_Sig nal_Enable Command_Complete_ Signal_Enable 5 4 3 2 1 0

Register (sdio) Auto_CMD12_error_status

Name Relative Address Absolute Address Width Access Type Reset Value Description Auto_CMD12_error_status 0x0000003C sd0: 0xE010003C sd1: 0xE010103C 8 bits ro 0x00000000 Auto CMD12 error status register

Register Auto_CMD12_error_status Details

When Auto CMD12 Error Status is set, the HD shall check this register to identify what kind of error Auto CMD12 indicated. This register is valid only when the Auto CMD12 Error is set.

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Appendix B: Register Details

Field Name Command_Not_Issued _By_Auto_CMD12_Err or

Bits 7

Type ro

Reset Value 0x0

Description Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register. 0 - No Error 1 - Not Issued

reserved Auto_CMD12_Index_E rror

6:5 4

ro ro

0x0 0x0

Reserved Occurs if the Command Index error occurs in response to a command. 0 - No Error 1 - Error

Auto_CMD12_End_Bit _Error

ro

0x0

Occurs when detecting that the end bit of command response is 0. 0 - No Error 1 - End Bit Error Generated

Auto_CMD12_CRC_Er ror

ro

0x0

Occurs when detecting a CRC error in the command response. 0 - No Error 1 - CRC Error Generated

Auto_CMD12_Timeout _Error

ro

0x0

Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (D04 D02) are meaningless. 0 - No Error 1 - Timeout

Auto_CMD12_not_Exe cuted

ro

0x0

If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits (D04 - D01) are meaningless. 0 - Executed 1 - Not Executed

Register (sdio) Capabilities

Name Relative Address Absolute Address Width Capabilities 0x00000040 sd0: 0xE0100040 sd1: 0xE0101040 31 bits

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Access Type Reset Value Description

ro 0x69EC0080 Capabilities register

Register Capabilities Details

This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization.
Field Name Spi_block_mode Bits 30 Type ro Reset Value 0x1 Spi block mode 0 - Not Supported 1 - Supported Spi_mode 29 ro 0x1 Spi mode 0 - Not Supported 1 - Supported 64_bit_System_Bus_Su pport 28 ro 0x0 1 - supports 64 bit system address 0 - Does not support 64 bit system address Interrupt_mode 27 ro 0x1 Interrupt mode 0 - Not Supported 1 - Supported Voltage_Support_1_8_ V Voltage_Support_3_0_ V Voltage_Support_3_3_ V Suspend_Resume_Sup port 26 25 24 23 ro ro ro ro 0x0 0x0 0x1 0x1 0 - 1.8 V Not Supported 1 - 1.8 V Supported 0 - 3.0 V Not Supported 1 - 3.0 V Supported 0 - 3.3 V Not Supported 1 - 3.3 V Supported This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands. 0 - Not Supported 1 - Supported SDMA_Support 22 ro 0x1 This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. 0 - SDMA Not Supported 1 - SDMA Supported. Description

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Appendix B: Register Details

Field Name High_Speed_Support

Bits 21

Type ro

Reset Value 0x1

Description This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 MHz (for SD)/ 20MHz to 52MHz (for MMC). 0 - High Speed Not Supported 1 - High Speed Supported

reserved ADMA2_Support Extended_Media_Bus_ Support

20 19 18

ro ro ro

0x0 0x1 0x1

Reserved 1 - ADMA2 support. 0 - ADMA2 not support This bit indicates whether the Host Controller is capable bus. 1 - Extended Media Bus Supported 0 - Extended Media Bus not Supported

Max_Block_Length

17:16

ro

0x0

This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 00 - 512 byte 01 - 1024 byte 10 - 2048 byte 11 - 4096 byte

reserved reserved Timeout_Clock_Unit

15:14 13:8 7

ro ro ro

0x0 0x0 0x1

Reserved Reserved. Do not modify. This bit shows the unit of base clock frequency used to detect Data Timeout Error. 0 - KHz 1 - MHz

reserved reserved

6 5:0

ro ro

0x0 0x0

Reserved Reserved. Do not modify.

Register (sdio) Maximum_current_capabilities

Name Relative Address Absolute Address Width Access Type Reset Value Maximum_current_capabilities 0x00000048 sd0: 0xE0100048 sd1: 0xE0101048 24 bits ro 0x00000001

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Description

Maximum current capabilities register

Register Maximum_current_capabilities Details

Field Name Maximum_Current_for _1_8V Maximum_Current_for _3_0V Maximum_Current_for _3_3V Bits 23:16 15:8 7:0 Type ro ro ro Reset Value 0x0 0x0 0x1 Description Maximum Current for 1.8V Maximum Current for 3.0V Maximum Current for 3.3V

Register (sdio) Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error _interrupt_status

Name Relative Address Absolute Address Width Access Type Reset Value Description Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interru pt_status 0x00000050 sd0: 0xE0100050 sd1: 0xE0101050 32 bits mixed 0x00000000 Force event register for Auto CMD12 error status register Force event register for error interrupt status

Register Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status Details

The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD12 Error Status Register can be written. Writing 1:set each bit of the Auto CMD12 Error Status Register Writing 0:no effect. The Force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1:set each bit of the Error Interrupt Status Register Writing 0:no effect

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Field Name Force_Event_for_Vend or_Specific_Error_Stat us

Bits 31:30

Type wo

Reset Value 0x0

Description Additional status bits can be defined in this register by the vendor. 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Ceata _error

29

wo

0x0

Force Event for Ceata Error 1 - Interrupt is generated 0 - No interrupt

Force_event_for_Target _Response_error

28

wo

0x0

Force Event for Target Response Error 1 - Interrupt is generated 0 - No interrupt

reserved Force_Event_for_ADM A_Error

27:26 25

ro wo

0x0 0x0

Reserved Force Event for ADMA Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Auto _CMD12_Error

24

wo

0x0

Force Event for Auto CMD12 Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Curre nt_Limit_Error

23

wo

0x0

Force Event for Current Limit Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Data_ End_Bit_Error

22

wo

0x0

Force Event for Data End Bit Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Data_ CRC_Error

21

wo

0x0

Force Event for Data CRC Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Data_ _Timeout_Error

20

wo

0x0

Force Event for Data Timeout Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Com mand_Index_Error

19

wo

0x0

Force Event for Command Index Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Com mand_End_Bit_Error

18

wo

0x0

Force Event for Command End Bit Error 1 - Interrupt is generated 0 - No interrupt

Force_Event_for_Com mand_CRC_Error

17

wo

0x0

Force Event for Command CRC Error 1 - Interrupt is generated 0 - No interrupt

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Field Name Force_Event_for_Com mand_Timeout_Error

Bits 16

Type wo

Reset Value 0x0

Description Force Event for Command Timeout Error 1 - Interrupt is generated 0 - No interrupt

reserved Force_Event_for_com mand_not_issued_by_ Auto_CMD12_Error reserved Force_Event_for_Auto _CMD12_Index_Error Force_Event_for_Auto _CMD12_End_bit_Erro r Force_Event_for_Auto _CMD12_CRC_Error Force_Event_for_Auto _CMD12_timeout_Erro r Force_Event_for_Auto _CMD12_NOT_Execut ed

15:8 7

ro wo

0x0 0x0

Reserved 1 - Interrupt is generated 0 - no interrupt

6:5 4 3

ro wo wo

0x0 0x0 0x0

Reserved 1 - Interrupt is generated 0 - no interrupt 1 - Interrupt is generated 0 - no interrupt

2 1

wo wo

0x0 0x0

1 - Interrupt is generated 0 - no interrupt 1 - Interrupt is generated 0 - no interrupt

wo

0x0

1 - Interrupt is generated 0 - no interrupt

Register (sdio) ADMA_error_status

Name Relative Address Absolute Address Width Access Type Reset Value Description ADMA_error_status 0x00000054 sd0: 0xE0100054 sd1: 0xE0101054 3 bits mixed 0x00000000 ADMA error status register

Register ADMA_error_status Details

When ADMA Error Interrupt occurs, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor.

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Field Name ADMA_Length_Mism atch_Error

Bits 2

Type wtc

Reset Value 0x0

Description This error occurs in the following 2 cases. 1. While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. 2. Total data length can not be divided by the block length. 1 - Error 0 - No error

ADMA_Error_State

1:0

ro

0x0

This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state. D01 - D00 : ADMA Error State when error is occurred Contents of SYS_SDR register 00 - ST_STOP (Stop DMA) Points next of the error descriptor 01 - ST_FDS (Fetch Descriptor) Points the error descriptor 10 - Never set this state (Not used) 11 - ST_TFR (Transfer Data) Points the next of the error descriptor

Register (sdio) ADMA_system_address

Name Relative Address Absolute Address Width Access Type Reset Value Description ADMA_system_address 0x00000058 sd0: 0xE0100058 sd1: 0xE0101058 32 bits rw 0x00000000 ADMA system address register

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Register ADMA_system_address Details

Field Name ADMA_System_Addre ss Bits 31:0 Type rw Reset Value 0x0 Description This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b. 32-bit Address ADMA Register Value 32bit System Address 0x00000000 0x00000000 0x00000004 0x00000004 to 0xFFFFFFFC 0xFFFFFFFC

Register (sdio) Boot_Timeout_control

Name Relative Address Absolute Address Width Access Type Reset Value Description Boot_Timeout_control 0x00000060 sd0: 0xE0100060 sd1: 0xE0101060 32 bits rw 0x00000000 Boot Timeout control register

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Register Boot_Timeout_control Details

Field Name Boot_Data_Timeout_C ounter_Value Bits 31:0 Type rw Reset Value 0x0 Description This value determines the interval by which DAT line time-outs are detected during boot operation for MMC3.31 card. The value is in number of sd clock.

Register (sdio) Debug_Selection

Name Relative Address Absolute Address Width Access Type Reset Value Description Debug_Selection 0x00000064 sd0: 0xE0100064 sd1: 0xE0101064 1 bits wo 0x00000000 Debug Selection Register

Register Debug_Selection Details

Field Name Debug_sel Bits 0 Type wo Reset Value 0x0 Description 1- cmd register, Interrupt status, transmitter module, ahb_iface module and clk sdcard signals are probed out. 0 - receiver module and fifo_ctrl module signals are probed out

Register (sdio) SPI_interrupt_support

Name Relative Address Absolute Address Width Access Type Reset Value Description SPI_interrupt_support 0x000000F0 sd0: 0xE01000F0 sd1: 0xE01010F0 8 bits rw 0x00000000 SPI interrupt support register

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Register SPI_interrupt_support Details

Field Name SPI_INT_SUPPORT Bits 7:0 Type rw Reset Value 0x0 Description This bit is set to indicate the assertion of interrupts in the SPI mode at any time, irrespective of the status of the card select (CS) line. If this bit is zero, then SDIO card can only assert the interrupt line in the SPI mode when the CS line is asserted.

Register (sdio) Slot_interrupt_status_Host_controller_version

Name Relative Address Absolute Address Width Access Type Reset Value Description Slot_interrupt_status_Host_controller_version 0x000000FC sd0: 0xE01000FC sd1: 0xE01010FC 32 bits ro 0x89010000 Slot interrupt status register and Host controller version register

Register Slot_interrupt_status_Host_controller_version Details

Field Name Bits Type ro ro Reset Value 0x89 0x1 Description This status is reserved for the vendor version number. The HD should not use this status. This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00 - SD Host Specification version 1.0 01 - SD Host Specification version 2.00 including only the feature of the Test Register others - Reserved

Vendor_Version_Numb 31:24 er Specification_Version_ Number 23:16

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Field Name reserved Interrupt_Signal_for_E ach_Slot

Bits 15:8 7:0

Type ro ro

Reset Value 0x0 0x0 Reserved

Description

These status bit indicate the logical OR of Interrupt signal and Wakeup signal for each slot. A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots. the HD can know which interrupt is generated by reading these status bits. By a power on reset or by Software Reset For All, the Interrupt signal shall be de asserted and this status shall read 00h. Bit 00 - Slot 1 Bit 01 - Slot 2 Bit 02 - Slot 3 ----- ----Bit 07 - Slot 8

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B.28 System Level Control Registers (slcr)

Module Name Base Address Description Vendor Info System Level Control Registers (slcr) 0xF8000000 slcr System Level Control Registers Xilinx Zynq slcr

Register Summary
Register Name SCL SLCR_LOCK SLCR_UNLOCK SLCR_LOCKSTA ARM_PLL_CTRL DDR_PLL_CTRL IO_PLL_CTRL PLL_STATUS ARM_PLL_CFG DDR_PLL_CFG IO_PLL_CFG ARM_CLK_CTRL DDR_CLK_CTRL DCI_CLK_CTRL APER_CLK_CTRL USB0_CLK_CTRL USB1_CLK_CTRL GEM0_RCLK_CTRL GEM1_RCLK_CTRL GEM0_CLK_CTRL GEM1_CLK_CTRL SMC_CLK_CTRL LQSPI_CLK_CTRL Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000100 0x00000104 0x00000108 0x0000010C 0x00000110 0x00000114 0x00000118 0x00000120 0x00000124 0x00000128 0x0000012C 0x00000130 0x00000134 0x00000138 0x0000013C 0x00000140 0x00000144 0x00000148 0x0000014C Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type rw wo wo ro rw rw rw ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x00000000 0x00000000 0x00000000 0x00000001 0x0001A008 0x0001A008 0x0001A008 0x0000003F 0x00177EA0 0x00177EA0 0x00177EA0 0x1F000400 0x18400003 0x01E03201 0x01FFCCCD 0x00101941 0x00101941 0x00000001 0x00000001 0x00003C01 0x00003C01 0x00003C21 0x00002821 Description Secure Configuration Lock SLCR Write Protection Lock SLCR Write Protection Unlock SLCR Write Protection Status ARM PLL Control DDR PLL Control IO PLL Control PLL Status ARM PLL Configuration DDR PLL Configuration IO PLL Configuration CPU Clock Control DDR Clock Control DCI clock control AMBA Peripheral Clock Control USB 0 ULPI Clock Control USB 1 ULPI Clock Control GigE 0 Rx Clock and Rx Signals Select GigE 1 Rx Clock and Rx Signals Select GigE 0 Ref Clock Control GigE 1 Ref Clock Control SMC Ref Clock Control Quad SPI Ref Clock Control

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Register Name SDIO_CLK_CTRL UART_CLK_CTRL SPI_CLK_CTRL CAN_CLK_CTRL CAN_MIOCLK_CTRL DBG_CLK_CTRL PCAP_CLK_CTRL TOPSW_CLK_CTRL FPGA0_CLK_CTRL FPGA0_THR_CTRL FPGA0_THR_CNT FPGA0_THR_STA FPGA1_CLK_CTRL FPGA1_THR_CTRL FPGA1_THR_CNT FPGA1_THR_STA FPGA2_CLK_CTRL FPGA2_THR_CTRL FPGA2_THR_CNT FPGA2_THR_STA FPGA3_CLK_CTRL FPGA3_THR_CTRL FPGA3_THR_CNT FPGA3_THR_STA CLK_621_TRUE PSS_RST_CTRL DDR_RST_CTRL TOPSW_RST_CTRL DMAC_RST_CTRL USB_RST_CTRL

Address 0x00000150 0x00000154 0x00000158 0x0000015C 0x00000160 0x00000164 0x00000168 0x0000016C 0x00000170 0x00000174 0x00000178 0x0000017C 0x00000180 0x00000184 0x00000188 0x0000018C 0x00000190 0x00000194 0x00000198 0x0000019C 0x000001A0 0x000001A4 0x000001A8 0x000001AC 0x000001C4 0x00000200 0x00000204 0x00000208 0x0000020C 0x00000210

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw ro rw rw rw ro rw rw rw ro rw rw rw ro rw rw rw rw rw rw

Reset Value 0x00001E03 0x00003F03 0x00003F03 0x00501903 0x00000000 0x00000F03 0x00000F01 0x00000000 0x00101800 0x00000000 0x00000000 0x00010000 0x00101800 0x00000000 0x00000000 0x00010000 0x00101800 0x00000000 0x00000000 0x00010000 0x00101800 0x00000000 0x00000000 0x00010000 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description SDIO Ref Clock Control UART Ref Clock Control SPI Ref Clock Control CAN Ref Clock Control CAN MIO Clock Control SoC Debug Clock Control PCAP Clock Control Central Interconnect Clock Control PL Clock 0 Output control PL Clock 0 Throttle control PL Clock 0 Throttle Count control PL Clock 0 Throttle Status read PL Clock 1 Output control PL Clock 1 Throttle control PL Clock 1 Throttle Count PL Clock 1 Throttle Status control PL Clock 2 output control PL Clock 2 Throttle Control PL Clock 2 Throttle Count PL Clock 2 Throttle Status PL Clock 3 output control PL Clock 3 Throttle Control PL Clock 3 Throttle Count PL Clock 3 Throttle Status CPU Clock Ratio Mode select PS Software Reset Control DDR Software Reset Control Central Interconnect Reset Control DMAC Software Reset Control USB Software Reset Control

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Register Name GEM_RST_CTRL SDIO_RST_CTRL SPI_RST_CTRL CAN_RST_CTRL I2C_RST_CTRL UART_RST_CTRL GPIO_RST_CTRL LQSPI_RST_CTRL SMC_RST_CTRL OCM_RST_CTRL FPGA_RST_CTRL A9_CPU_RST_CTRL RS_AWDT_CTRL REBOOT_STATUS BOOT_MODE APU_CTRL WDT_CLK_SEL PSS_IDCODE DDR_URGENT DDR_CAL_START DDR_REF_START DDR_CMD_STA DDR_URGENT_SEL DDR_DFI_STATUS MIO_PIN_00 MIO_PIN_01 MIO_PIN_02 MIO_PIN_03 MIO_PIN_04 MIO_PIN_05 MIO_PIN_06 MIO_PIN_07

Address 0x00000214 0x00000218 0x0000021C 0x00000220 0x00000224 0x00000228 0x0000022C 0x00000230 0x00000234 0x00000238 0x00000240 0x00000244 0x0000024C 0x00000258 0x0000025C 0x00000300 0x00000304 0x00000530 0x00000600 0x0000060C 0x00000614 0x00000618 0x0000061C 0x00000620 0x00000700 0x00000704 0x00000708 0x0000070C 0x00000710 0x00000714 0x00000718 0x0000071C

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw mixed rw rw ro rw mixed mixed mixed rw mixed rw rw rw rw rw rw rw rw

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01F33F0F 0x00000000 0x00000000 0x00400000 x 0x00000000 0x00000000 x 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001601 0x00001601 0x00000601 0x00000601 0x00000601 0x00000601 0x00000601 0x00000601

Description Gigabit Ethernet SW Reset Control SDIO Software Reset Control SPI Software Reset Control CAN Software Reset Control I2C Software Reset Control UART Software Reset Control GPIO Software Reset Control Quad SPI Software Reset Control SMC Software Reset Control OCM Software Reset Control FPGA Software Reset Control CPU Reset and Clock control Watchdog Timer Reset Control Reboot Status, persistent Boot Mode Strapping Pins APU Control SWDT clock source select PS IDCODE DDR Urgent Control DDR Calibration Start Triggers DDR Refresh Start Triggers DDR Command Store Status DDR Urgent Select DDR DFI status MIO Pin 0 Control MIO Pin 1 Control MIO Pin 2 Control MIO Pin 3 Control MIO Pin 4 Control MIO Pin 5 Control MIO Pin 6 Control MIO Pin 7 Control

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Register Name MIO_PIN_08 MIO_PIN_09 MIO_PIN_10 MIO_PIN_11 MIO_PIN_12 MIO_PIN_13 MIO_PIN_14 MIO_PIN_15 MIO_PIN_16 MIO_PIN_17 MIO_PIN_18 MIO_PIN_19 MIO_PIN_20 MIO_PIN_21 MIO_PIN_22 MIO_PIN_23 MIO_PIN_24 MIO_PIN_25 MIO_PIN_26 MIO_PIN_27 MIO_PIN_28 MIO_PIN_29 MIO_PIN_30 MIO_PIN_31 MIO_PIN_32 MIO_PIN_33 MIO_PIN_34 MIO_PIN_35 MIO_PIN_36 MIO_PIN_37 MIO_PIN_38 MIO_PIN_39 MIO_PIN_40 MIO_PIN_41

Address 0x00000720 0x00000724 0x00000728 0x0000072C 0x00000730 0x00000734 0x00000738 0x0000073C 0x00000740 0x00000744 0x00000748 0x0000074C 0x00000750 0x00000754 0x00000758 0x0000075C 0x00000760 0x00000764 0x00000768 0x0000076C 0x00000770 0x00000774 0x00000778 0x0000077C 0x00000780 0x00000784 0x00000788 0x0000078C 0x00000790 0x00000794 0x00000798 0x0000079C 0x000007A0 0x000007A4

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x00000601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601

Description MIO Pin 8 Control MIO Pin 9 Control MIO Pin 10 Control MIO Pin 11 Control MIO Pin 12 Control MIO Pin 13 Control MIO Pin 14 Control MIO Pin 15 Control MIO Pin 16 Control MIO Pin 17 Control MIO Pin 18 Control MIO Pin 19 Control MIO Pin 20 Control MIO Pin 21 Control MIO Pin 22 Control MIO Pin 23 Control MIO Pin 24 Control MIO Pin 25 Control MIO Pin 26 Control MIO Pin 27 Control MIO Pin 28 Control MIO Pin 29 Control MIO Pin 30 Control MIO Pin 31 Control MIO Pin 32 Control MIO Pin 33 Control MIO Pin 34 Control MIO Pin 35 Control MIO Pin 36 Control MIO Pin 37 Control MIO Pin 38 Control MIO Pin 39 Control MIO Pin 40 Control MIO Pin 41 Control

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Register Name MIO_PIN_42 MIO_PIN_43 MIO_PIN_44 MIO_PIN_45 MIO_PIN_46 MIO_PIN_47 MIO_PIN_48 MIO_PIN_49 MIO_PIN_50 MIO_PIN_51 MIO_PIN_52 MIO_PIN_53 MIO_LOOPBACK MIO_MST_TRI0 MIO_MST_TRI1 SD0_WP_CD_SEL SD1_WP_CD_SEL LVL_SHFTR_EN OCM_CFG Reserved GPIOB_CTRL GPIOB_CFG_CMOS18 GPIOB_CFG_CMOS25 GPIOB_CFG_CMOS33 GPIOB_CFG_HSTL GPIOB_DRVR_BIAS_C TRL DDRIOB_ADDR0 DDRIOB_ADDR1

Address 0x000007A8 0x000007AC 0x000007B0 0x000007B4 0x000007B8 0x000007BC 0x000007C0 0x000007C4 0x000007C8 0x000007CC 0x000007D0 0x000007D4 0x00000804 0x0000080C 0x00000810 0x00000830 0x00000834 0x00000900 0x00000910 0x00000A1C 0x00000B00 0x00000B04 0x00000B08 0x00000B0C 0x00000B14 0x00000B18 0x00000B40 0x00000B44

Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw mixed rw rw

Reset Value 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00001601 0x00000000 0xFFFFFFFF 0x003FFFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00010101 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000800 0x00000800

Description MIO Pin 42 Control MIO Pin 43 Control MIO Pin 44 Control MIO Pin 45 Control MIO Pin 46 Control MIO Pin 47 Control MIO Pin 48 Control MIO Pin 49 Control MIO Pin 50 Control MIO Pin 51 Control MIO Pin 52 Control MIO Pin 53 Control Loopback function within MIO MIO pin Tri-state Enables, 31:0 MIO pin Tri-state Enables, 53:32 SDIO 0 WP CD select SDIO 1 WP CD select Level Shifters Enable OCM Address Mapping Reserved PS IO Buffer Control MIO GPIOB CMOS 1.8V config MIO GPIOB CMOS 2.5V config MIO GPIOB CMOS 3.3V config MIO GPIOB HSTL config MIO GPIOB Driver Bias Control DDR IOB Config for A[14:0], CKE and DRST_B DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B DDR IOB Config for Data 15:0 DDR IOB Config for Data 31:16 DDR IOB Config for DQS 1:0

DDRIOB_DATA0 DDRIOB_DATA1 DDRIOB_DIFF0

0x00000B48 0x00000B4C 0x00000B50

32 32 32

rw rw rw

0x00000800 0x00000800 0x00000800

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Register Name DDRIOB_DIFF1 DDRIOB_CLOCK DDRIOB_DRIVE_SLE W_ADDR DDRIOB_DRIVE_SLE W_DATA DDRIOB_DRIVE_SLE W_DIFF DDRIOB_DRIVE_SLE W_CLOCK DDRIOB_DDR_CTRL DDRIOB_DCI_CTRL DDRIOB_DCI_STATU S

Address 0x00000B54 0x00000B58 0x00000B5C

Width 32 32 32

Type rw rw rw

Reset Value 0x00000800 0x00000800 0x00000000

Description DDR IOB Config for DQS 3:2 DDR IOB Config for Clock Output Drive and Slew controls for Address and Command pins of the DDR Interface Drive and Slew controls for DQ pins of the DDR Interface Drive and Slew controls for DQS pins of the DDR Interface Drive and Slew controls for Clock pins of the DDR Interface DDR IOB Buffer Control DDR IOB DCI Config DDR IO Buffer DCI Status

0x00000B60 0x00000B64 0x00000B68 0x00000B6C 0x00000B70 0x00000B74

32 32 32 32 32 32

rw rw rw rw rw mixed

0x00000000 0x00000000 0x00000000 0x00000000 0x00000020 0x00000000

Register (slcr) SCL

Name Relative Address Absolute Address Width Access Type Reset Value Description SCL 0x00000000 0xF8000000 32 bits rw 0x00000000 Secure Configuration Lock

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Register SCL Details

Field Name reserved LOCK Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Secure configuration lock for these slcr registers: SCL, PSS_RST_CTRL, APU_CTRL, and WDT_CLK_SEL. Read: 0: unlocked, Secure writes to secure configuration registers are enabled. 1: locked, all writes to secure configuration registers are ignored. Write: 0: noaffect. 1: lock the secure configuration registers. Once the secure registers are locked, they remain locked until a power-on reset cycle (PS_POR_B).

Register (slcr) SLCR_LOCK

Name Relative Address Absolute Address Width Access Type Reset Value Description SLCR_LOCK 0x00000004 0xF8000004 32 bits wo 0x00000000 SLCR Write Protection Lock

Register SLCR_LOCK Details

Field Name reserved LOCK_KEY Bits 31:16 15:0 Type wo wo Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.

Register (slcr) SLCR_UNLOCK

Name Relative Address Absolute Address SLCR_UNLOCK 0x00000008 0xF8000008

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Width Access Type Reset Value Description

32 bits wo 0x00000000 SLCR Write Protection Unlock

Register SLCR_UNLOCK Details

Field Name reserved UNLOCK_KEY Bits 31:16 15:0 Type wo wo Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.

Register (slcr) SLCR_LOCKSTA

Name Relative Address Absolute Address Width Access Type Reset Value Description SLCR_LOCKSTA 0x0000000C 0xF800000C 32 bits ro 0x00000001 SLCR Write Protection Status

Register SLCR_LOCKSTA Details

Field Name reserved LOCK_STATUS Bits 31:1 0 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Current state of write protection mode of SLCR: 0: Registers are writeable. Use the slcr.SLCR_LOCK register to lock the slcr registers. 1: Registers are not writeable. Any attempt to write to an slcr register is ignored, but reads will return valid register values. Use the slcr.SLCR_UNLOCK register to unlock the slcr registers.

Register (slcr) ARM_PLL_CTRL

Name Relative Address ARM_PLL_CTRL 0x00000100

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Absolute Address Width Access Type Reset Value Description

0xF8000100 32 bits rw 0x0001A008 ARM PLL Control

Register ARM_PLL_CTRL Details

Field Name reserved PLL_FDIV Bits 31:19 18:12 Type rw rw Reset Value 0x0 0x1A Description Reserved. Writes are ignored, read data is zero. Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. Reserved. Writes are ignored, read data is zero. ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. PLL_BYPASS_QUAL 3 rw 0x1 Select the source for the ARM PLL Bypass Control: 0: controlled by the PLL_BYPASS_FORCE bit, bit 4. 1: controlled by the value of the sampled BOOT_MODE pin strapping resistor PLL_BYPASS. This can be read using the BOOT_MODE[4] bit. reserved PLL_PWRDWN 2 1 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. PLL Power-down control: 0: PLL powered up 1: PLL powered down PLL_RESET 0 rw 0x0 PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)

reserved PLL_BYPASS_FORCE

11:5 4

rw rw

0x0 0x0

Register (slcr) DDR_PLL_CTRL

Name DDR_PLL_CTRL

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000104 0xF8000104 32 bits rw 0x0001A008 DDR PLL Control

Register DDR_PLL_CTRL Details

Field Name reserved PLL_FDIV Bits 31:19 18:12 Type rw rw Reset Value 0x0 0x1A Description Reserved. Writes are ignored, read data is zero. Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. Reserved. Writes are ignored, read data is zero. DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. PLL_BYPASS_QUAL 3 rw 0x1 Select the source for the DDR PLL Bypass: 0: controlled by the PLL_BYPASS_FORCE bit. 1: controlled by the value of the sampled BOOT_MODE pin strapping resistor PLL_BYPASS. This can be read using the slcr.BOOT_MODE[4] bit. reserved PLL_PWRDWN 2 1 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. PLL Power-down control: 0: PLL powered up 1: PLL powered down PLL_RESET 0 rw 0x0 PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)

reserved PLL_BYPASS_FORCE

11:5 4

rw rw

0x0 0x0

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Register (slcr) IO_PLL_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description IO_PLL_CTRL 0x00000108 0xF8000108 32 bits rw 0x0001A008 IO PLL Control

Register IO_PLL_CTRL Details

Field Name reserved PLL_FDIV Bits 31:19 18:12 Type rw rw Reset Value 0x0 0x1A Description Reserved. Writes are ignored, read data is zero. Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. Reserved. Writes are ignored, read data is zero. IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. PLL_BYPASS_QUAL 3 rw 0x1 Select the source for the IO PLL Bypass: 0: controlled by the PLL_BYPASS_FORCE bit. 1: controlled by the value of the sampled BOOT_MODE pin strapping resistor PLL_BYPASS. This can be read using the slcr.BOOT_MODE[4] bit. reserved PLL_PWRDWN 2 1 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. PLL Power-down control: 0: PLL powered up 1: PLL powered down PLL_RESET 0 rw 0x0 PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)

reserved PLL_BYPASS_FORCE

11:5 4

rw rw

0x0 0x0

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Register (slcr) PLL_STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description PLL_STATUS 0x0000010C 0xF800010C 32 bits ro 0x0000003F PLL Status

Register PLL_STATUS Details

Note: Reset condition is actually 0, but will read a 1 by the time this register can be read by software if PLLs are enabled by BOOT_MODE.
Field Name reserved IO_PLL_STABLE Bits 31:6 5 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. IO PLL clock stable status: 0: not locked and not in bypass 1: locked or bypassed DDR_PLL_STABLE 4 ro 0x1 DDR PLL clock stable status: 0: not locked and not in bypass 1: locked or bypassed ARM_PLL_STABLE 3 ro 0x1 ARM PLL clock stable status: 0: not locked and not in bypass 1: locked or bypassed IO_PLL_LOCK DDR_PLL_LOCK ARM_PLL_LOCK 2 1 0 ro ro ro 0x1 0x1 0x1 IO PLL lock status: 0: not locked, 1: locked DDR PLL lock status: 0: not locked, 1: locked ARM PLL lock status: 0: not locked, 1: locked

Register (slcr) ARM_PLL_CFG

Name Relative Address Absolute Address Width Access Type ARM_PLL_CFG 0x00000110 0xF8000110 32 bits rw

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Reset Value Description

0x00177EA0 ARM PLL Configuration

Register ARM_PLL_CFG Details

Field Name reserved LOCK_CNT Bits 31:22 21:12 Type rw rw Reset Value 0x0 0x177 Description Reserved. Writes are ignored, read data is zero. Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control Reserved. Writes are ignored, read data is zero.

PLL_CP PLL_RES reserved

11:8 7:4 3:0

rw rw rw

0xE 0xA 0x0

Register (slcr) DDR_PLL_CFG

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_PLL_CFG 0x00000114 0xF8000114 32 bits rw 0x00177EA0 DDR PLL Configuration

Register DDR_PLL_CFG Details

Field Name reserved LOCK_CNT Bits 31:22 21:12 Type rw rw Reset Value 0x0 0x177 Description Reserved. Writes are ignored, read data is zero. Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. Reserved. Writes are ignored, read data is zero.

PLL_CP PLL_RES reserved

11:8 7:4 3:0

rw rw rw

0xE 0xA 0x0

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Register (slcr) IO_PLL_CFG

Name Relative Address Absolute Address Width Access Type Reset Value Description IO_PLL_CFG 0x00000118 0xF8000118 32 bits rw 0x00177EA0 IO PLL Configuration

Register IO_PLL_CFG Details

Field Name reserved LOCK_CNT Bits 31:22 21:12 Type rw rw Reset Value 0x0 0x177 Description Reserved. Writes are ignored, read data is zero. Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. Reserved. Writes are ignored, read data is zero.

PLL_CP PLL_RES reserved

11:8 7:4 3:0

rw rw rw

0xE 0xA 0x0

Register (slcr) ARM_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description ARM_CLK_CTRL 0x00000120 0xF8000120 32 bits rw 0x1F000400 CPU Clock Control

Register ARM_CLK_CTRL Details

Field Name reserved CPU_PERI_CLKACT Bits 31:29 28 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Clock active: 0: Clock is disabled 1: Clock is enabled

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Field Name CPU_1XCLKACT CPU_2XCLKACT CPU_3OR2XCLKACT CPU_6OR4XCLKACT reserved DIVISOR reserved SRCSEL

Bits 27 26 25 24 23:14 13:8 7:6 5:4

Type rw rw rw rw rw rw rw rw

Reset Value 0x1 0x1 0x1 0x1 0x0 0x4 0x0 0x0

Description CPU_1x Clock control: 0: disable, 1: enable CPU_2x Clock control: 0: disable, 1: enable CPU_3x2x Clock control: 0: disable, 1: enable CPU_6x4x Clock control: 0: disable, 1: enable Reserved. Writes are ignored, read data is zero. Frequency divisor for the CPU clock source. (When PLL is being used, 1&3 are illegal values) Reserved. Writes are ignored, read data is zero. Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.

reserved

3:0

rw

0x0

Reserved. Writes are ignored, read data is zero.

Register (slcr) DDR_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_CLK_CTRL 0x00000124 0xF8000124 32 bits rw 0x18400003 DDR Clock Control

Register DDR_CLK_CTRL Details

Note: the DDR_3x and DDR_2x clocks are asynchronous to each other and without a fixed frequency ratio. The frequency of each DDR clock is independently programed. Generally, the DDR_3x clock runs faster than the DDR2x clock.
Field Name DDR_2XCLK_DIVISO R DDR_3XCLK_DIVISO R Bits 31:26 25:20 Type rw rw Reset Value 0x6 0x4 Description Frequency divisor for the ddr_2x clock Frequency divisor for the ddr_3x clock. (Only even divisors are allowed)

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Field Name reserved DDR_2XCLKACT DDR_3XCLKACT

Bits 19:2 1 0

Type rw rw rw

Reset Value 0x0 0x1 0x1

Description Reserved. Writes are ignored, read data is zero. DDR_2x Clock control: 0: disable, 1: enable DDR_3x Clock control: 0: disable, 1: enable

Register (slcr) DCI_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DCI_CLK_CTRL 0x00000128 0xF8000128 32 bits rw 0x01E03201 DCI clock control

Register DCI_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x1E Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Reserved. Writes are ignored, read data is zero. DCI clock control 0: Disable 1: Enable

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x32

reserved CLKACT

7:1 0

rw rw

0x0 0x1

Register (slcr) APER_CLK_CTRL

Name Relative Address Absolute Address Width APER_CLK_CTRL 0x0000012C 0xF800012C 32 bits

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Access Type Reset Value Description

rw 0x01FFCCCD AMBA Peripheral Clock Control

Register APER_CLK_CTRL Details

Field Name reserved SMC_CPU_1XCLKAC T LQSPI_CPU_1XCLKA CT GPIO_CPU_1XCLKAC T Bits 31:25 24 23 22 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x1 0x1 Description Reserved. Writes are ignored, read data is zero. SMC AMBA Clock control 0: disable, 1: enable Quad SPI AMBA Clock control 0: disable, 1: enable GPIO AMBA Clock control 0: disable, 1: enable UART 1 AMBA Clock control 0: disable, 1: enable UART 0 AMBA Clock control 0: disable, 1: enable I2C 1 AMBA Clock control 0: disable, 1: enable 18 17 16 15 14 13 12 11 10 I2C 0 AMBA Clock control 0: disable, 1: enable CAN 1 AMBA Clock control 0: disable, 1: enable CAN 0 AMBA Clock control 0: disable, 1: enable SPI 1 AMBA Clock control 0: disable, 1: enable SPI0_CPU_1XCLKACT reserved reserved SDI1_CPU_1XCLKAC T SDI0_CPU_1XCLKAC T SPI 0 AMBA Clock control 0: disable, 1: enable Reserved. Writes are ignored, read data is zero. Reserved. Writes are ignored, read data is zero. SDIO controller 1 AMBA Clock control 0: disable, 1: enable SDIO controller 0 AMBA Clock 0: disable, 1: enable reserved reserved 9 8 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. Reserved. Writes are ignored, read data is zero.

UART1_CPU_1XCLKA 21 CT UART0_CPU_1XCLKA 20 CT I2C1_CPU_1XCLKAC T I2C0_CPU_1XCLKAC T CAN1_CPU_1XCLKA CT CAN0_CPU_1XCLKA CT SPI1_CPU_1XCLKACT 19

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Field Name GEM1_CPU_1XCLKA CT GEM0_CPU_1XCLKA CT reserved reserved USB1_CPU_1XCLKAC T USB0_CPU_1XCLKAC T reserved DMA_CPU_2XCLKAC T

Bits 7 6 5 4 3 2 1 0

Type rw rw rw rw rw rw rw rw

Reset Value 0x1 0x1 0x0 0x0 0x1 0x1 0x0 0x1

Description Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable Reserved. Writes are ignored, read data is zero. Reserved. Writes are ignored, read data is zero. USB controller 1 AMBA Clock control 0: disable, 1: enable USB controller 0 AMBA Clock control 0: disable, 1: enable Reserved. Writes are ignored, read data is zero. DMA controller AMBA Clock control 0: disable, 1: enable

Register (slcr) USB0_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description USB0_CLK_CTRL 0x00000130 0xF8000130 32 bits rw 0x00101941 USB 0 ULPI Clock Control

Register USB0_CLK_CTRL Details

Field Name reserved reserved reserved reserved reserved SRCSEL Bits 31:26 25:20 19:14 13:8 7 6:4 Type rw rw rw rw rw rw Reset Value 0x0 0x1 0x0 0x19 0x0 0x4 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Writes are ignored, read data is zero. Select the source to generate USB controller 0 ULPI clock: 1xx: USB 0 MIO ULPI clock (top level MIO ULPI clock is an input)

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Field Name reserved reserved

Bits 3:1 0

Type rw rw

Reset Value 0x0 0x1

Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify.

Register (slcr) USB1_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description USB1_CLK_CTRL 0x00000134 0xF8000134 32 bits rw 0x00101941 USB 1 ULPI Clock Control

Register USB1_CLK_CTRL Details

Field Name reserved reserved reserved reserved reserved SRCSEL Bits 31:26 25:20 19:14 13:8 7 6:4 Type rw rw rw rw rw rw Reset Value 0x0 0x1 0x0 0x19 0x0 0x4 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Writes are ignored, read data is zero. Select the source to generate USB controller 1 ULPI clock: 1xx: USB 1 MIO ULPI clock (top level MIO ULPI clock is an input) reserved reserved 3:1 0 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. Reserved. Do not modify.

Register (slcr) GEM0_RCLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GEM0_RCLK_CTRL 0x00000138 0xF8000138 32 bits rw 0x00000001 GigE 0 Rx Clock and Rx Signals Select

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Register GEM0_RCLK_CTRL Details

Field Name reserved SRCSEL Bits 31:5 4 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO reserved CLKACT 3:1 0 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. Ethernet Controler 0 Rx Clock control 0: disable, 1: enable

Register (slcr) GEM1_RCLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GEM1_RCLK_CTRL 0x0000013C 0xF800013C 32 bits rw 0x00000001 GigE 1 Rx Clock and Rx Signals Select

Register GEM1_RCLK_CTRL Details

Field Name reserved SRCSEL Bits 31:5 4 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO reserved CLKACT 3:1 0 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. Ethernet Controller 1 Rx Clock control 0: disable, 1: enable

Register (slcr) GEM0_CLK_CTRL

Name Relative Address Absolute Address Width GEM0_CLK_CTRL 0x00000140 0xF8000140 32 bits

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Access Type Reset Value Description

rw 0x00003C01 GigE 0 Ref Clock Control

Register GEM0_CLK_CTRL Details

Field Name reserved DIVISOR1 reserved DIVISOR reserved SRCSEL Bits 31:26 25:20 19:14 13:8 7 6:4 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3C 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Second divisor for Ethernet controller 0 source clock. Reserved. Writes are ignored, read data is zero. First divisor for Ethernet controller 0 source clock. Reserved. Writes are ignored, read data is zero. Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock reserved CLKACT 3:1 0 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. Ethernet Controller 0 Reference Clock control 0: disable, 1: enable

Register (slcr) GEM1_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GEM1_CLK_CTRL 0x00000144 0xF8000144 32 bits rw 0x00003C01 GigE 1 Ref Clock Control

Register GEM1_CLK_CTRL Details

Field Name reserved DIVISOR1 reserved Bits 31:26 25:20 19:14 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Second divisor for Ethernet controller 1 source clock. Reserved. Writes are ignored, read data is zero.

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Field Name DIVISOR reserved SRCSEL

Bits 13:8 7 6:4

Type rw rw rw

Reset Value 0x3C 0x0 0x0

Description First divisor for Ethernet controller 1 source clock. Reserved. Writes are ignored, read data is zero. Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 1 EMIO clock

reserved CLKACT

3:1 0

rw rw

0x0 0x1

Reserved. Writes are ignored, read data is zero. Ethernet Controller 1 Reference Clock control 0: disable, 1: enable

Register (slcr) SMC_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description SMC_CLK_CTRL 0x00000148 0xF8000148 32 bits rw 0x00003C21 SMC Ref Clock Control

Register SMC_CLK_CTRL Details

Field Name reserved DIVISOR reserved SRCSEL reserved CLKACT Bits 31:14 13:8 7:6 5:4 3:1 0 Type rw rw rw rw rw rw Reset Value 0x0 0x3C 0x0 0x2 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Divisor for SMC source clock. Reserved. Writes are ignored, read data is zero. Select clock source generate SMC clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL Reserved. Writes are ignored, read data is zero. SMC Reference Clock control 0: disable, 1: enable

Register (slcr) LQSPI_CLK_CTRL

Name Relative Address LQSPI_CLK_CTRL 0x0000014C

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Absolute Address Width Access Type Reset Value Description

0xF800014C 32 bits rw 0x00002821 Quad SPI Ref Clock Control

Register LQSPI_CLK_CTRL Details

Field Name reserved DIVISOR reserved SRCSEL reserved CLKACT Bits 31:14 13:8 7:6 5:4 3:1 0 Type rw rw rw rw rw rw Reset Value 0x0 0x28 0x0 0x2 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Divisor for Quad SPI Controller source clock. Reserved. Writes are ignored, read data is zero. Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL Reserved. Writes are ignored, read data is zero. Quad SPI Controller Reference Clock control 0: disable, 1: enable

Register (slcr) SDIO_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description SDIO_CLK_CTRL 0x00000150 0xF8000150 32 bits rw 0x00001E03 SDIO Ref Clock Control

Register SDIO_CLK_CTRL Details

Field Name reserved DIVISOR Bits 31:14 13:8 Type rw rw Reset Value 0x0 0x1E Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Reserved. Writes are ignored, read data is zero.

reserved

7:6

rw

0x0

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Field Name SRCSEL

Bits 5:4

Type rw

Reset Value 0x0

Description Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.

reserved CLKACT1 CLKACT0

3:2 1 0

rw rw rw

0x0 0x1 0x1

Reserved. Writes are ignored, read data is zero. SDIO Controller 1 Clock control. 0: disable, 1: enable SDIO Controller 0 Clock control. 0: disable, 1: enable

Register (slcr) UART_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description UART_CLK_CTRL 0x00000154 0xF8000154 32 bits rw 0x00003F03 UART Ref Clock Control

Register UART_CLK_CTRL Details

Field Name reserved DIVISOR reserved SRCSEL Bits 31:14 13:8 7:6 5:4 Type rw rw rw rw Reset Value 0x0 0x3F 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Divisor for UART Controller source clock. Reserved. Writes are ignored, read data is zero. Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL reserved CLKACT1 3:2 1 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled CLKACT0 0 rw 0x1 UART 0 Reference clock control. 0: disable, 1: enable

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Register (slcr) SPI_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description SPI_CLK_CTRL 0x00000158 0xF8000158 32 bits rw 0x00003F03 SPI Ref Clock Control

Register SPI_CLK_CTRL Details

Field Name reserved DIVISOR Bits 31:14 13:8 Type rw rw Reset Value 0x0 0x3F Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved CLKACT1 3:2 1 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled CLKACT0 0 rw 0x1 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

Register (slcr) CAN_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description CAN_CLK_CTRL 0x0000015C 0xF800015C 32 bits rw 0x00501903 CAN Ref Clock Control

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Register CAN_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x5 Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved CLKACT1 3:2 1 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled CLKACT0 0 rw 0x1 CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x19

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

Register (slcr) CAN_MIOCLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description CAN_MIOCLK_CTRL 0x00000160 0xF8000160 32 bits rw 0x00000000 CAN MIO Clock Control

Register CAN_MIOCLK_CTRL Details

Field Name reserved CAN1_REF_SEL Bits 31:23 22 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field

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Field Name CAN1_MUX

Bits 21:16

Type rw

Reset Value 0x0

Description CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. Reserved. Writes are ignored, read data is zero. CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field

reserved CAN0_REF_SEL

15:7 6

rw rw

0x0 0x0

CAN0_MUX

5:0

rw

0x0

CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.

Register (slcr) DBG_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DBG_CLK_CTRL 0x00000164 0xF8000164 32 bits rw 0x00000F03 SoC Debug Clock Control

Register DBG_CLK_CTRL Details

Field Name reserved DIVISOR Bits 31:14 13:8 Type rw rw Reset Value 0x0 0xF Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated debug trace clock frequency. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 1xx: Source for generated clock EMIO trace clock 00x: Source for generated clock is IO PLL 010: Source for generated clock is ARM PLL 011: Source for generated clock is DDR PLL reserved 3:2 rw 0x0 Reserved. Writes are ignored, read data is zero.

reserved SRCSEL

7 6:4

rw rw

0x0 0x0

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Field Name CPU_1XCLKACT

Bits 1

Type rw

Reset Value 0x1 Debug

Description

CPU 1x Clock active. 0 - Clocks are disabled. 1 Clocks are enabled CLKACT_TRC 0 rw 0x1 Debug Trace Clock active: 0: Clock is disabled 1: Clock is enabled

Register (slcr) PCAP_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description PCAP_CLK_CTRL 0x00000168 0xF8000168 32 bits rw 0x00000F01 PCAP Clock Control

Register PCAP_CLK_CTRL Details

Field Name reserved DIVISOR Bits 31:14 13:8 Type rw rw Reset Value 0x0 0xF Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved CLKACT 3:1 0 rw rw 0x0 0x1 Reserved. Writes are ignored, read data is zero. Clock active: 0: Clock is disabled 1: Clock is enabled

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

Register (slcr) TOPSW_CLK_CTRL

Name Relative Address Absolute Address TOPSW_CLK_CTRL 0x0000016C 0xF800016C

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Width Access Type Reset Value Description

32 bits rw 0x00000000 Central Interconnect Clock Control

Register TOPSW_CLK_CTRL Details

Field Name reserved CLK_DIS Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Clock disable control: 0: Clock is not disabled 1: Clock can be disabled

Register (slcr) FPGA0_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA0_CLK_CTRL 0x00000170 0xF8000170 32 bits rw 0x00101800 PL Clock 0 Output control

Register FPGA0_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved 3:0 rw 0x0 Reserved. Writes are ignored, read data is zero.

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x18

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

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Register (slcr) FPGA0_THR_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA0_THR_CTRL 0x00000174 0xF8000174 32 bits rw 0x00000000 PL Clock 0 Throttle control

Register FPGA0_THR_CTRL Details

Field Name reserved reserved reserved CNT_RST Bits 31:4 3 2 1 Type rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Must be set to 1'b0 to use this feature Must be set to 1'b1 to use this feature Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered CPU_START 0 rw 0x0 Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.) 0: No effect 1: Start count or restart count if previous value was 0

Register (slcr) FPGA0_THR_CNT

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA0_THR_CNT 0x00000178 0xF8000178 32 bits rw 0x00000000 PL Clock 0 Throttle Count control

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Register FPGA0_THR_CNT Details

Field Name reserved reserved LAST_CNT Bits 31:20 19:16 15:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.

Register (slcr) FPGA0_THR_STA

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA0_THR_STA 0x0000017C 0xF800017C 32 bits ro 0x00010000 PL Clock 0 Throttle Status read

Register FPGA0_THR_STA Details

Field Name reserved RUNNING Bits 31:17 16 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static). CURR_VAL 15:0 ro 0x0 Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).

Register (slcr) FPGA1_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value FPGA1_CLK_CTRL 0x00000180 0xF8000180 32 bits rw 0x00101800

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Description

PL Clock 1 Output control

Register FPGA1_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved 3:0 rw 0x0 Reserved. Writes are ignored, read data is zero.

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x18

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

Register (slcr) FPGA1_THR_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA1_THR_CTRL 0x00000184 0xF8000184 32 bits rw 0x00000000 PL Clock 1 Throttle control

Register FPGA1_THR_CTRL Details

Field Name reserved reserved reserved Bits 31:4 3 2 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Must be set to 1'b0 to use this feature Must be set to 1'b1 to use this feature

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Field Name CNT_RST

Bits 1

Type rw

Reset Value 0x0

Description Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered

CPU_START

rw

0x0

Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.) 0: No effect 1: Start count or restart count if previous value was 0

Register (slcr) FPGA1_THR_CNT

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA1_THR_CNT 0x00000188 0xF8000188 32 bits rw 0x00000000 PL Clock 1 Throttle Count

Register FPGA1_THR_CNT Details

Field Name reserved reserved LAST_CNT Bits 31:20 19:16 15:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.

Register (slcr) FPGA1_THR_STA

Name Relative Address Absolute Address Width Access Type Reset Value FPGA1_THR_STA 0x0000018C 0xF800018C 32 bits ro 0x00010000

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Description

PL Clock 1 Throttle Status control

Register FPGA1_THR_STA Details

Field Name reserved RUNNING Bits 31:17 16 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static). CURR_VAL 15:0 ro 0x0 Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).

Register (slcr) FPGA2_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA2_CLK_CTRL 0x00000190 0xF8000190 32 bits rw 0x00101800 PL Clock 2 output control

Register FPGA2_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved 3:0 rw 0x0 Reserved. Writes are ignored, read data is zero.

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x18

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

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Register (slcr) FPGA2_THR_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA2_THR_CTRL 0x00000194 0xF8000194 32 bits rw 0x00000000 PL Clock 2 Throttle Control

Register FPGA2_THR_CTRL Details

Field Name reserved reserved reserved CNT_RST Bits 31:4 3 2 1 Type rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Must be set to 1'b0 to use this feature Must be set to 1'b1 to use this feature Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered CPU_START 0 rw 0x0 Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.) 0: No effect 1: Start count or restart count if previous value was 0

Register (slcr) FPGA2_THR_CNT

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA2_THR_CNT 0x00000198 0xF8000198 32 bits rw 0x00000000 PL Clock 2 Throttle Count

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Register FPGA2_THR_CNT Details

Field Name reserved reserved LAST_CNT Bits 31:20 19:16 15:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.

Register (slcr) FPGA2_THR_STA

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA2_THR_STA 0x0000019C 0xF800019C 32 bits ro 0x00010000 PL Clock 2 Throttle Status

Register FPGA2_THR_STA Details

Field Name reserved RUNNING Bits 31:17 16 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static). CURR_VAL 15:0 ro 0x0 Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).

Register (slcr) FPGA3_CLK_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value FPGA3_CLK_CTRL 0x000001A0 0xF80001A0 32 bits rw 0x00101800

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Description

PL Clock 3 output control

Register FPGA3_CLK_CTRL Details

Field Name reserved DIVISOR1 Bits 31:26 25:20 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide Reserved. Writes are ignored, read data is zero. Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. Reserved. Writes are ignored, read data is zero. Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved 3:0 rw 0x0 Reserved. Writes are ignored, read data is zero.

reserved DIVISOR0

19:14 13:8

rw rw

0x0 0x18

reserved SRCSEL

7:6 5:4

rw rw

0x0 0x0

Register (slcr) FPGA3_THR_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA3_THR_CTRL 0x000001A4 0xF80001A4 32 bits rw 0x00000000 PL Clock 3 Throttle Control

Register FPGA3_THR_CTRL Details

Field Name reserved reserved reserved Bits 31:4 3 2 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Must be set to 1'b0 to use this feature Must be set to 1'b1 to use this feature

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Field Name CNT_RST

Bits 1

Type rw

Reset Value 0x0

Description Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered

CPU_START

rw

0x0

Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.) 0: No effect 1: Start count or restart count if previous value was 0

Register (slcr) FPGA3_THR_CNT

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA3_THR_CNT 0x000001A8 0xF80001A8 32 bits rw 0x00000000 PL Clock 3 Throttle Count

Register FPGA3_THR_CNT Details

Field Name reserved reserved LAST_CNT Bits 31:20 19:16 15:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.

Register (slcr) FPGA3_THR_STA

Name Relative Address Absolute Address Width Access Type Reset Value FPGA3_THR_STA 0x000001AC 0xF80001AC 32 bits ro 0x00010000

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Description

PL Clock 3 Throttle Status

Register FPGA3_THR_STA Details

Field Name reserved RUNNING Bits 31:17 16 Type ro ro Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static). CURR_VAL 15:0 ro 0x0 Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted).

Register (slcr) CLK_621_TRUE

Name Relative Address Absolute Address Width Access Type Reset Value Description CLK_621_TRUE 0x000001C4 0xF80001C4 32 bits rw 0x00000001 CPU Clock Ratio Mode select

Register CLK_621_TRUE Details

Field Name reserved CLK_621_TRUE Bits 31:1 0 Type rw rw Reset Value 0x0 0x1 Description Reserved. Writes are ignored, read data is zero. Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1

Register (slcr) PSS_RST_CTRL

Name Relative Address Absolute Address Width PSS_RST_CTRL 0x00000200 0xF8000200 32 bits

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Access Type Reset Value Description

rw 0x00000000 PS Software Reset Control

Register PSS_RST_CTRL Details

Field Name reserved SOFT_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Processing System software reset control signal. 0: no affect 1: asserts PS software reset pulse (entire system except clock generator) There is no need to write a 0, the hardware generates a pulse everytime a 1 is written.

Register (slcr) DDR_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_RST_CTRL 0x00000204 0xF8000204 32 bits rw 0x00000000 DDR Software Reset Control

Register DDR_RST_CTRL Details

Field Name reserved DDR_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. DDR software reset control signal 0: disable, 1: enable

Register (slcr) TOPSW_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value TOPSW_RST_CTRL 0x00000208 0xF8000208 32 bits rw 0x00000000

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Description

Central Interconnect Reset Control

Register TOPSW_RST_CTRL Details

Field Name reserved TOPSW_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Central Interconnect Reset Control: 0: de-assert (no reset) 1: assert Care must be taken to ensure that the AXI interconnect does not have outstanding transactions and the bus is idle.

Register (slcr) DMAC_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DMAC_RST_CTRL 0x0000020C 0xF800020C 32 bits rw 0x00000000 DMAC Software Reset Control

Register DMAC_RST_CTRL Details

Field Name reserved DMAC_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. DMA Controller software reset signal. 0: de-assert (DMA controller TrustZone register is read only) 1: assert (DMA controller TrustZone register is writeable)

Register (slcr) USB_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value USB_RST_CTRL 0x00000210 0xF8000210 32 bits rw 0x00000000

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Description

USB Software Reset Control

Register USB_RST_CTRL Details

Field Name reserved USB1_CPU1X_RST Bits 31:2 1 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. USB 1 master and slave AMBA interfaces software reset: 0: de-assert (no reset) 1: assert (held in reset) USB0_CPU1X_RST 0 rw 0x0 USB 0 master and slave AMBA interfaces software reset: 0: de-assert (no reset) 1: assert (held in reset)

Register (slcr) GEM_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GEM_RST_CTRL 0x00000214 0xF8000214 32 bits rw 0x00000000 Gigabit Ethernet SW Reset Control

Register GEM_RST_CTRL Details

Each Gigabit Ethernet controller has 3 clock domains and each clock domain has a reset control: * Reference clock domain reset * RxClock domain reset * CPU_1x clock domain reset
Field Name reserved GEM1_REF_RST Bits 31:8 7 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Gigabit Ethernet 1 reference clock reset: 0: de-assert (no reset) 1: assert (interfaces are held in reset) GEM0_REF_RST 6 rw 0x0 Gigabit Ethernet 0 reference clock domain reset: 0: de-assert (no reset) 1: assert (controller is held in reset)

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Field Name GEM1_RX_RST

Bits 5

Type rw

Reset Value 0x0

Description Gigabit Ethernet 1 Rx clock domain reset: 0: de-assert (no reset) 1: assert (held in reset)

GEM0_RX_RST

rw

0x0

Gigabit Ethernet 0 Rx clock domain reset: 0: de-assert (no reset) 1: assert (held in reset)

reserved GEM1_CPU1X_RST

3:2 1

rw rw

0x0 0x0

Reserved. Writes are ignored, read data is zero. Gigabit Ethernet 1 CPU_1x clock domain reset: 0: de-assert (no reset) 1: assert (held in reset)

GEM0_CPU1X_RST

rw

0x0

Gigabit Ethernet 0 CPU_1x clock domain reset: 0: de-assert (no reset) 1: assert (held in reset)

Register (slcr) SDIO_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description SDIO_RST_CTRL 0x00000218 0xF8000218 32 bits rw 0x00000000 SDIO Software Reset Control

Register SDIO_RST_CTRL Details

Field Name reserved SDIO1_REF_RST Bits 31:6 5 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. SDIO 1 reference clock domain reset: 0: de-assert (no reset) 1: assert (controller is held in reset) SDIO0_REF_RST 4 rw 0x0 SDIO 0 reference clock domain reset: 0: de-assert (no reset) 1: assert (controller is held in reset) reserved 3:2 rw 0x0 Reserved. Writes are ignored, read data is zero.

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Field Name SDIO1_CPU1X_RST

Bits 1

Type rw

Reset Value 0x0

Description SDIO 1 master and slave AMBA interfaces reset: 0: de-assert (no reset) 1: assert (held in reset)

SDIO0_CPU1X_RST

rw

0x0

SDIO 0 master and slave AMBA interfaces reset: 0: de-assert (no reset) 1: assert (held in reset)

Register (slcr) SPI_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description SPI_RST_CTRL 0x0000021C 0xF800021C 32 bits rw 0x00000000 SPI Software Reset Control

Register SPI_RST_CTRL Details

Field Name reserved SPI1_REF_RST Bits 31:4 3 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. SPI 1 Reference software reset. On assertion of this reset, the Reference clock portion of the SPI 1 subsystem will be reset. 0: No reset 1: Reference clock portion of SPI 1 subsytem held in reset SPI0_REF_RST 2 rw 0x0 SPI 0 Reference software reset. On assertion of this reset, the Reference clock portion of the SPI 0 subsystem will be reset. 0: No reset 1: Reference clock portion of SPI 0 subsytem held in reset

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Field Name SPI1_CPU1X_RST

Bits 1

Type rw

Reset Value 0x0

Description SPI 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of SPI 1 subsytem held in reset

SPI0_CPU1X_RST

rw

0x0

SPI 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 0 subsystem will be reset. 0: No reset 1: AMBA clock portion of SPI 0 subsytem held in reset

Register (slcr) CAN_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description CAN_RST_CTRL 0x00000220 0xF8000220 32 bits rw 0x00000000 CAN Software Reset Control

Register CAN_RST_CTRL Details

Field Name reserved reserved reserved Bits 31:4 3 2 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Writes will maintain value Reserved. Writes will maintain value

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Field Name CAN1_CPU1X_RST

Bits 1

Type rw

Reset Value 0x0

Description CAN 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of CAN 1 subsytem held in reset

CAN0_CPU1X_RST

rw

0x0

CAN 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 0 subsystem will be reset. 0: No reset 1: AMBA clock portion of CAN 0 subsytem held in reset

Register (slcr) I2C_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description I2C_RST_CTRL 0x00000224 0xF8000224 32 bits rw 0x00000000 I2C Software Reset Control

Register I2C_RST_CTRL Details

Field Name reserved I2C1_CPU1X_RST Bits 31:2 1 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. I2C 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the I2C 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of I2C 1 subsytem held in reset I2C0_CPU1X_RST 0 rw 0x0 I2C 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the I2C 0 subsystem will be reset. 0: No reset 1: AMBA clock portion of I2C 0 subsytem held in reset

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Register (slcr) UART_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description UART_RST_CTRL 0x00000228 0xF8000228 32 bits rw 0x00000000 UART Software Reset Control

Register UART_RST_CTRL Details

Field Name reserved UART1_REF_RST Bits 31:4 3 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. UART 1 Reference software reset. 0: deassert soft reset 1: assert soft reset UART0_REF_RST 2 rw 0x0 UART 0 Reference software reset. 0: deassert soft reset 1: assert soft reset UART1_CPU1X_RST 1 rw 0x0 UART 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the UART 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of UART 1 subsytem held in reset UART0_CPU1X_RST 0 rw 0x0 UART 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the UART 0 subsystem will be reset. 0: No reset 1: AMBA clock portion of UART 0 subsytem held in reset

Register (slcr) GPIO_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value GPIO_RST_CTRL 0x0000022C 0xF800022C 32 bits rw 0x00000000

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Description

GPIO Software Reset Control

Register GPIO_RST_CTRL Details

Field Name reserved GPIO_CPU1X_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. GPIO AMBA software reset. On assertion of this reset, the AMBA clock portion of the GPIO subsystem will be reset. 0: No reset 1: AMBA clock portion of GPIO subsytem held in reset

Register (slcr) LQSPI_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description LQSPI_RST_CTRL 0x00000230 0xF8000230 32 bits rw 0x00000000 Quad SPI Software Reset Control

Register LQSPI_RST_CTRL Details

Field Name reserved QSPI_REF_RST Bits 31:2 1 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Quad SPI Reference software reset. On assertion of this reset, the Reference clock portion of the QSPI subsystem will be reset. 0: No reset. 1: Reference clock portion of QSPI subsytem held in reset. LQSPI_CPU1X_RST 0 rw 0x0 Quad SPI AMBA software reset. On assertion of this reset, the AMBA clock portion of the LQSPI subsystem will be reset. 0: No reset 1: AMBA clock portion of QSPI subsytem held in reset

Register (slcr) SMC_RST_CTRL

Name SMC_RST_CTRL

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000234 0xF8000234 32 bits rw 0x00000000 SMC Software Reset Control

Register SMC_RST_CTRL Details

Field Name reserved SMC_REF_RST Bits 31:2 1 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. SMC Reference software reset. On assertion of this reset, the Reference clock portion of the SMC subsystem will be reset. 0: No reset 1: Reference clock portion of SMC subsytem held in reset SMC_CPU1X_RST 0 rw 0x0 SMC AMBA software reset. On assertion of this reset, the AMBA clock portion of the SMC subsystem will be reset. 0: No reset 1: AMBA clock portion of SMC subsytem held in reset

Register (slcr) OCM_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description OCM_RST_CTRL 0x00000238 0xF8000238 32 bits rw 0x00000000 OCM Software Reset Control

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Register OCM_RST_CTRL Details

Field Name reserved OCM_RST Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. OCM software reset. On assertion of this reset, the OCM subsystem will be reset. 0: No reset 1: OCM subsytem held in reset

Register (slcr) FPGA_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description FPGA_RST_CTRL 0x00000240 0xF8000240 32 bits rw 0x01F33F0F FPGA Software Reset Control

Register FPGA_RST_CTRL Details

Field Name reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Bits 31:25 24 23 22 21 20 19:18 17 16 15:14 13 12 11 10 9 8 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x1 0x1 0x1 0x1 0x1 0x0 0x1 0x1 0x0 0x1 0x1 0x1 0x1 0x1 0x1 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0 Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify. Reserved. Writes are ignored, read data is zero. Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0 Reserved - always write with 0

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Field Name reserved FPGA3_OUT_RST

Bits 7:4 3

Type rw rw

Reset Value 0x0 0x1

Description Reserved. Writes are ignored, read data is zero. PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)

FPGA2_OUT_RST

rw

0x1

PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)

FPGA1_OUT_RST

rw

0x1

PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)

FPGA0_OUT_RST

rw

0x1

PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)

Register (slcr) A9_CPU_RST_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description A9_CPU_RST_CTRL 0x00000244 0xF8000244 32 bits rw 0x00000000 CPU Reset and Clock control

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Register A9_CPU_RST_CTRL Details

Field Name reserved PERI_RST Bits 31:9 8 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. CPU peripheral soft reset. 0: de-assert (no reset) 1: assert (held in reset) reserved A9_CLKSTOP1 7:6 5 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. CPU 1 clock stop control: 0: no stop (CPU runs) 1: clock stopped A9_CLKSTOP0 4 rw 0x0 CPU 0 clock stop control: 0: no stop (CPU runs) 1: clock stopped reserved A9_RST1 3:2 1 rw rw 0x0 0x0 Reserved. Writes are ignored, read data is zero. CPU 1 software reset control: 0: de-assert (no reset) 1: assert (held in reset) A9_RST0 0 rw 0x0 CPU 0 software reset control: 0: de-assert (no reset) 1: assert (held in reset)

Register (slcr) RS_AWDT_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description RS_AWDT_CTRL 0x0000024C 0xF800024C 32 bits rw 0x00000000 Watchdog Timer Reset Control

Register RS_AWDT_CTRL Details

Field Name reserved Bits 31:2 Type rw Reset Value 0x0 Description Reserved. Writes are ignored, read data is zero.

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Field Name CTRL1

Bits 1

Type rw

Reset Value 0x0

Description Select the target for the APU watchdog timer 1 reset signal. Route the WDT reset to: 0: the same system level as PS_SRST_B 1: the CPU associated with the watchdog timer

CTRL0

rw

0x0

Select the target for the APU watchdog timer 0 reset signal. Route the WDT reset to: 0: the same system level as PS_SRST_B 1: the CPU associated with the watchdog timer

Register (slcr) REBOOT_STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description REBOOT_STATUS 0x00000258 0xF8000258 32 bits rw 0x00400000 Reboot Status, persistent

Register REBOOT_STATUS Details

The Reboot Status persistent through all resets except Power-on reset.
Field Name REBOOT_STATE Bits 31:24 Type rw Reset Value 0x0 Description General 32-bit R/W field to allow software to store information that persists through all resets except power-on reset. This field is reset by POR only. The ROM will put the last known reset reason into this register. reserved POR SRST_B DBG_RST SLC_RST AWDT1_RST 23 22 21 20 19 18 rw rw rw rw rw rw 0x0 0x1 0x0 0x0 0x0 0x0 Reserved. Last reset was due to POR (power on reset), if set. This field is written by ROM code. Last reset was due to SRST_B (soft reset), if set. This field is written by ROM code. Last reset was due to debug system reset, if set. This field is written by ROM code. Last reset was due to SLC soft reset, if set. This field is written by ROM code. Last reset was due to APU watchdog timer 1, if set. This field is written by ROM code.

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Field Name AWDT0_RST

Bits 17

Type rw

Reset Value 0x0

Description Last reset was due to APU watchdog timer 0, if set. This field is written by ROM code Last reset was due to system watchdog timeout, if set (see watchdog status for more details). This field is written by ROM code This field is written by the BootROM to describe errors that occur during the boot proceess. Refer to the BootROM debug status section in the Zynq-7000 Technical Reference Manual, UG585.

SWDT_RST

16

rw

0x0

BOOTROM_ERROR_C ODE

15:0

rw

0x0

Register (slcr) BOOT_MODE

Name Relative Address Absolute Address Width Access Type Reset Value Description BOOT_MODE 0x0000025C 0xF800025C 32 bits mixed x Boot Mode Strapping Pins

Register BOOT_MODE Details

Boot mode strapping pins are sampled when Power-on Reset deasserts. The logic levels are stored in this register. The explanation of these boot mode pin settings are explained in the boot mode section of the Zynq Technical Reference Manual.
Field Name reserved PLL_BYPASS Bits 31:5 4 Type rw ro Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Boot mode pins are sampled when Power-on Reset deasserts. The logic levels are stored in this register. The PLL_BYPASS pin sets the initial operating mode of all three PLL clocks (ARM, IO and DDR): 0: PLLs are enabled and their outputs are routed to the clock generators 1: PLLs are disabled and bypassed BOOT_MODE 3:0 ro x Boot mode pins are sampled when Power-on Reset deasserts. The logic levels are stored in this register. The interpretation of these boot mode values are explained in the boot mode section of the Zynq Technical Reference Manual.

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Register (slcr) APU_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description APU_CTRL 0x00000300 0xF8000300 32 bits rw 0x00000000 APU Control

Register APU_CTRL Details

Field Name reserved CFGSDISABLE Bits 31:3 2 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Disable write access to some system control processor registers, and some GIC registers. Set only. Once set, individual core reset cannot reset this value. This field is reset by POR only. CP15SDISABLE 1:0 rw 0x0 Disable write access to some system control processor (CP15) registers, in each processor. Set only. Once set, individual core reset cannot reset this value. This field is reset by POR only.

Register (slcr) WDT_CLK_SEL

Name Relative Address Absolute Address Width Access Type Reset Value Description WDT_CLK_SEL 0x00000304 0xF8000304 32 bits rw 0x00000000 SWDT clock source select

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Register WDT_CLK_SEL Details

Field Name reserved SEL Bits 31:1 0 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. System watchdog timer clock source selection: 0: internal clock CPU_1x 1: external clock from PL via EMIO, or from pinout via MIO

Register (slcr) PSS_IDCODE

Name Relative Address Absolute Address Width Access Type Reset Value Description PSS_IDCODE 0x00000530 0xF8000530 32 bits ro x PS IDCODE

Register PSS_IDCODE Details

Field Name REVISION FAMILY SUBFAMILY DEVICE Bits 31:28 27:21 20:17 16:12 Type ro ro ro ro Reset Value x 0x1B 0x9 x Revision code Family code Subfamily code Device code 7z010: 0x02 7z020: 0x07 7z030: 0x0c 7z045: 0x11 MANUFACTURER_ID reserved 11:1 0 ro ro 0x49 0x1 Manufacturer ID Reserved. Writes are ignored, read data is one. Description

Register (slcr) DDR_URGENT

Name Relative Address Absolute Address Width DDR_URGENT 0x00000600 0xF8000600 32 bits

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Access Type Reset Value Description

rw 0x00000000 DDR Urgent Control

Register DDR_URGENT Details

Field Name reserved S3_ARURGENT S2_ARURGENT S1_ARURGENT S0_ARURGENT S3_AWURGENT S2_AWURGENT S1_AWURGENT S0_AWURGENT Bits 31:8 7 6 5 4 3 2 1 0 Type rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reserved Set Read port 3 prioritization. Set Read port 3 prioritization. Set Read port 2 prioritization. Set Read port 0 prioritization. Set Write port 3 prioritization. Set Write port 2 prioritization. Set Write port 1 prioritization. Set Write port 0 prioritization. Description

Register (slcr) DDR_CAL_START

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_CAL_START 0x0000060C 0xF800060C 32 bits mixed 0x00000000 DDR Calibration Start Triggers

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Register DDR_CAL_START Details

Field Name reserved START_CAL_DLL Bits 31:2 1 Type rw wo Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. This register creates a pulse that is first synchronised into the ddr_clk domain and then directly drives the co_gs_dll_calib input into the DDR controller. This signal is a command that indicates to the controller to issue a dll_calib to the DRAM. This signal should pulse for 1 ddrc_core_clk clock cycle to request a dll_calib to be issued. This is only required if the DDR controller register reg_ddrc_dis_dll_calib is 1. If reg_ddrc_dis_dll_calib is 0, the controller will automatically issue DLL Calibs. 0: Do nothing. 1: Start DLL calibration command. A read of this register returns zero. START_CAL_SHORT 0 wo 0x0 This register creates a pulse that is first synchronized into the ddr_clk domain and then directly drives the co_gs_zq_calib_short input into the DDR controller. This is required to pulse for 1 clock to issue ZQ Calibration Short Command to the DDR. There should be a minimum of 512 clks gap between 2 ZQ Calib Short commands from the core. If DDR controller register reg_ddrc_dis_auto_zq=0, asserting co_gs_zq_calib_short is not required, as this will be done automatically. If reg_ddrc_dis_auto_zq=1, then the core logic is required to assert co_gs_zq_calib_short periodically to update DDR3 ZQ calibration. 0: Do nothing. 1: Start ZQ calibration short command. A read of this register returns zero.

Register (slcr) DDR_REF_START

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_REF_START 0x00000614 0xF8000614 32 bits mixed 0x00000000 DDR Refresh Start Triggers

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Register DDR_REF_START Details

Field Name reserved START_REF Bits 31:1 0 Type rw wo Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. This register creates a pulse that is first synchronized into the ddr_clk domain and then directly drives the co_gs_rank_refresh input into the DDR controller. This register must be used with the Virage DRAM controller register bit reg_ddrc_dis_auto_refresh. This signal is a command that indicates to the controller to issue a refresh to the DRAM. One bit per rank. This signal should pulse for 1 ddrc_core_clk clock cycle to request a refresh to be issued. 0: Do nothing. 1: Start refresh. A read of this register returns zero.

Register (slcr) DDR_CMD_STA

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_CMD_STA 0x00000618 0xF8000618 32 bits mixed 0x00000000 DDR Command Store Status

Register DDR_CMD_STA Details

Field Name reserved CMD_Q_NEMPTY Bits 31:1 0 Type rw ro Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. DDR controller command store fill status. 0: indicates DDRC command store is empty. 1: indicates there are commands pending in DDRC command store. This register is a continuous monitor of the ddrc_co_q_not_empty output from the DDR controller, which is first synchronised from ddr_clk into amba1x_clk.

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Register (slcr) DDR_URGENT_SEL

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_URGENT_SEL 0x0000061C 0xF800061C 32 bits rw 0x00000000 DDR Urgent Select

Register DDR_URGENT_SEL Details

Field Name reserved S3_ARQOS_MODE Bits 31:16 15:14 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Selects between the AXI port s3_awqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s3_awurgent bit is driven from the 'S3_AWURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s3_awurgent bit is driven from the s3_awqos bit. 10: DDRC s3_awurgent bit is driven from the fabric ddr_arb[3] input. 11: undefined S2_ARQOS_MODE 13:12 rw 0x0 Selects between the AXI port s2_arqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s2_arurgent bit is driven from the 'S2_ARURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s2_arurgent bit is driven from the s2_arqos bit. 10: DDRC s2_arurgent bit is driven from the fabric ddr_arb[2] input. 11: undefined

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Field Name S1_ARQOS_MODE

Bits 11:10

Type rw

Reset Value 0x0

Description Selects between the AXI port s1_arqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s1_arurgent bit is driven from the 'S1_ARURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s1_arurgent bit is driven from the s1_arqos bit. 10: DDRC s1_arurgent bit is driven from the fabric ddr_arb[1] input. 11: undefined.

S0_ARQOS_MODE

9:8

rw

0x0

Selects between the fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s0_arurgent bit is driven from the 'S0_ARURGENT' field of the DDR_URGENT_VAL register. x1: undefined 10: DDRC s0_arurgent bit is driven from the fabric ddr_arb[0] input. 11: undefined

S3_AWQOS_MODE

7:6

rw

0x0

Selects between the AXI port s3_awqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s3_awurgent bit is driven from the 'S3_AWURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s3_awurgent bit is driven from the s3_awqos bit. 10: DDRC s3_awurgent bit is driven from the fabric ddr_arb[3] input. 11: undefined

S2_AWQOS_MODE

5:4

rw

0x0

Selects between the AXI port s2_awqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s2_awurgent bit is driven from the 'S2_AWURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s2_awurgent bit is driven from the s2_awqos bit. 10: DDRC s2_awurgent bit is driven from the fabric ddr_arb[2] input. 11: undefined

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Field Name S1_AWQOS_MODE

Bits 3:2

Type rw

Reset Value 0x0

Description Selects between the AXI port s1_awqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s1_awurgent bit is driven from the 'S1_AWURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s1_awurgent bit is driven from the s1_awqos bit. 10: DDRC s1_awurgent bit is driven from the fabric ddr_arb[1] input. 11: undefined

S0_AWQOS_MODE

1:0

rw

0x0

Selects between the fabric signal or static register to drive the DDRC urgent bit. 00: The DDRC s0_awurgent bit is driven from the 'S0_AWURGENT' field of the DDR_URGENT_VAL register. x1: undefined 10: The DDRC s0_awurgent bit is driven from the fabric ddr_arb[0] input. 11: undefined

Register (slcr) DDR_DFI_STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description DDR_DFI_STATUS 0x00000620 0xF8000620 32 bits mixed 0x00000000 DDR DFI status

Register DDR_DFI_STATUS Details

Field Name reserved DFI_CAL_ST Bits 31:1 0 Type rw ro Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. This signal is intended to allow a calibration of the IOB's at a time when the DDR controller is in its calibration mode, i.e. during an idle period.

Register (slcr) MIO_PIN_00

Name MIO_PIN_00

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000700 0xF8000700 32 bits rw 0x00001601 MIO Pin 0 Control

Register MIO_PIN_00 Details

Field Name reserved DisableRcvr Bits 31:14 13 Type rw rw Reset Value 0x0 0x0 reserved Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable PULLUP 12 rw 0x1 Enables Pullup on IO Buffer pin 0: disable 1: enable IO_Type 11:9 rw 0x3 Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011: LVCMOS33 100: HSTL 101: Reserved 110: Reserved 111: Reserved Speed 8 rw 0x0 Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output Description

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Field Name L1_SEL

Bits 2

Type rw

Reset Value 0x0

Description Level 1 Mux Select 0: Level 2 Mux 1: reserved

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output

TRI_ENABLE

rw

0x1

Tri-state enable, active high. 0: disable 1: enable

Register (slcr) MIO_PIN_01

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_01 0x00000704 0xF8000704 32 bits rw 0x00001601 MIO Pin 1 Control

Register MIO_PIN_01 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output Description

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Field Name L1_SEL

Bits 2

Type rw

Reset Value 0x0

Description Level 1 Mux Select 0: Level 2 Mux 1: reserved

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_02

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_02 0x00000708 0xF8000708 32 bits rw 0x00000601 MIO Pin 2 Control

Register MIO_PIN_02 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output Description

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Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_03

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_03 0x0000070C 0xF800070C 32 bits rw 0x00000601 MIO Pin 3 Control

Register MIO_PIN_03 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output Description

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Appendix B: Register Details

Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_04

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_04 0x00000710 0xF8000710 32 bits rw 0x00000601 MIO Pin 4 Control

Register MIO_PIN_04 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output Description

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Appendix B: Register Details

Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_05

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_05 0x00000714 0xF8000714 32 bits rw 0x00000601 MIO Pin 5 Control

Register MIO_PIN_05 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output Description

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Appendix B: Register Details

Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_06

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_06 0x00000718 0xF8000718 32 bits rw 0x00000601 MIO Pin 6 Control

Register MIO_PIN_06 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output Description

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Appendix B: Register Details

Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_07

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_07 0x0000071C 0xF800071C 32 bits rw 0x00000601 MIO Pin 7 Control

Register MIO_PIN_07 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output Description

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Appendix B: Register Details

Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: reserved

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_08

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_08 0x00000720 0xF8000720 32 bits rw 0x00000601 MIO Pin 8 Control

Register MIO_PIN_08 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output Description

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Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_09

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_09 0x00000724 0xF8000724 32 bits rw 0x00001601 MIO Pin 9 Control

Register MIO_PIN_09 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output Description

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Field Name L0_SEL

Bits 1

Type rw

Reset Value 0x0

Description Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_10

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_10 0x00000728 0xF8000728 32 bits rw 0x00001601 MIO Pin 10 Control

Register MIO_PIN_10 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output Description

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Field Name L1_SEL

Bits 2

Type rw

Reset Value 0x0

Description Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_11

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_11 0x0000072C 0xF800072C 32 bits rw 0x00001601 MIO Pin 11 Control

Register MIO_PIN_11 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output Description

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Field Name L2_SEL

Bits 4:3

Type rw

Reset Value 0x0

Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output

L1_SEL

rw

0x0

Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_12

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_12 0x00000730 0xF8000730 32 bits rw 0x00001601 MIO Pin 12 Control

Register MIO_PIN_12 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed Bits 31:14 13 12 11:9 8 Type rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Description

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Field Name L3_SEL

Bits 7:5

Type rw

Reset Value 0x0

Description Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output

L2_SEL

4:3

rw

0x0

Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output

L1_SEL

rw

0x0

Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_13

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_13 0x00000734 0xF8000734 32 bits rw 0x00001601 MIO Pin 13 Control

Register MIO_PIN_13 Details

Field Name reserved DisableRcvr PULLUP Bits 31:14 13 12 Type rw rw rw Reset Value 0x0 0x0 0x1 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Description

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Appendix B: Register Details

Field Name IO_Type Speed L3_SEL

Bits 11:9 8 7:5

Type rw rw rw

Reset Value 0x3 0x0 0x0

Description Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input

L2_SEL

4:3

rw

0x0

Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output

L1_SEL

rw

0x0

Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output

L0_SEL

rw

0x0

Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output

TRI_ENABLE

rw

0x1

Operates the same as MIO_PIN_00[TRI_ENABLE]

Register (slcr) MIO_PIN_14

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_14 0x00000738 0xF8000738 32 bits rw 0x00001601 MIO Pin 14 Control

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Register MIO_PIN_14 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1= Not Used TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_15

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_15 0x0000073C 0xF800073C 32 bits rw 0x00001601 MIO Pin 15 Control

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Register MIO_PIN_15 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1= Not Used TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_16

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_16 0x00000740 0xF8000740 32 bits rw 0x00001601 MIO Pin 16 Control

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Register MIO_PIN_16 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_17

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_17 0x00000744 0xF8000744 32 bits rw 0x00001601 MIO Pin 17 Control

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Register MIO_PIN_17 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_18

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_18 0x00000748 0xF8000748 32 bits rw 0x00001601 MIO Pin 18 Control

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Register MIO_PIN_18 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_19

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_19 0x0000074C 0xF800074C 32 bits rw 0x00001601 MIO Pin 19 Control

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Register MIO_PIN_19 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_20

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_20 0x00000750 0xF8000750 32 bits rw 0x00001601 MIO Pin 20 Control

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Appendix B: Register Details

Register MIO_PIN_20 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: reserved L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_21

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_21 0x00000754 0xF8000754 32 bits rw 0x00001601 MIO Pin 21 Control

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Register MIO_PIN_21 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: reserved L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_22

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_22 0x00000758 0xF8000758 32 bits rw 0x00001601 MIO Pin 22 Control

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Register MIO_PIN_22 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_23

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_23 0x0000075C 0xF800075C 32 bits rw 0x00001601 MIO Pin 23 Control

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Register MIO_PIN_23 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_24

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_24 0x00000760 0xF8000760 32 bits rw 0x00001601 MIO Pin 24 Control

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Register MIO_PIN_24 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_25

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_25 0x00000764 0xF8000764 32 bits rw 0x00001601 MIO Pin 25 Control

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Register MIO_PIN_25 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_26

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_26 0x00000768 0xF8000768 32 bits rw 0x00001601 MIO Pin 26 Control

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Register MIO_PIN_26 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_27

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_27 0x0000076C 0xF800076C 32 bits rw 0x00001601 MIO Pin 27 Control

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Register MIO_PIN_27 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_28

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_28 0x00000770 0xF8000770 32 bits rw 0x00001601 MIO Pin 28 Control

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Register MIO_PIN_28 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_29

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_29 0x00000774 0xF8000774 32 bits rw 0x00001601 MIO Pin 29 Control

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Register MIO_PIN_29 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_30

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_30 0x00000778 0xF8000778 32 bits rw 0x00001601 MIO Pin 30 Control

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Register MIO_PIN_30 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_31

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_31 0x0000077C 0xF800077C 32 bits rw 0x00001601 MIO Pin 31 Control

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Register MIO_PIN_31 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_32

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_32 0x00000780 0xF8000780 32 bits rw 0x00001601 MIO Pin 32 Control

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Register MIO_PIN_32 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_33

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_33 0x00000784 0xF8000784 32 bits rw 0x00001601 MIO Pin 33 Control

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Register MIO_PIN_33 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_34

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_34 0x00000788 0xF8000788 32 bits rw 0x00001601 MIO Pin 34 Control

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Register MIO_PIN_34 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_35

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_35 0x0000078C 0xF800078C 32 bits rw 0x00001601 MIO Pin 35 Control

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Register MIO_PIN_35 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_36

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_36 0x00000790 0xF8000790 32 bits rw 0x00001601 MIO Pin 36 Control

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Register MIO_PIN_36 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_37

Name Relative Address Absolute Address Width Access Type Reset Value MIO_PIN_37 0x00000794 0xF8000794 32 bits rw 0x00001601

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Description

MIO Pin 37 Control

Register MIO_PIN_37 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_38

Name Relative Address Absolute Address Width Access Type MIO_PIN_38 0x00000798 0xF8000798 32 bits rw

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Reset Value Description

0x00001601 MIO Pin 38 Control

Register MIO_PIN_38 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_39

Name Relative Address Absolute Address Width MIO_PIN_39 0x0000079C 0xF800079C 32 bits

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Access Type Reset Value Description

rw 0x00001601 MIO Pin 39 Control

Register MIO_PIN_39 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_40

Name Relative Address Absolute Address MIO_PIN_40 0x000007A0 0xF80007A0

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Width Access Type Reset Value Description

32 bits rw 0x00001601 MIO Pin 40 Control

Register MIO_PIN_40 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_41

Name Relative Address MIO_PIN_41 0x000007A4

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Absolute Address Width Access Type Reset Value Description

0xF80007A4 32 bits rw 0x00001601 MIO Pin 41 Control

Register MIO_PIN_41 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

Register (slcr) MIO_PIN_42

Name MIO_PIN_42

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Relative Address Absolute Address Width Access Type Reset Value Description

0x000007A8 0xF80007A8 32 bits rw 0x00001601 MIO Pin 42 Control

Register MIO_PIN_42 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1= Not Used TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_43

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_43 0x000007AC 0xF80007AC 32 bits rw 0x00001601 MIO Pin 43 Control

Register MIO_PIN_43 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_44

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_44 0x000007B0 0xF80007B0 32 bits rw 0x00001601 MIO Pin 44 Control

Register MIO_PIN_44 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_45

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_45 0x000007B4 0xF80007B4 32 bits rw 0x00001601 MIO Pin 45 Control

Register MIO_PIN_45 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_46

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_46 0x000007B8 0xF80007B8 32 bits rw 0x00001601 MIO Pin 46 Control

Register MIO_PIN_46 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_47

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_47 0x000007BC 0xF80007BC 32 bits rw 0x00001601 MIO Pin 47 Control

Register MIO_PIN_47 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_48

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_48 0x000007C0 0xF80007C0 32 bits rw 0x00001601 MIO Pin 48 Control

Register MIO_PIN_48 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_49

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_49 0x000007C4 0xF80007C4 32 bits rw 0x00001601 MIO Pin 49 Control

Register MIO_PIN_49 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_50

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_50 0x000007C8 0xF80007C8 32 bits rw 0x00001601 MIO Pin 50 Control

Register MIO_PIN_50 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_51

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_51 0x000007CC 0xF80007CC 32 bits rw 0x00001601 MIO Pin 51 Control

Register MIO_PIN_51 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_52

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_52 0x000007D0 0xF80007D0 32 bits rw 0x00001601 MIO Pin 52 Control

Register MIO_PIN_52 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: reserved L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_PIN_53

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_PIN_53 0x000007D4 0xF80007D4 32 bits rw 0x00001601 MIO Pin 53 Control

Register MIO_PIN_53 Details

Field Name reserved DisableRcvr PULLUP IO_Type Speed L3_SEL Bits 31:14 13 12 11:9 8 7:5 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x1 0x3 0x0 0x0 reserved Operates the same as MIO_PIN_00[DisableRcvr] Operates the same as MIO_PIN_00[PULLUP] Operates the same as MIO_PIN_00[IO_Type] Operates the same as MIO_PIN_00[Speed] Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: reserved L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Description

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Register (slcr) MIO_LOOPBACK

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_LOOPBACK 0x00000804 0xF8000804 32 bits rw 0x00000000 Loopback function within MIO

Register MIO_LOOPBACK Details

Field Name reserved I2C0_LOOP_I2C1 Bits 31:4 3 Type rw rw Reset Value 0x0 0x0 reserved I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs. CAN0_LOOP_CAN1 2 rw 0x0 CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. UA0_LOOP_UA1 1 rw 0x0 UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. SPI0_LOOP_SPI1 0 rw 0x0 SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. Description

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Register (slcr) MIO_MST_TRI0

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_MST_TRI0 0x0000080C 0xF800080C 32 bits rw 0xFFFFFFFF MIO pin Tri-state Enables, 31:0

Register MIO_MST_TRI0 Details

Parallel access to the master tri-state enables for MIO pins
Field Name PIN_31_TRI PIN_30_TRI PIN_29_TRI PIN_28_TRI PIN_27_TRI PIN_26_TRI PIN_25_TRI PIN_24_TRI PIN_23_TRI PIN_22_TRI PIN_21_TRI PIN_20_TRI PIN_19_TRI PIN_18_TRI PIN_17_TRI PIN_16_TRI PIN_15_TRI PIN_14_TRI PIN_13_TRI PIN_12_TRI PIN_11_TRI PIN_10_TRI PIN_09_TRI Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description Master Tri-state Enable for pin 31, active high Master Tri-state Enable for pin 30, active high Master Tri-state Enable for pin 29, active high Master Tri-state Enable for pin 28, active high Master Tri-state Enable for pin 27, active high Master Tri-state Enable for pin 26, active high Master Tri-state Enable for pin 25, active high Master Tri-state Enable for pin 24, active high Master Tri-state Enable for pin 23, active high Master Tri-state Enable for pin 22, active high Master Tri-state Enable for pin 21, active high Master Tri-state Enable for pin 20, active high Master Tri-state Enable for pin 19, active high Master Tri-state Enable for pin 18, active high Master Tri-state Enable for pin 17, active high Master Tri-state Enable for pin 16, active high Master Tri-state Enable for pin 15, active high Master Tri-state Enable for pin 14, active high Master Tri-state Enable for pin 13, active high Master Tri-state Enable for pin 12, active high Master Tri-state Enable for pin 11, active high Master Tri-state Enable for pin 10, active high Master Tri-state Enable for pin 9, active high

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Field Name PIN_08_TRI PIN_07_TRI PIN_06_TRI PIN_05_TRI PIN_04_TRI PIN_03_TRI PIN_02_TRI PIN_01_TRI PIN_00_TRI

Bits 8 7 6 5 4 3 2 1 0

Type rw rw rw rw rw rw rw rw rw

Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1

Description Master Tri-state Enable for pin 8, active high Master Tri-state Enable for pin 7, active high Master Tri-state Enable for pin 6, active high Master Tri-state Enable for pin 5, active high Master Tri-state Enable for pin 4, active high Master Tri-state Enable for pin 3, active high Master Tri-state Enable for pin 2, active high Master Tri-state Enable for pin 1, active high Master Tri-state Enable for pin 0, active high

Register (slcr) MIO_MST_TRI1

Name Relative Address Absolute Address Width Access Type Reset Value Description MIO_MST_TRI1 0x00000810 0xF8000810 32 bits rw 0x003FFFFF MIO pin Tri-state Enables, 53:32

Register MIO_MST_TRI1 Details

Parallel access to the master tri-state enables for MIO pins
Field Name reserved PIN_53_TRI PIN_52_TRI PIN_51_TRI PIN_50_TRI PIN_49_TRI PIN_48_TRI PIN_47_TRI PIN_46_TRI PIN_45_TRI PIN_44_TRI Bits 31:22 21 20 19 18 17 16 15 14 13 12 Type rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 reserved Master Tri-state Enable for pin 53, active high Master Tri-state Enable for pin 52, active high Master Tri-state Enable for pin 51, active high Master Tri-state Enable for pin 50, active high Master Tri-state Enable for pin 49, active high Master Tri-state Enable for pin 48, active high Master Tri-state Enable for pin 47, active high Master Tri-state Enable for pin 46, active high Master Tri-state Enable for pin 45, active high Master Tri-state Enable for pin 44, active high Description

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Field Name PIN_43_TRI PIN_42_TRI PIN_41_TRI PIN_40_TRI PIN_39_TRI PIN_38_TRI PIN_37_TRI PIN_36_TRI PIN_35_TRI PIN_34_TRI PIN_33_TRI PIN_32_TRI

Bits 11 10 9 8 7 6 5 4 3 2 1 0

Type rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1

Description Master Tri-state Enable for pin 43, active high Master Tri-state Enable for pin 42, active high Master Tri-state Enable for pin 41, active high Master Tri-state Enable for pin 40, active high Master Tri-state Enable for pin 39, active high Master Tri-state Enable for pin 38, active high Master Tri-state Enable for pin 37, active high Master Tri-state Enable for pin 36, active high Master Tri-state Enable for pin 35, active high Master Tri-state Enable for pin 34, active high Master Tri-state Enable for pin 33, active high Master Tri-state Enable for pin 32, active high

Register (slcr) SD0_WP_CD_SEL

Name Relative Address Absolute Address Width Access Type Reset Value Description SD0_WP_CD_SEL 0x00000830 0xF8000830 32 bits rw 0x00000000 SDIO 0 WP CD select

Register SD0_WP_CD_SEL Details

Field Name reserved SDIO0_CD_SEL Bits 31:22 21:16 Type rw rw Reset Value 0x0 0x0 reserved SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input reserved SDIO0_WP_SEL 15:6 5:0 rw rw 0x0 0x0 reserved SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input Description

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Register (slcr) SD1_WP_CD_SEL

Name Relative Address Absolute Address Width Access Type Reset Value Description SD1_WP_CD_SEL 0x00000834 0xF8000834 32 bits rw 0x00000000 SDIO 1 WP CD select

Register SD1_WP_CD_SEL Details

Field Name reserved SDIO1_CD_SEL Bits 31:22 21:16 Type rw rw Reset Value 0x0 0x0 reserved SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input reserved SDIO1_WP_SEL 15:6 5:0 rw rw 0x0 0x0 reserved SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input Description

Register (slcr) LVL_SHFTR_EN

Name Relative Address Absolute Address Width Access Type Reset Value Description LVL_SHFTR_EN 0x00000900 0xF8000900 32 bits rw 0x00000000 Level Shifters Enable

Register LVL_SHFTR_EN Details

Field Name reserved Bits 31:5 Type rw Reset Value 0x0 Description Reserved. Writes are ignored, read data is zero.

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Field Name reserved USER_LVL_SHFTR_E N

Bits 4 3:0

Type rw rw

Reset Value 0x0 0x0

Description Reserved. Do not modify. Level shifter enable to drive signals between PS and PL. 0x0 = disabled 0xF = enabled All other = reserved

Register (slcr) OCM_CFG

Name Relative Address Absolute Address Width Access Type Reset Value Description OCM_CFG 0x00000910 0xF8000910 32 bits rw 0x00000000 OCM Address Mapping

Register OCM_CFG Details

Field Name reserved reserved RAM_HI Bits 31:5 4 3:0 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Maps the OCM RAM (in 64 KB sections) to the high or low address space: 0: low address. 1: high address. RAM_HI [0] is first 64 KB RAM_HI [1] is second 64 KB RAM_HI [2] is third 64 KB RAM_HI [3] is fourth 64 KB Refer to the OCM chapter for more details.

Register (slcr) Reserved

Name Relative Address Absolute Address Width Access Type Reserved 0x00000A1C 0xF8000A1C 32 bits rw

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Reset Value Description

0x00010101 Reserved

Register Reserved Details

Field Name reserved reserved reserved reserved Bits 23:22 21 20:19 18:16 Type rw rw rw rw Reset Value 0x0 0x0 0x0 0x1 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Must be set to 2. Any other value including the reset value may lead to undefined behavior. reserved reserved reserved reserved 15:14 13 12:11 10:8 rw rw rw rw 0x0 0x0 0x0 0x1 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Must be set to 2. Any other value including the reset value may lead to undefined behavior. reserved reserved reserved reserved 7:6 5 4:3 2:0 rw rw rw rw 0x0 0x0 0x0 0x1 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Must be set to 2. Any other value including the reset value may lead to undefined behavior.

Register (slcr) GPIOB_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIOB_CTRL 0x00000B00 0xF8000B00 32 bits rw 0x00000000 PS IO Buffer Control

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Register GPIOB_CTRL Details

Field Name reserved VREF_SW_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Enables the VREF switch 0: internal 1: external reserved reserved reserved reserved VREF_SEL 10 9 8 7 6:4 rw rw rw rw rw 0x0 0x0 0x0 0x0 0x0 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Specifies GPIO VREF Selection 000: VREF = Disabled 001: VREF = 0.9V Other values reserved reserved reserved reserved VREF_EN 3 2 1 0 rw rw rw rw 0x0 0x0 0x0 0x0 Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Enables VREF internal generator

Register (slcr) GPIOB_CFG_CMOS18

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIOB_CFG_CMOS18 0x00000B04 0xF8000B04 32 bits rw 0x00000000 MIO GPIOB CMOS 1.8V config

Register GPIOB_CFG_CMOS18 Details

The only allowed values for this register are 0x00000000 (reset value) and 0x0C301166 (normal operation)
Field Name reserved reserved reserved reserved Bits 31:28 27:25 24:22 21:19 Type rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

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Field Name reserved reserved reserved reserved reserved

Bits 18:16 15:12 11:8 7:4 3:0

Type rw rw rw rw rw

Reset Value 0x0 0x0 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) GPIOB_CFG_CMOS25

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIOB_CFG_CMOS25 0x00000B08 0xF8000B08 32 bits rw 0x00000000 MIO GPIOB CMOS 2.5V config

Register GPIOB_CFG_CMOS25 Details

The only allowed values for this register are 0x00000000 (reset value) and 0x0C301100 (normal operation)
Field Name reserved reserved reserved reserved reserved reserved reserved reserved reserved Bits 31:28 27:25 24:22 21:19 18:16 15:12 11:8 7:4 3:0 Type rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) GPIOB_CFG_CMOS33

Name Relative Address Absolute Address Width GPIOB_CFG_CMOS33 0x00000B0C 0xF8000B0C 32 bits

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Access Type Reset Value Description

rw 0x00000000 MIO GPIOB CMOS 3.3V config

Register GPIOB_CFG_CMOS33 Details

The only allowed values for this register are 0x00000000 (reset value) and 0x0C301166 (normal operation)
Field Name reserved reserved reserved reserved reserved reserved reserved reserved reserved Bits 31:28 27:25 24:22 21:19 18:16 15:12 11:8 7:4 3:0 Type rw rw rw rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) GPIOB_CFG_HSTL

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIOB_CFG_HSTL 0x00000B14 0xF8000B14 32 bits rw 0x00000000 MIO GPIOB HSTL config

Register GPIOB_CFG_HSTL Details

The only allowed values for this register are 0x00000000 (reset value) and 0x0C750077 (normal operation). You must provide a VREF or use the internal VREF generator. When setting the input to HSTL, you must ensure that VCCO_MIO is below 1.8V. If not, this will lead to long term damage to the IO.
Field Name reserved reserved reserved Bits 31:28 27:25 24:22 Type rw rw rw Reset Value 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify.

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Field Name reserved reserved reserved reserved reserved reserved

Bits 21:19 18:16 15:12 11:8 7:4 3:0

Type rw rw rw rw rw rw

Reset Value 0x0 0x0 0x0 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) GPIOB_DRVR_BIAS_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GPIOB_DRVR_BIAS_CTRL 0x00000B18 0xF8000B18 32 bits mixed 0x00000000 MIO GPIOB Driver Bias Control

Register GPIOB_DRVR_BIAS_CTRL Details

Field Name RB_VCFG RB_DRVR_BIAS LB_VCFG LB_DRVR_BIAS Bits 31 30:16 15 14:0 Type ro rw ro rw Reset Value 0x0 0x0 0x0 0x0 Description Right Bank VCFG (Read Only) Right Bank driver bias control Left Bank VCFG (Read Only) Left Bank driver bias control

Register (slcr) DDRIOB_ADDR0

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_ADDR0 0x00000B40 0xF8000B40 32 bits rw 0x00000800 DDR IOB Config for A[14:0], CKE and DRST_B

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Register DDRIOB_ADDR0 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. IBUF_DISABLE_MOD E 7 rw 0x0 Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. DCI_TYPE 6:5 rw 0x0 DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF) TERM_EN 4 rw 0x0 Tri State Termination Enable: 0: disable 1: enable DCI_UPDATE_B 3 rw 0x0 DCI Update Enable: 0: disable 1: enable Description

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Field Name INP_TYPE

Bits 2:1

Type rw

Reset Value 0x0

Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_ADDR1

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_ADDR1 0x00000B44 0xF8000B44 32 bits rw 0x00000800 DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B

Register DDRIOB_ADDR1 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. Description

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Field Name IBUF_DISABLE_MOD E

Bits 7

Type rw

Reset Value 0x0

Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.

DCI_TYPE

6:5

rw

0x0

DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF)

TERM_EN

rw

0x0

Tri State Termination Enable: 0: disable 1: enable

DCI_UPDATE_B

rw

0x0

DCI Update Enable: 0: disable 1: enable

INP_TYPE

2:1

rw

0x0

Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_DATA0

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DATA0 0x00000B48 0xF8000B48 32 bits rw 0x00000800 DDR IOB Config for Data 15:0

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Register DDRIOB_DATA0 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. IBUF_DISABLE_MOD E 7 rw 0x0 Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. DCI_TYPE 6:5 rw 0x0 DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF) TERM_EN 4 rw 0x0 Tri State Termination Enable: 0: disable 1: enable DCI_UPDATE_B 3 rw 0x0 DCI Update Enable: 0: disable 1: enable Description

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Field Name INP_TYPE

Bits 2:1

Type rw

Reset Value 0x0

Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_DATA1

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DATA1 0x00000B4C 0xF8000B4C 32 bits rw 0x00000800 DDR IOB Config for Data 31:16

Register DDRIOB_DATA1 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. Description

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Field Name IBUF_DISABLE_MOD E

Bits 7

Type rw

Reset Value 0x0

Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.

DCI_TYPE

6:5

rw

0x0

DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF)

TERM_EN

rw

0x0

Tri State Termination Enable: 0: disable 1: enable

DCI_UPDATE_B

rw

0x0

DCI Update Enable: 0: disable 1: enable

INP_TYPE

2:1

rw

0x0

Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_DIFF0

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DIFF0 0x00000B50 0xF8000B50 32 bits rw 0x00000800 DDR IOB Config for DQS 1:0

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Register DDRIOB_DIFF0 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. IBUF_DISABLE_MOD E 7 rw 0x0 Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. DCI_TYPE 6:5 rw 0x0 DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF) TERM_EN 4 rw 0x0 Tri State Termination Enable: 0: disable 1: enable DCI_UPDATE_B 3 rw 0x0 DCI Update Enable: 0: disable 1: enable Description

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Field Name INP_TYPE

Bits 2:1

Type rw

Reset Value 0x0

Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_DIFF1

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DIFF1 0x00000B54 0xF8000B54 32 bits rw 0x00000800 DDR IOB Config for DQS 3:2

Register DDRIOB_DIFF1 Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. Description

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Field Name IBUF_DISABLE_MOD E

Bits 7

Type rw

Reset Value 0x0

Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.

DCI_TYPE

6:5

rw

0x0

DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF)

TERM_EN

rw

0x0

Tri State Termination Enable: 0: disable 1: enable

DCI_UPDATE_B

rw

0x0

DCI Update Enable: 0: disable 1: enable

INP_TYPE

2:1

rw

0x0

Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_CLOCK

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_CLOCK 0x00000B58 0xF8000B58 32 bits rw 0x00000800 DDR IOB Config for Clock Output

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Register DDRIOB_CLOCK Details

Field Name reserved PULLUP_EN Bits 31:12 11 Type rw rw Reset Value 0x0 0x1 Reserved enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. IBUF_DISABLE_MOD E 7 rw 0x0 Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. DCI_TYPE 6:5 rw 0x0 DCI Mode Selection: 00: DCI Disabled (DDR2/3L ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3/3L DATA and DIFF) TERM_EN 4 rw 0x0 Tri State Termination Enable: 0: disable 1: enable DCI_UPDATE_B 3 rw 0x0 DCI Update Enable: 0: disable 1: enable Description

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Field Name INP_TYPE

Bits 2:1

Type rw

Reset Value 0x0

Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.

reserved

rw

0x0

Reserved. Do not modify.

Register (slcr) DDRIOB_DRIVE_SLEW_ADDR

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DRIVE_SLEW_ADDR 0x00000B5C 0xF8000B5C 32 bits rw 0x00000000 Drive and Slew controls for Address and Command pins of the DDR Interface

Register DDRIOB_DRIVE_SLEW_ADDR Details

Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code. Values other than the one computed by EDK are not supported
Field Name reserved reserved reserved reserved reserved reserved Bits 31:27 26:24 23:19 18:14 13:7 6:0 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) DDRIOB_DRIVE_SLEW_DATA

Name Relative Address Absolute Address Width DDRIOB_DRIVE_SLEW_DATA 0x00000B60 0xF8000B60 32 bits

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Access Type Reset Value Description

rw 0x00000000 Drive and Slew controls for DQ pins of the DDR Interface

Register DDRIOB_DRIVE_SLEW_DATA Details

Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code. Values other than the one computed by EDK are not supported
Field Name reserved reserved reserved reserved reserved reserved Bits 31:27 26:24 23:19 18:14 13:7 6:0 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) DDRIOB_DRIVE_SLEW_DIFF

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DRIVE_SLEW_DIFF 0x00000B64 0xF8000B64 32 bits rw 0x00000000 Drive and Slew controls for DQS pins of the DDR Interface

Register DDRIOB_DRIVE_SLEW_DIFF Details

Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code. Values other than the one computed by EDK are not supported
Field Name reserved reserved reserved reserved reserved reserved Bits 31:27 26:24 23:19 18:14 13:7 6:0 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

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Register (slcr) DDRIOB_DRIVE_SLEW_CLOCK

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DRIVE_SLEW_CLOCK 0x00000B68 0xF8000B68 32 bits rw 0x00000000 Drive and Slew controls for Clock pins of the DDR Interface

Register DDRIOB_DRIVE_SLEW_CLOCK Details

Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code. Values other than the one computed by EDK are not supported
Field Name reserved reserved reserved reserved reserved reserved Bits 31:27 26:24 23:19 18:14 13:7 6:0 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

Register (slcr) DDRIOB_DDR_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DDR_CTRL 0x00000B6C 0xF8000B6C 32 bits rw 0x00000000 DDR IOB Buffer Control

Register DDRIOB_DDR_CTRL Details

Field Name reserved reserved reserved Bits 31:15 14 13 Type rw rw rw Reset Value 0x0 0x0 0x0 reserved Reserved. Do not modify. Reserved. Do not modify. Description

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Field Name reserved reserved REFIO_EN

Bits 12 11:10 9

Type rw rw rw

Reset Value 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio

reserved VREF_EXT_EN

8:7 6:5

rw rw

0x0 0x0

Reserved. Do not modify. Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits

VREF_SEL

4:1

rw

0x0

Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0010: VREF = 0.675V for DDR3L with 1.35V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO

VREF_INT_EN

rw

0x0

Enables VREF internal generator

Register (slcr) DDRIOB_DCI_CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DCI_CTRL 0x00000B70 0xF8000B70 32 bits rw 0x00000020 DDR IOB DCI Config

Register DDRIOB_DCI_CTRL Details

Field Name reserved reserved reserved reserved reserved reserved Bits 31:28 27 26 25 24 23 Type rw rw rw rw rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

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Field Name reserved reserved UPDATE_CONTROL PREF_OPT2 reserved PREF_OPT1 NREF_OPT4 NREF_OPT2 NREF_OPT1 reserved reserved reserved reserved ENABLE

Bits 22 21 20 19:17 16 15:14 13:11 10:8 7:6 5 4 3 2 1

Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0

Description Reserved. Do not modify. Reserved. Do not modify. DCI Update Mode. Use the values in the Calibration Table. DCI Calibration. Use the values in the Calibration Table. Reserved DCI Calibration. Use the values in the Calibration Table. DCI Calibration. Use the values in the Calibration Table. DCI Calibration. Use the values in the Calibration Table. DCI Calibration. Use the values in the Calibration Table. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3, DDR3L and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 At least toggle once to initialize flops in DCI system

RESET

rw

0x0

Register (slcr) DDRIOB_DCI_STATUS

Name Relative Address Absolute Address Width Access Type Reset Value Description DDRIOB_DCI_STATUS 0x00000B74 0xF8000B74 32 bits mixed 0x00000000 DDR IO Buffer DCI Status

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Register DDRIOB_DCI_STATUS Details

Field Name reserved DONE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved LOCK Bits 31:14 13 12 11 10 9 8 7 6 5 4:3 2 1 0 Type ro rw rw rw ro ro ro ro ro ro ro ro ro ro Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Reserved. Writes are ignored, read data is zero. DCI done signal Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. DCI Status input Read Only

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B.29 Static Memory Controller (pl353)

Module Name Software Name Base Address Description Vendor Info Static Memory Controller (pl353) XNANDPS 0xE000E000 smcc Shared memory controller

Register Summary
Register Name memc_status memif_cfg memc_cfg_set memc_cfg_clr direct_cmd set_cycles set_opmode refresh_period_0 refresh_period_1 sram_cycles0_0 opmode0_0 sram_cycles0_1 opmode0_1 nand_cycles1_0 opmode1_0 user_status user_config ecc_status_1 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x00000020 0x00000024 0x00000100 0x00000104 0x00000120 0x00000124 0x00000180 0x00000184 0x00000200 0x00000204 0x00000400 Width 13 18 7 7 26 24 16 4 4 21 32 21 32 24 32 8 8 30 Type ro ro wo wo wo wo mixed rw rw ro ro ro ro ro ro ro wo ro Reset Value 0x00000000 0x00011205 x x x x x 0x00000000 0x00000000 0x0002B3CC 0xE2FE0800 0x0002B3CC 0xE4FE0800 0x0024ABCC 0xE1FF0001 0x00000000 x 0x00000000 Description Operating and Interrupt Status SMC configuration information Enable interrupts and lower power state Disable interrupts and exit from low-power state Issue mem commands and register updates Stage a write to a Cycle register Stage a write to an OpMode register Idle cycles between read/write bursts Insert idle cycles between bursts SRAM/NOR chip select 0 timing, active SRAM/NOR chip select 0 OpCode, active SRAM/NOR chip select 1 timing, active SRAM/NOR chip select 1 OpCode, active NAND Flash timing, active NAND Flash OpCode, active User Status Register User Configuration Register ECC Status and Clear Register 1

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Register Name ecc_memcfg_1 ecc_memcommand1_1 ecc_memcommand2_1 ecc_addr0_1 ecc_addr1_1 ecc_value0_1 ecc_value1_1 ecc_value2_1 ecc_value3_1

Address 0x00000404 0x00000408 0x0000040C 0x00000410 0x00000414 0x00000418 0x0000041C 0x00000420 0x00000424

Width 13 25 25 32 24 32 32 32 32

Type rw rw rw ro ro ro ro ro ro

Reset Value 0x00000043 0x01300080 0x01E00585 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description ECC Memory Configuation Register 1 ECC Memory Command 1 Register 1 ECC Memory Command 2 Register 1 ECC Address 0 Register 1 ECC Address 1 Register 1 ECC Value 0 Register 1 ECC Value 1 Register 1 ECC Value 2 Register 1 ECC Value 3 Register 1

Register (pl353) memc_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description memc_status MEMC_STATUS 0x00000000 0xE000E000 13 bits ro 0x00000000 Operating and Interrupt Status

Register memc_status Details

The read-only memc_status Register provides information on the configuration of the SMC and also the current state of the SMC. You cannot read this register in the Reset state
Field Name raw_ecc_int1 (RAW_ECC_INT1) reserved ecc_int1 (ECC_INT1) 11 10 ro ro 0x0 0x0 Bits 12 Type ro Reset Value 0x0 Description NAND Flash ECC interrupt raw status: 0: Not asserted 1: Asserted Reserved. Do not modify. NAND Flash ECC interrupt status after mask/enable: 0: Not asserted 1: Asserted reserved 9 ro 0x0 Reserved. Do not modify.

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Field Name ecc_int1_en (ECC_INT_EN1) reserved raw_int_status1 (RAW_INT_STATUS1)

Bits 8

Type ro

Reset Value 0x0

Description NAND Flash ECC interrupt enable setting: 0: Masked 1: Enabled

7 6

ro ro

0x0 0x0

Reserved. Do not modify. NAND Flash raw interrupt status before mask/enable: 0: Not asserted 1: Asserted

raw_int_status0 (RAW_INT_STATUS0)

ro

0x0

SRAM/NOR raw interrupt raw status before the mask/enable: 0: Not asserted 1: Asserted

int_status1 (INT_STATUS1)

ro

0x0

NAND Flash interrupt status after the mask/enable: 0: Not asserted 1: Asserted

int_status0 (INT_STATUS0)

ro

0x0

SRAM/NOR interrupt status after the mask/enable : 0: Not asserted 1: Asserted

int_en1 (INT_EN1) int_en0 (INT_EN0) state (STATE)

ro

0x0

NAND Flash interrupt enable status: 0: Disabled 1: Enabled

ro

0x0

SRAM/NOR interface interrupt enable setting: 0: Disabled 1: Enabled

ro

0x0

SMC operating state: 0: Normal 1: Low-power state

Register (pl353) memif_cfg

Name Software Name Relative Address Absolute Address Width Access Type Reset Value memif_cfg MEMC_IF_CONFIG 0x00000004 0xE000E004 18 bits ro 0x00011205

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Description

SMC configuration information

Register memif_cfg Details

Provides information on the configuration of the memory interface. You cannot read this register in the Reset state. The state of this register cannot be changed.
Field Name exclusive_monitors (EX_MONITORS) Bits 17:16 Type ro Reset Value 0x1 Description Return the number of exclusive access monitor resources that are implemented in the SMC. B00: 0 monitors b01: 1 monitor b10: 2 monitors b11: 4 monitors reserved remap1 (REMAP1) memory_width1 (MEMORY_WIDTH1) 13:12 ro 0x1 The width of the NAND Flash interface can be 8 or 16 bits. 00: 8 Bit Interface 01: 16 Bit Interface memory_chips1 (MEMORY_CHIPS1) memory_type1 (MEMORY_TYPE1) reserved remap0 (REMAP0) memory_width0 (MEMORY_WIDTH0) memory_chips0 (MEMORY_CHIPS0) memory_type0 (MEMORY_TYPE0) 1:0 ro 0x1 3:2 ro 0x1 The SRAM/NOR interface provides two chip selects. Reads as {0,1} SMC controller 0 supports the SRAM/NOR interface. 5:4 ro 0x0 The width of the SRAM/NOR interface is 8 bits. 7 6 ro ro 0x0 0x0 9:8 ro 0x2 11:10 ro 0x0 The NAND Flash interface provides one chip select. SMC controller 1 supports the NAND Flash interface with hardware assisted ECC. Reserved Return the value of the remap_0 input 15 14 ro ro 0x0 0x0 Reserved Return the value of the remap_1 input.

Register (pl353) memc_cfg_set

Name Software Name Relative Address Absolute Address memc_cfg_set MEMC_SET_CONFIG 0x00000008 0xE000E008

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Width Access Type Reset Value Description

7 bits wo x Enable interrupts and lower power state

Register memc_cfg_set Details

The write-only memc_cfg_set enables the SMC to be changed to low-power state, and interrupts enabled. You cannot write to this register in the Reset state.
Field Name ecc_int_enable1 (ECC_INT_ENABLE1) reserved reserved low_power_req (LOW_POWER_REQ) 5 4:3 2 wo wo wo x x x Bits 6 Type wo Reset Value x Description NAND Flash ECC interrupt enable: 0: No change 1: Enable Reserved. Do not modify. Reserved, write as zero. Put SMC into low-power mode when memory interface goes idle: 0: No change 1: Enable low-power state int_enable1 (INT_ENABLE1) int_enable0 (INT_ENABLE0) 0 wo x 1 wo x NAND Flash interrupt enable: 0: No change 1: Enable SRAM/NOR interrupt enable: 0: No change 1: Enable

Register (pl353) memc_cfg_clr

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description memc_cfg_clr MEMC_CLR_CONFIG 0x0000000C 0xE000E00C 7 bits wo x Disable interrupts and exit from low-power state

Register memc_cfg_clr Details

The write-only memc_cfg_clr enables the SMC to be moved out of the low-power state, and the interrupts disabled. You cannot write to this register in the Reset state.

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Field Name ecc_int_disable1 (ECC_INT_DISABLE1) reserved int_clr_1 (INT_CLR1) int_clr_0 (INT_CLR0) low_power_exit (LOW_POWER_EXIT)

Bits 6

Type wo

Reset Value x

Description NAND Flash ECC interrupt disable: 0: No change 1: Disable

5 4

wo wo

x x

Reserved. Do not modify. 0: No effect 1: Clear SMC Interrupt 1 as an alternative to an AXI read

wo

0: No effect 1: Clear SMC Interrupt 0 as an alternative to an AXI read

wo

Exit low-power mode. The affect takes place when memory interface goes idle: 0: No change 1: Exit from low-power state

int_disable1 (INT_DISABLE1) int_disable0 (INT_DISABLE0)

wo

NAND Flash interrupt disable: 0: No change 1: disable (apply mask)

wo

SRAM/NOR interrupt disable: 0: No change 1: disable (apply mask)

Register (pl353) direct_cmd

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description direct_cmd DIRECT_CMD 0x00000010 0xE000E010 26 bits wo x Issue mem commands and register updates

Register direct_cmd Details

The write-only direct_cmd passes commands to the external memory, and controls the updating of the chip configuration registers with values held in the set_cycles Register and set_opmode Register. You cannot write to this register in either the Reset or low-power states.

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Field Name chip_select (CHIP_SELECT)

Bits 25:23

Type wo

Reset Value x

Description Select register bank to update and enable chip mode register access based on CMD_TYPE: 000: SRAM/NOR chip select 0. 001: SRAM/NOR chip select 1. 100: NAND Flash. others: reserved.

cmd_type (TYPE)

22:21

wo

Select the command type: 00: UpdateRegs and AXI 01: ModeReg 10: UpdateRegs 11: ModeReg and UpdateRegs

reserved addr (ADDR)

20 19:0

wo wo

x x

Reserved. Do not modify. When cmd_type = UpdateRegs and AXI then: Bits [15:0] are used to match wdata[15:0] Bits [19:16] are reserved. Write as zero. When cmd_type = ModeReg or ModeReg and UpdateRegs, these bits map to the external memory address bits [19:0]. When cmd_type = UpdateRegs, these bits are reserved. Write as zero.

Register (pl353) set_cycles

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description set_cycles SET_CYCLES 0x00000014 0xE000E014 24 bits wo x Stage a write to a Cycle register

Register set_cycles Details

This write-only register contains values that are written to the sram_cycles register or nand_cycles when the SMC receives a write to the Direct Command Register. You cannot write to this register in either the Reset or low-power states.

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Field Name Set_t6 (SET_T6)

Bits 23:20

Type wo

Reset Value x

Description Timing parameter for SRAM/NOR, bit 20 only (other bits are ignored): o For asynchronous multiplexed transfers this bit controls when the SMC asserts we_n: 0: assert we_n two mclk cycles after asserting cs_n. 1: assert we_n and cs_n together. Timing parameter for NAND Flash, bits 23:20: o Busy to RE timing (t_rr), minimum permitted value = 0.

Set_t5 (SET_T5)

19:17

wo

Timing parameter for SRAM/NOR: o Turnaround time (t_ta), minimum value = 1. Timing parameter for NAND Flash: o ID read time (t_ar), mnimum value = 0.

Set_t4 (SET_T4)

16:14

wo

Timing parameter for SRAM/NOR: o Page cycle time (t_pc), minimum value = 1. Timing parameter for NAND Flash: o Page cycle time (t_clr), minimum value = 1.

Set_t3 (SET_T3)

13:11

wo

Timing parameter for SRAM/NOR: o Write Enable (t_wp) assertion delay, minimum value = 1. Timing parameter for NAND Flash: o Write Enable (t_wp) deassertion delay, minimum value = 1.

Set_t2 (SET_T2)

10:8

wo

Timing parameter for SRAM/NOR: o Output Enable (t_ceoe) assertion delay, minimum value = 1. Timing parameter for NAND Flash: o REA (t_rea) assertion delay, minimum value = 1.

Set_t1 (SET_T1) Set_t0 (SET_T0)

7:4

wo

Timing parameter for SRAM/NOR and NAND Flash: Write cycle time, minimum value = 2. Timing parameter for SRAM/NOR and NAND Flash: Read cycle time, minimum value = 2.

3:0

wo

Register (pl353) set_opmode

Name Software Name Relative Address set_opmode SET_OPMODE 0x00000018

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Absolute Address Width Access Type Reset Value Description

0xE000E018 16 bits mixed x Stage a write to an OpMode register

Register set_opmode Details

This write-only register is the holding register for the opmode<x>_<n> Registers. You cannot write to it in either the Reset or low-power states.
Field Name reserved set_bls (SET_BLS) Bits 15:13 12 Type wo wo x x Reset Value Description Reserved. Do not modify. NAND Flash: reserved, write zero. SRAM/NOR: Value written to the byte lane strobe (bls) bit. This bit affects the assertion of the byte-lane strobe outputs. 0: bls timing equals chip select timing. This is the default setting. 1: bls timing equals we_n timing. This setting is used for eight memories that have no bls_n inputs. In this case, the bls_n output of the SMC is connected to the we_n memory input. set_adv (SET_ADV) 11 wo x Contains the value to be written to the specific SRAM chip opmode Register address valid (adv) bit. The memory uses the address advance signal adv_n when set. For a NAND memory interface this bit is reserved, and written as zero. set_baa (SET_BAA) 10 rw x NAND Flash: reserved, write zero. SRAM/NOR: Value written burst address advance (baa) bit. The memory uses the baa_n signal when set. 9:7 wo x NAND Flash: reserved, write zero. SRAM/NORE: Value written for wr_bl : 000: 1 beat 001: 4 beats 010: 8 beats 011: 16 beats 100: 32 beats 101: continuous others: reserved. reserved 6 wo x Reserved. Do not modify.

set_wr_bl (SET_WR_BL)

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Field Name set_rd_bl (SET_RD_BL)

Bits 5:3

Type wo

Reset Value x

Description NAND Flash: reserved, write zero. SRAM/NOR: value written to opmode (rd_bl field). Memory Burst Length: 000: 1 beat 001: 4 beats 010: 8 beats 011: 16 beats 100: 32 beats 101: continuous others: reserved

reserved set_mw (SET_MW)

2 1:0

wo wo

x x

Reserved. Do not modify. SRAM/NOR: mw= 00 (8-bit) NAND Flash: mw= 00 (8-bit) or 01 (16-bit)

Register (pl353) refresh_period_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description refresh_period_0 REFRESH_PERIOD_0 0x00000020 0xE000E020 4 bits rw 0x00000000 Idle cycles between read/write bursts

Register refresh_period_0 Details

The read/write refresh_period_0 enables the SMC to insert idle cycles during consecutive bursts, that enables the PSRAM devices on memory interface 0, to initiate a refresh cycle. You cannot access this register in either the Reset or low-power states. Note: You can only access this register when you are using an SRAM memory interface.

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Field Name period (MASK)

Bits 3:0

Type rw

Reset Value 0x0

Description Set the number of consecutive memory bursts that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle. The options are: b0000: disable the insertion of idle cycles between consecutive bursts b0001: an idle cycle occurs after each burst b0010: an idle cycle occurs after 2 consecutive bursts b0011: an idle cycle occurs after 3 consecutive bursts b0100: an idle cycle occurs after 4 consecutive bursts ... b1111: an idle cycle occurs after 15 consecutive bursts.

Register (pl353) refresh_period_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description refresh_period_1 REFRESH_PERIOD_1 0x00000024 0xE000E024 4 bits rw 0x00000000 Insert idle cycles between bursts

Register refresh_period_1 Details

The read/write refresh_period_1 Register enables the SMC to insert idle cycles during consecutive bursts, that enables the PSRAM devices on memory interface 1, to initiate a refresh cycle

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Field Name period (REFRESH_PERIOD_0)

Bits 3:0

Type rw

Reset Value 0x0

Description Set the number of consecutive memory bursts that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle. The options are: b0000: disable the insertion of idle cycles between consecutive bursts b0001: an idle cycle occurs after each burst b0010: an idle cycle occurs after 2 consecutive bursts b0011: an idle cycle occurs after 3 consecutive bursts b0100: an idle cycle occurs after 4 consecutive bursts ... b1111: an idle cycle occurs after 15 consecutive bursts.

Register (pl353) sram_cycles0_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description sram_cycles0_0 IF0_CHIP_0_CONFIG 0x00000100 0xE000E100 21 bits ro 0x0002B3CC SRAM/NOR chip select 0 timing, active

Register sram_cycles0_0 Details

There is an instance of this register for each SRAM chip supported. You cannot read the read-only sram_cycles Register in the Reset state
Field Name we_time t_tr t_pc t_wp t_ceoe Bits 20 19:17 16:14 13:11 10:8 Type ro ro ro ro ro Reset Value 0x0 0x1 0x2 0x6 0x3 Description Asynchronous assertion, refer to SET_CYCLES register. Turnaround time, refer to SET_CYCLES register. Page cycle time, refer to SET_CYCLES register. WE assertion delay, refer to SET_CYCLES register. OE assertion delay, refer to SET_CYCLES register.

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Field Name t_wc t_rc

Bits 7:4 3:0

Type ro ro

Reset Value 0xC 0xC

Description Write cycle time, refer to SET_CYCLES register. Read cycle time, refer to SET_CYCLES register.

Register (pl353) opmode0_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description opmode0_0 OPMODE 0x00000104 0xE000E104 32 bits ro 0xE2FE0800 SRAM/NOR chip select 0 OpCode, active

Register opmode0_0 Details

Field Name address_match (ADDRESS_MATCH) address_mask (ADDRESS) 23:16 ro 0xFE Bits 31:24 Type ro Reset Value 0xE2 Description Return the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected. Return the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. The memory uses the burst address advance signal, baa_n, when set. For a NAND memory interface, this bit is reserved. Selects the write burst lengths, see SET_OPMODE register. Reserved. Do not modify. Select memory burst lengths, see SET_OPMODE Register. Reserved. Do not modify. Select data bus width (8 or 16), see SET_OPMODE register.

reserved reserved reserved baa (BAA) wr_bl (WR_BL) reserved rd_bl (RD_BL) reserved mw (MW)

15:13 12 11 10

ro ro ro ro

0x0 0x0 0x1 0x0

9:7 6 5:3 2 1:0

ro ro ro ro ro

0x0 0x0 0x0 0x0 0x0

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Register (pl353) sram_cycles0_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description sram_cycles0_1 IF0_CHIP_1_CONFIG 0x00000120 0xE000E120 21 bits ro 0x0002B3CC SRAM/NOR chip select 1 timing, active

Register sram_cycles0_1 Details

There is an instance of this register for each SRAM chip supported. You cannot read the read-only sram_cycles Register in the Reset state
Field Name we_time t_tr t_pc t_wp t_ceoe t_wc t_rc Bits 20 19:17 16:14 13:11 10:8 7:4 3:0 Type ro ro ro ro ro ro ro Reset Value 0x0 0x1 0x2 0x6 0x3 0xC 0xC Description Asynchronous assertion, refer to SET_CYCLES register. Turnaround time, refer to SET_CYCLES register. Page cycle time, refer to SET_CYCLES register. WE assertion delay, refer to SET_CYCLES register. OE assertion delay, refer to SET_CYCLES register. Write cycle time, refer to SET_CYCLES register. Read cycle time, refer to SET_CYCLES register.

Register (pl353) opmode0_1

Name Relative Address Absolute Address Width Access Type Reset Value Description opmode0_1 0x00000124 0xE000E124 32 bits ro 0xE4FE0800 SRAM/NOR chip select 1 OpCode, active

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Register opmode0_1 Details

Field Name address_match (OPMODE_ADDRESS _MATCH) address_mask (OPMODE_ADDRESS) burst_align (OPMODE_BURST_AL IGN) bls (OPMODE_BLS) adv (OPMODE_ADV) baa (OPMODE_BAA) 10 ro 0x0 The memory uses the burst address advance signal, baa_n, when set. For a NAND memory interface, this bit is reserved. wr_bl (OPMODE_WR_BL) wr_sync (OPMODE_WR_SYNC ) rd_bl (OPMODE_RD_BL) rd_sync (OPMODE_RD_SYNC) mw (OPMODE_MW) 1:0 ro 0x0 Data bus width (8 or 16), see SET_OPMODE register. 2 ro 0x0 5:3 ro 0x0 6 ro 0x0 9:7 ro 0x0 Selects the write burst lengths, see SET_OPMODE register. SRAM/NOR interface operates in asynchronous mode Select memory burst lengths, see SET_OPMODE Register. reserved 11 ro 0x1 reserved 12 ro 0x0 reserved 15:13 ro 0x0 reserved 23:16 ro 0xFE see 0x120 Bits 31:24 Type ro Reset Value 0xE4 see 0x120 Description

Register (pl353) nand_cycles1_0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value nand_cycles1_0 IF1_CHIP_0_CONFIG 0x00000180 0xE000E180 24 bits ro 0x0024ABCC

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Description

NAND Flash timing, active

Register nand_cycles1_0 Details

There is an instance of this register for each NAND chip supported. You cannot read the read-only nand_cycles Register in the Reset state
Field Name t_rr t_ar t_clr Bits 23:20 19:17 16:14 Type ro ro ro Reset Value 0x2 0x2 0x2 Description BUSY to RE, refer to SET_CYCLES register. ID read time, refer to SET_CYCLES register. Page cycle time, refer to SET_CYCLES register. Status read time for NAND chip configurations.Minimum permitted value = 0. WE deassertion delay, refer to SET_CYCLES register. RE assertion delay, refer to SET_CYCLES register. Write cycle time, refer to SET_CYCLES register. Read cycle time, refer to SET_CYCLES register.

t_wp t_rea t_wc t_rc

13:11 10:8 7:4 3:0

ro ro ro ro

0x5 0x3 0xC 0xC

Register (pl353) opmode1_0

Name Relative Address Absolute Address Width Access Type Reset Value Description opmode1_0 0x00000184 0xE000E184 32 bits ro 0xE1FF0001 NAND Flash OpCode, active

Register opmode1_0 Details

Field Name address_match (OPMODE_ADDRESS _MATCH) address_mask (OPMODE_ADDRESS) 23:16 ro 0xFF Bits 31:24 Type ro Reset Value 0xE1 Description Return the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected. Return the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify.

reserved reserved reserved

15:13 12 11

ro ro ro

0x0 0x0 0x0

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Field Name reserved reserved reserved reserved reserved mw (OPMODE_MW)

Bits 10 9:7 6 5:3 2 1:0

Type ro ro ro ro ro ro

Reset Value 0x0 0x0 0x0 0x0 0x0 0x1

Description Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Data bus width is 8 bits, see SET_OPMODE register.

Register (pl353) user_status

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description user_status USER_STATUS 0x00000200 0xE000E200 8 bits ro 0x00000000 User Status Register

Register user_status Details

The user_status is read-only and returns the value of the user_status[7:0] signals. You can read this register in all operating states.
Field Name user_status (MASK) Bits 7:0 Type ro Reset Value 0x0 Description This value returns the state of the user_status[7:0] inputs.

Register (pl353) user_config

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description user_config USER_CONFIG 0x00000204 0xE000E204 8 bits wo x User Configuration Register

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Register user_config Details

The user_config is write-only and controls the status of the user_config[7:0] signals. You can write to this register in all operating states.
Field Name user_config (MASK) Bits 7:0 Type wo x Reset Value Description This value sets the state of the user_config[7:0] outputs.

Register (pl353) ecc_status_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_status_1 IF1_ECC 0x00000400 0xE000E400 30 bits ro 0x00000000 ECC Status and Clear Register 1

Register ecc_status_1 Details

The ecc_status is read-only and contains status information for the ECC. Although this is a read-only register, the bottom five bits can be written to clear the corresponding interrupts.To clear the interrupt, you must write a 1 to the appropriate bit.

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Field Name ecc_read (ECC_READ)

Bits 29:25

Type ro

Reset Value 0x0

Description Read flags for ECC blocks. Indicate whether the stored ECC value for each block has been read from memory: 0: not read 1: read Bit [29] Extra block (if used). Bit [28] Block 3. Bit [27] Block 2. Bit [26] Block 1. Bit [25] Block 0.

ecc_can_correct (ECC_CAN_CORREC T)

24:20

ro

0x0

Correctable flag for each ECC block: 0: not correctable error 1: correctable error Bit [24] Extra block (if used). Bit [23] Block 3. Bit [22] Block 2. Bit [21] Block 1. Bit [20] Block 0.

ecc_fail (ECC_FAIL) ecc_value_valid (ECC_VALID) ecc_read_not_write (ECC_READ_NOT_W RITE) ecc_last_status (ECC_LAST)

19:15 14:10 9

ro ro ro

0x0 0x0 0x0

Pass/fail flag for each ECC block Valid flag for each ECC block. ECC calcuation type: 0: write 1: read

8:7

ro

0x0

Last ECC result is updated after completing the ECC calculation: 00: Completed successfully. 01: Unaligned Address, or out-of-range. 10: Data stop after incomplete block. 11: Data stopped but values not read/written because of ecc_jump value.

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Field Name ecc_status (ECC_STATUS) raw_int_status (ECC_STATUS_RAW_I NT_STATUS)

Bits 6

Type ro

Reset Value 0x0

Description Status of the ECC block: 0: idle 1: busy

5:0

ro

0x0

The interrupts are: Bit [5] Abort. Bit [4] Extra block (if used). Bit [3] Block 3. Bit [2] Block 2. Bit [1] Block 1. Bit [0] Block 0. To clear the interrupt, write a 1 to the bit.

Register (pl353) ecc_memcfg_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_memcfg_1 0x00000404 0xE000E404 13 bits rw 0x00000043 ECC Memory Configuation Register 1

Register ecc_memcfg_1 Details

The ecc_memcfg Register is read-write and contains information about the structure of the memory. Note; You must not write to this register while the ECC block is busy. You can read the current ECC block status from the ECC Status Register.
Field Name ecc_extra_block_size (ECC_MEMCFG_ECC_ EXTRA_BLOCK_SIZE) Bits 12:11 Type rw Reset Value 0x0 Description The size of the extra block in memory after the last 512 block: 00: 4 bytes 01: 8 bytes 10: 16 bytes 11: 32 bytes Note: These bits are only present if you configure the SMC to use the ECC Extra Block Enable option. ecc_extra_block (ECC_MEMCFG_ECC_ EXTRA_BLOCK) 10 rw 0x0 If configured, this enables a small block for extra information after the last 512 bytes block in the page. Note: These bits are only present if the ECC Extra Block Enable option is configured.

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Field Name ecc_int_abort (ECC_MEMCFG_ECC_ INT_ABORT) ecc_int_pass (ECC_MEMCFG_ECC_ INT_PASS) ecc_ignore_add_eight (ECC_MEMCFG_IGN ORE_ADD8) ecc_jump (ECC_MEMCFG_ECC_ JUMP)

Bits 9

Type rw

Reset Value 0x0

Description Interrupt on ECC abort: 0: don't assert 1: assert

rw

0x0

Interrupt when a correct ECC value is read from memory: 0: don't assert 1: assert

rw

0x0

Use to indicate if A8 is output with the address, required to find the aligned start of blocks: 0: A8 is output 1: A8 is not output

6:5

rw

0x2

Indicate that the memory supports column change address commands: 00: no jumping, reads and writes only occur at end of page 01: jump using column change commands 10: jump using full command 11: reserved

ecc_read_end (ECC_MEMCFG_ECC_ READ_END)

rw

0x0

Indicate when ECC values are read from memory: 0: ECC value for a block must be read immediately after the block. Data access must stop on a 512 byte boundary. 1: ECC values for all blocks are read at the end of the page.

ecc_mode (ECC_MEMCFG_ECC_ MODE)

3:2

rw

0x0

Specify the mode of the ECC block: 00: bypassed 01: ECC values are calculated and made available on the APB interface. But they are not read to or written from memory. 10: ECC values and calculated and read/written to memory. For a read, the ECC value is checked and the result of the check is made available on the APB interface. 11: reserved

page_size (ECC_MEMCFG_PAG E_SIZE)

1:0

rw

0x3

The number of 512 byte blocks in a page: 00: No 512 byte blocks. Reserved if an ecc_extra_block is not configured and enabled. 01: One 512 byte block. 10: Two 512 byte blocks. 11: Four 512 byte blocks.

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Register (pl353) ecc_memcommand1_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_memcommand1_1 0x00000408 0xE000E408 25 bits rw 0x01300080 ECC Memory Command 1 Register 1

Register ecc_memcommand1_1 Details

The ecc_memcommand1 is read-write and contains the commands that the ECC block uses to detect the start of an ECC operation.
Field Name nand_rd_cmd_end_val id (ECC_MEMCOMMAN D1_RD_CMD_END_V ALID) nand_rd_cmd_end (ECC_MEMCOMMAN D1_RD_CMD_END) nand_rd_cmd (ECC_MEMCOMMAN D1_RD_CMD) nand_wr_cmd (ECC_MEMCOMMAN D1_WR_CMD) 7:0 rw 0x80 15:8 rw 0x0 23:16 rw 0x30 Use the NAND command to initiate a write (0x30). Use the NAND command used to initiate a read (0x00). Use the NAND command to initiate a write (0x80). Bits 24 Type rw Reset Value 0x1 Description Use the end command

Register (pl353) ecc_memcommand2_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_memcommand2_1 0x0000040C 0xE000E40C 25 bits rw 0x01E00585 ECC Memory Command 2 Register 1

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Register ecc_memcommand2_1 Details

The ecc_memcommand2 Register is read-write and contains the commands that the ECC block uses to access different parts of a NAND page. The reset value is suitable for ONFI 1.0 compliant devices
Field Name nand_rd_col_change_e nd_valid (ECC_MEMCOMMAN D2_RD_COL_CHANG E_END_VALID) nand_rd_col_change_e nd (ECC_MEMCOMMAN D2_RD_COL_CHANG E_END) nand_rd_col_change (ECC_MEMCOMMAN D2_RD_COL_CHANG E) nand_wr_col_change (ECC_MEMCOMMAN D2_WR_COL_CHAN GE) 7:0 rw 0x85 15:8 rw 0x5 Use the NAND command to initiate a read or Spare bits pointer command. 23:16 rw 0xE0 Use the NAND command to initiate a write. Bits 24 Type rw Reset Value 0x1 Description Use the end command

The NAND command used to initiate a write

Register (pl353) ecc_addr0_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_addr0_1 0x00000410 0xE000E410 32 bits ro 0x00000000 ECC Address 0 Register 1

Register ecc_addr0_1 Details

The ecc_addr0 Register is read-only and contains the lower 32 bits of the ECC address
Field Name ecc_addr Bits 31:0 Type ro Reset Value 0x0 Description Address bits 31 to 0

Register (pl353) ecc_addr1_1

Name ecc_addr1_1

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000414 0xE000E414 24 bits ro 0x00000000 ECC Address 1 Register 1

Register ecc_addr1_1 Details

The ecc_addr1 Register is read-only and contains the upper 24 bits of the ECC address.
Field Name ecc_addr Bits 23:0 Type ro Reset Value 0x0 Description Address bits 55 to 32

Register (pl353) ecc_value0_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_value0_1 0x00000418 0xE000E418 32 bits ro 0x00000000 ECC Value 0 Register 1

Register ecc_value0_1 Details

The five ecc_value Registers are read-only and contain block information for the ECC. Note: Writing any value to an ecc_value Register clears the ecc_int bit.
Field Name ecc_int (ECC_VALUE_INT) ecc_valid (ECC_VALUE_VALID) ecc_read (ECC_VALUE_READ) ecc_fail (ECC_VALUE_FAIL) ecc_correct (ECC_VALUE_CORRE CT) 27 ro 0x0 Indicate if this block is correctable 28 ro 0x0 29 ro 0x0 Indicate if the ECC value has been read from memory Indicate if this value has failed 30 ro 0x0 Indicate if this value is valid Bits 31 Type ro Reset Value 0x0 Description Interrupt flag for this value

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Field Name reserved ecc_value (ECC_VALUE)

Bits 26:24 23:0

Type ro ro

Reset Value 0x0 0x0

Description Reserved, read undefined ECC value of check result for block, depending on ECC configuration

Register (pl353) ecc_value1_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_value1_1 0x0000041C 0xE000E41C 32 bits ro 0x00000000 ECC Value 1 Register 1

Register ecc_value1_1 Details

The five ecc_value Registers are read-only and contain block information for the ECC. Note: writing any value to an ecc_value Register clears the ecc_int bit.
Field Name ecc_int (ECC_VALUE_INT) ecc_valid (ECC_VALUE_VALID) ecc_read (ECC_VALUE_READ) ecc_fail (ECC_VALUE_FAIL) ecc_correct (ECC_VALUE_CORRE CT) reserved ecc_value (ECC_VALUE) 26:24 23:0 ro ro 0x0 0x0 Reserved, read undefined ECC value of check result for block, depending on ECC configuration 27 ro 0x0 Indicate if this block is correctable 28 ro 0x0 29 ro 0x0 Indicate if the ECC value has been read from memory Indicate if this value has failed 30 ro 0x0 Indicate if this value is valid Bits 31 Type ro Reset Value 0x0 Description Interrupt flag for this value

Register (pl353) ecc_value2_1

Name Relative Address ecc_value2_1 0x00000420

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Absolute Address Width Access Type Reset Value Description

0xE000E420 32 bits ro 0x00000000 ECC Value 2 Register 1

Register ecc_value2_1 Details

The five ecc_value Registers are read-only and contain block information for the ECC. Note: writing any value to an ecc_value Register clears the ecc_int bit.
Field Name ecc_int (ECC_VALUE_INT) ecc_valid (ECC_VALUE_VALID) ecc_read (ECC_VALUE_READ) ecc_fail (ECC_VALUE_FAIL) ecc_correct (ECC_VALUE_CORRE CT) reserved ecc_value (ECC_VALUE) 26:24 23:0 ro ro 0x0 0x0 Reserved, read undefined ECC value of check result for block, depending on ECC configuration 27 ro 0x0 Indicate if this block is correctable 28 ro 0x0 29 ro 0x0 Indicate if the ECC value has been read from memory Indicate if this value has failed 30 ro 0x0 Indicate if this value is valid Bits 31 Type ro Reset Value 0x0 Description Interrupt flag for this value

Register (pl353) ecc_value3_1

Name Relative Address Absolute Address Width Access Type Reset Value Description ecc_value3_1 0x00000424 0xE000E424 32 bits ro 0x00000000 ECC Value 3 Register 1

Register ecc_value3_1 Details

The five ecc_value Registers are read-only and contain block information for the ECC. Note: writing any value to an ecc_value Register clears the ecc_int bit.

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Field Name ecc_int (ECC_VALUE_INT) ecc_valid (ECC_VALUE_VALID) ecc_read (ECC_VALUE_READ) ecc_fail (ECC_VALUE_FAIL) ecc_correct (ECC_VALUE_CORRE CT) reserved ecc_value (ECC_VALUE)

Bits 31 30 29 28 27

Type ro ro ro ro ro

Reset Value 0x0 0x0 0x0 0x0 0x0

Description Interrupt flag for this value Indicate if this value is valid Indicate if the ECC value has been read from memory Indicate if this value has failed Indicate if this block is correctable

26:24 23:0

ro ro

0x0 0x0

Reserved, read undefined ECC value of check result for block, depending on ECC configuration

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B.30 SPI Controller (SPI)

Module Name Software Name Base Address Description Vendor Info SPI Controller (SPI) XSPIPS 0xE0006000 spi0 0xE0007000 spi1 Serial Peripheral Interface Cadence SPI

Register Summary
Register Name Config_reg0 Intr_status_reg0 Intrpt_en_reg0 Intrpt_dis_reg0 Intrpt_mask_reg0 En_reg0 Delay_reg0 Tx_data_reg0 Rx_data_reg0 Slave_Idle_count_reg0 TX_thres_reg0 RX_thres_reg0 Mod_id_reg0 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x000000FC Width 32 32 32 32 32 32 32 32 32 32 32 32 32 Type mixed mixed mixed mixed ro mixed rw wo ro mixed rw rw ro Reset Value 0x00020000 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000000FF 0x00000001 0x00000001 0x00090106 Description SPI configuration register SPI interrupt status register Interrupt Enable register Interrupt disable register Interrupt mask register SPI_Enable Register Delay Register Transmit Data Register. Receive Data Register Slave Idle Count Register TX_FIFO Threshold Register RX FIFO Threshold Register Module ID register

Register (SPI) Config_reg0

Name Software Name Relative Address Absolute Address Width Access Type Config_reg0 CR 0x00000000 spi0: 0xE0006000 spi1: 0xE0007000 32 bits mixed

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Reset Value Description

0x00020000 SPI configuration register

Register Config_reg0 Details

Field Name reserved Modefail_gen_en Bits 31:18 17 Type ro rw Reset Value 0x0 0x1 Description Reserved, read as zero, ignored on write. ModeFail Generation Enable 1: enable 0: disable Man_start_com (MANSTRT) Man_start_en 15 rw 0x0 16 wo 0x0 Manual Start Command 1: start transmission of data 0: don't care Manual Start Enable 1: enables manual start 0: auto mode Manual_CS 14 rw 0x0 Manual CS 1: manual CS mode 0: auto mode CS 13:10 rw 0x0 Peripheral chip select lines (only valid if Manual_CS=1) xxx0 - slave 0 selected xx01 - slave 1 selected x011 - slave 2 selected 0111 - reserved 1111 - No slave selected PERI_SEL 9 rw 0x0 Peripheral select decode 1: allow external 3-to-8 decode 0: only 1 of 3 selects REF_CLK 8 rw 0x0 Master reference clock select 1: not supported 0: use SPI REFERENCE CLOCK reserved 7:6 rw 0x0 Reserved, read as zero, write with 00

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Field Name BAUD_RATE_DIV

Bits 5:3

Type rw

Reset Value 0x0

Description Master mode baud rate divisor controls the amount the spi_ref_clk is divided inside the SPI block 000: not supported 001: divide by 4 010: divide by 8 011: divide by 16 100: divide by 32 101: divide by 64 110: divide by 128 111: divide by 256

CLK_PH (CPHA) CLK_POL (CPOL) MODE_SEL (MSTREN)

rw

0x0

Clock phase 1: the SPI clock is inactive outside the word 0: the SPI clock is active outside the word

rw

0x0

Clock polarity outside SPI word 1: the SPI clock is quiescent high 0: the SPI clock is quiescent low

rw

0x0

Mode select 1: the SPI is in master mode 0: the SPI is in slave mode

Register (SPI) Intr_status_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intr_status_reg0 SR 0x00000004 spi0: 0xE0006004 spi1: 0xE0007004 32 bits mixed 0x00000004 SPI interrupt status register

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Register Intr_status_reg0 Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wtc Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow, write one to this bit location to clear. 1: underflow is detected 0: no underflow has been detected RX_FIFO_full (IXR_RXFULL) RX_FIFO_not_empty (IXR_RXNEMPTY) 4 wtc 0x0 5 wtc 0x0 RX FIFO full 1: FIFO is full 0: FIFO is not full RX FIFO not empty 1: FIFO has more than or equal to THRESHOLD entries 0: FIFO has less than RX THRESHOLD entries TX_FIFO_full (IXR_TXFULL) TX_FIFO_not_full (IXR_TXOW) 2 wtc 0x1 3 wtc 0x0 TX FIFO full 1: FIFO is full 0: FIFO is not full TX FIFO not full 1: FIFO has less than THRESHOLD entries 0: FIFO has more than or equal toTHRESHOLD entries MODE_FAIL (IXR_MODF) 1 wtc 0x0 Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention) or n_ss_in goes high during a transmission in slave mode. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read. ModeFail interrupt, write one to this bit location to clear. 1: a mode fault has occurred 0: no mode fault has been detected RX_OVERFLOW (IXR_RXOVR) 0 wtc 0x0 Receive Overflow interrupt, write one to this bit location to clear. 1: overflow occured 0: no overflow occurred

Register (SPI) Intrpt_en_reg0

Name Software Name Relative Address Intrpt_en_reg0 IER 0x00000008

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Absolute Address Width Access Type Reset Value Description

spi0: 0xE0006008 spi1: 0xE0007008 32 bits mixed 0x00000000 Interrupt Enable register

Register Intrpt_en_reg0 Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: enable the interrupt 0: no effect RX_FIFO_full (IXR_RXFULL) 5 wo 0x0 RX FIFO full enable 1: enable the interrupt 0: no effect RX_FIFO_not_empty (IXR_RXNEMPTY) 4 wo 0x0 RX FIFO not empty enable 1: enable the interrupt 0: no effect TX_FIFO_full (IXR_TXFULL) 3 wo 0x0 TX FIFO full enable 1: enable the interrupt 0: no effect TX_FIFO_not_full (IXR_TXOW) 2 wo 0x0 TX FIFO not full enable 1: enable the interrupt 0: no effect MODE_FAIL (IXR_MODF) 1 wo 0x0 ModeFail interrupt enable 1: enable the interrupt 0: no effect RX_OVERFLOW (IXR_RXOVR) 0 wo 0x0 Receive Overflow interrupt enable 1: enable the interrupt 0: no effect

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Register (SPI) Intrpt_dis_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_dis_reg0 IDR 0x0000000C spi0: 0xE000600C spi1: 0xE000700C 32 bits mixed 0x00000000 Interrupt disable register

Register Intrpt_dis_reg0 Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: disables the interrupt 0: no effect RX_FIFO_full (IXR_RXFULL) 5 wo 0x0 RX FIFO full enable 1: disables the interrupt 0: no effect RX_FIFO_not_empty (IXR_RXNEMPTY) 4 wo 0x0 RX FIFO not empty enable 1: disables the interrupt 0: no effect TX_FIFO_full (IXR_TXFULL) 3 wo 0x0 TX FIFO full enable 1: disables the interrupt 0: no effect TX_FIFO_not_full (IXR_TXOW) 2 wo 0x0 TX FIFO not full enable 1: disables the interrupt 0: no effect

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Field Name MODE_FAIL (IXR_MODF)

Bits 1

Type wo

Reset Value 0x0

Description ModeFail interrupt enable 1: disables the interrupt 0: no effect

RX_OVERFLOW (IXR_RXOVR)

wo

0x0

Receive Overflow interrupt enable 1: disables the interrupt 0: no effect

Register (SPI) Intrpt_mask_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_mask_reg0 IMR 0x00000010 spi0: 0xE0006010 spi1: 0xE0007010 32 bits ro 0x00000000 Interrupt mask register

Register Intrpt_mask_reg0 Details

Field Name reserved TX_FIFO_underflow (IXR_TXUF) Bits 31:7 6 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. TX FIFO underflow enable 1: interrupt is disabled 0: interrupt is enabled RX_FIFO_full (IXR_RXFULL) 5 ro 0x0 RX FIFO full enable 1: interrupt is disabled 0: interrupt is enabled RX_FIFO_not_empty (IXR_RXNEMPTY) 4 ro 0x0 RX FIFO not empty enable 1: interrupt is disabled 0: interrupt is enabled

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Field Name TX_FIFO_full (IXR_TXFULL)

Bits 3

Type ro

Reset Value 0x0 TX FIFO full enable

Description

1: interrupt is disabled 0: interrupt is enabled TX_FIFO_not_full (IXR_TXOW) 2 ro 0x0 TX FIFO not full enable 1: interrupt is disabled 0: interrupt is enabled MODE_FAIL (IXR_MODF) 1 ro 0x0 ModeFail interrupt enable 1: interrupt is disabled 0: interrupt is enabled RX_OVERFLOW (IXR_RXOVR) 0 ro 0x0 Receive Overflow interrupt enable 1: interrupt is disabled 0: interrupt is enabled

Register (SPI) En_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description En_reg0 ER 0x00000014 spi0: 0xE0006014 spi1: 0xE0007014 32 bits mixed 0x00000000 SPI_Enable Register

Register En_reg0 Details

Field Name reserved SPI_EN (ENABLE) Bits 31:1 0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. SPI_Enable 1: enable the SPI 0: disable the SPI

Register (SPI) Delay_reg0

Name Delay_reg0

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

DR 0x00000018 spi0: 0xE0006018 spi1: 0xE0007018 32 bits rw 0x00000000 Delay Register

Register Delay_reg0 Details

Field Name d_nss Bits 31:24 Type rw Reset Value 0x0 Description Delay in SPI REFERENCE CLOCK or ext_clk cycles for the length that the master mode chip select outputs are de-asserted between words when cpha=0. d_btwn (BTWN) 23:16 rw 0x0 Delay in SPI REFERENCE CLOCK or ext_clk cycles between one chip select being de-activated and the activation of another d_after (AFTER) d_int (INIT) 7:0 rw 0x0 15:8 rw 0x0 Delay in SPI REFERENCE CLOCK or ext_clk cycles between last bit of current word and the first bit of the next word. Added delay in SPI REFERENCE CLOCK or ext_clk cycles between setting n_ss_out low and first bit transfer.

Register (SPI) Tx_data_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Tx_data_reg0 TXD 0x0000001C spi0: 0xE000601C spi1: 0xE000701C 32 bits wo 0x00000000 Transmit Data Register.

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Register Tx_data_reg0 Details

Field Name TX_FIFO_data Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO. Valid data bits are [7:0].

Register (SPI) Rx_data_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Rx_data_reg0 RXD 0x00000020 spi0: 0xE0006020 spi1: 0xE0007020 32 bits ro 0x00000000 Receive Data Register

Register Rx_data_reg0 Details

Field Name RX_FIFO_data Bits 31:0 Type ro Reset Value 0x0 Description Data from RX FIFO. Valid data bits are [7:0].

Register (SPI) Slave_Idle_count_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Slave_Idle_count_reg0 SICR 0x00000024 spi0: 0xE0006024 spi1: 0xE0007024 32 bits mixed 0x000000FF Slave Idle Count Register

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Register Slave_Idle_count_reg0 Details

Field Name reserved Slave_Idle_coun Bits 31:8 7:0 Type ro rw Reset Value 0x0 0xFF Description Reserved, read as zero, ignored on write. SPI in slave mode detects a start only when the external SPI master serial clock (sclk_in) is stable (quiescent state) for SPI REFERENCE CLOCK cycles specified by slave idle count register or when the SPI is deselected.

Register (SPI) TX_thres_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TX_thres_reg0 TXWR 0x00000028 spi0: 0xE0006028 spi1: 0xE0007028 32 bits rw 0x00000001 TX_FIFO Threshold Register

Register TX_thres_reg0 Details

Field Name Bits Type rw Reset Value 0x1 Description Defines the level at which the TX FIFO not full interrupt is generated

Threshold_of_TX_FIFO 31:0

Register (SPI) RX_thres_reg0

Name Relative Address Absolute Address Width Access Type Reset Value Description RX_thres_reg0 0x0000002C spi0: 0xE000602C spi1: 0xE000702C 32 bits rw 0x00000001 RX FIFO Threshold Register

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Register RX_thres_reg0 Details

Field Name Threshold_of_RX_FIF O Bits 31:0 Type rw Reset Value 0x1 Description Defines the level at which the RX FIFO not empty interrupt is generated

Register (SPI) Mod_id_reg0

Name Relative Address Absolute Address Width Access Type Reset Value Description Mod_id_reg0 0x000000FC spi0: 0xE00060FC spi1: 0xE00070FC 32 bits ro 0x00090106 Module ID register

Register Mod_id_reg0 Details

Field Name reserved module_ID Bits 31:25 24:0 Type ro ro Reset Value 0x0 0x90106 Description Reserved, read as zero, ignored on write. Module ID number

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B.31 System Watchdog Timer (swdt)

Module Name Software Name Base Address Description Vendor Info System Watchdog Timer (swdt) XWDTPS 0xF8005000 swdt System Watchdog Timer Registers

Register Summary
Register Name MODE CONTROL RESTART STATUS Address 0x00000000 0x00000004 0x00000008 0x0000000C Width 24 26 16 1 Type mixed mixed wo ro Reset Value 0x000001C2 0x03FFC3FC 0x00000000 0x00000000 Description WD zero mode register Counter Control Register Restart key register - this not a real register as no data is stored Status Register

Register (swdt) MODE

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description MODE ZMR 0x00000000 0xF8005000 24 bits mixed 0x000001C2 WD zero mode register

Register MODE Details

Field Name ZKEY Bits 23:12 Type wo Reset Value 0x0 Description Zero access key - writes to the zero mode register are only valid if this field is set to 0xABC; this field is write only. Should be zero (sbz)

reserved

11:9

waz

0x0

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Field Name IRQLN

Bits 8:7

Type rw

Reset Value 0x3

Description Interrupt request length - selects the number of pclk cycles during which an interrupt request is held active after it is invoked: 00 = 4 01 = 8 10 = 16 11 = 32

RSTLN

6:4

rw

0x4

Reset length - selects the number of clock cycles (pclk) during which the internal system reset is held active after it is invoked: 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 Note: The minimum number of cycles required for an AMBA reset is two.

reserved IRQEN

3 2

waz rw

0x0 0x0

Should be zero (sbz) Interrupt request enable - if set, the watchdog will issue an interrupt request when the counter reaches zero, if WDEN = 1. Reset enable - if set, the watchdog will issue an internal reset when the counter reaches zero, if WDEN = 1. Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.

RSTEN

rw

0x1

WDEN

rw

0x0

Register (swdt) CONTROL

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description CONTROL CCR 0x00000004 0xF8005004 26 bits mixed 0x03FFC3FC Counter Control Register

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Register CONTROL Details

Field Name CKEY Bits 25:14 Type wo Reset Value 0xFFF Description Counter access key - writes to the control register are only valid if this field is set to 0x248; this field is write only. Counter restart value - the counter is restarted with the value 0xNNNFFF, where NNN is the value of this field. Counter clock prescale - selects the prescaler division ratio: 00 = pclk divided by 8 01 = pclk divided by 64 10 = pclk divided by 512 11 = pclk divided by 4096 Note: If a restart signal is received the prescaler should be reset.

CRV

13:2

rw

0xFF

CLKSEL

1:0

rw

0x0

Register (swdt) RESTART

Name Relative Address Absolute Address Width Access Type Reset Value Description RESTART 0x00000008 0xF8005008 16 bits wo 0x00000000 Restart key register - this not a real register as no data is stored

Register RESTART Details

Field Name RSTKEY (KEY_VAL) Bits 15:0 Type wo Reset Value 0x0 Description Restart key - the watchdog is restarted if this field is set to the value 0x1999

Register (swdt) STATUS

Name Software Name Relative Address Absolute Address Width STATUS SR 0x0000000C 0xF800500C 1 bits

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Access Type Reset Value Description

ro 0x00000000 Status Register

Register STATUS Details

Field Name WDZ Bits 0 Type ro Reset Value 0x0 Description set when the watchdog reaches zero count

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B.32 Triple Timer Counter (ttc)

Module Name Software Name Base Address Description Vendor Info Triple Timer Counter (ttc) XTTCPS 0xF8001000 ttc0 0xF8002000 ttc1 Triple Timer Counter

Register Summary
Register Name Clock_Control_1 Clock_Control_2 Clock_Control_3 Counter_Control_1 Counter_Control_2 Counter_Control_3 Counter_Value_1 Counter_Value_2 Counter_Value_3 Interval_Counter_1 Interval_Counter_2 Interval_Counter_3 Match_1_Counter_1 Match_1_Counter_2 Match_1_Counter_3 Match_2_Counter_1 Match_2_Counter_2 Match_2_Counter_3 Match_3_Counter_1 Match_3_Counter_2 Match_3_Counter_3 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x0000003C 0x00000040 0x00000044 0x00000048 0x0000004C 0x00000050 Width 7 7 7 7 7 7 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Type rw rw rw rw rw rw ro ro ro rw rw rw rw rw rw rw rw rw rw rw rw Reset Value 0x00000000 0x00000000 0x00000000 0x00000021 0x00000021 0x00000021 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description Clock Control register Clock Control register Clock Control register Operational mode and reset Operational mode and reset Operational mode and reset Current counter value Current counter value Current counter value Interval value Interval value Interval value Match value Match value Match value Match value Match value Match value Match value Match value Match value

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Register Name Interrupt_Register_1

Address 0x00000054

Width 6

Type ro

Reset Value 0x00000000

Description Counter 1 Interval, Match, Overflow and Event interrupts Counter 2 Interval, Match, Overflow and Event interrupts Counter 3 Interval, Match, Overflow and Event interrupts ANDed with corresponding Interrupt Register ANDed with corresponding Interrupt Register ANDed with corresponding Interrupt Register Enable, pulse and overflow Enable, pulse and overflow Enable, pulse and overflow pclk cycle count for event pclk cycle count for event pclk cycle count for event

Interrupt_Register_2 Interrupt_Register_3 Interrupt_Enable_1

0x00000058 0x0000005C 0x00000060

6 6 6

ro ro rw

0x00000000 0x00000000 0x00000000

Interrupt_Enable_2

0x00000064

rw

0x00000000

Interrupt_Enable_3

0x00000068

rw

0x00000000

Event_Control_Timer_ 1 Event_Control_Timer_ 2 Event_Control_Timer_ 3 Event_Register_1 Event_Register_2 Event_Register_3

0x0000006C 0x00000070 0x00000074 0x00000078 0x0000007C 0x00000080

3 3 3 16 16 16

rw rw rw ro ro ro

0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Register (ttc) Clock_Control_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Clock_Control_1 CLK_CNTRL 0x00000000 ttc0: 0xF8001000 ttc1: 0xF8002000 7 bits rw 0x00000000 Clock Control register

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Register Clock_Control_1 Details

Field Name Ex_E (EXT_EDGE) C_Src (SRC) PS_V (PS_VAL) PS_En (PS_EN) 0 rw 0x0 4:1 rw 0x0 5 rw 0x0 Bits 6 Type rw Reset Value 0x0 Description External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk. Prescale value (N): if prescale is enabled, the count rate is divided by 2^(N+1) Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default

Register (ttc) Clock_Control_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Clock_Control_2 0x00000004 ttc0: 0xF8001004 ttc1: 0xF8002004 7 bits rw 0x00000000 Clock Control register

Register Clock_Control_2 Details

Field Name Ex_E (CLK_CNTRL_EXT_E DGE) C_Src (CLK_CNTRL_SRC) PS_V (CLK_CNTRL_PS_VA L) PS_En (CLK_CNTRL_PS_EN) 0 rw 0x0 4:1 rw 0x0 5 rw 0x0 Bits 6 Type rw Reset Value 0x0 Description External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk. Prescale value (N): if prescale is enabled, the count rate is divided by 2^(N+1) Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default

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Register (ttc) Clock_Control_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Clock_Control_3 0x00000008 ttc0: 0xF8001008 ttc1: 0xF8002008 7 bits rw 0x00000000 Clock Control register

Register Clock_Control_3 Details

Field Name Ex_E (CLK_CNTRL_EXT_E DGE) C_Src (CLK_CNTRL_SRC) PS_V (CLK_CNTRL_PS_VA L) PS_En (CLK_CNTRL_PS_EN) 0 rw 0x0 4:1 rw 0x0 5 rw 0x0 Bits 6 Type rw Reset Value 0x0 Description External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk. Prescale value (N): if prescale is enabled, the count rate is divided by 2^(N+1) Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default

Register (ttc) Counter_Control_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Control_1 CNT_CNTRL 0x0000000C ttc0: 0xF800100C ttc1: 0xF800200C 7 bits rw 0x00000021 Operational mode and reset

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Register Counter_Control_1 Details

Field Name Wave_pol (POL_WAVE) Bits 6 Type rw Reset Value 0x0 Description Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. Output waveform enable, active low. Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart. Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register. Decrement: when this bit is high the counter counts down. When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode. Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.

Wave_en (EN_WAVE) RST

5 4

rw rw

0x1 0x0

Match (MATCH)

rw

0x0

DEC (DECR) INT

2 1

rw rw

0x0 0x0

DIS

rw

0x1

Register (ttc) Counter_Control_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Control_2 0x00000010 ttc0: 0xF8001010 ttc1: 0xF8002010 7 bits rw 0x00000021 Operational mode and reset

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Register Counter_Control_2 Details

Field Name Wave_pol (CNT_CNTRL_POL_W AVE) Bits 6 Type rw Reset Value 0x0 Description Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. Output waveform enable, active low.

Wave_en (CNT_CNTRL_EN_W AVE) RST (CNT_CNTRL_RST) Match (CNT_CNTRL_MATC H)

rw

0x1

rw

0x0

Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart. Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register. Decrement: when this bit is high the counter counts down. When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode. Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.

rw

0x0

DEC (CNT_CNTRL_DECR) INT (CNT_CNTRL_INT)

2 1

rw rw

0x0 0x0

DIS (CNT_CNTRL_DIS)

rw

0x1

Register (ttc) Counter_Control_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Control_3 0x00000014 ttc0: 0xF8001014 ttc1: 0xF8002014 7 bits rw 0x00000021 Operational mode and reset

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Register Counter_Control_3 Details

Field Name Wave_pol (CNT_CNTRL_POL_W AVE) Bits 6 Type rw Reset Value 0x0 Description Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. Output waveform enable, active low.

Wave_en (CNT_CNTRL_EN_W AVE) RST (CNT_CNTRL_RST) Match (CNT_CNTRL_MATC H)

rw

0x1

rw

0x0

Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart. Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register. Decrement: when this bit is high the counter counts down. When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode. Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again.

rw

0x0

DEC (CNT_CNTRL_DECR) INT (CNT_CNTRL_INT)

2 1

rw rw

0x0 0x0

DIS (CNT_CNTRL_DIS)

rw

0x1

Register (ttc) Counter_Value_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Value_1 COUNT_VALUE 0x00000018 ttc0: 0xF8001018 ttc1: 0xF8002018 16 bits ro 0x00000000 Current counter value

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Register Counter_Value_1 Details

Field Name Value (MASK) Bits 15:0 Type ro Reset Value 0x0 Description At any time, a Timer Counter's count value can be read from its Counter Value Register.

Register (ttc) Counter_Value_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Value_2 0x0000001C ttc0: 0xF800101C ttc1: 0xF800201C 16 bits ro 0x00000000 Current counter value

Register Counter_Value_2 Details

Field Name Value (COUNT_VALUE) Bits 15:0 Type ro Reset Value 0x0 Description At any time, a Timer Counter's count value can be read from its Counter Value Register.

Register (ttc) Counter_Value_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Counter_Value_3 0x00000020 ttc0: 0xF8001020 ttc1: 0xF8002020 16 bits ro 0x00000000 Current counter value

Register Counter_Value_3 Details

Field Name Value (COUNT_VALUE) Bits 15:0 Type ro Reset Value 0x0 Description At any time, a Timer Counter's count value can be read from its Counter Value Register.

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Register (ttc) Interval_Counter_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Interval_Counter_1 INTERVAL_VAL 0x00000024 ttc0: 0xF8001024 ttc1: 0xF8002024 16 bits rw 0x00000000 Interval value

Register Interval_Counter_1 Details

Field Name Interval (COUNT_VALUE) Bits 15:0 Type rw Reset Value 0x0 Description If interval is enabled, this is the maximum value that the counter will count up to or down from.

Register (ttc) Interval_Counter_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Interval_Counter_2 0x00000028 ttc0: 0xF8001028 ttc1: 0xF8002028 16 bits rw 0x00000000 Interval value

Register Interval_Counter_2 Details

Field Name Interval (INTERVAL_VAL) Bits 15:0 Type rw Reset Value 0x0 Description If interval is enabled, this is the maximum value that the counter will count up to or down from.

Register (ttc) Interval_Counter_3

Name Relative Address Interval_Counter_3 0x0000002C

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Absolute Address Width Access Type Reset Value Description

ttc0: 0xF800102C ttc1: 0xF800202C 16 bits rw 0x00000000 Interval value

Register Interval_Counter_3 Details

Field Name Interval (INTERVAL_VAL) Bits 15:0 Type rw Reset Value 0x0 Description If interval is enabled, this is the maximum value that the counter will count up to or down from.

Register (ttc) Match_1_Counter_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Match_1_Counter_1 MATCH_0 0x00000030 ttc0: 0xF8001030 ttc1: 0xF8002030 16 bits rw 0x00000000 Match value

Register Match_1_Counter_1 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_1_Counter_2

Name Relative Address Absolute Address Width Match_1_Counter_2 0x00000034 ttc0: 0xF8001034 ttc1: 0xF8002034 16 bits

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Access Type Reset Value Description

rw 0x00000000 Match value

Register Match_1_Counter_2 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_1_Counter_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Match_1_Counter_3 0x00000038 ttc0: 0xF8001038 ttc1: 0xF8002038 16 bits rw 0x00000000 Match value

Register Match_1_Counter_3 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_2_Counter_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Match_2_Counter_1 MATCH_1 0x0000003C ttc0: 0xF800103C ttc1: 0xF800203C 16 bits rw 0x00000000

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Description

Match value

Register Match_2_Counter_1 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_2_Counter_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Match_2_Counter_2 0x00000040 ttc0: 0xF8001040 ttc1: 0xF8002040 16 bits rw 0x00000000 Match value

Register Match_2_Counter_2 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_2_Counter_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Match_2_Counter_3 0x00000044 ttc0: 0xF8001044 ttc1: 0xF8002044 16 bits rw 0x00000000 Match value

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Register Match_2_Counter_3 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_3_Counter_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Match_3_Counter_1 MATCH_2 0x00000048 ttc0: 0xF8001048 ttc1: 0xF8002048 16 bits rw 0x00000000 Match value

Register Match_3_Counter_1 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_3_Counter_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Match_3_Counter_2 0x0000004C ttc0: 0xF800104C ttc1: 0xF800204C 16 bits rw 0x00000000 Match value

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Register Match_3_Counter_2 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Match_3_Counter_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Match_3_Counter_3 0x00000050 ttc0: 0xF8001050 ttc1: 0xF8002050 16 bits rw 0x00000000 Match value

Register Match_3_Counter_3 Details

Field Name Match (MATCH) Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.

Register (ttc) Interrupt_Register_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Register_1 ISR 0x00000054 ttc0: 0xF8001054 ttc1: 0xF8002054 6 bits ro 0x00000000 Counter 1 Interval, Match, Overflow and Event interrupts

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Register Interrupt_Register_1 Details

Field Name Ev Ov (IXR_CNT_OVR) M3 (IXR_MATCH_2) M2 (IXR_MATCH_1) M1 (IXR_MATCH_0) Iv (IXR_INTERVAL) 0 ro 0x0 Interval interrupt 1 ro 0x0 Match 1 interrupt 2 ro 0x0 Match 2 interrupt 3 ro 0x0 Match 3 interrupt Bits 5 4 Type ro ro Reset Value 0x0 0x0 Description Event timer overflow interrupt Counter overflow

Register (ttc) Interrupt_Register_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Register_2 0x00000058 ttc0: 0xF8001058 ttc1: 0xF8002058 6 bits ro 0x00000000 Counter 2 Interval, Match, Overflow and Event interrupts

Register Interrupt_Register_2 Details

Field Name Ev Ov (IXR_CNT_OVR) M3 (IXR_MATCH_2) M2 (IXR_MATCH_1) M1 (IXR_MATCH_0) Iv (IXR_INTERVAL) 0 ro 0x0 Interval interrupt 1 ro 0x0 Match 1 interrupt 2 ro 0x0 Match 2 interrupt 3 ro 0x0 Match 3 interrupt Bits 5 4 Type ro ro Reset Value 0x0 0x0 Description Event timer overflow interrupt Counter overflow

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Register (ttc) Interrupt_Register_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Register_3 0x0000005C ttc0: 0xF800105C ttc1: 0xF800205C 6 bits ro 0x00000000 Counter 3 Interval, Match, Overflow and Event interrupts

Register Interrupt_Register_3 Details

Field Name Ev Ov (IXR_CNT_OVR) M3 (IXR_MATCH_2) M2 (IXR_MATCH_1) M1 (IXR_MATCH_0) Iv (IXR_INTERVAL) 0 ro 0x0 Interval interrupt 1 ro 0x0 Match 1 interrupt 2 ro 0x0 Match 2 interrupt 3 ro 0x0 Match 3 interrupt Bits 5 4 Type ro ro Reset Value 0x0 0x0 Description Event timer overflow interrupt Counter overflow

Register (ttc) Interrupt_Enable_1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Enable_1 IER 0x00000060 ttc0: 0xF8001060 ttc1: 0xF8002060 6 bits rw 0x00000000 ANDed with corresponding Interrupt Register

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Register Interrupt_Enable_1 Details

Field Name IEN Bits 5:0 Type rw Reset Value 0x0 Description Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.

Register (ttc) Interrupt_Enable_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Enable_2 0x00000064 ttc0: 0xF8001064 ttc1: 0xF8002064 6 bits rw 0x00000000 ANDed with corresponding Interrupt Register

Register Interrupt_Enable_2 Details

Field Name IEN Bits 5:0 Type rw Reset Value 0x0 Description Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.

Register (ttc) Interrupt_Enable_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Interrupt_Enable_3 0x00000068 ttc0: 0xF8001068 ttc1: 0xF8002068 6 bits rw 0x00000000 ANDed with corresponding Interrupt Register

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Register Interrupt_Enable_3 Details

Field Name IEN Bits 5:0 Type rw Reset Value 0x0 Description Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.

Register (ttc) Event_Control_Timer_1

Name Relative Address Absolute Address Width Access Type Reset Value Description Event_Control_Timer_1 0x0000006C ttc0: 0xF800106C ttc1: 0xF800206C 3 bits rw 0x00000000 Enable, pulse and overflow

Register Event_Control_Timer_1 Details

Field Name E_Ov Bits 2 Type rw Reset Value 0x0 Description When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow. When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk. Enable timer: when this bit is high, the event timer is enabled.

E_Lo

rw

0x0

E_En

rw

0x0

Register (ttc) Event_Control_Timer_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Event_Control_Timer_2 0x00000070 ttc0: 0xF8001070 ttc1: 0xF8002070 3 bits rw 0x00000000 Enable, pulse and overflow

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Register Event_Control_Timer_2 Details

Field Name E_Ov Bits 2 Type rw Reset Value 0x0 Description When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow. When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk. Enable timer: when this bit is high, the event timer is enabled.

E_Lo

rw

0x0

E_En

rw

0x0

Register (ttc) Event_Control_Timer_3

Name Relative Address Absolute Address Width Access Type Reset Value Description Event_Control_Timer_3 0x00000074 ttc0: 0xF8001074 ttc1: 0xF8002074 3 bits rw 0x00000000 Enable, pulse and overflow

Register Event_Control_Timer_3 Details

Field Name E_Ov Bits 2 Type rw Reset Value 0x0 Description When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow. When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk. Enable timer: when this bit is high, the event timer is enabled.

E_Lo

rw

0x0

E_En

rw

0x0

Register (ttc) Event_Register_1

Name Relative Address Event_Register_1 0x00000078

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Absolute Address Width Access Type Reset Value Description

ttc0: 0xF8001078 ttc1: 0xF8002078 16 bits ro 0x00000000 pclk cycle count for event

Register Event_Register_1 Details

Field Name Event Bits 15:0 Type ro Reset Value 0x0 Description This register stores the result of the pclk count during the ext_clk high or low pulse.

Register (ttc) Event_Register_2

Name Relative Address Absolute Address Width Access Type Reset Value Description Event_Register_2 0x0000007C ttc0: 0xF800107C ttc1: 0xF800207C 16 bits ro 0x00000000 pclk cycle count for event

Register Event_Register_2 Details

Field Name Event Bits 15:0 Type ro Reset Value 0x0 Description This register stores the result of the pclk count during the ext_clk high or low pulse.

Register (ttc) Event_Register_3

Name Relative Address Absolute Address Width Access Type Reset Value Event_Register_3 0x00000080 ttc0: 0xF8001080 ttc1: 0xF8002080 16 bits ro 0x00000000

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Description

pclk cycle count for event

Register Event_Register_3 Details

Field Name Event Bits 15:0 Type ro Reset Value 0x0 Description This register stores the result of the pclk count during the ext_clk high or low pulse.

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B.33 UART Controller (UART)

Module Name Software Name Base Address Description Vendor Info UART Controller (UART) XUARTPS 0xE0000000 uart0 0xE0001000 uart1 Universal Asynchronous Receiver Transmitter Cadence UART

Register Summary
Register Name Control_reg0 mode_reg0 Intrpt_en_reg0 Intrpt_dis_reg0 Intrpt_mask_reg0 Chnl_int_sts_reg0 Baud_rate_gen_reg0 Rcvr_timeout_reg0 Rcvr_FIFO_trigger_lev el0 Modem_ctrl_reg0 Modem_sts_reg0 Channel_sts_reg0 TX_RX_FIFO0 Baud_rate_divider_reg 0 Flow_delay_reg0 Tx_FIFO_trigger_level 0 Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0x00000020 0x00000024 0x00000028 0x0000002C 0x00000030 0x00000034 0x00000038 0x00000044 Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Type mixed mixed mixed mixed ro wtc mixed mixed mixed mixed mixed ro mixed mixed mixed mixed Reset Value 0x00000128 0x00000000 0x00000000 0x00000000 0x00000000 0x00000200 0x0000028B 0x00000000 0x00000020 0x00000000 x 0x00000000 0x00000000 0x0000000F 0x00000000 0x00000020 Description UART Control Register UART Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Interrupt Status Register Baud Rate Generator Register. Receiver Timeout Register Receiver FIFO Trigger Level Register Modem Control Register Modem Status Register Channel Status Register Transmit and Receive FIFO Baud Rate Divider Register Flow Control Delay Register Transmitter FIFO Trigger Level Register

Register (UART) Control_reg0

Name Control_reg0

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

CR 0x00000000 uart0: 0xE0000000 uart1: 0xE0001000 32 bits mixed 0x00000128 UART Control Register

Register Control_reg0 Details

The UART Control register is used to enable and reset the transmitter and receiver blocks. It also controls the receiver timeout and the transmission of breaks.
Field Name reserved STPBRK (STOPBRK) Bits 31:9 8 Type ro rw Reset Value 0x0 0x1 Description Reserved, read as zero, ignored on write. Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. STTBRK (STARTBRK) 7 rw 0x0 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. RSTTO (TORST) 6 rw 0x0 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. TXDIS (TX_DIS) TXEN (TX_EN) 4 rw 0x0 5 rw 0x1 Transmit disable: 0: enable transmitter 1: disable transmitter Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. RXDIS (RX_DIS) 3 rw 0x1 Receive disable: 0: enable 1: disable, regardless of the value of RXEN

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Field Name RXEN (RX_EN)

Bits 2

Type rw

Reset Value 0x0 Receive enable: 0: disable 1: enable

Description

When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. TXRES (TXRST) 1 rw 0x0 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. RXRES (RXRST) 0 rw 0x0 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.

Register (UART) mode_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description mode_reg0 MR 0x00000004 uart0: 0xE0000004 uart1: 0xE0001004 32 bits mixed 0x00000000 UART Mode Register

Register mode_reg0 Details

The UART Mode register defines the setup of the data format to be transmitted or received. If this register is modified during transmission or reception, data validity cannot be guaranteed.
Field Name reserved reserved reserved Bits 31:12 11 10 Type ro rw rw Reset Value 0x0 0x0 0x0 Description Reserved, read as zero, ignored on write. Reserved. Do not modify. Reserved. Do not modify.

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Field Name CHMODE

Bits 9:8

Type rw

Reset Value 0x0

Description Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback

NBSTOP

7:6

rw

0x0

Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved

PAR

5:3

rw

0x0

Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity

CHRL

2:1

rw

0x0

Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits

CLKS (CLKSEL)

rw

0x0

Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8

Register (UART) Intrpt_en_reg0

Name Software Name Relative Address Absolute Address Width Access Type Intrpt_en_reg0 IER 0x00000008 uart0: 0xE0000008 uart1: 0xE0001008 32 bits mixed

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Reset Value Description

0x00000000 Interrupt Enable Register

Register Intrpt_en_reg0 Details

This write only register is used to enable interrupts. When any bit is written high, the corresponding interrupt is enabled. Writing a low to any bit has no effect.
Field Name reserved TOVR Bits 31:13 12 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Transmitter FIFO Overflow interrupt: 0: no affect 1: enable (clears mask = 0) TNFUL 11 wo 0x0 Transmitter FIFO Nearly Full interrupt: 0: no affect 1: enable (clears mask = 0) TTRIG DMSI (IXR_DMS) TIMEOUT (IXR_TOUT) PARE (IXR_PARITY) FRAME (IXR_FRAMING) ROVR (IXR_OVER) TFUL (IXR_TXFULL) TEMPTY (IXR_TXEMPTY) RFUL (IXR_RXFULL) 2 wo 0x0 3 wo 0x0 4 wo 0x0 5 wo 0x0 6 wo 0x0 7 wo 0x0 8 wo 0x0 10 9 wo wo 0x0 0x0 Transmitter FIFO Trigger interrupt: 0: disable 1: enable Delta Modem Status Indicator interrupt: 0: no affect 1: enable (clears mask = 0) Receiver Timeout Error interrupt: 0: no affect 1: enable (clears mask = 0) Receiver Parity Error interrupt: 0: disable 1: enable Receiver Framing Error interrupt: 0: no affect 1: enable (clears mask = 0) Receiver Overflow Error interrupt: 0: no affect 1: enable (clears mask = 0) Transmitter FIFO Full interrupt: 0: no affect 1: enable (clears mask = 0) Transmitter FIFO Empty interrupt: 0: disable 1: enable Receiver FIFO Full interrupt: 0: no affect 1: enable (clears mask = 0)

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Field Name REMPTY (IXR_RXEMPTY) RTRIG (IXR_RXOVR)

Bits 1

Type wo

Reset Value 0x0

Description Receiver FIFO Empty interrupt: 0: no affect 1: enable (clears mask = 0)

wo

0x0

Receiver FIFO Trigger interrupt: 0: no affect 1: enable (clears mask = 0)

Register (UART) Intrpt_dis_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Intrpt_dis_reg0 IDR 0x0000000C uart0: 0xE000000C uart1: 0xE000100C 32 bits mixed 0x00000000 Interrupt Disable Register

Register Intrpt_dis_reg0 Details

This write only register is used to disable interrupts. When any bit is written high, the corresponding interrupt is disabled. Writing a low to any bit has no effect.
Field Name reserved TOVR Bits 31:13 12 Type ro wo Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Transmitter FIFO Overflow interrupt: 0: no affect 1: disable (sets mask = 1) TNFUL 11 wo 0x0 Transmitter FIFO Nearly Full interrupt: 0: no affect 1: disable (sets mask = 1) TTRIG 10 wo 0x0 Transmitter FIFO Trigger interrupt: 0: no affect 1: disable (sets mask = 1) DMSI (IXR_DMS) 9 wo 0x0 Delta Modem Status Indicator interrupt: 0: no affect 1: disable (sets mask = 1)

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Field Name TIMEOUT (IXR_TOUT) PARE (IXR_PARITY) FRAME (IXR_FRAMING) ROVR (IXR_OVER) TFUL (IXR_TXFULL) TEMPTY (IXR_TXEMPTY) RFUL (IXR_RXFULL) REMPTY (IXR_RXEMPTY) RTRIG (IXR_RXOVR)

Bits 8

Type wo

Reset Value 0x0

Description Receiver Timeout Error interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver Parity Error interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver Framing Error interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver Overflow Error interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Transmitter FIFO Full interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Transmitter FIFO Empty interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver FIFO Full interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver FIFO Empty interrupt: 0: no affect 1: disable (sets mask = 1)

wo

0x0

Receiver FIFO Trigger interrupt: 0: no affect 1: disable (sets mask = 1)

Register (UART) Intrpt_mask_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Intrpt_mask_reg0 IMR 0x00000010 uart0: 0xE0000010 uart1: 0xE0001010 32 bits ro 0x00000000

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Description

Interrupt Mask Register

Register Intrpt_mask_reg0 Details

This read only register, indicates the current state of the interrupts mask. A high value indicates the interrupt is unmasked and therefore is enabled to generate an interrupt. A low value indicates the interrupt is masked and therefore is disabled from generating an interrupt.
Field Name reserved TOVR Bits 31:13 12 Type ro ro Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Transmitter FIFO Overflow interrupt status: 0: interrupt is disabled 1: interrupt is enabled TNFUL 11 ro 0x0 Transmitter FIFO Nearly Full interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled TTRIG 10 ro 0x0 Transmitter FIFO Trigger interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled DMSI (IXR_DMS) 9 ro 0x0 Delta Modem Status Indicator interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled TIMEOUT (IXR_TOUT) PARE (IXR_PARITY) FRAME (IXR_FRAMING) ROVR (IXR_OVER) TFUL (IXR_TXFULL) TEMPTY (IXR_TXEMPTY) 3 ro 0x0 4 ro 0x0 5 ro 0x0 6 ro 0x0 7 ro 0x0 8 ro 0x0 Receiver Timeout Error interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled Receiver Parity Error interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled Receiver Framing Error interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled Receiver Overflow Error interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled Transmitter FIFO Full interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled Transmitter FIFO Empty interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled

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Field Name RFUL (IXR_RXFULL) REMPTY (IXR_RXEMPTY) RTRIG (IXR_RXOVR)

Bits 2

Type ro

Reset Value 0x0

Description Receiver FIFO Full interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled

ro

0x0

Receiver FIFO Empty interrupt mask status: 0: interrupt is disabled 1: interrupt is enabled

ro

0x0

Receiver FIFO Trigger interrupt mask status: 0: interrupt is enabled 1: interrupt is enabled

Register (UART) Chnl_int_sts_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Chnl_int_sts_reg0 ISR 0x00000014 uart0: 0xE0000014 uart1: 0xE0001014 32 bits wtc 0x00000200 Channel Interrupt Status Register

Register Chnl_int_sts_reg0 Details

The Channel Interrupt Status register indicates any interrupt events that have occurred since this register was last cleared. The bits in this register are compared with the interrupt mask and used to assert the interrupt output. This register indicated the unmasked status, allowing software to implement a polling method of interrupt handling.
Field Name reserved TOVR Bits 31:13 12 Type wtc wtc Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Transmitter FIFO Overflow interrupt mask status: This event is triggered whenever a new word is pushed into the transmit FIFO when there is not enough room for all of the data. This will be set as a result of any write when the TFUL flag in Channel_sts_reg0 is already set, or a double byte write when the TNFUL flag in Channel_sts_reg0 is already set. 0: no interrupt occurred 1: interrupt occurred

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Field Name TNFUL

Bits 11

Type wtc

Reset Value 0x0

Description Transmitter FIFO Nearly Full interrupt mask status: This event is triggered whenever a new word is pushed into the transmit FIFO causing the fill level to be such that there is not enough space for a further write of the number of bytes currently specified in the WSIZE bits in the Mode register. If this further write were currently attempted it would cause an overflow. Note that when WSIZE is 00, this assumes that a two byte write would be attempted and hence a single byte write is still possible without overflow by driving byte_sel low for the write. 0: no interrupt occurred 1: interrupt occurred

TTRIG

10

wtc

0x0

Transmitter FIFO Trigger interrupt mask status. This event is triggered whenever a new word is pushed into the transmit FIFO causing the fill level to become equal to the value defined by TTRIG. 0: no interrupt occurred 1: interrupt occurred

DMSI (IXR_DMS)

wtc

0x1

Delta Modem Status Indicator interrupt mask status: This event is triggered whenever the DCTS, DDSR, TERI, or DDCD in the modem status register are being set. 0: no interrupt occurred 1: interrupt occurred

TIMEOUT (IXR_TOUT)

wtc

0x0

Receiver Timeout Error interrupt mask status: This event is triggered whenever the receiver timeout counter has expired due to a long idle condition. 0: no interrupt occurred 1: interrupt occurred

PARE (IXR_PARITY)

wtc

0x0

Receiver Parity Error interrupt mask status: This event is triggered whenever the received parity bit does not match the expected value. 0: no interrupt occurred 1: interrupt occurred

FRAME (IXR_FRAMING)

wtc

0x0

Receiver Framing Error interrupt mask status: This event is triggered whenever the receiver fails to detect a valid stop bit. 0: no interrupt occurred 1: interrupt occurred

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Field Name ROVR (IXR_OVER)

Bits 5

Type wtc

Reset Value 0x0

Description Receiver Overflow Error interrupt mask status: This event is triggered whenever the contents of the receiver shift register have not yet been transferred to the receiver FIFO and a new start bit is detected. This may be due to the FIFO being full, or due to excessive clock boundary delays. 0: no interrupt occurred 1: interrupt occurred

TFUL (IXR_TXFULL)

wtc

0x0

Transmitter FIFO Full interrupt mask status: This event is triggered whenever a new word is inserted into the transmit FIFO causing it to go from a non-full condition to a full condition. 0: no interrupt occurred 1: interrupt occurred

TEMPTY (IXR_TXEMPTY)

wtc

0x0

Transmitter FIFO Empty interrupt mask status: This event is triggered whenever the final word is removed from the transmit FIFO. 0: no interrupt occurred 1: interrupt occurred

RFUL (IXR_RXFULL)

wtc

0x0

Receiver FIFO Full interrupt mask status: This event is triggered whenever a new word is inserted into the receive FIFO causing it to go from a non-full condition to a full condition. 0: no interrupt occurred 1: interrupt occurred

REMPTY (IXR_RXEMPTY)

wtc

0x0

Receiver FIFO Empty interrupt mask status: This event is triggered upon exit of the final word from the receive FIFO. 0: no interrupt occurred 1: interrupt occurred

RTRIG (IXR_RXOVR)

wtc

0x0

Receiver FIFO Trigger interrupt mask status: This event is triggered whenever a new word is inserted into the receive FIFO . 0: no interrupt occurred 1: interrupt occurred

Register (UART) Baud_rate_gen_reg0

Name Software Name Relative Address Baud_rate_gen_reg0 BAUDGEN 0x00000018

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Absolute Address Width Access Type Reset Value Description

uart0: 0xE0000018 uart1: 0xE0001018 32 bits mixed 0x0000028B Baud Rate Generator Register.

Register Baud_rate_gen_reg0 Details

The read/write baud rate generator control register controls the amount by which to divide sel_clk to generate the bit rate clock enable, baud_sample.
Field Name reserved CD Bits 31:16 15:0 Type ro rw Reset Value 0x0 0x28B Description Reserved, read as zero, ignored on write. Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample

Register (UART) Rcvr_timeout_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Rcvr_timeout_reg0 RXTOUT 0x0000001C uart0: 0xE000001C uart1: 0xE000101C 32 bits mixed 0x00000000 Receiver Timeout Register

Register Rcvr_timeout_reg0 Details

The read/write Receiver Timeout register is used to enable the UART to detect an idle condition on the receiver data line. The timeout value (RTO) indicates the maximum delay for which the UART should wait for a new character to arrive before issuing a timeout interrupt.
Field Name reserved RTO Bits 31:8 7:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Receiver timeout value: 0: Disables receiver timeout counter 1 - 255: Receiver timeout in number of baud_sample clocks.

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Register (UART) Rcvr_FIFO_trigger_level0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Rcvr_FIFO_trigger_level0 RXWM 0x00000020 uart0: 0xE0000020 uart1: 0xE0001020 32 bits mixed 0x00000020 Receiver FIFO Trigger Level Register

Register Rcvr_FIFO_trigger_level0 Details

The read/write Receiver FIFO Trigger Level Register is used to set the value at which the receiver FIFO triggers an interrupt event.
Field Name reserved RTRIG Bits 31:6 5:0 Type ro rw Reset Value 0x0 0x20 Description Reserved, read as zero, ignored on write. Receiver FIFO trigger level value: 0: Disables receiver FIFO trigger level function 1 - 63:Trigger set when receiver FIFO fills to RTRIG bytes

Register (UART) Modem_ctrl_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Modem_ctrl_reg0 MODEMCR 0x00000024 uart0: 0xE0000024 uart1: 0xE0001024 32 bits mixed 0x00000000 Modem Control Register

Register Modem_ctrl_reg0 Details

The read/write Modem Control register controls the interface with the modem or data set, or a peripheral device emulating a modem.

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Field Name reserved FCM

Bits 31:6 5

Type ro rw

Reset Value 0x0 0x0

Description Reserved, read as zero, ignored on write. Automatic flow control mode: 0: disable Transmission is continuous regardless of the value of the EMIOUARTxCTSN input, and the EMIOUARTxRTSN output is driven completely under software control. 1: enable Transmission will only occur when the EMIOUARTxCTSN input is asserted low, and the EMIOUARTxRTSN output is driven using a compare of the RX FIFO fill level to the programmed FDEL value.

reserved RTS

4:2 1

ro rw

0x0 0x0

Reserved, read as zero, ignored on write. Request to send output control: This bit is ignored if automatic flow control mode is enabled by FCM being high. If FCM is low, the value of this bit is inverted when applied to the EMIOUARTxRTSN output. 0: EMIOUARTxRTSN output forced to logic 1 1: EMIOUARTxRTSN output forced to logic 0

DTR

rw

0x0

Data Terminal Ready: The value of this bit is inverted when applied to the EMIOUARTxDTRN output. 0: EMIOUARTxDTRN output forced to logic 1 1: EMIOUARTxDTRN output forced to logic 0

Register (UART) Modem_sts_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Modem_sts_reg0 MODEMSR 0x00000028 uart0: 0xE0000028 uart1: 0xE0001028 32 bits mixed x Modem Status Register

Register Modem_sts_reg0 Details

The Modem Status register indicates the current state of the control lines from the modem, or peripheral device, to the CPU. In addition, four bits of the modem status register provide change of state or delta

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information. These bits are set to logic 1 whenever a control input from the modem changes state. In the default configuration, these delta bits are all cleared simultaneously when this register is read. This may be parameterised at compile time such that a one must be written to a bit in order to clear it and a read has no effect.
Field Name reserved FCMS Bits 31:9 8 Type ro rw x x Reset Value Description Reserved, read as zero, ignored on write. Flow Control Mode: 0: disabled 1: enabled DCD 7 ro x Data Carrier Detect (DCD) input signal from PL (EMIOUARTxDCDN) status: 0: input is high 1: input is low RI 6 ro x Ring Indicator (RI) input signal from PL (EMIOUARTxRIN) status: 0: input is high 1: input is low DSR 5 ro x Data Set Ready (DSR) input signal from PL (EMIOUARTxDSRN) status: 0: input is high 1: input is low CTS 4 ro x Clear to Send (CTS) input signal from PL (EMIOUARTxCTSN) status: 0: input is high 1: input is low DDCD (MEDEMSR_DCDX) 3 wtc x Delta Data Carrier Detect status: Indicates a change in state of the EMIOUARTxDCDN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred TERI (MEDEMSR_RIX) 2 wtc x Trailing Edge Ring Indicator status: Indicates that the EMIOUARTxRIN input has change from high to low state since this bit was last cleared. 0: No trailing edge has occurred 1: Trailing edge has occurred

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Field Name DDSR (MEDEMSR_DSRX)

Bits 1

Type wtc

Reset Value x

Description Delta Data Set Ready status: Indicates a change in state of the EMIOUARTxDSRN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred

DCTS (MEDEMSR_CTSX)

wtc

Delta Clear To Send status: Indicates a change in state of the EMIOUARTxCTSN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred

Register (UART) Channel_sts_reg0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description Channel_sts_reg0 SR 0x0000002C uart0: 0xE000002C uart1: 0xE000102C 32 bits ro 0x00000000 Channel Status Register

Register Channel_sts_reg0 Details

The read only Channel Status register is provided to enable the continuous monitoring of the raw unmasked status information of the UART design. Bits [4:0] and [14:10] are not latched and provide raw status of the FIFO flags, such that if the FIFO level changes these bits are updated immediately.

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Field Name reserved TNFUL

Bits 31:15 14

Type ro ro

Reset Value 0x0 0x0

Description Reserved, read as zero, ignored on write. Transmitter FIFO Nearly Full continuous status: This indicates that there is not enough space for the number of bytes currently specified in the WSIZE bits in the Mode register. If a write were currently attempted it would cause an overflow. Note that when WSIZE is 00, this assumes that a two byte write would be attempted and hence a single byte write is still possible without overflow by driving byte_sel low for the write. 0: More than one byte is unused in the Tx FIFO 1: Only one byte is free in the Tx FIFO

TTRIG

13

ro

0x0

Transmitter FIFO Trigger continuous status: 0: Tx FIFO fill level is less than TTRIG 1: Tx FIFO fill level is greater than or equal to TTRIG

FDELT (FLOWDEL)

12

ro

0x0

Receiver flow delay trigger continuous status: 0: Rx FIFO fill level is less than FDEL 1: Rx FIFO fill level is greater than or equal to FDEL

TACTIVE

11

ro

0x0

Transmitter state machine active status: 0: inactive state 1: active state

RACTIVE

10

ro

0x0

Receiver state machine active status: 0: inactive state 1: active state

reserved reserved reserved reserved reserved TFUL (TXFULL) TEMPTY (TXEMPTY) RFUL (RXFULL)

9 8 7 6 5 4

ro ro ro ro ro ro

0x0 0x0 0x0 0x0 0x0 0x0

Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Reserved. Do not modify. Transmitter FIFO Full continuous status: 0: Tx FIFO is not full 1: Tx FIFO is full

ro

0x0

Transmitter FIFO Empty continuous status: 0: Tx FIFO is not empty 1: Tx FIFO is empty

ro

0x0

Receiver FIFO Full continuous status: 1: Rx FIFO is full 0: Rx FIFO is not full

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Field Name REMPTY (RXEMPTY) RTRIG (RXOVR)

Bits 1

Type ro

Reset Value 0x0

Description Receiver FIFO Full continuous status: 0: Rx FIFO is not empty 1: Rx FIFO is empty

ro

0x0

Receiver FIFO Trigger continuous status: 0: Rx FIFO fill level is less than RTRIG 1: Rx FIFO fill level is greater than or equal to RTRIG

Register (UART) TX_RX_FIFO0

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TX_RX_FIFO0 FIFO 0x00000030 uart0: 0xE0000030 uart1: 0xE0001030 32 bits mixed 0x00000000 Transmit and Receive FIFO

Register TX_RX_FIFO0 Details

Field Name reserved FIFO Bits 31:8 7:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. Operates as Tx FIFO and Rx FIFO.

Register (UART) Baud_rate_divider_reg0

Name Relative Address Absolute Address Width Access Type Reset Value Description Baud_rate_divider_reg0 0x00000034 uart0: 0xE0000034 uart1: 0xE0001034 32 bits mixed 0x0000000F Baud Rate Divider Register

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Register Baud_rate_divider_reg0 Details

The baud rate divider register controls how much baud_sample is divided by to generate the baud rate clock enables, baud_rx_rate and baud_tx_rate.
Field Name reserved BDIV Bits 31:8 7:0 Type ro rw Reset Value 0x0 0xF Description Reserved, read as zero, ignored on write. Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate

Register (UART) Flow_delay_reg0

Name Relative Address Absolute Address Width Access Type Reset Value Description Flow_delay_reg0 0x00000038 uart0: 0xE0000038 uart1: 0xE0001038 32 bits mixed 0x00000000 Flow Control Delay Register

Register Flow_delay_reg0 Details

The Flow Control Delay register is only used if automatic flow control mode is enabled in the FCM field in the Modem Control register. When automatic flow control mode is enabled, this register specifies the receiver FIFO level at which the EMIOUARTxRTSN output is de-asserted. The EMIOUARTxRTSN output is only asserted again once the fill level drops to below four less than FDEL.
Field Name reserved FDEL Bits 31:6 5:0 Type ro rw Reset Value 0x0 0x0 Description Reserved, read as zero, ignored on write. RxFIFO trigger level for Ready To Send (RTS) output signal (EMIOUARTxRTSN) de-assertion: 0 - 3: Flow delay triggering is disabled, since minimum 4 word hysteresis cannot be satisfied. 4 to 65535: EMIOUARTxRTSN is driven high when Rx FIFO fill level equals FDEL

Register (UART) Tx_FIFO_trigger_level0

Name Relative Address Absolute Address Tx_FIFO_trigger_level0 0x00000044 uart0: 0xE0000044 uart1: 0xE0001044

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Width Access Type Reset Value Description

32 bits mixed 0x00000020 Transmitter FIFO Trigger Level Register

Register Tx_FIFO_trigger_level0 Details

The read/write Transmitter FIFO Trigger Level Register is used to set the value at which the transmitter FIFO triggers an interrupt event.
Field Name reserved TTRIG Bits 31:6 5:0 Type ro rw Reset Value 0x0 0x20 Description Reserved, read as zero, ignored on write. Transmitter FIFO trigger level: 0: Disables transmitter FIFO trigger level function 1 - 63: Trigger set when transmitter FIFO fills to TTRIG bytes

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B.34 USB Controller (usb)

Module Name Software Name Base Address Description Vendor Info USB Controller (usb) XUSBPS 0xE0002000 usb0 0xE0003000 usb1 USB controller registers Synopsys

Register Summary
Register Name ID HWGENERAL HWHOST HWDEVICE HWTXBUF HWRXBUF GPTIMER0LD GPTIMER0CTRL GPTIMER1LD GPTIMER1CTRL SBUSCFG CAPLENGTH_HCIVE RSION HCSPARAMS HCCPARAMS DCIVERSION DCCPARAMS Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000080 0x00000084 0x00000088 0x0000008C 0x00000090 0x00000100 0x00000104 0x00000108 0x00000120 0x00000124 Width 32 12 32 6 32 32 24 32 24 32 3 32 28 16 16 9 Type ro ro ro ro ro ro rw mixed rw mixed rw ro ro ro ro ro Reset Value 0xE441FA05 0x00000083 0x10020001 0x00000019 0x80060A10 0x00000A10 0x00000000 0x00000000 0x00000000 0x00000000 0x00000003 0x01000040 0x00010011 0x00000006 0x00000001 0x0000018C Description IP version and revision, read-only Misc IP config constants, read-only Host Mode IP config constants, read-only Device Mode IP config constants, read-only TxBuffer IP config constants, read-only IP constants, RX buffer constants, read-only GP Timer 0 Load Value GP Timer 1 Control GP Timer 1 Load Value GP Timer 1 Control DMA Master AHB Burst Mode EHCI Addr Space and HCI constants, read-only TT counts and EHCI HCS constants, read-only EHCI Host configuration constants Device Mode CI version constant EHCI, device and endpoint capabilities

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Register Name USBCMD USBSTS USBINTR FRINDEX PERIODICLISTBASE_ DEVICEADDR ASYNCLISTADDR_E NDPOINTLISTADDR TTCTRL BURSTSIZE TXFILLTUNING TXTTFILLTUNING IC_USB ULPI_VIEWPORT ENDPTNAK ENDPTNAKEN CONFIGFLAG PORTSC1 OTGSC USBMODE ENDPTSETUPSTAT ENDPTPRIME ENDPTFLUSH ENDPTSTAT ENDPTCOMPLETE ENDPTCTRL0 ENDPTCTRL1 ENDPTCTRL2 ENDPTCTRL3 ENDPTCTRL4 ENDPTCTRL5

Address 0x00000140 0x00000144 0x00000148 0x0000014C 0x00000154 0x00000158 0x0000015C 0x00000160 0x00000164 0x00000168 0x0000016C 0x00000170 0x00000178 0x0000017C 0x00000180 0x00000184 0x000001A4 0x000001A8 0x000001AC 0x000001B0 0x000001B4 0x000001B8 0x000001BC 0x000001C0 0x000001C4 0x000001C8 0x000001CC 0x000001D0 0x000001D4

Width 24 26 26 14 32 32 32 17 22 13 32 32 32 32 32 32 32 32 16 32 32 32 32 24 24 24 24 24 24

Type mixed mixed mixed rw mixed mixed mixed rw mixed mixed mixed mixed wtc rw ro mixed mixed mixed wtc wtc wtc ro rw mixed mixed mixed mixed mixed mixed

Reset Value 0x00000B00 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001010 0x00020000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000000 0x00000020 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00800080 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description USB Commands (EHCI extended) Interrupt/Raw Status (EHCI extended) (Host/Device) Interrrupts and Enables Frame List Index Host/Device Address dual-use Host/Device dual-use TT Control Burst Size TxFIFO Fill Tuning TT TX latency FIFO Low and Fast Speed Control constants ULPI Viewport Endpoint NAK (Device mode) Endpoint NAK (Device mode) reserved Port Status & Control OTG Status and Control USB Mode Selection Endpoint Status Setup (Device mode) Endpoint Primer (Device mode) Endpoint Flush (Device mode) Endpoint Buffer Ready Status (Device mode), RO Endpoint Tx Complete (Device mode) Endpoint 0 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode)

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Register Name ENDPTCTRL6 ENDPTCTRL7 ENDPTCTRL8 ENDPTCTRL9 ENDPTCTRL10 ENDPTCTRL11

Address 0x000001D8 0x000001DC 0x000001E0 0x000001E4 0x000001E8 0x000001EC

Width 24 24 24 24 24 24

Type mixed mixed mixed mixed mixed mixed

Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

Description Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode) Endpoints 1 to 11 (Device mode)

Register (usb) ID
Name Relative Address Absolute Address Width Access Type Reset Value Description ID 0x00000000 usb0: 0xE0002000 usb1: 0xE0003000 32 bits ro 0xE441FA05 IP version and revision, read-only

Register ID Details
IP supplier controller identification (revision and synthesized configuration). Hardwired (constant value).
Field Name CIVERSION VERSION Bits 31:29 28:25 Type ro ro Reset Value 0x7 0x2 Description Reserved, reads 111. IP entire version code: [VERSION].[REVISION][TAG] refers to IP version 2.20a. Refer to [VERSION]. Refer to [VERSION]. reserved, writes ignored. Controller ID: Ones complement of [ID]. reserved, writes ignored. Controller ID: USB controller supports HS, On-the-Go, and FS/LS.

REVISION TAG reserved NID reserved ID

24:21 20:16 15:14 13:8 7:6 5:0

ro ro ro ro ro ro

0x2 0x1 0x3 0x3A 0x0 0x5

Register (usb) HWGENERAL

Name HWGENERAL

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Relative Address Absolute Address Width Access Type Reset Value Description

0x00000004 usb0: 0xE0002004 usb1: 0xE0003004 12 bits ro 0x00000083 Misc IP config constants, read-only

Register HWGENERAL Details

General hardware parameters provided by the IP supplier and defined by Xilinx for synthesis. Hardwired (constant value). Bits [31:12] are reserved.
Field Name SM Bits 11:10 Type ro Reset Value 0x0 Description VUSB_HS_PHY_SERIAL constant. 0: Parallel I/O Port interface. Note: VUSB_HS_PHY_UTMI = 0 (UTMI not used) and VUSB_HS_PHY_ULPI = 1 (ULPI implemented). PHYM PHYW 9:6 5:4 ro ro 0x2 0x0 VUSB_HS_PHY_TYPE constant. 0010: 8-bit ULPI single data rate I/O interface. VUSB_HS_PHY16_8 constant. 0: 8-bit data bus BWT CLKC 3 2:1 ro ro 0x0 0x1 reserved VUSB_HS_CLOCK_CONFIGURATION constant. 1: CPU_1x clock must have a higher frequency than the UTMI clock (60 MHz). RT 0 ro 0x1 VUSB_HS_RESET_TYPE constant. 1: Asynchronous Reset

Register (usb) HWHOST

Name Relative Address Absolute Address Width Access Type Reset Value HWHOST 0x00000008 usb0: 0xE0002008 usb1: 0xE0003008 32 bits ro 0x10020001

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Description

Host Mode IP config constants, read-only

Register HWHOST Details

Field Name TTPER TTASY Bits 31:24 23:16 15:4 NPORT HC 3:1 0 Type ro ro ro ro ro Reset Value 0x10 0x2 0x0 0x0 0x1 Description VUSB_HS_TT_PERIODIC_CONTEXTS constant. 0x010: Sixteen periodic contexts in TT. VUSB_HS_TT_ASYNC_CONTEXTS constant. 0x02: Two asynchronous contexts in TT. reserved VUSB_HS_NUM_PORT constant. 000: one downstream port supported. VUSB_HS_HOST constant. 1: Host mode supported.

Register (usb) HWDEVICE

Name Relative Address Absolute Address Width Access Type Reset Value Description HWDEVICE 0x0000000C usb0: 0xE000200C usb1: 0xE000300C 6 bits ro 0x00000019 Device Mode IP config constants, read-only

Register HWDEVICE Details

Field Name DEVEP DC Bits 5:1 0 Type ro ro Reset Value 0xC 0x1 Description VUSB_HS_DEV_EP constant. 0x0C: Twelve endpoints supported (EP 0 to 11). Controller supports Device Mode.

Register (usb) HWTXBUF

Name Relative Address Absolute Address Width HWTXBUF 0x00000010 usb0: 0xE0002010 usb1: 0xE0003010 32 bits

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Access Type Reset Value Description

ro 0x80060A10 TxBuffer IP config constants, read-only

Register HWTXBUF Details

Field Name reserved reserved TXCHANADD Bits 31 30:24 23:16 Type ro ro ro Reset Value 0x1 0x0 0x6 reserved reserved VUSB_HS_TX_CHAN_ADD constant. 0x06: Six address bits for each 64-byte endpoint TxBuffer (VBUS_HS_TX_CHAN = 64). TXADD TXBURST 15:8 7:0 ro ro 0xA 0x10 VUSB_HS_TX_ADD constant. 0x0A0: 10-bit address. TxBuffer size is 768. VUSB_HS_TX_BURST constant. 0x010: 16-byte bursts on AHB by DMA engine. Description

Register (usb) HWRXBUF

Name Relative Address Absolute Address Width Access Type Reset Value Description HWRXBUF 0x00000014 usb0: 0xE0002014 usb1: 0xE0003014 32 bits ro 0x00000A10 IP constants, RX buffer constants, read-only

Register HWRXBUF Details

Field Name Bits 31:24 RXADD 15:8 Type ro ro Reset Value 0x0 0xA reserved VUSB_HS_RX_ADD constant. 0x0A0: 10-bit address. RxBuffer address size is 1024. RXBURST 7:0 ro 0x10 VUSB_HS_RX_BURST constant. 0x010: 16-byte bursts on AHB by DMA engine. Description

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Register (usb) GPTIMER0LD

Name Relative Address Absolute Address Width Access Type Reset Value Description GPTIMER0LD 0x00000080 usb0: 0xE0002080 usb1: 0xE0003080 24 bits rw 0x00000000 GP Timer 0 Load Value

Register GPTIMER0LD Details

Field Name GPTLD Bits 23:0 Type rw Reset Value 0x0 Description General Purpose Timer Load Value. This field is loaded into the usb.GPTIMERxCTRL [GPTCNT] countdown timer. The value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000 - 1 = 999 (0x0003E7). Note: Maximum value is 0xFF_FFFF (16.777215 seconds).

Register (usb) GPTIMER0CTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description GPTIMER0CTRL 0x00000084 usb0: 0xE0002084 usb1: 0xE0003084 32 bits mixed 0x00000000 GP Timer 1 Control

Register GPTIMER0CTRL Details

This register contains the control for the timer and a data field, which can be queried to determine the running count value.

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Field Name GPTRUN

Bits 31

Type rw

Reset Value 0x0

Description General Purpose Timer Enable. 0: disable. 1: enable. The setting of [GPTRUN] will not have an effect on the [GPTCNT] counter value.

GPTRST

30

wo

0x0

General Purpose Timer Reset. Write 1 to reload. 0: no affect. 1: Reload the [GPTCNT] with the value in [GPTLD].

29:25 GPTMODE 24

ro rw

0x0 0x0

reserved Select Countdown Timer mode. 0: One Shot (single timer countdown). The timer will count down to zero, generate an interrupt and stop until the counter is reset by software. 1: Repeat (looped countdown). The timer will count down to zero, generate an interrupt and automatically reload the counter to begin again.

GPTCNT

23:0

rw

0x0

General Purpose Countdown Timer. Value of the running timer.

Register (usb) GPTIMER1LD

Name Relative Address Absolute Address Width Access Type Reset Value Description GPTIMER1LD 0x00000088 usb0: 0xE0002088 usb1: 0xE0003088 24 bits rw 0x00000000 GP Timer 1 Load Value

Register GPTIMER1LD Details

Field Name GPTLD Bits 23:0 Type rw Reset Value 0x0 Description Refer to description for GPTIMER0LD [GPTLD].

Register (usb) GPTIMER1CTRL

Name Relative Address GPTIMER1CTRL 0x0000008C

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Absolute Address Width Access Type Reset Value Description

usb0: 0xE000208C usb1: 0xE000308C 32 bits mixed 0x00000000 GP Timer 1 Control

Register GPTIMER1CTRL Details

Field Name GPTRUN GPTRST Bits 31 30 29:25 GPTMODE GPTCNT 24 23:0 Type rw wo ro rw rw Reset Value 0x0 0x0 0x0 0x0 0x0 Description Refer to GPTIMER0CTRL [GPTRUN]. Refer to GPTIMER0CTRL [GPTRST]. reserved Refer to GPTIMER0CTRL [GPTMODE]. Refer to GPTIMER0CTRL [GPTCNT].

Register (usb) SBUSCFG

Name Relative Address Absolute Address Width Access Type Reset Value Description SBUSCFG 0x00000090 usb0: 0xE0002090 usb1: 0xE0003090 3 bits rw 0x00000003 DMA Master AHB Burst Mode

Register SBUSCFG Details

Field Name AHBBRST Bits 2:0 Type rw Reset Value 0x3 Description VUSB_HS_AHBBRST constant.

Register (usb) CAPLENGTH_HCIVERSION

Name Relative Address Absolute Address Width CAPLENGTH_HCIVERSION 0x00000100 usb0: 0xE0002100 usb1: 0xE0003100 32 bits

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Access Type Reset Value Description

ro 0x01000040 EHCI Addr Space and HCI constants, read-only

Register CAPLENGTH_HCIVERSION Details

Field Name HCIVERSION CAPLENGTH Bits 31:16 15:0 Type ro ro Reset Value 0x100 0x40 Description VUSB_HS_HCIVERSION constant. Host Mode (EHCI). Read-only. Address space taken by the Capability registers. Host Mode (EHCI). Read-only. 0x100: add this offset to the address of the first Capability register to get the address of the first Operational register.

Register (usb) HCSPARAMS

Name Relative Address Absolute Address Width Access Type Reset Value Description HCSPARAMS 0x00000104 usb0: 0xE0002104 usb1: 0xE0003104 28 bits ro 0x00010011 TT counts and EHCI HCS constants, read-only

Register HCSPARAMS Details

Port steering logic capabilities are confined to the single host port implementation..
Field Name N_TT N_PTT reserved PI Bits 27:24 23:20 19:17 16 Type ro ro ro ro Reset Value 0x0 0x0 0x0 0x1 Description Transaction Translators (TT), read-only. 0: none. Number of ports per TT, read-only. 0: single host port. reserved. Port Indicator (EHCI contant), read-only. 1: indicator available via EMIO, controlled by usb.PORTSC1 [PIC]. N_CC 15:12 ro 0x0 Companion controller hardware (EHCI constant). 0: no companion controller hardware, refer to the embeded Transaction Translator (TT).

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Field Name N_PCC

Bits 11:8

Type ro

Reset Value 0x0

Description Ports supported by each Companion Controller (EHCI constant). 0: no companion controller hardware refer to the embeded Transaction Translator (TT).

reserved PPC N_PORTS

7:5 4 3:0

ro ro ro

0x0 0x1 0x1

reserved VBUS Power Control (EHCI constant). 1: signal avaiable via EMIO, see PORTSC1 [PP]. Downstream ports (EHCI constant). 1: one downstream port.

Register (usb) HCCPARAMS

Name Relative Address Absolute Address Width Access Type Reset Value Description HCCPARAMS 0x00000108 usb0: 0xE0002108 usb1: 0xE0003108 16 bits ro 0x00000006 EHCI Host configuration constants

Register HCCPARAMS Details

This register identifies multiple mode control (time-base bit functionality) addressing capability
Field Name EECP IST Bits 15:8 7:4 Type ro ro Reset Value 0x0 0x0 EHCI Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. 3 ASP 2 ro ro 0x0 0x1 reserved Park mode capability. Read-only. Enables the controller to execute a QH transactions successively before traversing to next QH. Description

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Field Name PFL

Bits 1

Type ro

Reset Value 0x1

Description Programmable Frame List sizes (Host mode). Software can specify the size of the frame list for the periodic schedule. Configure the size using the usb.USBCMD [FS2] [FS0] Frame List Size field: 8, 16, 32, .... 512, 1024.

ADC

ro

0x0

0: 32-bit system memory address.

Register (usb) DCIVERSION

Name Relative Address Absolute Address Width Access Type Reset Value Description DCIVERSION 0x00000120 usb0: 0xE0002120 usb1: 0xE0003120 16 bits ro 0x00000001 Device Mode CI version constant

Register DCIVERSION Details

Field Name DCIVERSION Bits 15:0 Type ro Reset Value 0x1 Description VUSB_HS_DCIVERSION constant.

Register (usb) DCCPARAMS

Name Relative Address Absolute Address Width Access Type Reset Value Description DCCPARAMS 0x00000124 usb0: 0xE0002124 usb1: 0xE0003124 9 bits ro 0x0000018C EHCI, device and endpoint capabilities

Register DCCPARAMS Details

Host and device mode capability.

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Field Name HC DC

Bits 8 7 6:5

Type ro ro ro ro

Reset Value 0x1 0x1 0x0 0xC

Description 1: the controller supports EHCI compatible mode. 1: the controller supports Device mode. reserved Number of endpoints supported in Device mode. 1100: 12 endpoints; control EP0 plus EP {11:1}.

DEN

4:0

Register (usb) USBCMD

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description USBCMD CMD 0x00000140 usb0: 0xE0002140 usb1: 0xE0003140 24 bits mixed 0x00000B00 USB Commands (EHCI extended)

Register USBCMD Details

The serial bus host/device controller executes the command indicated in this register
Field Name ITC Bits 23:16 Type rw Reset Value 0x0 Description Interrupt Threshold Control (EHCI) (Host and mode). Program the maximum rate at which the host controller will issue an interrupt. 0x00: Immediate 0x01: 1 micro-frame. 0x02: 2 micro-frames. 0x04: 4 micro-frames. 0x08: 8 micro-frames. (1 ms) 0x10: 16 micro-frames. 0x20: 32 micro-frames. 0x40: 64 micro-frames. others: reserved. FS2 ATDTW 15 14 rw rw 0x0 0x0 MSB bit of Frame List Size. Refer to [FS0] bit field for description. Add dTD TripWire (Host extended). This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's linked list.

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Field Name SUTW

Bits 13

Type rw

Reset Value 0x0

Description Setup TripWire (Device mode). This semaphore is between the DCD and the hardware for extracting setup data from QH with out any corruption. Refer to the chapter text for usage.

reserved ASPE

12 11

ro rw

0x0 0x1

reserved Asynchronous Schedule Park Mode Enable (EHCI). This bit enables/disables the Asynchronous Schedule Park Mode if Asynchronous Park Capability bit in HCCPARAMS is one. Otherwise this bit is zero and Park Mode is disabled.

reserved ASP

10 9:8

ro rw

0x0 0x3

reserved Asynchronous Schudule Park Capability is supported (EHCI). The default is 3. Use any value between 1 and 3. The value 3 gives the maximum throughput in terms of number endpoint transactions compared to 1 or 2.

LR IAA

7 6

ro rw

0x0 0x0

Light Host/Device Controller Reset (EHCI). 0: not supported. Interrupt on Async Schedule Advance Doorbell (EHCI). 0: no affect 1: ring the doorbell when the controller advances the asynchronous schedule.

ASE

rw

0x0

Asyncronous Schedule Enable (EHCI) (Host mode). 0: disable Async Schedule processing (the current DMA transactions finishes). 1: enable Async Schedule processing (the memory address for the async schedule is programmed into usb.ASYNCLISTADDR).

PSE

rw

0x0

Periodic Schedule Enable (EHCI) (Host mode). 0: disable Periodic Schedule processing 1: enable Periodic Schedule Note: The memory address for the periodic schedule is programmed into usb.PERIODICLISTBASE.

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Field Name FS0 (FS01)

Bits 3:2

Type rw

Reset Value 0x0

Description Frame List Size (EHCI extended). usb.USBCMD [15] [3] [2] bits: 000: 1024 elements (4096 bytes) 001: 512 elements (2048 bytes) ... 111: 8 elements (32 bytes)

RST RS

1 0

rw rw

0x0 0x0

Controller Reset and Status (ECHI) (Host and Device mode). Run/Stop (ECHI) (Host and Device modes). Device Mode: 0: the controller halts activity after the current packet transfer is complete. 1: the controller proceeds to execute the periodic and async schedules. Host Mode: 0: TBD 1: TBD

Register (usb) USBSTS

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description USBSTS ISR 0x00000144 usb0: 0xE0002144 usb1: 0xE0003144 26 bits mixed 0x00000000 Interrupt/Raw Status (EHCI extended) (Host/Device)

Register USBSTS Details

Various USB bus and port interrupts, controller state status, controller event and general purpose timer interrupts.

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Field Name TI1 (IXR_TI1) TI0 (IXR_TI0)

Bits 25 24

Type rw rw

Reset Value 0x0 0x0

Description GP timer 1 raw interrupt (Host/Device). Refer to [TI0] bit description. GP timer 0 raw interrupt status (Host/Device). Read -0: inactive. 1: active. Hardware sets this bit = 1 when the counter in the GPTIMER0CTRL register transitions to zero. Write -0: no effect. 1: clear this bit to 0.

reserved UPI (IXR_UP)

23:20 19

ro rw

0x0 0x0

reserved Host Periodic raw interrupt status. (Host mode) Read -0: inactive. 1: active. Note: Hardware sets this bit = 1 when a periodic TD is completed with IOC = 1. Write -0: no effect. 1: clear the interrupt bit to 0.

UAI (IXR_UA)

18

rw

0x0

Host Async Schedule raw interrupt status. (Host mode) Read -0: inactive. 1: active. Note: Hardware sets this bit = 1 when an async TD is completed with IOC = 1. Write -0: no effect. 1: clear the interrupt bit to 0.

reserved NAKI (IXR_NAK)

17 16

ro ro

0x0 0x0

RESERVED NAK Interrupt (Device mode), read-only. Read -0: inactive. 1: active. Note: Hardware sets this bit = 1 when the endpoint sends a NAK response and NAK bit is set. Write -0: no effect. 1: clear the interrupt bit to 0.

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Field Name AS (IXR_AS)

Bits 15

Type ro

Reset Value 0x0

Description Async Schedule Processing Status (EHCI) (Host mode), read-only. 0: inactive. 1: active, async schedule is enabled. Note: This status bit is used with the usb.USBCMD [ASE] enable bit. When the software sets usb.USBCMD [ASE], this bit reflects when HW really enabled processing async schedule.

PS (IXR_PS)

14

ro

0x0

Periodic Schedule Processing Status (EHCI) (Host mode), read-only. 0: inactive. 1: active, periodic schedule is enabled. Note: This status bit is used with the usb.USBCMD [PSE] enable bit. When the software sets usb.USBCMD [PSE], this bit reflects when HW really enabled processing periodic schedule.

RCL (IXR_RCL) HCH (IXR_HCH)

13

ro

0x0

Reclamation (EHCI) (Host mode), read-only. 0: unprocessed async transactions. 1: empty async schedule.

12

ro

0x0

HCHaIted (EHCI) (Host mode). This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (e.g. internal error).

reserved ULPII (IXR_ULPI)

11 10

ro rw

0x0 0x0

reserved ULPI Event Completion Interrupt (Host and Device mode). 0: not completed. 1: completed (write 1 to clear).

reserved SLI (IXR_SLE)

9 8

ro rw

0x0 0x0

reserved DCSuspend (Device mode). Write-to-clear. When the controller enters a suspend state from an active state, this bit will be set to a one. This bit is only cleared by software writing a 1 to it.

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Field Name SRI (IXR_SR)

Bits 7

Type rw

Reset Value 0x0

Description SOF Received (Device and Host mode). Indicates start-of-frame detected. 0: not detected 1: SOF detected by hardware (write 1 to clear) Device mode -When the controller detects an SOF on the ULPI bus, this bit is set. This normally occurs at 1 ms or 125 us intervals. Host mode -The controller sets this bit every 125 us. Host software can use this tic for a time base.

URI (IXR_UR)

rw

0x0

USB Reset Received (Device mode). Indicates a USB reset detected by hardware on ULPI bus. 0: not detected 1: reset detected by hardware (write 1 to clear)

AAI (IXR_AA)

rw

0x0

Async Schedule Advance (EHCI) (Host mode). The async advance interrupt can be generated when the controller advances the async schedule. 0: no change 1: controller advanced (write 1 to clear) This event is primed using the async advance doorbell bit, usb.USBCMD [6].

SEI

rw

0x0

System Error (EHCI). AHB interconnect. 0: no error detected. 1: AHB error received (write 1 to clear)

FRI (IXR_FRE)

rw

0x0

Frame List Rollover (EHCI?). Write-to-clear. Read: 0: no rollover. 1: roll over to frame element 0. Write: 0: no effect. 1: clear bit to 0.

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Field Name PCI (IXR_PC)

Bits 2

Type rw

Reset Value 0x0

Description Port Change Detect. The Controller in host mode sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Controller in device mode sets this bit to a one when it detects resume signaling or the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively.

UEI (IXR_UE) UI (IXR_UI)

rw

0x0

USB Error Interrupt. When completion of a USB transaction results in an error condition, this bit is set by the Controller USB Packet Interrupt on Completion (IOC). Write-to-clear. This bit is set by the hardware in situations: * after a transaction descriptor (TD or dTD) is finished and it's interrupt on complete (IOC) bit set. * a short packet is detected. A short packet is when the actual number of bytes received was less than expected.

rw

0x0

Register (usb) USBINTR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description USBINTR IER 0x00000148 usb0: 0xE0002148 usb1: 0xE0003148 26 bits mixed 0x00000000 Interrrupts and Enables

Register USBINTR Details

The to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software.

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Field Name TIE1 (IXR_TI1)

Bits 25

Type rw

Reset Value 0x0

Description GP Timer 1 Interrupt Enable (Host/Device). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [TI1].

TIE0 (IXR_TI0)

24

rw

0x0

GP Timer 0 Interrupt Enable (Host/Device). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [TI0].

reserved UPEI (IXR_UP)

23:20 19

ro rw

0x0 0x0

reserved Host Periodic Interrupt Enable (Host mode). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [UPI].

UAEI (IXR_UA)

18

rw

0x0

Host Async Interrupt Enable (Host mode). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [UAE].

reserved NAKEI (IXR_NAK)

17 16

ro ro

0x0 0x0

reserved NAK Interrupt Enable (Device mode). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [NAKI].

reserved ULPIE (IXR_ULPI)

11 10

ro rw

0x0 0x0

reserved [15:11] ULPI Interrupt Enable (Host/Device). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [ULPII].

reserved SLE (IXR_SLE)

9 8

ro rw

0x0 0x0

reserved DCSuspend Interrupt Enable (Device mode). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [SLI].

SRE (IXR_SR)

rw

0x0

SOF Received Interrupt Enable (Device?). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [SRI].

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Field Name URE (IXR_UR)

Bits 6

Type rw

Reset Value 0x0

Description USB Reset Received Interrupt Enable (Device mode). 0: disable. 1: enable interrupt on receiving USB reset. Refer to raw interrupt status: USBSTS [URI].

AAE (IXR_AA)

rw

0x0

Async Advance Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [AAI].

SEE

rw

0x0

System Error Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [SEI].

FRE (IXR_FRE)

rw

0x0

Frame List Rollover Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [FRI].

PCE (IXR_PC)

rw

0x0

Port Change Detect Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [PCI].

UEE (IXR_UE)

wtc

0x0

USB Error Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [UEI].

UE (IXR_UI)

rw

0x0

USB Interrupt Enable (EHCI). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [UI].

Register (usb) FRINDEX

Name Software Name Relative Address Absolute Address Width Access Type FRINDEX FRAME 0x0000014C usb0: 0xE000214C usb1: 0xE000314C 14 bits rw

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Reset Value Description

0x00000000 Frame List Index

Register FRINDEX Details

This register is used by the host controller to index the periodic frame list. The register updates every 125 us (once each micro-frame).
Field Name FRINDEX Bits 13:0 Type rw Reset Value 0x0 Description Frame Index (EHCI) (Host and Device mode). Host mode -Read: current frame index value. Write: set the frame index value. Device mode -Read-only: frame index from received packet.

Register (usb) PERIODICLISTBASE_DEVICEADDR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description PERIODICLISTBASE_DEVICEADDR LISTBASE 0x00000154 usb0: 0xE0002154 usb1: 0xE0003154 32 bits mixed 0x00000000 Host/Device Address dual-use

Register PERIODICLISTBASE_DEVICEADDR Details

Host mode: PERIODICLISTBASE. Device mode: Device Address Advance and

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Appendix B: Register Details

Field Name PERBASE_USBADRA

Bits 31:25

Type rw

Reset Value 0x0

Description Host mode ---- Periodic List Base Address. Memory address bits [31:25]. Device Mode ---- Device Address Advance. When this bit is '0b', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the hidden register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from hidden register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0).

PERBASE_USBADR

24

rw

0x0

Host mode ---- Periodic List Base Address. Memory address bits [24]. Device Mode ----

PERBASE_Reserved

23:12

rw

0x0

Host mode ---- Periodic List Base Address. Memory address bits [23:12]. Device Mode ---Reserved.

reserved

11:0

ro

0x0

reserved

Register (usb) ASYNCLISTADDR_ENDPOINTLISTADDR

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ASYNCLISTADDR_ENDPOINTLISTADDR ASYNCLISTADDR 0x00000158 usb0: 0xE0002158 usb1: 0xE0003158 32 bits mixed 0x00000000 Host/Device dual-use

Register ASYNCLISTADDR_ENDPOINTLISTADDR Details

Host mode: ASYNCLISTADDR. Device mode: ENDPOINTLISTADDR.

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Field Name ASYBASE_EPBASE

Bits 31:11

Type rw

Reset Value 0x0

Description Host mode -- Async List Base Address. Memory address bits [31:11] point to the Queue Heads (QH) . Refer to [ASYBASE} bit field for [10:5] address bits. Device Mode -- Endpoint List Base Address. Memory address bits [31:11] point to the Queue Heads (QH). There are unused memory locations. The stride for the base address is for a 16-endpoint model using both IN and OUT functions. However, twelve endpoints are implemented.

ASYBASE

10:5

rw

0x0

Host mode ---- Asynchronous List Base Address. Memory address bits [10:5]. Device Mode ---- Reserved.

reserved

4:0

ro

0x0

reserved

Register (usb) TTCTRL

Name Relative Address Absolute Address Width Access Type Reset Value Description TTCTRL 0x0000015C usb0: 0xE000215C usb1: 0xE000315C 32 bits mixed 0x00000000 TT Control

Register TTCTRL Details

This register contains parameters needed for internal TT operations.
Field Name reserved TTHA (HUBADDR) Bits 31 30:24 Type ro rw Reset Value 0x0 0x0 reserved Internal TT Hub Address Representation. This field is used to match against the Hub Address field in QH & siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices. If the Hub Address in the QH or siTD does not match this address then the packet will be broadcast on the High Speed ports destined for a downstream High Speed hub with the address in the QH/siTD. reserved 23:2 ro 0x0 reserved Description

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Appendix B: Register Details

Field Name TTAS

Bits 1

Type rw

Reset Value 0x0

Description Embedded TT Asynchronous Buffers Clear. This field will clear all pending transactions in the embedded TT Asynchronous Buffer(s). The clear will take as much time as necessary to clear buffer without interfering with a transaction in progress. TTAC will return to zero after being set by software only after the actual clear occurs. The TT supports up to two contexts. Embedded TT Async Buffers Status. This read only bit will be '1' if one or more transactions are being held in the embedded TT Asynchronous Buffers. When this bit is a zero, then all outstanding transactions in the embedded TT have been flushed.

TTAC

ro

0x0

Register (usb) BURSTSIZE

Name Relative Address Absolute Address Width Access Type Reset Value Description BURSTSIZE 0x00000160 usb0: 0xE0002160 usb1: 0xE0003160 17 bits rw 0x00001010 Burst Size

Register BURSTSIZE Details

This register controls the burst size used during data movement on the initiator/master interface.

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Field Name TXPBURST (TX)

Bits 16:8

Type rw

Reset Value 0x10

Description Programmable TX Burst Length. Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. If field AHBBRST of register SBUSCFG is different from zero, this field TXPBURST will return the value of the INCRx length. Supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_TX_CHAN. Different values will not use all the available buffer space, preventing proper TX endpoint priming in stream disable mode (SDIS bit of USBMODE register set to '1').

RXPBURST (RX)

7:0

rw

0x10

Programmable RX Burst Length. Default is the constant VUSB_HS_RX_BURST. This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. If field AHBBRST of register SBUSCFG is different from zero, this field RXPBRUST will return the value of the INCRx length. The supported values are integer values from 4 to 128. It is recommended to set this value to a integer sub-multiple of VUSB_HS_RX_DEPTH.

Register (usb) TXFILLTUNING

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description TXFILLTUNING TXFILL 0x00000164 usb0: 0xE0002164 usb1: 0xE0003164 22 bits mixed 0x00020000 TxFIFO Fill Tuning

Register TXFILLTUNING Details

The fields in this register control performance tuning associated with how the Controller posts data to the TX latency FIFO before moving the data onto the USB bus.

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Field Name TXFIFOTHRES (BURST)

Bits 21:16

Type rw

Reset Value 0x2

Description FIFO Burst Threshold: This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth, where the FIFO may under run because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set (SDIS).

reserved TXSCHEALTH (HEALTH)

15:13 12:8

ro rw

0x0 0x0

reserved Scheduler Health Counter. This register increments when the Controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. This counter will max. at 31.

reserved TXSCHOH (OVERHEAD)

7 6:0

ro rw

0x0 0x0

RESERVED Scheduler Overhead. This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG(on the go) & SPH(single port host) implementations. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode for OTG & SPH implementations. The time unit represented in this register is always 1.267us for the MPH implementation

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Register (usb) TXTTFILLTUNING

Name Relative Address Absolute Address Width Access Type Reset Value Description TXTTFILLTUNING 0x00000168 usb0: 0xE0002168 usb1: 0xE0003168 13 bits mixed 0x00000000 TT TX latency FIFO

Register TXTTFILLTUNING Details

This register provides a function similar to TXFILLTUNING except there is no equivalent to TXFIFOTHRES because the TT TX latency FIFO is always loaded in a single burst. Even
Field Name TXTTSCHHEALTH reserved TXTTSCHOH Bits 12:8 7:5 4:0 Type rw ro rw Reset Value 0x0 0x0 0x0 Description TT Scheduler Health Counter Same description as TXSCHHEALTH reserved TT Scheduler Overhead Same description as TXSCHOH. The time unit represented in this register is 6.333us.

Register (usb) IC_USB

Name Relative Address Absolute Address Width Access Type Reset Value Description IC_USB 0x0000016C usb0: 0xE000216C usb1: 0xE000316C 32 bits mixed 0x00000000 Low and Fast Speed Control constants

Register IC_USB Details

This register enable and controls the IC_USB FS/LS transceiver.

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Field Name IC8

Bits 31

Type ro

Reset Value 0x0

Description Inter-Chip transceiver enable 8. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC8. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 8 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD8

30:28

ro

0x0

IC7

27

ro

0x0

Inter-Chip transceiver enable 7. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC7. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 7 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD7

26:24

ro

0x0

IC6

23

ro

0x0

Inter-Chip transceiver enable 6. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC6. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 6 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD6

22:20

ro

0x0

IC5

19

ro

0x0

Inter-Chip transceiver enable 5. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC5. Writing a '1' to each bit selects the IC_USB interface for that port.

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Appendix B: Register Details

Field Name IC_VDD5

Bits 18:16

Type ro

Reset Value 0x0

Description Inter-Chip voltage selection 5 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC4

15

ro

0x0

Inter-Chip transceiver enable 4. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC4. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 4 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD4

14:12

ro

0x0

IC3

11

ro

0x0

Inter-Chip transceiver enable 3. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC3. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 3 It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD3

10:8

ro

0x0

IC2

ro

0x0

Inter-Chip transceiver enable 2. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC2. Writing a '1' to each bit selects the IC_USB interface for that port. Inter-Chip voltage selection 2 It selects which voltage is being supplied to the peripheral through each port. This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller.

IC_VDD2

6:4

ro

0x0

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Field Name IC1

Bits 3

Type rw

Reset Value 0x0

Description Inter-Chip transceiver enable 1. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC1. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not a MPH implementation, IC8 to IC2 will be '0' and Read-Only.

IC_VDD1

2:0

rw

0x0

Inter-Chip voltage selection 1 -- Host mode. Select the voltage being supplied to the peripheral: 000: No voltage 001: 1.0V 010: 1.2V 011: 1.5V 100: 1.8V 101: 3.0V 110, 111: reserved The voltage negotiation should happen between enabling port power (PP) in PORTSC1 register and asserting the run/stop bit in USBCMD register. Device Mode: Read-only and equals 000.

Register (usb) ULPI_VIEWPORT

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ULPI_VIEWPORT ULPIVIEW 0x00000170 usb0: 0xE0002170 usb1: 0xE0003170 32 bits mixed 0x00000000 ULPI Viewport

Register ULPI_VIEWPORT Details

The register provides indirect access to the ULPI PHY register set. Although the core performs access to the ULPI PHY register set, there may be extraordinary circumstances where software may need direct access.

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Field Name ULPIWU (WU)

Bits 31

Type rw

Reset Value 0x0

Description ULPI Wake Up Operation. Write: 0: no affect. 1: execute the Wake Up operation (no undoing). Read: 0: operation complete. 1: operation in-progress. Note: Do not issue a ULPI Wake Up and ULPI Read/Write (via Viewport operation) with the same register write.

ULPIRUN (RUN)

30

rw

0x0

ULPI Viewport Transaction. Write: 0: no affect. 1: execute the ULPI viewport transaction (no undoing). Read: 0: transaction complete. 1: transaction in-progress. Note: Do not issue a ULPI Wake Up and Viewport operations with the same register write.

ULPIRW (RW) reserved ULPISS (SS)

29

rw

0x0

ULPI Viewport Read/Write Select. 0: read operation. 1: write operation.

28 27

ro ro

0x0 0x0

reserved ULPI Synchronous State 0: In another state (i.e. carkit, serial, low power). 1: Normal synchronous state. This bit represents the state of the ULPI interface. Before reading this bit, the ULPIPORT field should be set accordingly if used in a MPH implementation.

ULPIPORT ULPIADDR (ADDR) ULPIDATRD (DATRD) ULPIDATWR (DATWR)

26:24 23:16

rw rw

0x0 0x0

Reserved, always write 0. ULPI Data Address. When a read or write operation is commanded, the address of the operation is written to this field. ULPI Data Read. After a read operation completes, the result is placed in this field.

15:8

ro

0x0

7:0

rw

0x0

ULPI Data Write. When a write operation is commanded, the data to be sent is written to this field

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Register (usb) ENDPTNAK

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ENDPTNAK EPNAKISR 0x00000178 usb0: 0xE0002178 usb1: 0xE0003178 32 bits wtc 0x00000000 Endpoint NAK (Device mode)

Register ENDPTNAK Details

Field Name EPTN Bits 31:16 Type wtc Reset Value 0x0 Description TX Endpoint NAK (Device mode). The Endpoint bit is set = 1 when the device controller sends a NAK handshake on a received IN token for the corresponding endpoint. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. EPRN 15:0 wtc 0x0 RX Endpoint NAK (Device mode). The bit is set = 1 when the Controller sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

Register (usb) ENDPTNAKEN

Name Software Name Relative Address Absolute Address Width ENDPTNAKEN EPNAKIER 0x0000017C usb0: 0xE000217C usb1: 0xE000317C 32 bits

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Access Type Reset Value Description

rw 0x00000000 Endpoint NAK (Device mode)

Register ENDPTNAKEN Details

Field Name EPTNE Bits 31:16 Type rw Reset Value 0x0 Description TX Endpoint NAK Enable (Device mode). 0: disable. 1: enable. Each bit is an enable bit for the corresponding TX Endpoint NAK. If NAK is enabled and the corresponding TX Endpoint NAK bit is set, then the NAK Interrupt bit is set. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. EPRNE 15:0 rw 0x0 RX Endpoint NAK Enable (Device mode). 0: disable. 1: enable. Each bit is an enable bit for the corresponding RX Endpoint NAK. If NAK is enabled and the corresponding RX Endpoint NAK bit is set, then the NAK Interrupt bit is set. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

Register (usb) CONFIGFLAG

Name Relative Address Absolute Address Width Access Type Reset Value Description CONFIGFLAG 0x00000180 usb0: 0xE0002180 usb1: 0xE0003180 32 bits ro 0x00000001 reserved

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Register CONFIGFLAG Details

Field Name reserved Bits 31:0 Type ro Reset Value 0x1 reserved Description

Register (usb) PORTSC1

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description PORTSC1 PORTSCR1 0x00000184 usb0: 0xE0002184 usb1: 0xE0003184 32 bits mixed 0x00000000 Port Status & Control

Register PORTSC1 Details

The Controller implement one The number of port registers implemented by a particular instantiation is documented in the HCSPARAM register. Software uses this information as an input parameter to determine how many ports need service. This implement contains only 1 host port.
Field Name PTS Bits 31:30 Type rw Reset Value 0x0 Description PHY Type Status constant (Host/Device). [PTS2] + [PTS] bit fields: 010: ULPI interface. STS 29 ro 0x0 Serial Transceiver Select constant (Host/Device). VUSB_HS_PHY_SERIAL = 0. Serial interface engine (SIE) not implemented. PTW 28 ro 0x0 Parallel Transceiver Width constant (Host/Device). 0: 8-bit (60MHz) UTMI+ interface to ULPI. PSPD (PORTSCR_PSPD) 27:26 rw 0x0 Port Speed operating mode (Host/Device). 00: Full Speed 01: Low Speed 10: High Speed 11: Not connected (default) PTS2 25 rw 0x0 Parallel Transceiver Select MSB (Host/Device). Refer to the [PTS] bit field for a description.

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Field Name PFSC (PORTSCR_PFSC)

Bits 24

Type rw

Reset Value 0x0

Description Port Force Full Speed Connect -- Debug. 0: ???? (default) 1: write a 1 to force the port to only connect at Full Speed. Writing a 1 disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.

PHCD (PORTSCR_PHCD)

23

ro

0x0

PHY Low Power Clock Disable - RW. Default = 0b. Writing this bit to a '1b' will disable the PHY clock. Writing a '0b' enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, the PHY can be put into Low Power Clock Disable when the device is not running (USBCMD RS=0b) or the host has signaled suspend (PORTSCx SUSP=1b). Low Power Clock Disable will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the Controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low Power Clock Disable is completely under the control of software.

WKOC (PORTSCR_WKOC)

22

ro

0x0

Wake on Over-current Enable Writing '1' to this bit enables the port to be sensitive to over-current conditions as wakeup events. This field is zero if Port Power (PP) is '0' or in device mode. This bit is output from the controller as signal pwrctl_wake_ovrcurr_en for use by an external power control circuit. Only used in host mode.

WKDS (PORTSCR_WKDS)

21

rw

0x0

Wake on Disconnect Enable (Host mode). 0: disable 1: enable In device mode, always set = 0.

WKCN (PORTSCR_WKCN)

20

rw

0x0

Wake on Connect Enable (Host mode). 0: disable 1: enable In device mode, always set = 0.

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Field Name PTC (PORTSCR_PTC)

Bits 19:16

Type rw

Reset Value 0x0 Port Test Control.

Description

0000: Normal operation. All others are test modes: 0001: J_STATE 0010: K_STATE 0011: SE0 (host) / NAK (device) 0100: Packet 0101: FORCE_ENABLE_HS 0110: FORCE_ENABLE_FS 0111: FORCE_ENABLE_LS Others: reserved

PIC (PORTSCR_PIC)

15:14

rw

0x0

Port Indicator Control outputs (EHCI) (Host mode). 00: Port indicators are off. 01: Amber (PL output signal EMIOUSBxPORTINDCTL0 is driven High). 10: Green (PL output signal EMIOUSBxPORTINDCTL1 is driven High). 11: undefined. Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used.

PO (PORTSCR_PO) PP (PORTSCR_PP)

13 12

ro rw

0x0 0x0

Port Owner hand off is not implemented. Hardwired to 0. Port Power enable (ECHI) (Host mode). Controls the PL output signal EMIOUSBxVBUSPWRSELECT. 0: disable, driven Low. 1: enable, driven High. This bit represents the current setting of the switch ('0'=off, '1'=on). When power is not available on a port (i.e. [PP] equals to '0'), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and [PPC] is a one, the [PP] bit in each affected port may be transitioned by the controller driver from '1' to '0'(removing power from the port).

LS (PORTSCR_LS)

11:10

ro

0x0

Line State: 00: SE0 01: J-state 10: K-state 11: undefined.

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Field Name HSP (PORTSCR_HSP)

Bits 9

Type ro

Reset Value 0x0

Description High-Speed Port status (Host and Device mode). 0: LS or FS mode 1: HS mode Note: [HSP] is redundant with [PSPD].

PR (PORTSCR_PR)

rw

0x0

Port Reset - RW. Default = 0b. This field is zero if Port Power(PP) is '0'. Host mode: 1=Port is in Reset. 0=Port is not in Reset. Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register

SUSP (PORTSCR_SUSP)

rw

0x0

Suspend Host mode: 1=Port in suspend state. 0=Port not in suspend state. Port Enabled bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0x Disable 10 Enable 11 Suspend Device mode: Read Only. 1=Port in suspend state. 0=Port not in suspend state. In device mode this bit is a read only status bit.

FPR (PORTSCR_FPR) OCC (PORTSCR_OCC)

rw

0x0

Force Port Resume 1= Resume detected/driven on port. 0=No resume (K-state) detected/driven on port.

rw

0x0

Over-current Change This bit gets set to '1' when there is a change to Over-current Active. Software clears this bit by writing a '1' to this bit position. When in host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device mode this bit shall always be '0'.

OCA (PORTSCR_OCA)

ro

0x0

Over-current Active Value Meaning'1b' -> This port currently has an over-current condition.'0b' -> This port does not have an over-current condition. This bit will automatically transition from '1' to '0' when the over current condition is removed. For host mode implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device mode implementations this bit shall always be '0'.

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Field Name PEC (PORTSCR_PEC)

Bits 3

Type wtc

Reset Value 0x0

Description Port Enabled Change If set to '1' indicates a Port Enabled/Disabled status change. Host mode: For the root hub, this bit gets set to a '1' only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a '1' to it. This field is '0' if Port Power(PP) is '0'. Device mode: The device port is always enabled. (This bit will be '0').

PE (PORTSCR_PE)

wtc

0x0

Port Enabled 1 -> Enable 0-> Disable Host mode: Ports can only be enabled by Controller as a part of the reset and enable. Software cannot enable a port by writing a '1' to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the software. This field is '0' if Port Power(PP) is '0' in host mode. Device mode: The device port is always enabled. (This bit will be always '1').

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Field Name CSC (PORTSCR_CSC)

Bits 1

Type wtc

Reset Value 0x0

Description Connect Status Change If set to '1' indicates a change in Current Connect Status (CCS). Host mode: Indicates a change has occurred in the port's Current Connect Status. The Controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a '1' to it. This field is '0' if Port Power(PP) is '0' in host mode. Device mode: This bit is undefined in device mode.

CCS (PORTSCR_CCS)

ro

0x0

Current Connect Status. Host mode: 1 -> Device is present on port. 0 -> No device is present. Device mode: 1 -> Attached. 0 -> Not Attached.

Register (usb) OTGSC

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description OTGSC OTGCSR 0x000001A4 usb0: 0xE00021A4 usb1: 0xE00031A4 32 bits mixed 0x00000020 OTG Status and Control

Register OTGSC Details

The OTGSC register has four sections: * OTG Interrupt enables (Read/Write) * OTG Interrupt status (Read/Write to Clear)

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* OTG Status inputs (Read Only) * OTG Controls (Read/Write) IP Config Note: The Controller implements one On-The-Go (OTG) Status and Control register.
Field Name reserved DPIE (OTGSC_DPIE) 1msE (OTGSC_1MSE) BSEIE (OTGSC_BSEE) BSVIE (OTGSC_BSVIE) ASVIE (OTGSC_ASVIE) AVVIE (OTGSC_AVVIE) IDIE (OTGSC_IDIE) reserved DPIS (OTGSC_DPIS) 23 22 ro wtc 0x0 0x0 24 rw 0x0 25 rw 0x0 26 rw 0x0 27 rw 0x0 28 rw 0x0 29 rw 0x0 Bits 31 30 Type ro rw Reset Value 0x0 0x0 reserved Data Pulse Interrupt Enable. 0: disable. 1: enable usb.OTGSC [DPIS] interrupt. 1 ms Timer Interrupt Enable. 0: disable. 1: enable usb.OTGSC [1msS] interrupt. B Session End Interrupt Enable. 0: disable. 1: enable usb.OTGSC [BSEIS] interrupt. B Session Valid Interrupt Enable. 0: disable. 1: enable usb.OTGSC [BSVIS] interrupt. A Session Valid Interrupt Enable. 0: disable. 1: enable usb.OTGSC [ASVIS] interrupt. Interrupt Enable. 0: disable. 1: enable usb.OTGSC [AVVIS] interrupt. USB ID Interrupt Enable. 0: disable. 1: enable usb.OTGSC [IDIS] interrupt. reserved Data Pulse Interrupt Status. 0: no pulses detected. 1: pulses detected. Write 1 to clear bit. The pulses being detected can be on DP or DM. Data bus pulsing is only detected when usb.USBMODE [CM] = 11 (Host mode) and usb.PORTSC0 [PP] = 0 (off). Non-latched status can be read using the [DPS] bit. 1msS (OTGSC_1MSS) 21 wtc 0x0 1 millisecond Timer Interrupt Status. 0: no timer alert. 1: timer alert. Write 1 to clear bit. The hardware sets this bit every 1 milliseconds (based on a timer using 60 MHz ULPI). Description

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Field Name BSEIS (OTGSC_BSEIS)

Bits 20

Type wtc

Reset Value 0x0

Description B Session End Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has fallen below the B session end threshold.

BSVIS (OTGSC_BSVIS)

19

wtc

0x0

B Session Valid Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC).

ASVIS (OTGSC_ASVIS)

18

wtc

0x0

A Session Valid Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC).

AVVIS (OTGSC_AVVIS)

17

wtc

0x0

A Session End Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has either risen above or fallen below the VBus valid threshold (4.4 VDC) on an A device.

IDIS (OTGSC_IDIS)

16

wtc

0x0

USB ID Interrupt Status. 0: no interrupt latched 1: interrupt detected. Write 1 to clear this bit. This bit is set when a change on the ID input has been detected.

reserved DPS (OTGSC_DPS)

15 14

ro ro

0x0 0x0

reserved Data Bus Pulsing Status, read-only. 0: no pulses being detected. 1: pulses are being detected. Note: refer to the [DPSI] bit for more information.

1msT (OTGSC_1MST)

13

ro

0x0

1 ms Timer High-Low Toggle, read-only. Software will usually read a 0. This bit toggles high-low every millisecond to set the [1msS] bit.

BSE (OTGSC_BSE)

12

ro

0x0

B Session End Status, read-only. 0: Vbus not below threshold. 1: Vbus below threshold.

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Field Name BSV (OTGSC_BSV) ASV (OTGSC_ASV) AVV (OTGSC_AVV) ID (OTGSC_ID) HABA (OTGSC_HABA)

Bits 11

Type ro

Reset Value 0x0 B Session Valid

Description

Indicates VBus is above the B session valid threshold. 10 ro 0x0 A Session Valid Indicates VBus is above the A session valid threshold. 9 ro 0x0 A VBus Valid. Indicates VBus is above the A VBus valid threshold. 8 7 ro rw 0x0 0x0 USB ID'0' = A device, '1' = B device. Hardware assisted B-Disconnect to A-connect. 0: disabled. 1: enable automatic B-Disconnect to A-Connect sequence.

HADP (OTGSC_HADP) IDPU (OTGSC_IDPU) DP (OTGSC_DP)

rw

0x0

Hardware assisted Data-Pulse 0: disable 1: hardware assisted data pulsing sequence starts.

rw

0x1

ID Pullup. Control the ID Pullup resistor. 0: off (the ID input will not be sampled). 1: on.

rw

0x0

Data Pulsing enable. 0: 1: pullup on DP is asserted for data pulsing during SRP.

OT (OTGSC_OT)

rw

0x0

OTG Termination 0: 1: This bit must be set when the Controller is in device mode. It controls the pulldown on DM.

HAAR (OTGSC_HAAR) VC (OTGSC_VC) VD (OTGSC_VD)

2 1

rw rw

0x0 0x0

Hardware Assist Auto-Reset'0' = Disabled, '1' = Enable automatic reset after connect on host port. VBUS Charge Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP.

rw

0x0

VBUS Discharge. Setting this bit causes VBus to discharge through a resistor.

Register (usb) USBMODE

Name USBMODE

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

MODE 0x000001A8 usb0: 0xE00021A8 usb1: 0xE00031A8 32 bits mixed 0x00000000 USB Mode Selection

Register USBMODE Details

Field Name SRT reserved VBPS Bits 15 14:6 5 Type rw ro rw Reset Value 0x0 0x0 0x0 Description Reseverd, set = 0. (Shorten Reset Time) reserved Vbus Power Select'0' -> Output is '0''1' -> Output is '1'This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available. Only used in host mode. SDIS 4 rw 0x0 Stream Disable Mode'0' -> Inactive'1' -> Active Device mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. Host Mode: Setting to a '1' ensures that overruns/under runs of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. SLOM 3 rw 0x0 Setup Lockout Mode This bit controls behavior of the setup lock mechanism.'0' -> Setup Lockouts On.'1' -> Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD). Only used in device mode

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Field Name ES CM

Bits 2 1:0

Type ro rw

Reset Value 0x0 0x0

Description Reseverd, set = 0. (Endian Select) Controller Mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability (OTG), the Controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RST bit in the USBCMD register before reprogramming this register.'00b' -> Idle (Default for combination host/device).'01b' -> Reserved.'10b' -> Controller in device mode (Default for device only controller).'11b' -> Controller in host mode (Default for host only controller).

Register (usb) ENDPTSETUPSTAT

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ENDPTSETUPSTAT EPSTAT 0x000001AC usb0: 0xE00021AC usb1: 0xE00031AC 16 bits wtc 0x00000000 Endpoint Status Setup (Device mode)

Register ENDPTSETUPSTAT Details

Field Name ENDPTSETUPSTAT Bits 15:0 Type wtc Reset Value 0x0 Description Setup Endpoint Status (Device mode). When a Setup transaction is received, the corresponding bit is set = 1. Software reads the setup data from the Queue Head and then writes a 1 to clear the status bit. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Other bits: reserved.

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Register (usb) ENDPTPRIME

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ENDPTPRIME EPPRIME 0x000001B0 usb0: 0xE00021B0 usb1: 0xE00031B0 32 bits wtc 0x00000000 Endpoint Primer (Device mode)

Register ENDPTPRIME Details

For each endpoint a corresponding bit is used to request that a buffer be prepared for an operation in order to respond to a USB transaction. Software writes a 1 to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for the new transfer descriptor. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated.
Field Name PETB Bits 31:16 Type wtc Reset Value 0x0 Description Prime Endpoint TxBuffer (Device mode). Write a 1 to the corresponding bit to request TxBuffer to respond to a USB IN/INTERRUPT transaction. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. PERB 15:0 wtc 0x0 Prime Endpoint RxBuffer (Device mode). Write a 1 to the corresponding bit to request RxBuffer to respond to a USB OUT transaction. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

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Register (usb) ENDPTFLUSH

Name Software Name Relative Address Absolute Address Width Access Type Reset Value Description ENDPTFLUSH EPFLUSH 0x000001B4 usb0: 0xE00021B4 usb1: 0xE00031B4 32 bits wtc 0x00000000 Endpoint Flush (Device mode)

Register ENDPTFLUSH Details

The Flush operation of an endpoint will clear the usb.ENDPTSTAT bit and reset the RX/TX data buffer. Ready status of that endpoint and re-align the Latency Buffer pointers, but not clear the actual data that resides in the Latency Buffers. Write a 1 to a bit(s) to cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
Field Name FETB Bits 31:16 Type wtc Reset Value 0x0 Description Flush Endpoint TxBuffer (Device mode). Write a 1 to the corresponding bit to flush the TxBuffer. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. FERB 15:0 wtc 0x0 Flush Endpoint RxBuffer (Device mode). Write a 1 to the corresponding bit to flush the RxBuffer. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

Register (usb) ENDPTSTAT

Name ENDPTSTAT

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

EPRDY 0x000001B8 usb0: 0xE00021B8 usb1: 0xE00031B8 32 bits ro 0x00000000 Endpoint Buffer Ready Status (Device mode), RO

Register ENDPTSTAT Details

For each endpoint, there is one buffer ready status (ENDPTSTAT) bit for the TX buffer and one bit for RX buffer. An ENDPTSTAT bit is set to a 1 by the hardware in a response to receiving an EP prime command (write 1 to usb.ENDPTPRIME regsiter). There will always be a delay between writing a 1 to a usb.ENDPTPRIME register bit and the ENDPTSTAT bit asserting to indicate ready. This delay time varies based upon the current USB traffic and the number of bits in the usb.ENDPTPRIME register that transition from 0 to 1. An ENDPTSTAT bit is cleared in one of three ways: by a USB reset, by the DMA engine hardware, or by a flush command using the usb.ENDPTFLUSH register. Note: The ENDPTSTAT bit will be momentarily read = 0 during the time the hardware is retiring a dTD and updating the dQH transfer descriptors.
Field Name ETBR Bits 31:16 Type ro Reset Value 0x0 Description TxBuffer ready status (Device mode), read-only. 0: cleared by reset, DMA, or ENDPTFLUSH. 1: ENDPTPRIME command received. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. ERBR 15:0 ro 0x0 RxBuffer ready status (Device mode), read-only. 0: cleared by reset, DMA, or ENDPTFLUSH. 1: ENDPTPRIME command received. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

Register (usb) ENDPTCOMPLETE

Name ENDPTCOMPLETE

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Software Name Relative Address Absolute Address Width Access Type Reset Value Description

EPCOMPL 0x000001BC usb0: 0xE00021BC usb1: 0xE00031BC 32 bits rw 0x00000000 Endpoint Tx Complete (Device mode)

Register ENDPTCOMPLETE Details

Each bit indicates an event (Transmit/Receive) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a 1 will clear the corresponding bit in this register.
Field Name ETCE Bits 31:16 Type rw Reset Value 0x0 Description Endpoint Transmit Complete Event (Device mode), read-only. 0: not completed. 1: completed. Write a 1 to clear. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12. Bits[31:29]: reserved. ERCE 15:0 rw 0x0 Endpoint Receive Complete Event (Device mode), read-only. 0: not completed. 1: completed. Write a 1 to clear. Bit[0]: Endpoint 0. Bit[1]: Endpoint 1. ... Bit[12]: Endpoint 12. Bits[15:13]: reserved.

Register (usb) ENDPTCTRL0

Name Software Name Relative Address ENDPTCTRL0 EPCR0 0x000001C0

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Absolute Address Width Access Type Reset Value Description

usb0: 0xE00021C0 usb1: 0xE00031C0 24 bits mixed 0x00800080 Endpoint 0 (Device mode)

Register ENDPTCTRL0 Details

Every device controller implements Endpoint 0 as a control endpoint. Rx and Tx Endpoint Stall bits [0] and [16]: Software can write a one to a stall bit to force the endpoint to return a STALL handshake to the Host. The device controller will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, the stall bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the software will observe this delay. However, should the software observe that the stall bit is not set after writing a 1 to it then follow this procedure: continually write this stall bit until it is set or until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit.
Field Name TXE (EPCR_TXE) reserved TXT (EPCR_TXT_INTR) reserved TXS (EPCR_TXS) 17 16 ro rw 0x0 0x0 22:20 19:18 ro ro 0x0 0x0 Bits 23 Type ro Reset Value 0x1 Description Transmit Endpoint Enable, read-only. 1: EP 0 is always enabled. reserved TX Endpoint Type, read-only. 00: EP 0 is always a control endpoint. reserved TX Endpoint Stall, read-only. 0: Normal operation. 1: Force Stall handshake. Note: refer to the register description for more description. reserved RXE (EPCR_RXE) reserved RXT (EPCR_RXT_INTR) 6:4 3:2 ro ro 0x0 0x0 15:8 7 ro ro 0x0 0x1 reserved RX Endpoint Enable, read-only. 1: EP 0 is always enabled. reserved RX Endpoint Type, read-only. 00: EP0 is always a control endpoint.

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Field Name reserved RXS (EPCR_RXS)

Bits 1 0

Type ro rw

Reset Value 0x0 0x0 reserved

Description

RX Endpoint Stall. 0: Normal operation. 1: Force Stall handshake. Note: refer to the register description for more description.

Register (usb) ENDPTCTRL1

Name Relative Address Absolute Address Width Access Type Reset Value Description ENDPTCTRL1 0x000001C4 usb0: 0xE00021C4 usb1: 0xE00031C4 24 bits mixed 0x00000000 Endpoints 1 to 11 (Device mode)

Note: This register is the first in an array of 11 identical registers listed in the table below. The details provided in this section apply to the entire array.
Name ENDPTCTRL1 ENDPTCTRL2 ENDPTCTRL3 ENDPTCTRL4 ENDPTCTRL5 ENDPTCTRL6 ENDPTCTRL7 ENDPTCTRL8 ENDPTCTRL9 ENDPTCTRL10 ENDPTCTRL11 Address 0xe00021c4 0xe00021c8 0xe00021cc 0xe00021d0 0xe00021d4 0xe00021d8 0xe00021dc 0xe00021e0 0xe00021e4 0xe00021e8 0xe00021ec

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Register ENDPTCTRL1 to ENDPTCTRL11 Details

Field Name TXE Bits 23 Type rw Reset Value 0x0 Description TX Endpoint Enable. 0: disable. 1: enable. Enable an Endpoing after it has been configured. TXR 22 rw 0x0 TX Data Toggle Reset. Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device. TXI 21 ro 0x0 TX Data Toggle Inhibit. (testing) 0: PID Sequencing enabled 1: PID Sequencing disabled reserved TXT 20 19:18 ro rw 0x0 0x0 reserved TX Endpoint Type control. 00: Control 01: Isochronous 10: Bulk 11: Interrupt TXD 17 rw 0x0 TX Endpoint Data datapath. 0: dual-port memory buffer with a DMA Engine. Always write a 0. TXS 16 rw 0x0 TX Endpoint Stall. 0: Normal operation. 1: Force Stall handshake. Note: refer to the ENDPTCTRL 0 register description for more description. reserved RXE 15:8 7 ro rw 0x0 0x0 reserved RX Endpoint Enable 0: Disable 1: Enable Enable an Endpoing after it has been configured. RXR 6 rw 0x0 RX Data Toggle Reset. Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device. RXI 5 rw 0x0 RX Data Toggle Inhibit. 0: PID Sequencing enabled 1: PID Sequencing disabled

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Field Name reserved RXT

Bits 4 3:2

Type rw rw

Reset Value 0x0 0x0 reserved

Description

RX Endpoint Type. 00: Control 01: Isochronous 10: Bulk 11: Interrupt

RXD

rw

0x0

RX Endpoint Data datapath. 0: dual-port memory buffer with a DMA Engine. Always write a 0.

RXS

rw

0x0

RX Endpoint Stall. 0: Normal operation. 1: Force Stall handshake. Note: refer to the ENDPTCTRL 0 register description for more description.

Access Types Legend

Access Type clronrd clronwr nsnsro nsnsrw nsnswo nssraz raz ro rs rud rw rwso sro srw swo w0c w0crs w0s Readable, clears value on read Readable, clears value on write During non-secure access, if thread is non-secure, it is read only During non-secure access, if thread is non-secure, it is read write During non-secure access, if thread is non-secure, it is write only During non-secure access, if thread is secure, it is read as zero Read as zero Read-only w: no effect, r: sets all bits Read undefined Normal read/write Read/write, set only During secure access, it is read only During secure access, it is read write During secure access, it is write only w: 1/0 no effect on/clears matching bit, r: no effect w: 1/0 no effect on/clears matching bit, r: sets all bits w: 1/0 no effect on/sets matching bit, r: no effect Description

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Access Type w0src w0t w1 w1crs w1src w1t waz wcrs wo wo1 woc wos wrc wrs ws wsrc wtc z

Description w: 1/0 no effect on/sets matching bit, r: clears all bits w: 1/0 no effect on/toggles matching bit, r: no effect w: first one after ~hard~ reset is as-is, other w have no effects, r: no effect w: 1/0 clears/no effect on matching bit, r: sets all bits w: 1/0 sets/no effect on matching bit, r: clears all bits w: 1/0 toggles/no effect on matching bit, r: no effect Write as zero w: clears all bits, r: sets all bits Write-only w: first one after ~hard~ reset is as-is, other w have no effects, r: error w: clears all bits, r: error w: sets all bits, r: error w: as-is, r: clears all bits w: as-is, r: sets all bits w: sets all bits, r: no effect w: sets all bits, r: clears all bits Readable, write a 1 to clear Access (read or write) as zero

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