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Assignment No.1 Que-Explain in Detail With Flow Diagram Complete Extraction Flow in ASIC Ans

Parasitic extraction is crucial for accurate timing analysis as process geometries shrink below 0.35 microns. Resistance can be estimated using algorithms like square counting but capacitance extraction requires considering neighboring conductors for electromagnetic coupling effects. Parasitic extraction occurs after layout and clock tree insertion in the design flow. The output is a detailed standard parasitic format used for delay calculation and timing analysis.

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48 views

Assignment No.1 Que-Explain in Detail With Flow Diagram Complete Extraction Flow in ASIC Ans

Parasitic extraction is crucial for accurate timing analysis as process geometries shrink below 0.35 microns. Resistance can be estimated using algorithms like square counting but capacitance extraction requires considering neighboring conductors for electromagnetic coupling effects. Parasitic extraction occurs after layout and clock tree insertion in the design flow. The output is a detailed standard parasitic format used for delay calculation and timing analysis.

Uploaded by

humtum_shri5736
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Assignment No.1 QueExplain in detail with flow diagram complete extraction flow in ASIC Ans.

Parasitic Extraction Accurate extraction of on-chip parasitic is crucial due to shrinking size and increasing contribution of interconnects delay. The parasitic consist of Resistance(R), Inductance (L) and Capacitance(C). Inductance is not critical for signal propagation until transmission line effect occurs. Resistance is easy to compute using algorithms like square counting and 2D finite-difference approach. Another reason for easy resistance estimation is that one has to consider only one conductor trace at a time. On the other hand capacitance extraction requires that neighborhood conductors be considered for electromagnetic coupling effect.
Netlist (from synthesis)

Placement & Route Rule File (generated from process specific data) Routed Design Parasitic Extraction Detailed std. Parasitic Formate (DSPF/RSPF)

Delay Calculator

Standard Delay Formate (SDF)

Verification

Static Timing Analysis

Gate Level Simulation

Parasitic Extraction Flow

As design get larger and process geometries smaller than 0.35 micron, the impact of wire resistance and capacitance on the overall delay becomes significant. Hence, techniques are required to accurately model both the resistance & capacitance (also called parasitic) in a design. In the design flow, extraction of parasitic follows the layout & clock tree insertion steps. The output from parasitic extraction known as Detailed Standard Parasitic Format (DSPF) is fed to a delay calculator, which in turn drives the timing analysis process (both static timing and gate level simulation) as shown in figure. Hence, accurate extraction of parasitic is critical to delay calculation and hence to timing analysis Automation tools for layout parameter extraction are Cadence Dracula, Diva, and Vampire, Avanti's Star-RC, and Mentor's xCalibre and ICextract for complete resistance and capacitance extraction.

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