1.

BASIC GATES AND OR NOR NAND

module gates_1(a,b,yand,yor,ynor,ynand);
input a,b;
output yand,yor,ynor,ynand;
and X1(yand,a,b);
or X2(yor,a,b);
nor X3(ynor,a,b);
nand X4(ynand,a,b);
endmodule

//TEST BENCH
module gates_1_tst();
reg a,b;
wire yand,yor;
gates_1 m1(a,b,yand,yor,ynor,ynand);
initial
begin
a = 1'b0;
b=1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b1;
b = 1'b1;
#100 $stop;
end
endmodule

2.BASIC GATES XOR XNOR NOT

module gates_2(a,b,yxor,yxnor,ynot);
input a,b;
output yxor,yxnor,ynot;
not X1(ynot,a);
xor X2(yxor,a,b);
xnor X3(yxnor,a,b);
endmodule

//TEST BENCH
module gates_2_tst();
reg a,b;
wire yxor,yxnor,ynot;
gates_2 m1(a,b,yxor,yxnor,ynot);
initial
begin
#10 a = 1'b0;
b=1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b1;
b = 1'b1;
end
endmodule

3.BCD TO GRAY CODE CONVERTER

module BCD2GRAY(in,out);
input [3:0]in;
output [3:0]out;
assign out[0] = (in[0] ^ in[1]);
assign out[1] = (in[1] ^ in[2]);
assign out[2] = (in[2] ^ in[3]);
assign out[3] = in[3];
endmodule

//TEST BENCH
module BCD2GRAYtst ();
wire [3:0]out;
reg [3:0]in;
BCD2GRAY m1(in,out);
initial #1200 $finish;
initial
begin
#20 in = 0;
#20 in = 1;
#20 in = 2;
#20 in = 3;
#20 in = 4;
#20 in = 5;
#20 in = 6;
#20 in = 7;
#20 in = 8;
#20 in = 9;
end
endmodule

4.BCD TO 7 SEGMENT
module bcd_to_7seg(in,out);
input [3:0]in;
output reg [6:0]out;
always@(in)
begin
case(in)
4'd0:out=7'b1111110;
4'd1:out=7'b0110000;
4'd2:out=7'b1101101;
4'd3:out=7'b1111001;
4'd4:out=7'b0110011;
4'd5:out=7'b1011011;
4'd6:out=7'b1011111;
4'd7:out=7'b1110000;
4'd8:out=7'b1111111;
4'd9:out=7'b1111011;
default: out=7'b0;
endcase
end

OUTPUT={a,b,c,d,e,f,g}(7segments)

//TEST BENCH
module bcd_to_7segtst ();
wire [6:0]out;
reg [3:0]in;
bcd_to_7seg m1(in,out);
initial #1200 $finish;
initial
begin
in = 0;
#20 in = 1;
#20 in = 2;
#20 in = 3;
#20 in = 4;
#20 in = 5;
#20 in = 6;
#20 in = 7;
#20 in = 8;
#20 in = 9;
end
endmodule

5.BCD TO DECIMAL DECODER

module bcd_to_decimal(in,out);
input [3:0]in;
output reg [9:0]out;
always@(in)
begin
case(in)
4'b0000:out=10'b0000000000;
4'b0001:out=10'b0000000001;
4'b0010:out=10'b0000000010;
4'b0011:out=10'b0000000100;
4'b0100:out=10'b0000001000;
4'b0101:out=10'b0000010000;
4'b0110:out=10'b0000100000;
4'b0111:out=10'b0001000000;
4'b1000:out=10'b0010000000;
4'b1001:out=10'b0100000000;
default: out=4'bx;
endcase
end
endmodule

module bcd_to_decimaltst ();

wire [9:0]out;
reg [3:0]in;
bcd_to_decimal m1(in,out);
initial #1200 $finish;
initial
begin
#00 in = 0;
#20 in = 1;
#20 in = 2;
#20 in = 3;
#20 in = 4;
#20 in = 5;
#20 in = 6;
#20 in = 7;
#20 in = 8;
#20 in = 9;
end
endmodule

6.MAGNITUDE COMPARATOR 4-BIT

module comp(a_les_b,a_great_b,a_equal_b,
a, b);
output a_les_b, a_great_b, a_equal_b ;
input [3:0] a, b ;
assign a_les_b = (a<b);
assign a_great_b = (a>b );
assign a_equal_b = (a==b);
endmodule

//test bench
module comptst();
reg [3:0]a, b;
wire a_les_b,a_great_b,a_equal_b;
comp tst(a_les_b,a_great_b,a_equal_b, a, b);
initial
begin
a = 0;
b = 0;
end
initial
begin
#150 a = 4'b0111;
#150 b = 4'b1111;
#150 a = 4'b0111;
end
endmodule

7.COMPLEX FUNCTION USING MUX

/complex function using mux

//y = f(a,b,c) = {1,2,6,7}
module complex_fun(a,b,c,y);
input a,b,c;
output y;
mux4_1 m1(y,c,~c,0,1,b,a);
endmodule

//TEST BENCH
module complex_funtst();
reg a,b,c;
wire y ;
complex_fun tst(a,b,c,y);
initial
begin
{a,b,c} = 3'b000;
#100 {a,b,c} = 3'b001;
#100 {a,b,c} = 3'b010;
#100 {a,b,c} = 3'b011;
#100 {a,b,c} = 3'b100;
#100 {a,b,c} = 3'b101;
#100 {a,b,c} = 3'b110;
#100 {a,b,c} = 3'b111;
#100 $stop;
end
endmodule

8.DECODER 2 TO 4
module decoder2_4(in,en,out);
input [1:0]in;
input en;
output [3:0]out;
assign out[0] =(~in[0])&(~in[1])&en;
assign out[1] =(in[0])&(~in[1])&en;
assign out[2] =(~in[0])&(in[1])&en;
assign out[3] =(in[0])&(in[1])&en;
endmodule

//TEST BENCH
module decoder2_4tst() ;
reg [1:0]in;
reg en;
wire [3:0]out ;
decoder2_4 tst(in,en,out);
initial
begin
in = 2'b00;
en = 0;
#100 en = 1'b1;
#100 in = 2'b00;
#100 in = 2'b01;
#100 in = 2'b10;
#100 in = 2'b11;
#200 en = 1'b0;
end
endmodule

9.DECODER 3 TO 8
module decoder3_8(in,en,out);
input [2:0]in;
input en;
output [7:0]out;
assign out[0] =(~in[0])&(~in[1])&(~in[2])&en;
assign out[1] =(in[0])&(~in[1])&(~in[2])&en;
assign out[2] =(~in[0])&(in[1])&(~in[2])&en;
assign out[3] =(in[0])&(in[1])&(~in[2])&en;
assign out[4] =(~in[0])&(~in[1])&(in[2])&en;
assign out[5] =(in[0])&(~in[1])&(in[2])&en;
assign out[6] =(~in[0])&(in[1])&(in[2])&en;
assign out[7] =(in[0])&(in[1])&(in[2])&en;
endmodule

//TEST BENCH
module decoder3_8tst() ;
reg [2:0]in;
reg en;
wire [7:0]out ;
decoder3_8 tst(in,en,out);
initial
begin
in = 3'b000;
en = 0;
#100 en = 1'b1;
#100 in = 3'b000;
#100 in = 3'b001;
#100 in = 3'b010;
#100 in = 3'b011;
#100 in = 3'b100;
#100 in = 3'b101;
#100 in = 3'b110;
#100 in = 3'b111;
#200 en = 1'b0;
end
endmodule

10.DEMUX 4 TO 1
//4_to_1demux using 2_4decoder
module demux4_1(in,sel,y);
input in;
input [1:0]sel;
output [3:0]y;
decoder2_4 m1(sel,in,y);
endmodule

//TEST BENCH
module demux4_1tst();
reg [1:0]sel;
reg in;
wire [3:0]y ;
demux4_1 tst(in,sel,y);
initial
begin
sel = 2'b00;
#100 in = 1'b1;
#100 sel = 2'b00;
#100 sel = 2'b01;
#100 sel = 2'b10;
#100 sel = 2'b11;
#200 in = 1'b0;
end
endmodule

11.EXCESS3 TO DECIMAL CODE CONVERTER

module xs3_to_decimal(in,out);
input [3:0]in;
output [3:0]out;
assign out = in - 4'b0011;
endmodule

//TEST BENCH
module xs3_to_decimaltst();
wire [3:0]out;
reg [3:0]in;
xs3_to_decimal m1(in,out);
initial
begin
#50 in = 4'b0011;
#50 in = 4'b0100;
#50 in = 4'b0101;
#50 in = 4'b0110;
#50 in = 4'b0111;
#50 in = 4'b1000;
#50 in = 4'b1001;
#50 in = 4'b1010;
#50 in = 4'b1011;
#50 in = 4'b1100;
end
endmodule

12.FULL ADDER 4BIT

module FA_4bit(a,b,c_in,s,c_out);
input [3:0]a,b;
input c_in;
output [3:0]s;
output c_out;
assign {c_out,s} = a+b+c_in;
endmodule

//TEST BENCH
module FA_4bittst();
reg [3:0]a,b;
reg c_in;
wire [3:0]s;
wire c_out;
FA_4bit tst(a,b,c_in,s,c_out);
initial
begin
a = 0;b = 0;c_in = 0;
#100 a = 4'b0010;
#100 b = 4'b1010;
#100 a = 4'b0000;
#100 a = 4'b1001;b = 4'b0111;
end
endmodule

13.FULL ADDER
module FA(a,b,c,s,c_out);
input a,b,c;
output s,c_out;
assign {c_out,s} = a+b+c;
endmodule

//TEST BENCH
module FA_tst();
reg a,b,c;
wire s,c_out;
FA tst(a,b,c,s,c_out);
initial
begin
a = 0;b = 0;c = 0;
#100 a = 0;b = 0;c = 1;
#100 a = 0;b = 1;c = 0;
#100 a = 0;b = 1;c = 1;
#100 a = 1;b = 0;c = 0;
#100 a = 1;b = 0;c = 1;
#100 a = 1;b = 1;c = 0;
#100 a = 1;b = 1;c = 1;
end
endmodule

14.GRAY TO BINARY CODE CONVERTER

module GRAY2BINARY(in,out);
input [3:0]in;
output [3:0]out;
assign out[3] = in[3];
assign out[2] = (in[2] ^ out[3]);
assign out[1] = (in[1] ^ out[2]);
assign out[0] = (in[0] ^ out[1]);
endmodule

//test bench
module grey_to_binarytst ();
wire [3:0]out;
reg [3:0]in;
GRAY2BINARY m1(in,out);
initial
begin
#50 in = 4'b0000;
#50 in = 4'b0001;
#50 in = 4'b0011;
#50 in = 4'b0010;
#50 in = 4'b0110;
#50 in = 4'b0111;
#50 in = 4'b0101;
#50 in = 4'b0100;
#50 in = 4'b1100;
#50 in = 4'b1101;
end
endmodule

15.HALF ADDER
module HA(a,b,s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

//TEST BENCH
module HA_tst();
reg a,b;
wire s,c;
HA tst(a,b,s,c);
initial
begin
# a = 1'b0;
b=1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b1;
b = 1'b1;
end
endmodule

16.JOHNSON COUNTER
module johnson_counter(rst,clk,qout);
parameter N = 4;
input clk, rst;
output reg [0:N-1]qout;
always @(posedge clk or posedge rst)
if (rst) qout <= {N{1'b0}};
else qout <= {~qout[N-1],qout[0:N-2]};
endmodule

//TEST BENCH
module johnson_countertst();
parameter N = 4;
reg clk, rst;
wire [0:N-1]qout;
johnson_counter tst(rst,clk,qout);
initial clk = 0;
always #20 clk = ~clk;
initial
begin
rst = 1;
#100 rst = 0;
#500 rst = 1;
#100 $stop;
end
endmodule

17.modulo 10 COUNTER

module modulo10_sync_counter(clk, en, rst,

qout);
parameter N = 4;
input clk, en, rst;
output reg [N-1:0]qout;
always @(posedge clk)
if (rst) qout <= {N{1'b0}};
else
begin
if (en)begin
if (qout==4'd9) qout <= 0;
else qout <= qout + 1;
end
end
endmodule

//TEST BENCH
module modulo10_sync_countertst();
parameter N = 4;
reg clk, en, rst;
wire [N-1:0]qout;
modulo10_sync_counter tst(clk, en, rst, qout);
initial clk = 0;
always #10 clk = ~clk;
initial
begin
rst = 1;
#40 rst = 0;en = 1;
#300 rst = 1;
#200 $stop;
end
endmodule

18.MUX 2_1
module mux2_1(y,a, b, sel) ;
input a, b, sel;
output y ;
wire w1, w2, w3;
and a1 (w2, a, w1);
and a2 (w3, b, sel);
not n1( w1, sel);
or o1 (y, w2, w3);
endmodule

//TEST BENCH
module mux2_1tst() ;
reg a, b, sel;
wire y ;
mux2_1 tst(y,a,b,sel) ;
initial
begin
a = 1'b0;
b = 1'b1;
sel = 0;
#100 sel = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 sel = 1'b0;
end
endmodule

19.MUX 4_1
module mux4_1(y,a,b,c,d,sel0,sel1);
input a,b,c,d,sel0,sel1;
output y;
wire w1,w2;
mux2_1 m1(w1,a,b,sel0);
mux2_1 m2(w2,c,d,sel0);
mux2_1 m3(y,w1,w2,sel1);
endmodule

module mux4_1tst() ;
reg a, b,c,d,sel0,sel1;
wire y ;
mux4_1 tst(y,a,b,c,d,sel0,sel1) ;
initial
begin
a = 1'b0;b = 1'b1;c=1'b1;d=1'b1;
sel0 = 1'b0;sel1 = 1'b0;
#100 a = 1'b1;
#100 sel0 = 1'b1;b = 1'b0;
#100 b = 1'b1;
#100 sel0 = 1'b0;sel1 = 1'b1;c=1'b0;
#100 c = 1'b1;
#100 sel0 = 1'b1;d = 1'b0;
#100 d = 1'b1;
#300 $stop;
end
endmodule

20.MUX 8_1
module mux8_1(y,in,sel);
input [7:0]in;
input [2:0]sel;
output y;
wire w1,w2;
mux4_1
m1(w1,in[0],in[1],in[2],in[3],sel[0],sel[1]);
mux4_1
m2(w2,in[4],in[5],in[6],in[7],sel[0],sel[1]);
assign y = ((~sel[2])&w1)+sel[2]&w2;
endmodule

module mux8_1tst();
reg [7:0]in;
reg [2:0]sel;
wire y ;
mux8_1 tst(y,in,sel);
initial
begin
in = 8'b11111110;sel = 3'b000;
#100 in[0] = 1'b1;
#100 sel = 3'b001;in[1] = 1'b0;
#100 in[1] = 1'b1;
#100 sel = 3'b010;in[2] = 1'b0;
#100 in[2] = 1'b1;
#100 sel = 3'b011;in[3] = 1'b0;
#100 in[3] = 1'b1;
#100 sel = 3'b100;in[4] = 1'b0;
#100 in[4] = 1'b1;
#100 sel = 3'b101;in[5] = 1'b0;
#100 in[5] = 1'b1;
#100 sel = 3'b110;in[6] = 1'b0;
#100 in[6] = 1'b1;
#100 sel = 3'b111;in[7] = 1'b0;
#100 in[7] = 1'b1;
#300 $stop;
end
endmodule

21.MUX 16_1
module mux16_1(y,in,sel);
input [15:0]in;
input [3:0]sel;
output y;
wire w1,w2,w3,w4;
mux4_1
m1(w1,in[0],in[1],in[2],in[3],sel[0],sel[1]);
mux4_1
m2(w2,in[4],in[5],in[6],in[7],sel[0],sel[1]);
mux4_1
m3(w3,in[8],in[9],in[10],in[11],sel[0],sel[1]);
mux4_1
m4(w4,in[12],in[13],in[14],in[15],sel[0],sel[1])
;
mux4_1 m5(y,w1,w2,w3,w4,sel[2],sel[3]);
endmodule

//TEST BENCH
module mux16_1tst();
reg [15:0]in;
reg [3:0]sel;
wire y ;
mux16_1 tst(y,in,sel);
initial
begin
in = 16'hffff;sel = 4'b0000;
#100 in[0] = 1'b1;
#100 sel = 4'b0001;in[1] = 1'b0;
#100 in[1] = 1'b1;
#100 sel = 4'b0010;in[2] = 1'b0;
#100 in[2] = 1'b1;
#100 sel = 4'b0011;in[3] = 1'b0;
#100 in[3] = 1'b1;
#100 sel = 4'b0100;in[4] = 1'b0;
#100 in[4] = 1'b1;
#100 sel = 4'b0101;in[5] = 1'b0;
#100 in[5] = 1'b1;
#100 sel = 4'b0110;in[6] = 1'b0;
#100 in[6] = 1'b1;
#100 sel = 4'b0111;in[7] = 1'b0;
#100 in[7] = 1'b1;
#100 sel = 4'b1000;in[8] = 1'b0;
#100 in[8] = 1'b1;
#100 sel = 4'b1001;in[9] = 1'b0;
#100 in[9] = 1'b1;
#100 sel = 4'b1010;in[10] = 1'b0;
#100 in[10] = 1'b1;
#100 sel = 4'b1011;in[11] = 1'b0;
#100 in[11] = 1'b1;
#100 sel = 4'b1100;in[12] = 1'b0;
#100 in[12] = 1'b1;
#100 sel = 4'b1101;in[13] = 1'b0;
#100 in[13] = 1'b1;
#100 sel = 4'b1110;in[14] = 1'b0;
#100 in[14] = 1'b1;
#100 sel = 4'b1111;in[15] = 1'b0;
#100 in[15] = 1'b1;
#300 $stop;
end endmodule

21.MUX 16_1

22.RIPPLE ADDER
module FA_ripple(a,b,c_in,s,c_out);
input [3:0]a,b;
input c_in;
output [3:0]s;
output c_out;
wire c1,c2,c3;
FA m1(a[0],b[0],c_in,s[0],c1);
FA m2(a[1],b[1],c1,s[1],c2);
FA m3(a[2],b[2],c2,s[2],c3);
FA m4(a[3],b[3],c3,s[3],c_out);
endmodule

//TEST BENCH
module FA_rippletst();
reg [3:0]a,b;
reg c_in;
wire [3:0]s;
wire c_out,c1,c2,c3;
FA_ripple tst(a,b,c_in,s,c_out);
initial
begin
a = 0;b = 0;c_in = 0;
#100 a = 4'b0010;
#100 b = 4'b1010;
#100 a = 4'b0000;
#100 a = 4'b1001;b = 4'b0111;
end
endmodule

23.ROTATE BY 2 BIT(2BIT RING COUNTER)

//rotate 8bit data by 2bit
module rotate2bit(in,clk,out);
input [7:0]in;
input clk;
output reg [7:0]out;
always @(posedge clk)
out <= {in[1],in[0],in[7:2]};
endmodule

//TEST BENCH
module rotate2bittst();
reg [7:0]in;
reg clk;
wire [7:0]out;
rotate2bit tst(in,clk,out);
initial
clk = 1;
always #40 clk = ~clk;
initial
begin
in =8'b0;
#50 in = 8'b00111011;
#100 in = 8'b11000100;
#50 in = 8'b01101101;
#400 $stop;
end
endmodule

24.PRIORITY ENCODER
//Example of 4_2 priority encoder
module priority_encoder4 (y, in) ;
input [3:0] in ;
output [1:0] y ;
reg [1:0] y ;
always @(in)
begin
casex(in) //x represents don?t care
4'b1xxx : y = 2'd0 ;
4'b01xx : y = 2'd1 ;
4'b001x : y = 2'd2 ;
4'b0001 : y = 2'd3 ;
endcase
end
endmodule

//TEST BENCH
module priority_encoder4tst();
reg [3:0] in ;
wire [1:0] y ;
priority_encoder4 tst(y, in) ;
initial
begin
#000 in = 4'b1111; #100 in = 4'b1110;
#100 in = 4'b1101; #100 in = 4'b1100;
#100 in = 4'b1011; #100 in = 4'b1010;
#100 in = 4'b1001; #100 in = 4'b1000;
#100 in = 4'b0111; #100 in = 4'b0110;
#100 in = 4'b0101; #100 in = 4'b0100;
#100 in = 4'b0011; #100 in = 4'b0010;
#100 in = 4'b0001; #100 $stop;
end
endmodule

25.XOR AND XNOR USING NAND

//xor and xnor using nand gates

module
xor_xnor1(a,b,y_xor_nand,y_xnor_nand);
input a,b;
output y_xor_nand,y_xnor_nand;
wire w1,w2,w3;
nand n1(w1,a,b);
nand n2(w2,a,w1);
nand n3(w3,b,w1);
nand n4(y_xor_nand,w2,w3);
nand
n5(y_xnor_nand,y_xor_nand,y_xor_nand);
endmodule

//TEST BENCH
module xor_xnor1tst();
reg a,b;
wire y_xor_nand,y_xnor_nand;
wire w1,w2,w3;
xor_xnor1
m1(a,b,y_xor_nand,y_xnor_nand);
initial
begin
#10 a = 1'b0;
b=1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b1;
b = 1'b1;
end
endmodule

26.XOR AND XNOR USING NOR

//xor and xnor using nor gates

module
xor_xnor2(a,b,y_xnor_nor,y_xor_nor);
input a,b;
output y_xnor_nor,y_xor_nor;
wire w1,w2,w3;
nor n1(w1,a,b);
nor n2(w2,a,w1);
nor n3(w3,b,w1);
nor n4(y_xnor_nor,w2,w3);
nor n5(y_xor_nor,y_xnor_nor,y_xnor_nor);
endmodule

//TEST BENCH
module xor_xnor2tst();
reg a,b;
wire y_xor_nor,y_xnor_nor;
wire w1,w2,w3;
xor_xnor2 m1(a,b,y_xnor_nor,y_xor_nor);
initial
begin
#10 a = 1'b0;
b=1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b1;
b = 1'b1;
end
endmodule

27.UP AND DOWN COUNTERS WITH RESPECTIVE ENABLES

//up counter and down counter
module
updown_counter(rst,clk,enup,endn,qout,carry
,borrow);
input rst,clk,enup,endn;
output reg [3:0]qout;
output carry, borrow;
parameter N=4;
always @(posedge clk)
if (rst) qout <= {N{1'b0}};
// synchronous reset
else if (enup) qout <= qout + 1;
else if (endn) qout <= qout - 1;
assign #5 carry = (&qout)&enup;
//in upcounter after qout=111..ntimes
overflow occurs
assign #5 borrow =(~|qout)&endn;
//in downcounter after qout=000..ntimes
underflow occurs
endmodule

//TEST BENCH
//up counter and down counter
module updown_countertst();
parameter N =4;
reg rst,clk,enup,endn;
wire [N-1:0]qout;
wire carry, borrow;
updown_counter
tst(rst,clk,enup,endn,qout,carry,borrow);
initial clk = 0;
always #20 clk = ~clk;
initial
begin
rst = 1; enup = 0;endn = 0;
#50 rst = 0;
#50 enup = 1;
#600 enup = 0;endn = 1;
#600 endn = 0;rst =1;
#500 $stop;
end
endmodule

28.UNIVERSAL SHIFT REGISTER

module universal_shift_register (rst,clk,sel1,sel0,left_shift_in,right_shift_in,parallel_in,qout);

parameter N = 4;
input left_shift_in,right_shift_in,clk,rst,sel1,sel0;
input [N-1:0]parallel_in;
output reg [N-1:0]qout;
always @(posedge clk or negedge rst)
if (rst) qout <= {N{1'b0}};
else case ({sel1,sel0})
2'b00: ;
// No change in output
2'b01: qout <= {left_shift_in, qout[N-1:1]}; // right shift
2'b10: qout <= {qout[N-2:0],right_shift_in}; // left shift
2'b11: qout <= parallel_in; // Parallel input
endcase
endmodule

//TEST BENCH
module universal_shift_registertst();
parameter N = 4;
reg left_shift_in,right_shift_in,clk,rst,sel1,sel0;
reg [N-1:0]parallel_in;
wire [N-1:0]qout;
universal_shift_register tst(rst,clk,sel1,sel0,left_shift_in,right_shift_in,parallel_in,qout);
initial clk=0;
always #20 clk = ~clk;
initial
begin
left_shift_in=0;right_shift_in=0;
rst = 1;sel1=0;sel0=0; parallel_in =0;
#60 rst = 0;sel0 = 1;left_shift_in = 1;
#50 left_shift_in = 0;
#50 left_shift_in = 1;
#50 rst = 1;
#50 rst = 0;sel0 = 0;sel1 = 1;right_shift_in = 1;
#50 right_shift_in = 0;
#70 right_shift_in = 1;#30 rst = 1;
#70 rst = 0;sel0 =1;parallel_in = 1001;
#70 parallel_in = 1101;#50 rst = 1;
#50 $stop;end endmodule

28.UNIVERSAL SHIFT REGISTER

29.ENCODER 4 TO 2
//Example of 4_2 encoder
module encoder4_2 (y, in) ;
input [3:0] in ;
output [1:0] y ;
reg [1:0] y ;
always @(in)
begin
case(in)
4'b1000 : y = 2'd0 ;
4'b0100 : y = 2'd1 ;
4'b0010 : y = 2'd2 ;
4'b0001 : y = 2'd3 ;
endcase
end
endmodule

//TEST BENCH
module encoder4_2tst();
reg [3:0] in ;
wire [1:0] y ;
encoder4_2 tst(y, in) ;
initial
begin
#000 in = 4'b1000;
#100 in = 4'b0100;
#100 in = 4'b0010;
#100 in = 4'b0001;
#100 $stop;
end
endmodule

29.ENCODER 4 TO 2