ARM Processors

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Introduction

Key Component in Embedded Systems. ARM cores are used in mobile phones,handheld organizers(PDA),portable consumer devices. Originally Acorn RISC Machines,but now called as Advanced RISC Machines. Development started in 1985. Over 1 billion ARM processors were sold by 2001. ARM7TDMI was most successful ARM core.
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Features of ARM Processors

32 bit RISC* processor. High Code density.( Less memory) Hardware Debug Technology. Load store architecture. Variable cycle execution for certain instructions. Inline barrel shifter. Thumb 16 bit instruction set. Conditional execution : An instruction is only executed when a specific condition has been 4/12/2006 Y.H.Dandawate 3 satisfied.

Features Contd.

Enhanced Instructions: DSP Orthogonal instruction Set Large 16 x 32 register file. Fixed op code width of 32 bits to ease decoding and pipelining. Powerful indexed addressing modes. Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.
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Embedded System Hardware

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Contd
Bus used in ARM based embedded system is to connect different peripheral devices with ARM core. ARM processors use AMBA ( Advanced Microcontroller Bus Architecture) Bus. Earlier AMBA introduced ARM system Bus (ASB) and ARM peripheral Bus(APB),but later ARM high performance bus (AHB) AHB provides higher data throughput. Memory plays vital role in performance of embedded system. 4/12/2006 Y.H.Dandawate 6

Contd

While using memory you have to compare price,performance and power consumption when deciding upon memory characteristics such as, hierarchy width and type. Peripherals : All peripherals are memory mapped. Memory Controllers. Interrupt Controllers.
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Embedded System Software

Hard Ware Device Initialization(Boot) Code and Device Drivers Operating System Application
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ARM Core

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Registers

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Registers Contd

There are 37 ARM registers in total of which variable amount is available as banked registers depending on the mode of operation.20 registers are hidden from a program at different times. r13 functions always as stack pointer r14 functions as link register, where the core puts the return address whenever it calls a subroutine. r15 is the program counter (pc) and contains the address of the next instruction to be fetched by the processor. CPSR : Current program status register SPSR : Saved Program status register.
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CPSR

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Processor Modes
7 modes 6 privileged (Allows full read write access to cspr) viz 1] Abort ( failed attempt to access memory) 2] Fast Interrupt request 3] Interrupt request 4] Supervisor ( after reset, OS kernal operation) 5] System (Special version of user mode) 6] Undefined ( undefined instruction) 1 non-privileged mode (allows read access to control field and read write to conditional flags) 1] User mode (programs and applications)
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Banked Registers
Spsr is Available in All modes Except user.

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Pipeline

Using a pipeline speeds up execution by fetching the next instruction while other instructions are being decoded and executed. No.of cycles required are less. ARM7 has 3 stage pipeline.
Fetch Decode Execute

ARM9 has 5 stage pipeline.

Fetch
Decode

Execute

Memory

Write
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Exceptions,Interrupts and Vector Table

The memory map address 0x00000000 is reserved for vector table.on some processors the vector table cab be optionally located at a higher address in memory 0xffff0000. There is difference of 4 bytes Reset Vector, Undefined instruction vector,software interrupt vector(SWI),pre fetch abort vector,data abort vector,interrupt request vector,fast interrupt vector. HW : Table 2.6

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Core Extensions
They are standard components placed next to the ARM core. They improve performance,manage resources and provide extra functionality. 1] Cache and tightly coupled memory(deterministic guarantees clock cycles). 2] Memory Management a) Non protected memory. b) Memory Protection Unit. c) Memory Management Units 3] Co-processors (Vector Floating Point)
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Architecture Revisions

ISA : Instruction Set Architecture Nomenclature ARM {x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{S}

X: family, y: Memory Mangmt/Protection,Z : Cache I : Embedded ICE macrocell F: Vector floating point unit S: Synthesizable version ( Core is provided as source code and used by EDA tools)
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ARM Processor Families

Instruction Set of ARM

Instruction Set Categories

Data Processing Instructions Load Store Instructions Software Interrupt Instructions Program Status Register Instructions Loading Constants Conditional Execution

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Data Processing Instructions

Move Instructions MOV {<cond>}{S} Rd,N Move 32 bit value in register If S suffix on data processing instruction,then it updates flags in the cpsr. Ex. MOV r7,r5 MOV r6,#immediate MNV : Move the NOT of the 32 bit value into a register.
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DPI contd.
Barrel Shifter Barrel Shifter Operations LSL = Logical Shift left LSR = Logical Shift right ASR = Arithmetic right shift ROR = Rotate right RRX = Rotate right extended MOV r0,r2,LSL #1 MOV r0,r3,LSL r2 MOVS r0,r1,ROR #4 4/12/2006 Y.H.Dandawate

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DPI contd.

Arithmetic Instructions ADD {S} Rd,Rn,N (Rd= Rn+N) ADD r0,r3,r4 (r0= r3+r4) ADC RSB : Reverse subtract of two 32 bit values ( Rd = N-Rn) RSC : Reverse subtract with carry SBC : Subtract with carry SUB : Subtract
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DPI contd.

Arithmetic with Barrel Shifter (Write examples) Logical Instructions AND {S} Rd,Rn,N : Logical bitwise AND ORR : Logical bit wise OR EOR : Logical bitwise Exclusive OR BIC :Logical bit clear (AND NOT)
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DPI contd.

Comparison Instructions CMP {<cond>}Rn,N ( no need of S) CMN : Compare negated TEQ : Test for equality of two 32 bit values TST : Test bits of a 32 bit value ( AND)

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DPI contd.
Multiply Instructions MUL {S} Rd,Rm,Rs (Rd = Rm*Rs) MLA : Multiply and Accumulate MLA Rd,Rm,Rs,Rn ( Rd=(Rm*Rs)+Rn) SMLAL : Signed Multiply accumulate long [Rdhi,Rdlo]= [Rdhi,Rdlo]+(Rm*Rs) SMULL : Signed Multiply Long [Rdhi,Rdlo]=(Rm*Rs) UMLAL : Unsigned multiply accumulate long UMULL : Unsigned multiply long 4/12/2006 Y.H.Dandawate 28

Branch Instructions

B{<cond>} label : Branch BL label : branch with link pc=label lr= address of next instruction after the BL BX : Branch Exchange pc=Rm & 0xfffffffe, T = Rm &1 BLX : Branch exchange with link same as above , lr is used like BL
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Load-Store Instructions

Single register transfer LDR : load word into register (32) STR :Save word from register LDRB: Load byte into a register (8) STRB : Save byte from register LDRH : Load halfword into a register(16) STRH : Save halfword LDRSB: load signed byte into register LDRSH: load signed halfword into register
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LS contd..

Single load store addressing modes

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LS contd..

Multiple register transfer LDM : Load multiple registers STM : Save multiple registers LDM| STM <add mode>Rn!,<reg>

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LS contd..

Stack Operations Load store multiple instructions are used to carry out stack operations. The stack can be either ascending or descending. If full(F) the stack pointer points to the last used or full location. If empty (E) SP points to address that is the first unused or empty location.
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Contd

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Swap Instruction SWP : Swap a word between memory and register SWPB : Swap a byte

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Software Interrupt Instruction

A software interrupt instruction (SWI) causes a software interrupt exception,which provides a mechanism for applications to call operating system routines. SWI {<cond>} SWI_number Lr_svc = add.of inst.following SWI Spsr_svc=cpsr Pc=vectors+0x8 Cpsr mode=SVC
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Program Status Register Instructions

Directly controls a program status register. MRS Rd,<cpsr|spsr> MSR <cpsr|spsr>,Rm or #immediate Co-Processor Instructions CDP :Perform operation in cop MRC,MCR : cop register transfer LDC,STC : cop memory transfer

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