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Lab FSM2

This lab experiment involves designing a BCD-to-excess-3 encoder using both combination logic and a finite state machine. Students will first implement the encoder using combination logic and simulate it. They will then create an FSM for the encoder which will have a serial 1-bit input and serial 1-bit output. To test the design on an FPGA board, students will build parallel-to-serial and serial-to-parallel converters to interface between the board and the encoder FSM. Clocks, resets, read and write signals will be used to control the data flow between modules.

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Ali Ahmad
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67 views

Lab FSM2

This lab experiment involves designing a BCD-to-excess-3 encoder using both combination logic and a finite state machine. Students will first implement the encoder using combination logic and simulate it. They will then create an FSM for the encoder which will have a serial 1-bit input and serial 1-bit output. To test the design on an FPGA board, students will build parallel-to-serial and serial-to-parallel converters to interface between the board and the encoder FSM. Clocks, resets, read and write signals will be used to control the data flow between modules.

Uploaded by

Ali Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lab-Experiment-10

This lab will help you learn the integration between your different sequential logic modules on Xilinx Schematics. You will practice how to make FSM from a given Problem Statement.

BCD-to-Excess-3-Encoder
S.No.
0 1 2 3

BCD
0000 0001 0010 0011

Excess-3 Code
0011 0100 0101 0110

4
5 6 7 8 9

0100
0101 0110 0111 1000 1001

0111
1000 1001 1010 1011 1100

BCD-to-Excess-3-Encoder
In Excess-3 Code is just an addition of 3 in the BCD code. first try to implement it using a Combination Logic and simulate your code. The Next step will be to make a Finite State Machine for this Encoder. For that purpose, we will assume that the FSM controller for this machine will have serial 1 bit input and serial 1 bit output

BCD-to-Excess-3
Serial Input 0000

Serial output 0011

Encoder

Clock Reset

BCD-to-Excess-3-Encoder
To implement your design in Spartan-2 Kit it will be very difficult to show your serial output. You must have an oscillator to see your result which has a clock rate of 16MHz. What else can be done is to make a parallel to Serial converter and then a Serial to Parallel Converter. You will design your own converters and code it in Verilog.
Parallel to Serial Converter BCD-toExcess-3 Encoder Serial to Parallel Converter

BCD-to-Excess-3-Encoder
Do not forget to give clock to each module and a reset signal and a Write and read signal. The Read signal will read your result once the date is available at the S-to-P module. The write signal will write the new BCD 4-bit value to P-to-S module. You can also do it using your reset signal for the purpose.

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