Alu (For Old Kit)
Alu (For Old Kit)
module arith(op, a,b, cin, y, cout, zout); input [03:0] op; input [07:0] a,b; input cin; output [07:0] y; output cout; input zout; wire [7:0]a; wire [7:0]b; wire [3:0]po; wire cin; //wire zout; reg [7:0]y; reg cout; wire reg zout; addercout;
parameter ADD = 4'd0; parameter SUB = 4'd1; parameter AND = 4'd2; parameter OR = 4'd3; parameter XOR = 4'd4; parameter NOT = 4'd5; parameter RLF = 4'd6; parameter RRF = 4'd7;
//assign zout = ~|y; always @(a or b or cin or op) begin case (op) ADD: {addercout,y} = a + b; SUB: {addercout,y} = a - b; AND: {addercout,y} = {1'b0, a & b}; OR : {addercout,y} = {1'b0, a | b}; XOR: {addercout,y} = {1'b0, a ^ b}; NOT: {addercout,y} = {1'b0, ~a}; RLF: {addercout,y} = {a[7], a[6:0], cin}; RRF: {addercout,y} = {a[0], cin, a[7:1]}; SWP: {addercout,y} = {1'b0, a[3:0], a[7:4]}; default: {addercout,y} = 9'h0; endcase end always @(addercout or op) begin if (op == SUB) cout = ~addercout; else cout = addercout; end end module