MTech VLSI 2nd Sem RGPV Teaching Scheme
MTech VLSI 2nd Sem RGPV Teaching Scheme
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Scheme of Examination
Second Semester- Master of Engineering ( Embedded System and VLSI Design,Micro electronics and VLSI Design)
S.No. Subject Code Subject Name Periods per week Credits Maximum Marks (Theory Slot) End. Tests Assign Sem. (Two) ments Exam. /Quiz Maximum Marks (Practical Slot) End. Practical Sem. Record/A Practical/ ssignmen Viva t/Quiz/Pr esentatio n Total Marks
1. 2. 3. 4. 5.
VLSI Technology Real Time Operating System VLSI Test and Testability Microelectronics Embedded Computing System Design Lab-III Real Time Operative System Lab-IV VLSI Technology Total
3 3 3 3 3
1 1 1 1 1
4 4 4 4 4
70 70 70 70 70
20 20 20 20 20
10 10 10 10 10
6.
90
60
150
7.
15
6 12
6 32
350
100
50
90 180
60 120
150 800
L: Lecture -
T: Tutorial -
P: Practical
w.e.f. July-2010