Upf Tutorial Interopforum
Upf Tutorial Interopforum
Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
3
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
4
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
External power configuration file for verification Magma Power Management commands Vast System level modeling methodology and format Synopsys RTL constructs (Verilog and VHDL) Power Management commands Switching activity format SAIF TI Retention cell semantics Atrenta, Synchronous DA
Feb 07 - UPF 1.0 standard approved by Accellera ! March 07 IEEE P1801 PAR / Study Group underway
Digital Design
COT/ASIC/FPGA Synthesis + Physical Implementation + DFT + Signoff
CPF 31%
Other 2%
UPF 67%
Based on Q4 05 through Q3 06 EDAC MSS data plus other publicly available market data
Digital Verification
RTL Verification + Formal Verification (TTM Revenue: $579.8M)
Based on Q4 05 through Q3 06 EDAC MSS data plus other publicly available market data
Digital Verification
Other 1% CPF 33%
UPF 66%
Based on 2007 John Cooley DeepChip Verification Survey Mindshare 818 Respondents
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What is UPF?
Unified Power Format UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. Why UPF?
No existing HDL adequately supports the specification of power distribution and management Vendor-specific formats are non-portable and create opportunities for bugs via inconsistent specifications
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<100nm
Static leakage consumes >50% of power!
Intel 45nm Test Chip Intel 45nm Memory Cell
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Design Compiler
IC Compiler
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UPF in a Nutshell
What is UPF?
Abstract supply distribution and control network specification Power-aware design intent Used throughout design flow
UPF UPF HDL HDL (RTL) (RTL) Simulation, Logical Equivalence Checking,
Synthesis
Key Concept: UPF extends without changing the logic design specification
Golden source is not touched No re-verification of logic-only UPF augments the HDL specification
P&R
Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
17
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
IP Accommodating
Specify how separate from what
Which registers require retention Specifics of retention (supplies, control signals)
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Lp1 Lp2
Ln1 Ln2
Ln3
Lp3
Lp3
pdA
create_power_domain
create_power_domain domain_name [-elements list] [-include_scope] [-scope instance_name]
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Ln3
Lp3
spAOn
pdA
create_supply_port
create_supply_port port_name -domain domain_name [-direction <in | out>]
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Ln3
Lp3 RET
pdA
Ln3
Lp3 PR
pdA
create_supply_net
create_supply_net net_name -domain domain_name [-reuse] [-resolve < unresolved | one_hot | parallel >]
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pdA
create_power_switch
create_power_switch switch_name -domain domain_name -output_supply_port { port_name supply_net_name } {-input_supply_port { port_name supply_net_name }}* {-control_port { port_name net_name }}* {-on_state {state_name input_supply_port {boolean_function}}}* [-on_partial_state { state_name input_supply_port { boolean_function }}]* [-ack_port { port_name net_name [{boolean_function}] }]* [-ack_delay { port_name delay}]* [-off_state { state_name {boolean_function} }]* [-error_state { state_name {boolean_function} }]*
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Ln3 PR
Lp3
pdA
connect_supply_net
connect_supply_net net_name [-ports list] [-pins list] [< -cells list | -domain domain_name >] [< -rail_connection rail_type | -pg_type pg_type >]* [-vct vct_name]
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pdA
Automation
Supply_port Supply_net Supply_net
Flexibility
Supply_port Supply_net Supply_net
U1
U1
Supply_net
Supply_net
U2
U17
U2
Single create_supply_port command Single create_supply_net command Supply is routed to all design elements in PD
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OFF:
Primary power and/or ground are OFF Voltage value is irrelevant
PARTIAL_ON
For power-aware models may more accurately reflect switching capacitive transition
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Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
OFF Means
All registers are corrupted
Retention (shadow) registers have separate supply(ies) Logic types = X Other types = default initial value
ON Means
When logic is powered on (event)
Combinatorial processes are evaluated Including continuous assignments Edge triggered processes are not evaluated until the next active edge Logic (processes) are re-enabled for evaluation
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VDDchip
one_hot resolution: Predefined Specified in create_supply_net command At most one supply (PARTIAL_)ON at any time Voltage value is the value of the ON port
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Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
reconVDD
parallel resolution: Predefined Specified in create_supply_net command All must be OFF Or all must be ON and at same voltage If any PARTIAL_ON, then PARTIAL_ON
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Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
Synthesis
P&R
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Questa Simulation
Synthesis
FormalPro
Is the implementation equivalent to what was verified?
P&R
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Library
Vsim Simulation
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FormalPro Accelleras UPF: The Power of One- Product Update 2006 Interoperability Forum 26 Apr 07
Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
44
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
Talus TM Platform
Rapid concurrent closure of timing, power and yield
25% less power Power signoff
RTL to GDSII
Automation
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RTL
Sign-off power and IR drop
Static and Transient Intelligent de-cap methodology Built-in spice engine
Leakage Power
Automated MTCMOS/VTCMOS Concurrent Multi-vt flow
Talus Design
Talus Power Quartz Rail
Optimization
MTCMOS
Power On/Off behavior Rush current analysis
Analysis
Thermal
Impact on delay/leakage
Talus Vortex
GDSII
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Talus Power
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Talus Power
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MTCMOS
Switched
DVFS
Lp3
pdA
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pdA
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Logical Mapping
sub2 ($m3)
Electrical Mapping
Mapping
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B2
clk
B3
B4
R5
G6
P7
B7
B8
Floating outputs of power-gated circuits Isolation control signals force known value Isolation and level shifting can be merged
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Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
P5 P6
P7
Vlo P5 P6
Vhi P7
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P5 P6
P7
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1.08v Constant
0.9v Switched
1.2v Constant
1.08v Constant
Isolation cell insertion
0.9v Switched
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1.08v Constant
1.2v switched
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MTCMOS Switches
Coarse Grain Distributed Switches
Switches placed in rows to control groups of logic
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MTCMOS
pdA
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Vbu
D Q u37
D Q u37
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MTCMOS Domain
1.08v Constant
Flow
Voltage Drop Rail analysis used to determine the location of the current sinks
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Standalone Power sign-off accuracy with early predictability Concurrently addresses power, voltage drop, electromigration, Thermal and Timing issues Analyze impact of temperature on leakage and performance On-the-fly characterization for accurate dynamic IR drop analysis Leakage optimization through intelligent de-cap insertion MTCMOS power-on and rush current analysis
Quartz SSTA
Talus Power
Quartz Rail
Talus DFM
Spice Engine
Rail EM
Talus ACC
Power IR Drop
Quartz Rail
Thermal IR Drop Delay
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UPF Roadmap
UPF version 1.0 released Feb 22nd 2007 Magma support for UPF
UPF Implementation support May 07 Talus Power for Implementation Quartz Rail for Analysis
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Continuous Innovation
Outstanding Partnerships
Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
66
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
UPF Workshop
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Synthesis
P&R
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Architecture design
MVSIM MVRC
Implementation
MVSIM
Multi-voltage co-simulator works with ModelSim and VCS
2f 01 1
0a 0 1
30 30 0.0
00
0b
0b
MVRC
Vectorless verification of multi-voltage conditions Power sequence prediction
1.2 200
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MVSYN
Scriptless insertion of protection devices into RTL
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Accelleras UPF: The Power of One
30 Z 30 X
00
0b
0b
0.0 100
1.2 200
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Functional
BOM Cost
Whats Next
The Panel Get involved with UPF for your customers sake
Download current standard at accellera.org Join the IEEE P1801 study/working group UPF Workshop at DAC
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THANK YOU
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Piyush Sancheti
Voltage and power domain verification Power domain sequencing verification Domain-aware power estimation Power reduction and planning
Interoperability Forum 26 Apr 07
Atrenta plans to support UPF in SpyGlass Power by July 2007 Atrenta will work closely with customers for UPF support in SpyGlass Power
Provide a transition path from/to SpyGlass SGDC format to/from UPF Ensure UPF support in SpyGlass is adequate and robust for use in design projects Work with UPF members to resolve any tool interoperability issues
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Talus Power
Talus Vortex
Talus Power
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SpyGlass Power
UPF
Library data Supplies Scope Domains signals
Power Estimation
Timing-aware power estimation at RTL, gates, layout
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UPF examined
UPF contains all the major categories required by Atrenta SpyGlass Atrenta is planning a power format translator for our customers
CPF
Library
define_always_on_cell define_isolation_cell always_on_cell always_on_pin set_pin_related_supply set_power_switch define_level_shifter_cell aonbuffer define_open_source_input_pin apcell define_power_clamp_cell define_power_switch_cell define_state_retention_cell identify_power_logic inisocell isocell pgcell pgpins_naming powerswitch retencell
Atrenta UPF
CPF
create_power_switch_rule update_power_switch_rule
Atrenta
UPF
create_power_switch map_power_switch
Design - scoping
end_design set_design set_instance
Atrenta
Design - modes
create_mode_transition create_supply_net create_power_mode update_power_mode
Design - supplies
create_bias_net create_power_nets create_ground_nets supply
Multimode analysis
create_analysis_view voltagedomain pinvoltage add_domain_elements create_power_domain merge_power_domains set_domain_supply_net create_nominal_condition create_operating_corner set_switching_activity update_nominal_condition
Design - domains
create_power_domain update_power_domain
CPF
bind_checker create_hdl2upf_vct create_upf2hdl_vct
UPF
Simulation semantics
Design - levelshifters
create_level_shifter_rule update_level_shifter_rules create_state_retention_rule update_state_retention_rules levelshifter map_level_shifter_cell set_level_shifter
Miscellaneous
create_global_connection define_library_set set_array_naming_style set_cpf_version set_hierarchy_separator set_power_target set_power_unit set_register_naming_style set_time_unit add_port_state connect_supply_net create_supply_port get_supply_net name_format save_upf upf_version
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UPF UPF
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Agenda
Introduction (00:15)
Kevin Kranen, Synopsys
Q&A
82
Accelleras UPF: The Power of One
Interoperability Forum 26 Apr 07
Floorplan View
PD_main PD0 in2wire pkt_ counter VDD
in2wire PD0
pkt_ counter
out2wire PD1
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