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Myapp: File1.o File2.o GCC - o Myapp File1.o File2.o File1.o: File1.c Macros.h GCC - C File1.c File2.o: File2.c Macros.h GCC - C File2.c

This document provides an overview of Makefiles and the make tool in 3 sections: 1) It describes a sample Makefile that compiles two C source files into an executable and shows the basic Makefile syntax. 2) It explains how make uses dependencies to determine what needs recompiling and only performs necessary recompiles. 3) It discusses additional make features like specifying targets, minimizing recompiles, and finding more documentation.

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Suyashi Purwar
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36 views

Myapp: File1.o File2.o GCC - o Myapp File1.o File2.o File1.o: File1.c Macros.h GCC - C File1.c File2.o: File2.c Macros.h GCC - C File2.c

This document provides an overview of Makefiles and the make tool in 3 sections: 1) It describes a sample Makefile that compiles two C source files into an executable and shows the basic Makefile syntax. 2) It explains how make uses dependencies to determine what needs recompiling and only performs necessary recompiles. 3) It discusses additional make features like specifying targets, minimizing recompiles, and finding more documentation.

Uploaded by

Suyashi Purwar
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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A sample Makefile

myapp : file1.o file2.o gcc -o myapp file1.o file2.o file1.o : file1.c macros.h gcc -c file1.c file2.o : file2.c macros.h gcc -c file2.c

This Makefile describes the dependencies require to compile the C source files file1.c, file2.c (and header file macros.h) into the executable called myapp.

Basic Makefile syntax


The basic syntax of a Makefile is
target: dep dep dep [tab] cmd [tab] cmd [tab] ...

Such a rule builds the file target in the following way Checks to see if target does not exists Checks to see if it is older than any of the dependency files dep If either of the above are true, the file target needs to be rebuilt and the commands are executed A command must start with a tab character!

Our example again

myapp : file1.o file2.o gcc -o myapp file1.o file2.o file1.o : file1.c macros.h gcc -c file1.c file2.o : file2.c macros.h gcc -c file2.c This rebuilds the file myapp if either it does not exist or is older than either file1.o or file2.o. But make does more, also checks to see that file1.o and file2.o are

newer than file1.c macros.h and file2.c macros.h respectively. If it is not it first
recompiles either of these files, then recompiles myapp automatically!

The power of make

The real advantage of make is it does as little work as possible. It only recompiles the files that need updating to insure the executable (or file) is update date. To execute such a makefile, you simply call make in the directory of the makefile (assuming the makefile is called makefile or Makefile. If you want to specify a different filename run make -f makefilename.

more make

You can also specify which target you wish to compile by typing
make target

make will execute the first target if none is specified. So in our example we could type
make file2.o

To just recompile file2.o if we wanted to for some reason.

There is tons and tons more

For a not so concise summary check out the make documentation

http://www.gnu.org/software/make/manual/make.html

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