Chapter 9 Asynchronous Sequential Logic

9-1

Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-2

Sequential Circuits

Consist of a combinational circuit to which storage elements are connected to form a feedback path Specified by a time sequence of inputs, outputs, and internal states Two types of sequential circuits:

Synchronous Asynchronous

primary difference

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Synchronous vs. Asynchronous

Asynchronous sequential circuits

change in the input variables No clock signal is required Have better performance but hard to design due to timing problems

Internal states can change at any instant of time when there is a

Synchronous sequential circuits

Synchronized by a periodic train of clock pulses Much easier to design (preferred design style) 9-4

Why Asynchronous Circuits ?

Used when speed of operation is important

Response quickly without waiting for a clock pulse Only a few components are required

Used in small independent systems

Used when the input signals may change independently of internal clock

Asynchronous in nature

Used in the communication between two units that have their own independent clocks

Must be done in an asynchronous fashion

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Definitions of Asyn. Circuits

Inputs / Outputs Delay elements:

Only a short term memory May not really exist due to original gate delay Current state (small y) Next state (big Y) Have some delay in response to input changes
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Secondary variable:

Excitation variable:

Operational Mode

Steady-state condition:

Current states and next states are the same Difference between Y and y will cause a transition No simultaneous changes of two or more variables The time between two input changes must be longer than the time it takes the circuit to a stable state The input signals change one at a time and only when the circuit is in a stable condition

Fundamental mode:

9-7

Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-8

Transition Table

Transition table is useful to analyze an asynchronous circuit from the circuit diagram Procedure to obtain transition table:
1. Determine all feedback loops in the circuits 2. Mark the input (yi) and output (Yi) of each feedback loop 3. Derive the Boolean functions of all Ys 4. Plot each Y function in a map and combine all maps into one table 5. Circle those values of Y in each square that are equal to the value of y in the same row
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An Example of Transition Table

feedback

Y1 = xy1 + xy2 Y2 = xy1 + xy2

feedback

inputs current states

Y = Y1Y2

stable !!
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State Table

When input x changes from 0 to 1 while y=00:

Y changes to 01 unstable y becomes 01 after a short delay stable at the second row The next state is Y=01

Each row must have at least one stable state Analyze each state in this way can obtain its state table
Present State 0 0 1 1 0 1 0 1 0 1 0 1 Next State X=0 0 1 0 1 0 0 1 1 X=1 1 1 0 0

y1y2x : total state

4 stable total states: 000,011, 110,101
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Flow Table

Similar to a transition table except the states are represented by letter symbols Can also include the output values Suitable to obtain the logic diagram from it Primitive flow table: only one stable state in each row (ex: 9-4(a))

Equivalent to 9-3(c) if a=00, b=01, c=11, d=10

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Flow Table to Circuits

Procedure to obtain circuits from flow table:

Assign to each state a distinct binary value (convert to a transition table) Obtain circuits from the map The binary state assignment (to avoid race) The output assigned to the unstable states

Two difficulties:

Ex: from the flow table 9-4(b)

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Race Conditions

Race condition:

two or more binary state variables will change value when one input variable changes Cannot predict state sequence if unequal delay is encountered
The final stable state does not depend on the change order of state variables The change order of state variables will result in different stable states Should be avoided !!

Non-critical race:

Critical race:

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Race-Free State Assignment

Race can be avoided by proper state assignment

Direct the circuit through intermediate unstable states with a unique state-variable change It is said to have a cycle

Must ensure that a cycle will terminate with a stable state

Otherwise, the circuit will keep going in unstable states

More details will be discussed in Section 9-6

9-15

Stability Check

Asynchronous sequential circuits may oscillate between unstable states due to the feedback

Must check for stability to ensure proper operations Any column has no stable states unstable Ex: when x1x2=11 in Fig. 9-9(b), Y and y are never the same
Y = x1x2 + x2y

Can be easily checked from the transition table

9-16

Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-17

Latches in Asynchronous Circuits

The traditional configuration of asynchronous circuits is using one or more feedback loops

No real delay elements

It is more convenient to employ the SR latch as a memory element in asynchronous circuits

Produce an orderly pattern in the logic diagram with the memory elements clearly visible Will be analyzed first using the method for asynchronous circuits
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SR latch is also an asynchronous circuit

SR Latch with NOR Gates

feedback

S=1, R=1 (SR = 1) should not be used SR = 0 is normal mode * should be carefully checked first 9-19

SR Latch with NAND Gates

feedback

S=0, R=0 (SR = 1) should not be used SR = 0 is normal mode * should be carefully checked first 9-20

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Analysis Procedure

Procedure to analyze an asynchronous sequential circuits with SR latches:

1. Label each latch output with Yi and its external feedback path (if any) with yi 2. Derive the Boolean functions for each Si and Ri 3. Check whether SR=0 (NOR latch) or SR=0 (NAND latch) is satisfied 4. Evaluate Y=S+Ry (NOR latch) or Y=S+Ry (NAND latch) 5. Construct the transition table for Y=Y1Y2Yk 6. Circle all stable states where Y=y
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Analysis Example
S1=x1y2 R1=x1x2 S1R1 = x1y2x1x2 = 0 (OK) S2=x1x2 R2=x2y1 S2R2 = x1x2x2y1 = 0 (OK)

Y1=S1 + R1y1 =x1y2 + (x1+x2)y1 =x1y2+x1y1+x2y1 Y2=S2 + R2y2 =x1x2 + (x2+y1)y2 =x1x2+x2y2+y1y2

feedback

critical race !!

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Implementation Procedure

Procedure to implement an asynchronous sequential circuits with SR latches:

1. Given a transition table that specifies the excitation function Y = Y1Y2Yk, derive a pair of maps for each Si and Ri using the latch excitation table 2. Derive the Boolean functions for each Si and Ri
(do not to make Si and Ri equal to 1 in the same minterm square)

3. Draw the logic diagram using k latches together with the gates required to generate the S and R
(for NAND latch, use the complemented values in step 2)
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Implementation Example
Excitation table: list the required S and R for each possible transition from y to Y

y = 1 (outside) 0 (inside) S=0, R=1 from excitation table

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Debounce Circuit

Mechanical switches are often used to generate binary signals to a digital circuit

It may vibrate or bounce several times before going to a final rest Cause the signal to oscillate between 1 and 0

A debounce circuit can remove the series of pulses from a contact bounce and produce a single smooth transition

Position A (SR=01) bouncing (SR=11) Position B (SR=10) Q = 1 (set) Q = 1 (no change) Q = 0 (reset)

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Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-26

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Design Procedure
1. Obtain a primitive flow table from the given design specifications 2. Reduce the flow table by merging rows in the primitive flow table 3. Assign binary state variables to each row of the reduced flow to obtain the transition table 4. Assign output values to the dashes associated with the unstable states to obtain the output map 5. Simplify the Boolean functions of the excitation and output variables and draw the logic diagram
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Primitive Flow Table

Design example: gated latch

Accept the value of D when G=1 Retain this value after G goes to 0 (D has no effects now) Dash marks are given when both inputs change simultaneously Outputs of unstable states are dont care
Input D G 0 1 1 1 0 0 1 0 1 0 0 0 Output Q 0 1 0 0 1 1 Comments D=Q because G=1 D=Q because G=1 After states a or d After state c After states b or f After state e

Obtain the flow table by listing all possible states

State a b c d e f

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Reduce the Flow Table

Two or more rows can be merged into one row if there are non-conflicting states and outputs in every columns After merged into one row:

Dont care entries are overwritten Stable states and output values are included A common symbol is given to the merged row

Formal reduction procedure is given in next section

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Transition Table and Logic Diagram

Assign a binary value to each state to generate the transition table

a=0, b=1 in this example

Directly use the simplified Boolean function for the excitation variable Y

An asynchronous circuit without latch is produced

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Implementation with SR Latch

Listed according to the transition table and the excitation table of SR latch

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Outputs for Unstable States

Objective: no momentary false outputs occur when the circuit switches between stable states If the output value is not changed, the intermediate unstable state must have the same output value

0 1 (unstable) 0 (X) 0 0 (unstable) 0 (O)

If the output value changed, the intermediate outputs are dont care

It makes no difference when the output change occurs

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Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-33

State Reduction

Two states are equivalent if they have the same output and go to the same (equivalent) next states for each possible input

Ex: (a,b) are equivalent (c,d) are equivalent

State reduction procedure is similar in both sync. & async. sequential circuits

Present Next State Output State x=0 x=1 x=0 x=1 a c b 0 1 b d a 0 1 c a d 1 0 d b d 1 0

For completely specified state tables: use implication table For incompletely specified state tables: use compatible pairs
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Implication Table Method (1/2)

Step 1: build the implication chart

ab iff de bc since outputs are not equivalent d and e are the same

Present Next State Output State x=0 x=1 x=0 x=1 a d b 0 0 b e a 0 0 c g f 0 1 d a d 1 0 e a d 1 0 f c b 0 0 g a e 1 0

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Implication Table Method (2/2)

Step 2: delete the node with unsatisfied conditions Step 3: repeat Step 2 until equivalent states found
af because cd bf because ce equivalent states : (a,b) (d,e) (d,g) (e,g) d == e == g Present Next State Output State x=0 x=1 x=0 x=1 a d a 0 0 c d f 0 1 d a d 1 0 f c a 0 0 *Reduced State Table*
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Merge the Flow Table

The state table may be incompletely specified

Some next states and outputs are dont care Several synchronous circuits also have this property Instead, we are going to find compatible states Two states are compatible if they have the same output and compatible next states whenever specified Determine all compatible pairs Find the maximal compatibles Find a minimal closed collection of compatibles

Primitive flow tables are always incompletely specified

Incompletely specified states are not equivalent

Three procedural steps:

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Compatible Pairs

Implication tables are used to find compatible states

We can adjust the dashes to fit any desired condition Must have no conflict in the output values to be merged
compatible pairs : (a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f)

output conflict !

output conflict !

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Maximal Compatibles

A group of compatibles that contains all the possible combinations of compatible states

Obtained from a merger diagram A line in the diagram represents that two states are compatible All its diagonals connected

n-state compatible n-sided fully connected polygon

Not all maximal compatibles are necessary

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Closed Covering Condition

The set of chosen compatibles must cover all the states and must be closed

Closed covering There are no implied states The implied states are included within the set (a,c,d) (b,e,f) are left in the set All six states are still included No implied states according to its implication table 9-23(b)
9-40

The closure condition is satisfied if

Ex: if remove (a,b) in the right

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Closed Covering Example

*(a,b) (c,d,e) (X) implied (b,c) is not included in the set * better choice: (a,d) (b,c) (c,d,e) all implied states are included 9-41

Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-42

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Race-Free State Assignment

Objective: choose a proper binary state assignment to

prevent critical races

Only one variable can change at any given time when a state transition occurs States between which transitions occur will be given adjacent assignments

Two binary values are said to be adjacent if they differ in only one variable

To ensure that a transition table has no critical races, every possible state transition should be checked

A tedious work when the flow table is large Only 3-row and 4-row examples are demonstrated
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3-Row Flow Table Example (1/2)

Three states require two binary variables Outputs are omitted for simplicity Adjacent info. are represented by a transition diagram a and c are still not adjacent in such an assignment !!

Impossible to make all states adjacent if only 3 states are used

b has a transition to c

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3-Row Flow Table Example (2/2)

A race-free assignment can be obtained if we add an extra row to the flow table

Only provide a race-free transition between the stable states 00 10 11 (no race condition)

The transition from a to c must now go through d

dont care but cannot be 10 (cannot stable)

9-45

4-Row Flow Table Example (1/2)

Sometimes, just one extra row may not be sufficient to prevent critical races

More binary state variables may also required

With one or two diagonal transitions, there is no way of using two binary variables that satisfy all adjacency

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4-Row Flow Table Example (2/2)

still has only 4 stable states

9-47

Multiple-Row Method

Multiple-row method is easier

May not as efficient as in above shared-row method

Each stable state is duplicated with exactly the same output

Behaviors are still the same

While choosing the next states, choose the adjacent one

can be used to any 4-row flow table

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Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-49

Hazards

Unwanted switching appears at the output of a circuit

Due to different propagation delay in different paths Cause temporary false-output values in combinational circuits Cause a transition to a wrong state in asynchronous circuits Not a concern to synchronous sequential circuits

May cause the circuit to mal-function

Three types of hazards:

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Circuits with Hazards

Static hazard: a momentary output change when no output change should occur If implemented in sum of products:

no static 1-hazard no static 0-hazard or dynamic hazard

Two examples for static 1-hazard:

o o pq o p n o p pq

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Hazard-Free Circuit

Hazard can be detected by inspecting the map The change of input results in a change of covered product term Hazard exists

Ex: 111 101 in (a)

To eliminate the hazard, enclose the two minterms in another product term

Results in redundant gates

Redundant !!
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Remove Hazard with Latches

Implement the asynchronous circuit with SR latches can also remove static hazards

A momentary 0 has no effects to the S and R inputs of a NOR latch A momentary 1 has no effects to the S and R inputs of a NAND latch Replaced by a latch

Hazards exist !!

9-53

Implementation with SR Latches

Given:
S = AB + CD R = AC

For NAND latch, use complemented inputs

S = (AB + CD) = (AB)(CD) R = (AC)

Merged !!

(this is the output we want)

Q = (QS) = [Q(AB)(CD)] Two-level circuits

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Essential Hazards

Besides static and dynamic hazards, another type of hazard in asynchronous circuits is called

essential hazard

Caused by unequal delays along two or more paths that originate from the same input Cannot be corrected by adding redundant gates Can only be corrected by adjusting the amount of delay in the affected path

Each feedback path should be examined carefully !!

9-55

Outline

Asynchronous Sequential Circuits Analysis Procedure Circuits with Latches Design Procedure Reduction of State and Flow Tables Race-Free State Assignment Hazards Design Example
9-56

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Recommended Design Procedure

1. State the design specifications 2. Derive a primitive flow table 3. Reduce the flow table by merging the rows 4. Make a race-free binary state assignment 5. Obtain the transition table and output map 6. Obtain the logic diagram using SR latches
9-57

Primitive Flow Table

Design a negative-edge-triggered T flip-flop Two inputs: T(toggle) and C(clock)

T=1: toggle, T=0: no change

Input T C 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1 Output Q 0 1 1 0 0 0 1 1

One output: Q
Comments Initial output is 0 After state a Initial output is 1 After state c After states d or f After states e or a After states b or h After states g or c

State a b c d e f g h

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Merging the Flow Table

Compatible pairs: (a,f) (b,g) (b,h) (c,h) (d,e) (d,f) (e,f) (g,h) Maximal compatible set: (a,f) (b,g,h) (c,h) (d,e,f) a b c d

9-59

State Assignment & Transition Table

No diagonal lines in the transition diagram No need to add extra states

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Logic Diagram

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