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The document provides Verilog code examples for different 4-bit counters, including: 1) An unsigned up counter with asynchronous clear. 2) An unsigned down counter with synchronous set. 3) An unsigned up counter with asynchronous load from primary input. 4) An unsigned up counter with synchronous load and constant. 5) An unsigned up counter with asynchronous clear and clock enable. 6) An unsigned up/down counter with asynchronous clear. 7) A signed up counter with asynchronous reset. 8) A signed up counter with asynchronous reset and modulo maximum.

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Sharath Chandra
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115 views

Counters

The document provides Verilog code examples for different 4-bit counters, including: 1) An unsigned up counter with asynchronous clear. 2) An unsigned down counter with synchronous set. 3) An unsigned up counter with asynchronous load from primary input. 4) An unsigned up counter with synchronous load and constant. 5) An unsigned up counter with asynchronous clear and clock enable. 6) An unsigned up/down counter with asynchronous clear. 7) A signed up counter with asynchronous reset. 8) A signed up counter with asynchronous reset and modulo maximum.

Uploaded by

Sharath Chandra
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Verilog Codes for different COUNTERS

Verilog code for a 4-bit unsigned up counter with asynchronous clear.


module counter (clk, clr, q); input clk, clr; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4b0000; else tmp <= tmp + 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit unsigned down counter with synchronous set.
module counter (clk, s, q); input clk, s; output [3:0] q; reg [3:0] tmp; always @(posedge clk) begin if (s) tmp <= 4b1111; else tmp <= tmp - 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit unsigned up counter with an asynchronous load from the primary input.
module counter (clk, load, d, q); input clk, load; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge load) begin if (load) tmp <= d; else tmp <= tmp + 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit unsigned up counter with a synchronous load with a constant.

module counter (clk, sload, q); input clk, sload; output [3:0] q; reg [3:0] tmp; always @(posedge clk) begin if (sload) tmp <= 4b1010; else tmp <= tmp + 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit unsigned up counter with an asynchronous clear and a clock enable.
module counter (clk, clr, ce, q); input clk, clr, ce; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4b0000; else if (ce) tmp <= tmp + 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear.
module counter (clk, clr, up_down, q); input clk, clr, up_down; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4b0000; else if (up_down) tmp <= tmp + 1b1; else tmp <= tmp - 1b1; end assign q = tmp; endmodule

e Verilog code for a 4-bit signed up counter with an asynchronous reset.


module counter (clk, clr, q); input clk, clr; output signed [3:0] q; reg signed [3:0] tmp; always @ (posedge clk or posedge clr) begin if (clr) tmp <= 4b0000;

else tmp <= tmp + 1b1; end assign q = tmp; endmodule

Verilog code for a 4-bit signed up counter with an asynchronous reset and a modulo maximum.
module counter (clk, clr, q); parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT); input clk, clr; output [MAX_SQRT-1:0] q; reg [MAX_SQRT-1:0] cnt; always @ (posedge clk or posedge clr) begin if (clr) cnt <= 0; else cnt <= (cnt + 1) %MAX; end assign q = cnt; endmodule

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