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Experiment 3:: 1) D Flipflop

The document describes 8 experiments involving different types of flip-flops and counters: 1) D flip-flop and JK flip-flop modules are defined 2) An asynchronous 4-bit up-down counter using JK flip-flops is implemented 3) A 4-bit synchronous up-down counter is created using JK flip-flops and control signals 4) Shift register circuits like SISO and PIPO are built using D flip-flops to shift in and store input bits.

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kamarajvlsi
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© Attribution Non-Commercial (BY-NC)
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49 views

Experiment 3:: 1) D Flipflop

The document describes 8 experiments involving different types of flip-flops and counters: 1) D flip-flop and JK flip-flop modules are defined 2) An asynchronous 4-bit up-down counter using JK flip-flops is implemented 3) A 4-bit synchronous up-down counter is created using JK flip-flops and control signals 4) Shift register circuits like SISO and PIPO are built using D flip-flops to shift in and store input bits.

Uploaded by

kamarajvlsi
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT 3:

1) D FLIPFLOP:
module dff(clk,reset,d,q);
input clk,reset,d;
output q;
reg q;
always@(posedge clk)
begin
if(reset==1)
q=0;
else q=d;
end
endmodule

OUTPUT:

2) JK FLIPFLOP:
module jkff(clk,reset,j,k,q,q1);
input clk,reset,j,k;
output q,q1;
reg q,q1;
always @(negedge clk)
begin
if(reset==1)
begin
q=0;
q1=1;
end
else
begin
if(j==0&&k==0)
begin
q=q;
q1=q1;
end
else if(j==0&&k==1)

begin
q=0;
q1=1;
end
else if(j==1&&k==0)
begin
q=1;
q1=0;
end
else
begin
q=~q;
q1=~(q1);
end
end
end
endmodule
OUTPUT:

3)SR FLIPFLOP:
module srff(clk,rst,s,r,q,qn);
input clk,rst,s,r;
output q,qn;
reg q;
reg qn;
always @(posedge clk)
begin
if(rst==1)
begin
q=0;
qn=1;
end
else if(s==0&&r==0)
begin

q=q;
qn=qn;
end
else if(s==0&&r==1)
begin
q=0;
qn=1;
end
else if(s==1&&r==0)
begin
q=1;
qn=0;
end
else
begin
q=0;
qn=1;
end
end
endmodule
OUTPUT:

4) 4 BIT RIPPLE COUNTER:


module ripple(clk,reset,vcc,q,qn);
input clk,reset,vcc;
output [3:0]q;
output [3:0]qn;
jkff ff1(clk,reset,vcc,vcc,q[0],qn[0]);
jkff ff2(q[0],reset,vcc,vcc,q[1],qn[1]);
jkff ff3(q[1],reset,vcc,vcc,q[2],qn[2]);
jkff ff4(q[2],reset,vcc,vcc,q[3],qn[3]);
endmodule

module jkff(clk,reset,j,k,q,q1);
input clk,reset,j,k;
output q,q1;
reg q,q1;
always @(negedge clk)
begin
if(reset==1)
begin
q<=0;
q1<=1;
end
else
begin
if(j==0&&k==0)
begin
q<=q;
q1<=q1;
end
else if(j==0&&k==1)
begin
q<=0;
q1<=1;
end
else if(j==1&&k==0)
begin
q<=1;
q1<=0;
end
else if(j==1 && k==1)
begin
q<=~q;
q1<=~(q1);
end
end
end
endmodule
(OR)
module ripple1(clk1,reset,vcc,q,qn);
input clk1,reset,vcc;
output [3:0]q;
output [3:0]qn;
clk1 ff0(clk1,oclk);
jkff ff1(oclk,reset,vcc,vcc,q[0],qn[0]);
jkff ff2(q[0],reset,vcc,vcc,q[1],qn[1]);
jkff ff3(q[1],reset,vcc,vcc,q[2],qn[2]);
jkff ff4(q[2],reset,vcc,vcc,q[3],qn[3]);
endmodule

module jkff(clk1,reset,j,k,q,q1);
input clk1,reset,j,k;
output q,q1;
reg q,q1;
always @(negedge clk1)
begin
if(reset==1)
begin
q<=0;
q1<=1;
end
else
begin
if(j==0&&k==0)
begin
q<=q;
q1<=q1;
end
else if(j==0&&k==1)
begin
q<=0;
q1<=1;
end
else if(j==1&&k==0)
begin
q<=1;
q1<=0;
end
else if(j==1 && k==1)
begin
q<=~q;
q1<=~(q1);
end
end
end
endmodule
module clk1(clk,oclk);
input clk;
output reg oclk;
integer c1;
initial oclk=1;
initial c1=0;
always@(posedge clk)
begin
if(c1==10000000)

begin
oclk=~oclk;
c1=0;
end
else
oclk=oclk;
c1=c1+1;
end
endmodule
OUTPUT:

5) ASYNCHRONOUS 4 BIT UP-DOWN COUNTER:


module asynupdown(clk,rst,vcc,cu,cd,q,qn);
input clk,rst,vcc,cu,cd;
output [3:0]q;
output [3:0]qn;
wire s1,s2,s3,s4,s5,s6,s7,s8,s9;
jkff ff1(clk,rst,vcc,vcc,q[0],qn[0]);
and(s1,cu,q[0]);
and(s2,cd,qn[0]);
or(s3,s1,s2);
jkff ff2(s3,rst,vcc,vcc,q[1],qn[1]);
and(s4,cu,q[1]);
and(s5,cd,qn[1]);
or(s6,s5,s4);
jkff ff3(s6,rst,vcc,vcc,q[2],qn[2]);
and(s7,cu,q[2]);
and(s8,cd,qn[2]);
or(s9,s7,s8);
jkff ff4(s9,rst,vcc,vcc,q[3],qn[3]);
endmodule
module jkff(clk,rst,j,k,q,q1);
input clk,rst,j,k;
output q,q1;
reg q,q1;

always @(negedge clk)


begin
if(rst==1)
begin
q=0;
q1=1;
end
else
begin
if(j==0&&k==0)
begin
q=q;
q1=q1;
end
else if(j==0&&k==1)
begin
q=0;
q1=1;
end
else if(j==1&&k==0)
begin
q=1;
q1=0;
end
else if(j==1&&k==1)
begin
q=~q;
q1=~(q1);
end
end
end
endmodule
OUTPUT:

6) 4 BIT SYNCHRONOUS UP-DOWN COUNTER:


module synupdown(clk,rst,vcc,cu,cd,q,q1);
input clk,rst,vcc,cu,cd;
output [3:0]q;
output [3:0]q1;
wire s1,s2,s3,s4,s5,s6,s7,s8,s9;
jkff ff1(clk,rst,vcc,vcc,q[0],q1[0]);
and(s1,cu,q[0]);
and(s2,cd,q1[0]);
or(s3,s1,s2);
jkff ff2(clk,rst,s3,s3,q[1],q1[1]);
and(s4,s1,q[1]);
and(s5,s2,q1[1]);
or(s6,s4,s5);
jkff ff3(clk,rst,s6,s6,q[2],q1[2]);
and(s7,s4,q[1]);
and(s8,s5,q1[1]);
or(s9,s7,s8);
jkff ff4(clk,rst,s9,s9,q[3],q1[3]);
endmodule
module jkff(clk,rst,j,k,q,q1);
input clk,rst,j,k;
output q,q1;
reg q,q1;
always @(posedge clk)
begin
if(rst==1)
begin
q=0;
q1=1;
end
else
begin
if(j==0&&k==0)
begin
q=q;
q1=q1;
end
else if(j==0&&k==1)
begin
q=0;
q1=1;
end
else if(j==1&&k==0)

begin
q=1;
q1=0;
end
else if(j==1&&k==1)
begin
q=~q;
q1=~(q1);
end
end
end
endmodule
OUTPUT:

7) SISO
module siso(clk,rst,d,q);
input clk,rst;
input d;
output q;
wire q0,q1,q2;
dff ff1(clk,rst,d,q0);
dff ff2(clk,rst,q0,q1);
dff ff3(clk,rst,q1,q2);
dff ff4(clk,rst,q2,q);
endmodule
module dff(clk,reset,d,q);
input clk,reset,d;
output q;
reg q;
always@(posedge clk)
begin
if(reset==1)
q=0;

else q=d;
end
endmodule
OUTPUT:

8) PIPO
module pipo(clk,rst,a,b,c,d,q);
input clk,rst;
input a,b,c,d;
output [3:0]q;
dff ff1(clk,rst,a,q[0]);
dff ff2(clk,rst,b,q[1]);
dff ff3(clk,rst,c,q[2]);
dff ff4(clk,rst,d,q[3]);
endmodule
module dff(clk,reset,d,q);
input clk,reset,d;
output q;
reg q;
always@(posedge clk)
begin
if(reset==1)
q=0;
else q=d;
end
endmodule
OUTPUT:

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