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VLSI Array Subsystems

The document discusses different types of memory arrays including SRAM, DRAM, ROM, and serial access memories. It provides details on ROM cell organization and types of ROM including mask programmed ROM, NAND-based ROM, and flash memory. It also summarizes serial access memories like shift registers, tapped delay lines, and queues.

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Sireesha Tekuru
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5K views

VLSI Array Subsystems

The document discusses different types of memory arrays including SRAM, DRAM, ROM, and serial access memories. It provides details on ROM cell organization and types of ROM including mask programmed ROM, NAND-based ROM, and flash memory. It also summarizes serial access memories like shift registers, tapped delay lines, and queues.

Uploaded by

Sireesha Tekuru
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Array Subsystems

SRAM DRAM ROM Serial Access Memories Content Addressable Memory

Categories of memory arrays

ROM (Read Only Memory)


ROM is a semiconductor memory device used to store data which is permanent. ROM can be manufactured by bipolar as well as MOS technology. The process of storing data into a ROM is called programming the ROM. On the basis of programming, ROM can be classified as, 1) Mask programmable Read Only Memory 2) Programmable Read Only Memory 3) Erasable Programmable Read Only Memory

ROM Cell Organization


A ROM is an array of unidirectional contacts which are selectively open and closed.

These memory locations are addressed by the address decoders.


Address decoders are divided into two parts, one for row selection and another for column selection. This type of addressing is called two dimensional addressing. The decoders may be NAND or NOR based. MOS transistors can be used in place of diodes.

While using nMOS technology each column must be connected to VDD through a nMOS load device.
On the other hand if CMOS technology is used then each column must be connected.

Fig: 16-bit ROM using Diodes

Mask Programmed Memory Circuits


NOR-based ROM
The building block of this ROM is a pseudo-nMOS NOR gate. Unlike in standard CMO , the pMOS pull-up circuitry is replaced by a single pMOS with its gate tied up to GND, hence being permanently on acting as a load resistor. A NOR-based ROM consists of m n-input pseudo-nMOS NOR gates, one n-input NOR per column If none of the nMOS transistor are activated then the output signal c is high. If any of the nMOS transistors is activated then the output signal c is low.

NOR-based ROM

NAND-based ROM
A NAND-based ROM consists of m n-input pseudo-nMOS NAND gates, one n-input NAND per column.

Flash Memory
A flash memory cell uses two gates, one is control gate, another is floating gate. Under the normal mode of operation, there are no charges on the floating gate, and the transistor behaves like a normal transistor with low threshold voltage. When a high voltage is applied is applied to the control gate , the floating gate is charged and the threshold voltage is increased. The transistor becomes permanently OFF. The flash transistors are placed at the cross-point of word line and bit line. If the flash transistor is programmed, its threshold voltage Vt becomes high.

Flash Memory

Serial Access Memories


A Serial access memory is one which the particular memory location is accessed sequentially, that is, ith memory location is accessed only after sequencing through previous (i-1)th memory location. So the access time of a serial memory varies depending on the location to be accessed. Serial access memories do not use an address. - Shift Registers - Tapped Delay Lines - Serial In Parallel Out (SIPO) - Parallel In Serial Out (PISO) - Queues (FIFO, LIFO)

Shift Register
Shift registers store and delay data Simple design: cascade of registers
clk Din 8 Dout

Tapped Delay Line


A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux o Ex: 0 63 stages of delay
clk

SR32
delay5

SR16

SR8

SR4

SR2

SR1

Din

Dout

delay4

delay3

delay2

delay1

delay0

Serial-In-Parallel-Out
1-bit shift register reads in serial data o After N steps, presents N-bit parallel output

clk Sin P0 P1 P2 P3

Parallel-In-Serial-Out
Load all N bits in parallel when shift = 0 o Then shift one bit out per cycle
P0 shift/load clk Sout P1 P2 P3

Queues
Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers)

WriteClk WriteData FULL Queue

ReadClk ReadData EMPTY

FIFO, LIFO Queues


First In First Out (FIFO) o Initialize read and write pointers to first element o Queue is EMPTY o On write, increment write pointer o If write almost catches read, Queue is FULL o On read, increment read pointer Last In First Out (LIFO) o Also called a stack o Use a single stack pointer for read and write

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