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Design of Serial Multiplier

This document summarizes the design and operation of a serial-parallel multiplier. It describes how a 4-bit serial-parallel multiplier works by shifting and adding the multiplicand appropriately based on the bits of the multiplier over multiple clock cycles. The behavioral model of the control unit uses a state machine with states to control shifting and adding the partial products until the final product is obtained after 9 clock cycles.

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Assini Hussain
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136 views

Design of Serial Multiplier

This document summarizes the design and operation of a serial-parallel multiplier. It describes how a 4-bit serial-parallel multiplier works by shifting and adding the multiplicand appropriately based on the bits of the multiplier over multiple clock cycles. The behavioral model of the control unit uses a state machine with states to control shifting and adding the partial products until the final product is obtained after 9 clock cycles.

Uploaded by

Assini Hussain
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design of serial multiplier

Binary unsigned multiplier An eg.

Each partial product is either the multiplicand shifted over by the appropriate number of places or zero Multiplication of two 4-bit numbers require a 4 bit multiplicand register, a 4-bit multiplier register, a 4-bit full adder and an 8-bit register for product, where the product register serves as an accumulator

Serial-Parallel Multiplier A type of binary multiplier

Operation:

State graph:

Behavioral model of control unit: ENTITY mult4x4 IS PORT(clk,st:IN BIT; mplr,mcand:IN BIT_VECTOR(3 DOWNTO 0); done:OUT BIT); END mult4x4; ARCHITECTURE behav OF mult4x4 IS SIGNAL state:INTEGER RANGE 0 TO 9; SIGNAL acc:BIT_VECTOR(8 DOWNTO 0); ALIAS M:BIT IS acc(0);

BEGIN PROCESS BEGIN WAIT UNTIL clk=1; CASE state IS WHEN 0 => IF st =1 THEN acc(8 DOWNTO 4) <= 00000; acc(3 DOWNTO 0) <= mplr; state <= 1; END IF;

WHEN 1|3|5|7 => IF M=1 THEN acc(8 DOWNTO 4) <= add4bit(acc(7 DOWNTO 4),mcand,0); --add4bit( ) is a function to add 4 bit --numbers and was in used library which is not --shown in the model state <= state +1; ELSE acc <= 0 & acc(8 DOWNTO 1); state <= state +2; END IF;

WHEN 2|4|6|8 => acc<= 0 & acc(8 DOWNTO 1); state<=state + 1; WHEN 9 => state <= 0; END CASE; END PROCESS; done <= 1 WHEN state =9 ELSE 0; END behav;

4x4 multiplier require more states for large number of bits Multiplier control with counter reduces states Referred as Counter & Add/Shift control multiplier

Add-shift signals generated properly, but multiplier never stops

Operation

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