LOW POWER VLSI

By, K.Venkataramana reddy 07c31a0458

Why worry about power? --Heat Dissipation

Microprocessor power Consumption

Why we go to Low Power..

PORTABILITY: Enhanced run-time, Reduced weight, Reduced volume, Low cost operation High Performance: Low-cost cooling, Low-cost packaging, Low-cost operation RELIABILITY: Avoid thermal problems Avoid scaling related problems

Speed/Power performance for available Technologies

Where Does Power Go In CMOS

Dynamic Power Consumption : Charging and Discharging Capacitors Short Circuit Currents : Short circuit path between supply rails during switching Leakage: Leakage diodes and transistors

Ptotal = PDYN + PSC + PLeakage =CLVDDF+VDDIPEAK{(Tr + Tf)/2}F+VDD ILEAK

Dynamic Power Consumption

2 dd

Energy/transition = C * V

Dynamic Power Consumption

Power = Energy / Transition * transition rate = CL* V 2 * f dd

So, power is proportional to Vdd , f ,CL

Power dissipation is data dependent Function of switching activity

Reducing Vdd
Power P is proportional to square of V VDD has decreased in modern processes
High VDD would damage modern tiny transistors Lower VDD saves power

VDD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, Further decreasing may cause affect to Threshold voltage Relatively independent of logic function and style. Power Delay Product Improves with lowering Vdd. By reducing Vdd Noise margin will be affected

Noise Margin

NML = VIL - VOL NMH = VOH - VIH

Power Consumption is Data Dependent

Ex: Static 2 i/p NOR Gate

A B Y

A B Y
0 0 1

P(A=1) = P(B=1) = Then P(out=1) = P(out=0) = 1-P(out=1) =1-1/4 =

0
1

1
0

0
0

P(0->1) = P(out=1).P(out=0) = * = 3/16

Transition Probability of 2-input NOR Gate

A B Y

Transition Probabilities for Basic Gates

P0 -> 1
(1-Pa * Pb) Pa Pb AND (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb)) OR EXOR (1-(Pa + Pb - 2Pa * Pb)) (Pa + Pb 2Pa * Pb)
Switching Activity for Static CMOS
P0 -> 1 = P0 * P1

How about Dynamic Circuits..?

Clk In1 In2 In3 Clk
Mp

Out CL PDN

Power is only dissipated when out=0

Ceff = P(out=0) * CL

Me

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

2 input NOR gate

A B Y

0
0 1 1

0
1 0 1

1
0 0 0

P(A=1) = P(B=1) = P(out=0) = Ceff = * CL Switching activity is always Higher in Dynamic Circuits

Transition Probabilities For Dynamic GATES

P0 -> 1
AND OR
(1-Pa * Pb) (1-Pa)(1-Pb)

EXOR (1-(Pa + Pb - 2Pa * Pb))

Switching Activity for Precharged Dynamic Gates

Glitching
Glitching refers to spurious and unwanted transitions that occur before a node settle down to its final steady-state value. Glitching often arises when paths with unbalanced propagation delay converges at the same point in the circuit. The dissipation caused by the spurious transitions can reach up to 25% of the total dissipation for some circuits.

Glitching in Static CMOS

Each gate has Unit delay Input A, B, C arrive at same time. No glitching in dynamic circuits

How to Cope With Glitching..?

Short Circuit Currents

Short circuit currents are encountered only in static design. In static CMOS circuits the flow current from VDD to GND during Switching when both NMOS and PMOS conducting Simultaneously. Such path never exists in a dynamic circuits.

Short Circuit Currents

Vdd

Vin CL

Vout

Vout
2.5

NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat

0.15

IV DD (mA)

0.10

1.5

0.05

NMOS res PMOS off 2.5 Vin

0.5

0.0

1.0

2.0 3.0 Vin (V)

4.0

5.0

0.5

1.5

Impact of rise/fall time on ShortCircuit Currents

V DD V DD

V in

V out CL

V in

V out CL

Large Capacitive Load

The input through the transient region before the output start to change

Small capacitive Load

Output fall time is Substantially smaller than the input rise time

Short-Circuit energy as a function of slope ratio

Short-Circuit energy dissipation (normalized with respect to zero i/p rise time energy) for a static CMOS. The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals. Short-Circuit reduced by lower the Supply Voltage.

Leakage
Vdd

Vout

Drain Junction Leakage Sub-Threshold Current

Sub-Threshold current Dominant factor

Sub-Threshold Current Dominant Factor

Static Power Consumption

Vd d

Dominates over dynamic consumption

Istat Vout CL
Reduce switching activity Not a function of Switching Frequency.

Vin =5V

Pstat = P(In=1).Vdd . Istat

Reduce physical capacitance

nates over dynamic consumption

System-Level optimization : Power Management

In event-driven application, large amounts of power are wasted while the system is in idlemode. The power consumption can be reduced significantly by using power management scheme to shunt down idle component.

Conclusion
Thus the low power can be achieved by decreasing Vdd to certain level. As leakage current cannot be reduced, the short circuit currents are eliminated by dynamic circuits. The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals Glitching makes power to dissipate so it is reduced by cope process

References
Digital Integrated Circuits JAN M.RABAEY Encyclopedia of computer science and technology,1995. VLSI Design Techniques for Analog and Digital Circuits Randall L.Geiger, Phillip E.Allen. Basic VLSI Design A.PUCKNELL. Low-Power CMOS Design IEEE journal of solid state circuit -pages 472-484,Aprill 1992.

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