x86 Assembly Language Reference Manual

Part No: 817547711 March 2010

Copyright 2010 Oracle and/or its affiliates.

All rights reserved.

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Contents

Preface .....................................................................................................................................................7

Overview of the Solaris x86 Assembler ........................................................................................... 11 Assembler Overview ........................................................................................................................... 11 Syntax Differences Between x86 Assemblers ................................................................................... 12 Assembler Command Line ................................................................................................................. 12

Solaris x86 Assembly Language Syntax .......................................................................................... 13 Lexical Conventions ............................................................................................................................ 13 Statements ..................................................................................................................................... 13 Tokens ........................................................................................................................................... 15 Instructions, Operands, and Addressing .......................................................................................... 17 Instructions ................................................................................................................................... 17 Operands ....................................................................................................................................... 18 Assembler Directives .......................................................................................................................... 19

Instruction Set Mapping ....................................................................................................................25 Instruction Overview .......................................................................................................................... 25 General-Purpose Instructions ........................................................................................................... 26 Data Transfer Instructions .......................................................................................................... 26 Binary Arithmetic Instructions .................................................................................................. 29 Decimal Arithmetic Instructions ............................................................................................... 30 Logical Instructions ..................................................................................................................... 31 Shift and Rotate Instructions ...................................................................................................... 31 Bit and Byte Instructions ............................................................................................................. 32 Control Transfer Instructions .................................................................................................... 34 String Instructions ....................................................................................................................... 36
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Contents

I/O Instructions ............................................................................................................................ 37 Flag Control (EFLAG) Instructions ........................................................................................... 38 Segment Register Instructions .................................................................................................... 39 Miscellaneous Instructions ......................................................................................................... 39 Floating-Point Instructions ................................................................................................................ 40 Data Transfer Instructions (Floating Point) ............................................................................. 40 Basic Arithmetic Instructions (Floating-Point) ....................................................................... 41 Comparison Instructions (Floating-Point) .............................................................................. 42 Transcendental Instructions (Floating-Point) ......................................................................... 43 Load Constants (Floating-Point) Instructions ......................................................................... 44 Control Instructions (Floating-Point) ...................................................................................... 44 SIMD State Management Instructions ............................................................................................. 46 MMX Instructions ............................................................................................................................... 46 Data Transfer Instructions (MMX) ........................................................................................... 47 Conversion Instructions (MMX) ............................................................................................... 47 Packed Arithmetic Instructions (MMX) ................................................................................... 48 Comparison Instructions (MMX) ............................................................................................. 49 Logical Instructions (MMX) ....................................................................................................... 49 Shift and Rotate Instructions (MMX) ....................................................................................... 50 State Management Instructions (MMX) ................................................................................... 50 SSE Instructions ................................................................................................................................... 51 SIMD Single-Precision Floating-Point Instructions (SSE) ..................................................... 51 MXCSR State Management Instructions (SSE) ........................................................................ 57 64Bit SIMD Integer Instructions (SSE) ................................................................................... 57 Miscellaneous Instructions (SSE) .............................................................................................. 58 SSE2 Instructions ................................................................................................................................. 59 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions ............................... 59 SSE2 Packed Single-Precision Floating-Point Instructions .................................................... 65 SSE2 128Bit SIMD Integer Instructions .................................................................................. 66 SSE2 Miscellaneous Instructions ............................................................................................... 67 Operating System Support Instructions ........................................................................................... 68 64Bit AMD Opteron Considerations ............................................................................................. 70

Index ......................................................................................................................................................73

x86 Assembly Language Reference Manual March 2010

Tables

TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 310 TABLE 311 TABLE 312 TABLE 313 TABLE 314 TABLE 315 TABLE 316 TABLE 317 TABLE 318 TABLE 319 TABLE 320 TABLE 321 TABLE 322 TABLE 323 TABLE 324 TABLE 325 TABLE 326 TABLE 327 TABLE 328

Data Transfer Instructions ....................................................................................... 26 Binary Arithmetic Instructions ................................................................................ 29 Decimal Arithmetic Instructions ............................................................................ 30 Logical Instructions ................................................................................................... 31 Shift and Rotate Instructions ................................................................................... 31 Bit and Byte Instructions .......................................................................................... 32 Control Transfer Instructions .................................................................................. 34 String Instructions ..................................................................................................... 36 I/O Instructions ......................................................................................................... 38 Flag Control Instructions ......................................................................................... 38 Segment Register Instructions ................................................................................. 39 Miscellaneous Instructions ...................................................................................... 39 Data Transfer Instructions (Floating-Point) .......................................................... 40 Basic Arithmetic Instructions (Floating-Point) ..................................................... 41 Comparison Instructions (Floating-Point) ............................................................ 42 Transcendental Instructions (Floating-Point) ....................................................... 43 Load Constants Instructions (Floating-Point) ...................................................... 44 Control Instructions (Floating-Point) .................................................................... 44 SIMD State Management Instructions ................................................................... 46 Data Transfer Instructions (MMX) ......................................................................... 47 Conversion Instructions (MMX) ............................................................................ 47 Packed Arithmetic Instructions (MMX) ................................................................ 48 Comparison Instructions (MMX) ........................................................................... 49 Logical Instructions (MMX) .................................................................................... 50 Shift and Rotate Instructions (MMX) ..................................................................... 50 State Management Instructions (MMX) ................................................................ 51 Data Transfer Instructions (SSE) ............................................................................. 51 Packed Arithmetic Instructions (SSE) .................................................................... 53
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Tables

TABLE 329 TABLE 330 TABLE 331 TABLE 332 TABLE 333 TABLE 334 TABLE 335 TABLE 336 TABLE 337 TABLE 338 TABLE 339 TABLE 340 TABLE 341 TABLE 342 TABLE 343 TABLE 344 TABLE 345

Comparison Instructions (SSE) ............................................................................... 54 Logical Instructions (SSE) ........................................................................................ 55 Shuffle and Unpack Instructions (SSE) ................................................................... 56 Conversion Instructions (SSE) ................................................................................ 56 MXCSR State Management Instructions (SSE) ..................................................... 57 64Bit SIMD Integer Instructions (SSE) ................................................................ 57 Miscellaneous Instructions (SSE) ............................................................................ 58 SSE2 Data Movement Instructions ......................................................................... 60 SSE2 Packed Arithmetic Instructions ..................................................................... 61 SSE2 Logical Instructions ......................................................................................... 62 SSE2 Compare Instructions ..................................................................................... 63 SSE2 Shuffle and Unpack Instructions .................................................................... 63 SSE2 Conversion Instructions ................................................................................. 64 SSE2 Packed Single-Precision Floating-Point Instructions ................................. 66 SSE2 128Bit SIMD Integer Instructions ............................................................... 66 SSE2 Miscellaneous Instructions ............................................................................. 67 Operating System Support Instructions ................................................................. 68

x86 Assembly Language Reference Manual March 2010

Preface

The x86 Assembly Language Reference Manual documents the syntax of the SolarisTM x86 assembly language. This manual is provided to help experienced programmers understand the assembly language output of Solaris compilers. This manual is neither an introductory book about assembly language programming nor a reference manual for the x86 architecture.
Note In this document the term x86 refers to 64-bit and 32-bit systems manufactured using

processors compatible with the AMD64 or Intel Xeon/Pentium product families. For supported systems, see the Solaris 10 Hardware Compatibility List.

Who Should Use This Book

This manual is intended for experienced x86 assembly language programmers who are familiar with the x86 architecture.

Before You Read This Book

You should have a thorough knowledge of assembly language programming in general and be familiar with the x86 architecture in specific. You should be familiar with the ELF object file format. This manual assumes that you have the following documentation available for reference:

IA-32 Intel Architecture Software Developer's Manual (Intel Corporation, 2004). Volume 1: Basic Architecture. Volume 2: Instruction Set Reference A-M. Volume 3: Instruction Set Reference N-Z. Volume 4: System Programming Guide. AMD64 Architecture Programmer's Manual (Advanced Micro Devices, 2003). Volume 1: Application Programming. Volume 2: System Programming. Volume 3: General-Purpose and System Instructions. Volume 4: 128-Bit Media Instructions. Volume 5: 64-Bit Media and x87 Floating-Point Instructions. Linker and Libraries Guide Sun Studio 9: C User's Guide Sun Studio 9: Fortran User's Guide and Fortran Programming Guide
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Preface

Man pages for the as(1), ld(1), and dis(1) utilities.

How This Book Is Organized

Chapter 1, Overview of the Solaris x86 Assembler, provides an overview of the x86 functionality supported by the Solaris x86 assembler. Chapter 2, Solaris x86 Assembly Language Syntax, documents the syntax of the Solaris x86 assembly language. Chapter 3, Instruction Set Mapping, maps Solaris x86 assembly language instruction mnemonics to the native x86 instruction set.

Accessing Sun Documentation Online

The docs.sun.comSM Web site enables you to access Sun technical documentation online. You can browse the docs.sun.com archive or search for a specific book title or subject. The URL is http://docs.sun.com.

Ordering Sun Documentation

Sun Microsystems offers select product documentation in print. For a list of documents and how to order them, see Buy printed documentation at http://docs.sun.com.

Typographic Conventions
The following table describes the typographic changes that are used in this book.
TABLE P1

Typographic Conventions
Meaning Example

Typeface or Symbol

AaBbCc123

The names of commands, files, and directories, and onscreen computer output

Edit your .login file. Use ls -a to list all files. machine_name% you have mail.

AaBbCc123

What you type, contrasted with onscreen computer output Command-line placeholder: replace with a real name or value

machine_name% su Password: The command to remove a file is rm filename.

AaBbCc123

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Preface

TABLE P1

Typographic Conventions
Meaning

(Continued)
Example

Typeface or Symbol

AaBbCc123

Book titles, new terms, and terms to be emphasized

Read Chapter 6 in the User's Guide. Perform a patch analysis. Do not save the file. [Note that some emphasized items appear bold online.]

Shell Prompts in Command Examples

The following table shows the default system prompt and superuser prompt for the C shell, Bourne shell, and Korn shell.
TABLE P2 Shell

Shell Prompts
Prompt

C shell prompt C shell superuser prompt Bourne shell and Korn shell prompt Bourne shell and Korn shell superuser prompt

machine_name% machine_name# $ #

10

C H A P T E R

Overview of the Solaris x86 Assembler

This chapter provides a brief overview of the Solaris x86 assembler as. This chapter discusses the following topics: Assembler Overview on page 11 Syntax Differences Between x86 Assemblers on page 12 Assembler Command Line on page 12

Assembler Overview
The Solaris x86 assembler as translates Solaris x86 assembly language into Executable and Linking Format (ELF) relocatable object files that can be linked with other object files to create an executable file or a shared object file. (See Chapter 7, Object File Format, in Linker and Libraries Guide, for a complete discussion of ELF object file format.) The assembler supports macro processing by the C preprocessor (cpp) or the m4 macro processor. The assembler supports the instruction sets of the following CPUs: Intel 8086/8088 processors Intel 286 processor Intel386 processor Intel486 processor Intel Pentium processor Intel Pentium Pro processor Intel Pentium II processor Pentium II Xeon processor Intel Celeron processor Intel Pentium III processor Pentium III Xeon processor Advanced Micro Devices Athlon processor Advanced Micro Devices Opteron processor
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Syntax Differences Between x86 Assemblers

Syntax Differences Between x86 Assemblers

There is no standard assembly language for the x86 architecture. Vendor implementations of assemblers for the x86 architecture instruction sets differ in syntax and functionality. The syntax of the Solaris x86 assembler is compatible with the syntax of the assembler distributed with earlier releases of the UNIX operating system (this syntax is sometimes termed AT&T syntax). Developers familiar with other assemblers derived from the original UNIX assemblers, such as the Free Software Foundation's gas, will find the syntax of the Solaris x86 assembler very straightforward. However, the syntax of x86 assemblers distributed by Intel and Microsoft (sometimes termed Intel syntax) differs significantly from the syntax of the Solaris x86 assembler. These differences are most pronounced in the handling of instruction operands:

The Solaris and Intel assemblers use the opposite order for source and destination operands. The Solaris assembler specifies the size of memory operands by adding a suffix to the instruction mnemonic, while the Intel assembler prefixes the memory operands. The Solaris assembler prefixes immediate operands with a dollar sign ($) (ASCII 0x24), while the Intel assembler does not delimit immediate operands.

See Chapter 2, Solaris x86 Assembly Language Syntax, for additional differences between x86 assemblers.

Assembler Command Line

During the translation of higher-level languages such as C and Fortran, the compilers might invoke as using the alias fbe (Fortran back end). You can invoke the assembler manually from the shell command line with either name, as or fbe. See the as(1) man page for the definitive discussion of command syntax and command line options.

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C H A P T E R

Solaris x86 Assembly Language Syntax

This chapter documents the syntax of the Solaris x86 assembly language.

Lexical Conventions on page 13 Instructions, Operands, and Addressing on page 17 Assembler Directives on page 19

Lexical Conventions
This section discusses the lexical conventions of the Solaris x86 assembly language.

Statements
An x86 assembly language program consists of one or more files containing statements. A statement consists of tokens separated by whitespace and terminated by either a newline character (ASCII 0x0A) or a semicolon (;) (ASCII 0x3B). Whitespace consists of spaces (ASCII 0x20), tabs (ASCII 0x09), and formfeeds (ASCII 0x0B) that are not contained in a string or comment. More than one statement can be placed on a single input line provided that each statement is terminated by a semicolon. A statement can consist of a comment. Empty statements, consisting only of whitespace, are allowed.

Comments
A comment can be appended to a statement. The comment consists of the slash character (/) (ASCII 0x2F) followed by the text of the comment. The comment is terminated by the newline that terminates the statement.

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Lexical Conventions

Labels
A label can be placed at the beginning of a statement. During assembly, the label is assigned the current value of the active location counter and serves as an instruction operand. There are two types of lables: symbolic and numeric.

Symbolic Labels
A symbolic label consists of an identifier (or symbol) followed by a colon (:) (ASCII 0x3A). Symbolic labels must be defined only once. Symbolic labels have global scope and appear in the object file's symbol table. Symbolic labels with identifiers beginning with a period (.) (ASCII 0x2E) are considered to have local scope and are not included in the object file's symbol table.

Numeric Labels
A numeric label consists of a single digit in the range zero (0) through nine (9) followed by a colon (:). Numeric labels are used only for local reference and are not included in the object file's symbol table. Numeric labels have limited scope and can be redefined repeatedly. When a numeric label is used as a reference (as an instruction operand, for example), the suffixes b (backward) or f (forward) should be added to the numeric label. For numeric label N, the reference Nb refers to the nearest label N defined before the reference, and the reference Nf refers to the nearest label N defined after the reference. The following example illustrates the use of numeric labels:
1: one: / define numeric label "1" / define symbolic label "one"

/ ... assembler code ... jmp 1f / jump to first numeric label "1" defined / after this instruction / (this reference is equivalent to label "two") / jump to last numeric label "1" defined / before this instruction / (this reference is equivalent to label "one") / redefine label "1" / define symbolic label "two" 1b / jump to last numeric label "1" defined / before this instruction / (this reference is equivalent to label "two")

jmp

1b

1: two: jmp

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Lexical Conventions

Tokens
There are five classes of tokens:

Identifiers (symbols) Keywords Numerical constants String Constants Operators

Identifiers
An identifier is an arbitrarily-long sequence of letters and digits. The first character must be a letter; the underscore (_) (ASCII 0x5F) and the period (.) (ASCII 0x2E) are considered to be letters. Case is significant: uppercase and lowercase letters are different.

Keywords
Keywords such as x86 instruction mnemonics (opcodes) and assembler directives are reserved for the assembler and should not be used as identifiers. See Chapter 3, Instruction Set Mapping, for a list of the Solaris x86 mnemonics. See Assembler Directives on page 19 for the list of as assembler directives.

Numerical Constants
Numbers in the x86 architecture can be integers or floating point. Integers can be signed or unsigned, with signed integers represented in two's complement representation. Floating-point numbers can be: single-precision floating-point; double-precision floating-point; and double-extended precision floating-point.

Integer Constants
Integers can be expressed in several bases:

Decimal. Decimal integers begin with a non-zero digit followed by zero or more decimal digits (09). Binary. Binary integers begin with 0b or 0B followed by zero or more binary digits (0, 1). Octal. Octal integers begin with zero (0) followed by zero or more octal digits (07). Hexadecimal. Hexadecimal integers begin with 0x or 0X followed by one or more hexadecimal digits (09, AF). Hexadecimal digits can be either uppercase or lowercase.

Chapter 2 Solaris x86 Assembly Language Syntax

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Lexical Conventions

Floating Point Constants

Floating point constants have the following format:

Sign (optional) either plus (+) or minus () Integer (optional) zero or more decimal digits (09) Fraction (optional) decimal point (.) followed by zero or more decimal digits Exponent (optional) the letter e or E, followed by an optional sign (plus or minus), followed by one or more decimal digits (09)

A valid floating point constant must have either an integer part or a fractional part.

String Constants
A string constant consists of a sequence of characters enclosed in double quotes ( ") (ASCII 0x22). To include a double-quote character ("), single-quote character (), or backslash character (\) within a string, precede the character with a backslash (\) (ASCII 0x5C). A character can be expressed in a string as its ASCII value in octal preceded by a backslash (for example, the letter J could be expressed as \112). The assembler accepts the following escape sequences in strings:
Escape Sequence Character Name ASCII Value (hex)

\n \r \b \t \f \v

newline carriage return backspace horizontal tab form feed vertical tab

0A 0D 08 09 0C 0B

Operators
The assembler supports the following operators for use in expressions. Operators have no assigned precedence. Expressions can be grouped in square brackets ([]) to establish precedence. + \* \/ &
16

Addition Subtraction Multiplication Division Bitwise logical AND

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Instructions, Operands, and Addressing

| >> << \% ! ^

Bitwise logical OR Shift right Shift left Remainder Bitwise logical AND NOT Bitwise logical XOR

Note The asterisk (*), slash (/), and percent sign (%) characters are overloaded. When used as operators in an expression, these characters must be preceded by the backslash character (\).

Instructions, Operands, and Addressing

Instructions are operations performed by the CPU. Operands are entities operated upon by the instruction. Addresses are the locations in memory of specified data.

Instructions
An instruction is a statement that is executed at runtime. An x86 instruction statement can consist of four parts:

Label (optional) Instruction (required) Operands (instruction specific) Comment (optional)

See Statements on page 13 for the description of labels and comments. The terms instruction and mnemonic are used interchangeably in this document to refer to the names of x86 instructions. Although the term opcode is sometimes used as a synonym for instruction, this document reserves the term opcode for the hexadecimal representation of the instruction value. For most instructions, the Solaris x86 assembler mnemonics are the same as the Intel or AMD mnemonics. However, the Solaris x86 mnemonics might appear to be different because the Solaris mnemonics are suffixed with a one-character modifier that specifies the size of the instruction operands. That is, the Solaris assembler derives its operand type information from the instruction name and the suffix. If a mnemonic is specified with no type suffix, the operand type defaults to long. Possible operand types and their instruction suffixes are:

Chapter 2 Solaris x86 Assembly Language Syntax

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Instructions, Operands, and Addressing

b w l q

Byte (8bit) Word (16bit) Long (32bit) (default) Quadword (64bit)

The assembler recognizes the following suffixes for x87 floating-point instructions: [no suffix] l (long) s (short) Instruction operands are registers only Instruction operands are 64bit Instruction operands are 32bit

See Chapter 3, Instruction Set Mapping, for a mapping between Solaris x86 assembly language mnemonics and the equivalent Intel or AMD mnemonics.

Operands
An x86 instruction can have zero to three operands. Operands are separated by commas (,) (ASCII 0x2C). For instructions with two operands, the first (lefthand) operand is the source operand, and the second (righthand) operand is the destination operand (that is, sourcedestination).
Note The Intel assembler uses the opposite order (destinationsource) for operands.

Operands can be immediate (that is, constant expressions that evaluate to an inline value), register (a value in the processor number registers), or memory (a value stored in memory). An indirect operand contains the address of the actual operand value. Indirect operands are specified by prefixing the operand with an asterisk (*) (ASCII 0x2A). Only jump and call instructions can use indirect operands.

Immediate operands are prefixed with a dollar sign ($) (ASCII 0x24) Register names are prefixed with a percent sign (%) (ASCII 0x25) Memory operands are specified either by the name of a variable or by a register that contains the address of a variable. A variable name implies the address of a variable and instructs the computer to reference the contents of memory at that address. Memory references have the following syntax: segment:offset(base, index, scale).

Segment is any of the x86 architecture segment registers. Segment is optional: if specified, it must be separated from offset by a colon (:). If segment is omitted, the value of %ds (the default segment register) is assumed.

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Assembler Directives

Offset is the displacement from segment of the desired memory value. Offset is optional. Base and index can be any of the general 32bit number registers. Scale is a factor by which index is to be multipled before being added to base to specify the address of the operand. Scale can have the value of 1, 2, 4, or 8. If scale is not specified, the default value is 1.

Some examples of memory addresses are: movl var, %eax movl %cs:var, %eax Move the contents of memory location var into number register %eax. Move the contents of memory location var in the code segment (register %cs) into number register %eax. Move the address of var into number register %eax. Add the address of memory location array_base to the contents of number register %esi to determine an address in memory. Move the contents of this address into number register %eax. Multiply the contents of number register %esi by 4 and add the result to the contents of number register %ebx to produce a memory reference. Move the contents of this memory location into number register %eax. Multiply the contents of number register %esi by 4, add the result to the contents of number register %ebx, and add the result to the address of struct_base to produce an address. Move the contents of this address into number register %eax.

movl $var, %eax movl array_base(%esi), %eax

movl (%ebx, %esi, 4), %eax

movl struct_base(%ebx, %esi, 4), %eax

Assembler Directives
Directives are commands that are part of the assembler syntax but are not related to the x86 processor instruction set. All assembler directives begin with a period (.) (ASCII 0x2E).

Chapter 2 Solaris x86 Assembly Language Syntax

19

Assembler Directives

.align integer, pad The .align directive causes the next data generated to be aligned modulo integer bytes. Integer must be a positive integer expression and must be a power of 2. If specified, pad is an integer bye value used for padding. The default value of pad for the text section is 0x90 (nop); for other sections, the default value of pad is zero (0). .ascii "string" The .ascii directive places the characters in string into the object module at the current location but does not terminate the string with a null byte (\0). String must be enclosed in double quotes (") (ASCII 0x22). The .ascii directive is not valid for the .bss section. .bcd integer The .bcd directive generates a packed decimal (80-bit) value into the current section. The .bcd directive is not valid for the .bss section. .bss The .bss directive changes the current section to .bss. .bss symbol, integer Define symbol in the .bss section and add integer bytes to the value of the location counter for .bss. When issued with arguments, the .bss directive does not change the current section to .bss. Integer must be positive. .byte byte1,byte2,...,byteN The .byte directive generates initialized bytes into the current section. The .byte directive is not valid for the .bss section. Each byte must be an 8-bit value. .2byte expression1, expression2, ..., expressionN Refer to the description of the .value directive. .4byte expression1, expression2, ..., expressionN Refer to the description of the .long directive. .8byte expression1, expression2, ..., expressionN Refer to the description of the .quad directive. .comm name, size,alignment The .comm directive allocates storage in the data section. The storage is referenced by the identifier name. Size is measured in bytes and must be a positive integer. Name cannot be predefined. Alignment is optional. If alignment is specified, the address of name is aligned to a multiple of alignment. .data The .data directive changes the current section to .data. .double float The .double directive generates a double-precision floating-point constant into the current section. The .double directive is not valid for the .bss section. .even The .even directive aligns the current program counter (.) to an even boundary.
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Assembler Directives

.ext expression1, expression2, ..., expressionN The .ext directive generates an 80387 80bit floating point constant for each expression into the current section. The .ext directive is not valid for the .bss section. .file "string" The .file directive creates a symbol table entry where string is the symbol name and STT_FILE is the symbol table type. String specifies the name of the source file associated with the object file. .float float The .float directive generates a single-precision floating-point constant into the current section. The .float directive is not valid in the .bss section. .globl symbol1, symbol2, ..., symbolN The .globl directive declares each symbol in the list to be global. Each symbol is either defined externally or defined in the input file and accessible in other files. Default bindings for the symbol are overridden. A global symbol definition in one file satisfies an undefined reference to the same global symbol in another file. Multiple definitions of a defined global symbol are not allowed. If a defined global symbol has more than one definition, an error occurs. The .globl directive only declares the symbol to be global in scope, it does not define the symbol. .group group, section, #comdat The .group directive adds section to a COMDAT group. Refer to COMDAT Section in Linker and Libraries Guide for additional information about COMDAT. .hidden symbol1, symbol2, ..., symbolN The .hidden directive declares each symbol in the list to have hidden linker scoping. All references to symbol within a dynamic module bind to the definition within that module. Symbol is not visible outside of the module. .ident "string" The .ident directive creates an entry in the .comment section containing string. String is any sequence of characters, not including the double quote ("). To include the double quote character within a string, precede the double quote character with a backslash (\) (ASCII 0x5C). .lcomm name, size, alignment The .lcomm directive allocates storage in the .bss section. The storage is referenced by the symbol name, and has a size of size bytes. Name cannot be predefined, and size must be a positive integer. If alignment is specified, the address of name is aligned to a multiple of alignment bytes. If alignment is not specified, the default alignment is 4 bytes. .local symbol1, symbol2, ..., symbolN The .local directive declares each symbol in the list to be local. Each symbol is defined in the input file and not accessible to other files. Default bindings for the symbols are overridden. Symbols declared with the .local directive take precedence over weak and global symbols. (See Symbol Table Section in Linker and Libraries Guide for a description of global and
Chapter 2 Solaris x86 Assembly Language Syntax 21

Assembler Directives

weak symbols.) Because local symbols are not accessible to other files, local symbols of the same name may exist in multiple files. The .local directive only declares the symbol to be local in scope, it does not define the symbol. .long expression1, expression2, ..., expressionN The .long directive generates a long integer (32-bit, two's complement value) for each expression into the current section. Each expression must be a 32bit value and must evaluate to an integer value. The .long directive is not valid for the .bss section. .popsection The .popsection directive pops the top of the section stack and continues processing of the popped section. .previous The .previous directive continues processing of the previous section. .pushsection section The .pushsection directive pushes the specified section onto the section stack and switches to another section. .quad expression1, expression2, ..., expressionN The .quad directive generates an initialized word (64-bit, two's complement value) for each expression into the current section. Each expression must be a 64-bit value, and must evaluate to an integer value. The .quad directive is not valid for the .bss section. .rel symbol@ type The .rel directive generates the specified relocation entry type for the specified symbol. The .lit directive supports TLS (thread-local storage). Refer to Chapter 8, Thread-Local Storage, in Linker and Libraries Guide for additional information about TLS. .section section, attributes The .section directive makes section the current section. If section does not exist, a new section with the specified name and attributes is created. If section is a non-reserved section, attributes must be included the first time section is specified by the .section directive. .set symbol, expression The .set directive assigns the value of expression to symbol. Expression can be any legal expression that evaluates to a numerical value. .skip integer, value While generating values for any data section, the .skip directive causes integer bytes to be skipped over, or, optionally, filled with the specified value. .sleb128 expression The .sleb128 directive generates a signed, little-endian, base 128 number from expression. .string "string" The .string directive places the characters in string into the object module at the current location and terminates the string with a null byte (\0). String must be enclosed in double quotes (") (ASCII 0x22). The .string directive is not valid for the .bss section.
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Assembler Directives

.symbolic symbol1, symbol2, ..., symbolN The .symbolic directive declares each symbol in the list to havesymbolic linker scoping. All references to symbol within a dynamic module bind to the definition within that module. Outside of the module, symbol is treated as global. .tbss The .tbss directive changes the current section to .tbss. The .tbss section contains uninitialized TLS data objects that will be initialized to zero by the runtime linker. .tcomm The .tcomm directive defines a TLS common block. .tdata The .tdata directive changes the current section to .tdata. The .tdata section contains the initialization image for initialized TLS data objects. .text The .text directive defines the current section as .text. .uleb128 expression The .uleb128 directive generates an unsigned, little-endian, base 128 number from expression. .value expression1, expression2, ..., expressionN The .value directive generates an initialized word (16-bit, two's complement value) for each expression into the current section. Each expression must be a 16-bit integer value. The .value directive is not valid for the .bss section. .weak symbol1, symbol2, ..., symbolN The .weak directive declares each symbol in the argument list to be defined either externally or in the input file and accessible to other files. Default bindings of the symbol are overridden by the .weak directive. A weak symbol definition in one file satisfies an undefined reference to a global symbol of the same name in another file. Unresolved weak symbols have a default value of zero. The link editor does not resolve these symbols. If a weak symbol has the same name as a defined global symbol, the weak symbol is ignored and no error results. The .weak directive does not define the symbol. .zero expression While filling a data section, the .zero directive fills the number of bytes specified by expression with zero (0).

Chapter 2 Solaris x86 Assembly Language Syntax

23

24

C H A P T E R

Instruction Set Mapping

This chapter provides a general mapping between the Solaris x86 assembly language mnemonics and the Intel or Advanced Micro Devices (AMD) mnemonics.

Instruction Overview on page 25 General-Purpose Instructions on page 26 Floating-Point Instructions on page 40 SIMD State Management Instructions on page 46 MMX Instructions on page 46 SSE Instructions on page 51 SSE2 Instructions on page 59 Operating System Support Instructions on page 68 64Bit AMD Opteron Considerations on page 70

Instruction Overview
It is beyond the scope of this manual to document the x86 architecture instruction set. This chapter provides a general mapping between the Solaris x86 assembly language mnemonics and the Intel or AMD mnemonics to enable you to refer to your vendor's documentation for detailed information about a specific instruction. Instructions are grouped by functionality in tables with the following sections:

Solaris mnemonic Intel/AMD mnemonic Description (short) Notes

For certain Solaris mnemonics, the allowed data type suffixes for that mnemonic are indicated in braces ({}) following the mnemonic. For example, bswap{lq} indicates that the following mnemonics are valid: bswap, bswapl (which is the default and equivalent to bswap), and bswapq. See Instructions on page 17 for information on data type suffixes. To locate a specific Solaris x86 mnemonic, look up the mnemonic in the index.
25

General-Purpose Instructions

General-Purpose Instructions
The general-purpose instructions perform basic data movement, memory addressing, arithmetic and logical operations, program flow control, input/output, and string operations on integer, pointer, and BCD data types.

Data Transfer Instructions

The data transfer instructions move data between memory and the general-purpose and segment registers, and perform operations such as conditional moves, stack access, and data conversion.
TABLE 31

Data Transfer Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

bswap{lq}

BSWAP

byte swap convert byte to word convert doubleword to quadword convert doubleword to quadword

bswapq valid only under -xarch=amd64

cbtw cltd

CBW CDQ

%eax %edx:%eax %eax %rax cltq valid only under -xarch=amd64

cltq

CDQE

cmova{wlq}, cmov{wlq}.a cmovae{wlq}, cmov{wlq}.ae cmovb{wlq}, cmov{wlq}.b cmovbe{wlq}, cmov{wlq}.be cmovc{wlq}, cmov{wlq}.c cmove{wlq}, cmov{wlq}.e cmovg{wlq}, cmov{wlq}.g

CMOVA

conditional move if above cmovaq valid only under -xarch=amd64 conditional move if above cmovaeq valid only under or equal -xarch=amd64 conditional move if below cmovbq valid only under -xarch=amd64 conditional move if below cmovbeq valid only under or equal -xarch=amd64 conditional move if carry conditional move if equal conditional move if greater cmovcq valid only under -xarch=amd64 cmoveq valid only under -xarch=amd64 cmovgq valid only under -xarch=amd64

CMOVAE

CMOVB

CMOVBE

CMOVC

CMOVE

CMOVG

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TABLE 31

Data Transfer Instructions

CMOVGE

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

cmovge{wlq}, cmov{wlq}.ge cmovl{wlq}, cmov{wlq}.l cmovle{wlq}, cmov{wlq}.le cmovna{wlq}, cmov{wlq}.na cmovnae{wlq}, cmov{wlq}.nae cmovnb{wlq}, cmov{wlq}.nb cmovnbe{wlq}, cmov{wlq}.nbe cmovnc{wlq}, cmov{wlq}.nc cmovne{wlq}, cmov{wlq}.ne cmovng{wlq}, cmov{wlq}.ng cmovnge{wlq}, cmov{wlq}.nge cmovnl{wlq}, cmov{wlq}.nl cmovnle{wlq}, cmov{wlq}.nle cmovno{wlq}, cmov{wlq}.no cmovnp{wlq}, cmov{wlq}.np cmovns{wlq}, cmov{wlq}.ns cmovnz{wlq}, cmov{wlq}.nz

conditional move if greater or equal conditional move if less

cmovgeq valid only under -xarch=amd64 cmovlq valid only under -xarch=amd64

CMOVL

COMVLE

conditional move if less or cmovleq valid only under equal -xarch=amd64 conditional move if not above conditional move if not above or equal conditional move if not below conditional move if not below or equal conditional move if not carry conditional move if not equal conditional move if greater conditional move if not greater or equal conditional move if not less conditional move if not above or equal conditional move if not overflow conditional move if not parity conditional move if not sign (non-negative) conditional move if not zero cmovnaq valid only under -xarch=amd64 cmovnaeq valid only under -xarch=amd64 cmovnbq valid only under -xarch=amd64 cmovnbeq valid only under -xarch=amd64 cmovncq valid only under -xarch=amd64 cmovneq valid only under -xarch=amd64 cmovngq valid only under -xarch=amd64 cmovngeq valid only under -xarch=amd64 cmovnlq valid only under -xarch=amd64 cmovnleq valid only under -xarch=amd64 cmovnoq valid only under -xarch=amd64 cmovnpq valid only under -xarch=amd64 cmovnsq valid only under -xarch=amd64 cmovnzq valid only under -xarch=amd64

CMOVNA

CMOVNAE

CMOVNB

CMOVNBE

CMOVNC

CMOVNE

CMOVNG

CMOVNGE

CMOVNL

CMOVNLE

CMOVNO

CMOVNP

CMOVNS

CMOVNZ

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General-Purpose Instructions

TABLE 31

Data Transfer Instructions

CMOVO

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

cmovo{wlq}, cmov{wlq}.o cmovp{wlq}, cmov{wlq}.p cmovpe{wlq}, cmov{wlq}.pe cmovpo{wlq}, cmov{wlq}.po cmovs{wlq}, cmov{wlq}.s cmovz{wlq}, cmov{wlq}.z cmpxchg{bwlq}

conditional move if overflow

cmovoq valid only under -xarch=amd64

CMOVP

conditional move if parity cmovpq valid only under -xarch=amd64 conditional move if parity cmovpeq valid only under even -xarch=amd64 conditional move if parity cmovpoq valid only under odd -xarch=amd64 conditional move if sign (negative) conditional move if zero compare and exchange compare and exchange 8 bytes convert quadword to octword %rax %rdx:%rax cqtd valid only under -xarch=amd64 %rax %rdx:%rax cqto valid only under -xarch=amd64 %ax %dx:%ax %ax %eax cmovsq valid only under -xarch=amd64 cmovzq valid only under -xarch=amd64 cmpxchgq valid only under -xarch=amd64

CMOVPE

CMOVPO

CMOVS

CMOVZ

CMPXCHG

cmpxchg8b

CMPXCHG8B

cqtd

CQO

cqto

CQO

convert quadword to octword

cwtd

CWD

convert word to doubleword convert word to doubleword in %eax register

cwtl

CWDE

mov{bwlq}

MOV

move data between movq valid only under immediate values, general -xarch=amd64 purpose registers, segment registers, and memory move immediate value to register movabs valid only under -xarch=amd64

movabs{bwlq}

MOVABS

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TABLE 31

Data Transfer Instructions

MOVABS

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

movabs{bwlq}A

move immediate value to register {AL, AX, GAX, RAX} move and sign extend move and zero extend pop stack pop general-purpose registers from stack pop general-purpose registers from stack push onto stack push general-purpose registers onto stack push general-purpose registers onto stack exchange and add exchange exchange

movabs valid only under -xarch=amd64 movsbq and movswq valid only under -xarch=amd64 movzbq and movzwq valid only under -xarch=amd64 popq valid only under -xarch=amd64 popaw invalid under -xarch=amd64 invalid under -xarch=amd64 pushq valid only under -xarch=amd64 pushaw invalid under -xarch=amd64 invalid under -xarch=amd64 xaddq valid only under -xarch=amd64 xchgq valid only under -xarch=amd64 xchgqA valid only under -xarch=amd64

movsb{wlq}, movsw{lq}

MOVSX

movzb{wlq}, movzw{lq}

MOVZX

pop{wlq}

POP

popaw

POPA

popal, popa

POPAD

push{wlq}

PUSH

pushaw

PUSHA

pushal, pusha

PUSHAD

xadd{bwlq}

XADD

xchg{bwlq}

XCHG

xchg{bwlq}A

XCHG

Binary Arithmetic Instructions

The binary arithmetic instructions perform basic integer computions on operands in memory or the general-purpose registers.
TABLE 32

Binary Arithmetic Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

adc{bwlq}

ADC

add with carry

adcq valid only under -xarch=amd64

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General-Purpose Instructions

TABLE 32

Binary Arithmetic Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

add{bwlq}

ADD

integer add compare decrement divide (unsigned) divide (signed) multiply (signed) increment multiply (unsigned) negate subtract with borrow subtract

addq valid only under -xarch=amd64 cmpq valid only under -xarch=amd64 decq valid only under -xarch=amd64 divq valid only under -xarch=amd64 idivq valid only under -xarch=amd64 imulq valid only under -xarch=amd64 incq valid only under -xarch=amd64 mulq valid only under -xarch=amd64 negq valid only under -xarch=amd64 sbbq valid only under -xarch=amd64 subq valid only under -xarch=amd64

cmp{bwlq}

CMP

dec{bwlq}

DEC

div{bwlq}

DIV

idiv{bwlq}

IDIV

imul{bwlq}

IMUL

inc{bwlq}

INC

mul{bwlq}

MUL

neg{bwlq}

NEG

sbb{bwlq}

SBB

sub{bwlq}

SUB

Decimal Arithmetic Instructions

The decimal arithmetic instructions perform decimal arithmetic on binary coded decimal (BCD) data.
TABLE 33

Decimal Arithmetic Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

aaa

AAA

ASCII adjust after addition ASCII adjust before division

invalid under -xarch=amd64 invalid under -xarch=amd64

aad

AAD

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TABLE 33

Decimal Arithmetic Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

aam

AAM

ASCII adjust after multiplication ASCII adjust after subtraction decimal adjust after addition decimal adjust after subtraction

invalid under -xarch=amd64 invalid under -xarch=amd64 invalid under -xarch=amd64 invalid under -xarch=amd64

aas

AAS

daa

DAA

das

DAS

Logical Instructions
The logical instructions perform basic logical operations on their operands.
TABLE 34

Logical Instructions
Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

and{bwlq}

AND

bitwise logical AND bitwise logical NOT bitwise logical OR bitwise logical exclusive OR

andq valid only under -xarch=amd64 notq valid only under -xarch=amd64 orq valid only under -xarch=amd64 xorq valid only under -xarch=amd64

not{bwlq}

NOT

or{bwlq}

OR

xor{bwlq}

XOR

Shift and Rotate Instructions

The shift and rotate instructions shift and rotate the bits in their operands.
TABLE 35

Shift and Rotate Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

rcl{bwlq}

RCL

rotate through carry left

rclq valid only under -xarch=amd64

rcr{bwlq}

RCR

rotate through carry right rcrq valid only under -xarch=amd64

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General-Purpose Instructions

TABLE 35

Shift and Rotate Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

rol{bwlq}

ROL

rotate left rotate right shift arithmetic left shift arithmetic right shift logical left shift left double shift logical right shift right double

rolq valid only under -xarch=amd64 rorq valid only under -xarch=amd64 salq valid only under -xarch=amd64 sarq valid only under -xarch=amd64 shlq valid only under -xarch=amd64 shldq valid only under -xarch=amd64 shrq valid only under -xarch=amd64 shrdq valid only under -xarch=amd64

ror{bwlq}

ROR

sal{bwlq}

SAL

sar{bwlq}

SAR

shl{bwlq}

SHL

shld{bwlq}

SHLD

shr{bwlq}

SHR

shrd{bwlq}

SHRD

Bit and Byte Instructions

The bit instructions test and modify individual bits in operands. The byte instructions set the value of a byte operand to indicate the status of flags in the %eflags register.
TABLE 36

Bit and Byte Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

bsf{wlq}

BSF

bit scan forward bit scan reverse bit test bit test and complement bit test and reset

bsfq valid only under -xarch=amd64 bsrq valid only under -xarch=amd64 btq valid only under -xarch=amd64 btcq valid only under -xarch=amd64 btrq valid only under -xarch=amd64

bsr{wlq}

BSR

bt{wlq}

BT

btc{wlq}

BTC

btr{wlq}

BTR

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TABLE 36

Bit and Byte Instructions

BTS

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

bts{wlq}

bit test and set set byte if above set byte if above or equal set byte if below set byte if below or equal set byte if carry set byte if equal set byte if greater set byte if greater or equal set byte if less set byte if less or equal set byte if not above set byte if not above or equal set byte if not below set byte if not below or equal set byte if not carry set byte if not equal set byte if not greater set byte if not greater or equal set byte if not less set byte if not less or equal set byte if not overflow set byte if not parity set byte if not sign (non-negative) set byte if not zero

btsq valid only under -xarch=amd64

seta setae setb setbe setc sete setg setge setl setle setna setnae

SETA SETAE SETB SETBE SETC SETE SETG SETGE SETL SETLE SETNA SETNAE

setnb setnbe

SETNB SETNBE

setnc setne setng setnge

SETNC SETNE SETNG SETNGE

setnl setnle setno setnp setns

SETNL SETNLE SETNO SETNP SETNS

setnz

SETNZ

Chapter 3 Instruction Set Mapping

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General-Purpose Instructions

TABLE 36

Bit and Byte Instructions

SETO SETP SETPE SETPO SETS SETZ TEST

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

seto setp setpe setpo sets setz test{bwlq}

set byte if overflow set byte if parity set byte if parity even set byte if parity odd set byte if sign (negative) set byte if zero logical compare testq valid only under -xarch=amd64

Control Transfer Instructions

The control transfer instructions control the flow of program execution.
TABLE 37

Control Transfer Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

bound{wl}

BOUND

detect value out of range call procedure high-level procedure entry software interrupt interrupt on overflow return from interrupt jump if above jump if above or equal jump if below jump if below or equal jump if carry jump register %cx zero jump if equal

boundw invalid under -xarch=amd64

call enter

CALL ENTER

int into

INT INTO

invalid under -xarch=amd64

iret ja jae jb jbe jc jcxz je

IRET JA JAE JB JBE JC JCXZ JE

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TABLE 37

Control Transfer Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

jecxz

JECXZ

jump register %ecx zero jump if greater jump if greater or equal jump if less jump if less or equal jump jump if not above or equal jump if not below jump if not below or equal jump if not carry jump if not equal jump if not greater jump if not greater or equal jump if not less jump if not less or equal jump if not overflow jump if not parity jump if not sign (non-negative) jump if not zero jump if overflow jump if parity jump if parity even jump if parity odd jump if sign (negative) jump if zero

invalid under -xarch=amd64

jg jge jl jle jmp jnae jnb jnbe jnc jne jng jnge

JG JGE JL JLE JMP JNAE JNB JNBE JNC JNE JNG JNGE

jnl jnle jno jnp jns

JNL JNLE JNO JNP JNS

jnz jo jp jpe jpo js jz

JNZ JO JP JPE JPO JS JZ

Chapter 3 Instruction Set Mapping

35

General-Purpose Instructions

TABLE 37

Control Transfer Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

lcall

CALL

call far procedure high-level procedure exit loop with %ecx counter loop with %ecx and equal loop with %ecx and not equal loop with %ecx and not zero loop with %ecx and zero

valid as indirect only for -xarg=amd64

leave loop loope loopne

LEAVE LOOP LOOPE LOOPNE

loopnz

LOOPNZ

loopz lret

LOOPZ RET

return from far procedure valid as indirect only for -xarg=amd64 return

ret

RET

String Instructions
The string instructions operate on strings of bytes. Operations include storing strings in memory, loading strings from memory, comparing strings, and scanning strings for substrings.
Note The Solaris mnemonics for certain instructions differ slightly from the Intel/AMD mnemonics. Alphabetization of the table below is by the Solaris mnemonic. All string operations default to long (doubleword).
TABLE 38

String Instructions
Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cmps{q}

CMPS

compare string compare byte string compare doubleword string compare word string load string

cmpsq valid only under -xarch=amd64

cmpsb cmpsl

CMPSB CMPSD

cmpsw lods{q}

CMPSW LODS

lodsq valid only under -xarch=amd64

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TABLE 38

String Instructions
LODSB LODSD LODSW MOVS

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

lodsb lodsl lodsw movs{q}

load byte string load doubleword string load word string move string move byte string move doubleword string move word string repeat while %ecx not zero repeat while not equal repeat while not zero repeat while equal repeat while zero scan string scan byte string scan doubleword string scan word string store string store byte string store doubleword string store word string stosq valid only under -xarch=amd64 scasq valid only under -xarch=amd64 movsw is not movsw{lq}. See Table 31 movsq valid only under -xarch=amd64 movsb is not movsb{wlq}. See Table 31

movsb

MOVSB

movsl, smovl movsw, smovw

MOVSD MOVSW

rep repnz repnz repz repz scas{q}

REP REPNE REPNZ REPE REPZ SCAS

scasb scasl scasw stos{q}

SCASB SCASD SCASW STOS

stosb stosl stosw

STOSB STOSD STOSW

I/O Instructions
The input/output instructions transfer data between the processor's I/O ports, registers, and memory.

Chapter 3 Instruction Set Mapping

37

General-Purpose Instructions

TABLE 39

I/O Instructions
Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

in ins insb

IN INS INSB

read from a port input string from a port input byte string from port input doubleword string from port input word string from port write to a port output string to port output byte string to port output doubleword string to port output word string to port

insl

INSD

insw

INSW

out outs outsb outsl

OUT OUTS OUTSB OUTSD

outsw

OUTSW

Flag Control (EFLAG) Instructions

The status flag control instructions operate on the bits in the %eflags register.
TABLE 310

Flag Control Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

clc cld cli cmc lahf popfw popf{lq}

CLC CLD CLI CMC LAHF POPF POPFL

clear carry flag clear direction flag clear interrupt flag complement carry flag load flags into %ah register pop %eflags from stack pop %eflags from stack push %eflags onto stack popfq valid only under -xarch=amd64

pushfw

PUSHF

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TABLE 310

Flag Control Instructions

PUSHFL

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

pushf{lq}

push %eflags onto stack store %ah register into flags set carry flag set direction flag set interrupt flag

pushfq valid only under -xarch=amd64

sahf

SAHF

stc std sti

STC STD STI

Segment Register Instructions

The segment register instructions load far pointers (segment addresses) into the segment registers.
TABLE 311

Segment Register Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

lds{wl}

LDS

load far pointer using %ds ldsl and ldsw invalid under -xarch=amd64 load far pointer using %es lesl and lesw invalid under -xarch=amd64 load far pointer using %fs load far pointer using %gs load far pointer using %ss

les{wl}

LES

lfs{wl} lgs{wl} lss{wl}

LFS LGS LSS

Miscellaneous Instructions
The instructions documented in this section provide a number of useful functions.
TABLE 312

Miscellaneous Instructions
Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cpuid lea{wlq}

CPUID LEA

processor identification load effective address no operation leaq valid only under -xarch=amd64

nop

NOP

Chapter 3 Instruction Set Mapping

39

Floating-Point Instructions

TABLE 312

Miscellaneous Instructions
UD2 XLAT XLATB

(Continued)
Description Notes

Solaris Mnemonic

Intel/AMD Mnemonic

ud2 xlat xlatb

undefined instruction table lookup translation table lookup translation

Floating-Point Instructions
The floating point instructions operate on floating-point, integer, and binary coded decimal (BCD) operands.

Data Transfer Instructions (Floating Point)

The data transfer instructions move floating-point, integer, and BCD values between memory and the floating point registers.
TABLE 313

Data Transfer Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fbld fbstp fcmovb

FBLD FBSTP FCMOVB

load BCD store BCD and pop floating-point conditional move if below floating-point conditional move if below or equal floating-point conditional move if equal floating-point conditional move if not below floating-point conditional move if not below or equal floating-point conditional move if not equal floating-point conditional move if unordered

fcmovbe

FCMOVBE

fcmove

FCMOVE

fcmovnb

FCMOVNB

fcmovnbe

FCMOVNBE

fcmovne

FCMOVNE

fcmovnu

FCMOVNU

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TABLE 313

Data Transfer Instructions (Floating-Point)

Intel/AMD Mnemonic

(Continued)
Notes

Solaris Mnemonic

Description

fcmovu

FCMOVU

floating-point conditional move if unordered load integer store integer store integer and pop load floating-point value store floating-point value store floating-point value and pop exchange registers

fild fist fistp fld fst fstp

FILD FIST FISTP FLD FST FSTP

fxch

FXCH

Basic Arithmetic Instructions (Floating-Point)

The basic arithmetic instructions perform basic arithmetic operations on floating-point and integer operands.
TABLE 314

Basic Arithmetic Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fabs fadd faddp

FABS FADD FADDP

absolute value add floating-point add floating-point and pop change sign divide floating-point divide floating-point and pop divide floating-point reverse divide floating-point reverse and pop add integer divide integer

fchs fdiv fdivp

FCHS FDIV FDIVP

fdivr

FDIVR

fdivrp

FDIVRP

fiadd fidiv

FIADD FIDIV

Chapter 3 Instruction Set Mapping

41

Floating-Point Instructions

TABLE 314

Basic Arithmetic Instructions (Floating-Point)

Intel/AMD Mnemonic Description

(Continued)
Notes

Solaris Mnemonic

fidivr fimul fisub fisubr fmul fmulp

FIDIVR FIMUL FISUB FISUBR FMUL FMULP

divide integer reverse multiply integer subtract integer subtract integer reverse multiply floating-point multiply floating-point and pop partial remainder IEEE partial remainder round to integer scale by power of two square root subtract floating-point subtract floating-point and pop subtract floating-point reverse subtract floating-point reverse and pop extract exponent and significand

fprem fprem1 frndint fscale fsqrt fsub fsubp

FPREM FPREM1 FRNDINT FSCALE FSQRT FSUB FSUBP

fsubr

FSUBR

fsubrp

FSUBRP

fxtract

FXTRACT

Comparison Instructions (Floating-Point)

The floating-point comparison instructions operate on floating-point or integer operands.
TABLE 315

Comparison Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fcom fcomi

FCOM FCOMI

compare floating-point compare floating-point and set %eflags

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x86 Assembly Language Reference Manual March 2010

Floating-Point Instructions

TABLE 315

Comparison Instructions (Floating-Point)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

fcomip

FCOMIP

compare floating-point, set %eflags, and pop compare floating-point and pop compare floating-point and pop twice compare integer compare integer and pop test floating-point (compare with 0.0) unordered compare floating-point unordered compare floating-point and set %eflags unordered compare floating-point, set %eflags, and pop unordered compare floating-point and pop compare floating-point and pop twice examine floating-point

fcomp

FCOMP

fcompp

FCOMPP

ficom ficomp ftst

FICOM FICOMP FTST

fucom

FUCOM

fucomi

FUCOMI

fucomip

FUCOMIP

fucomp

FUCOMP

fucompp

FUCOMPP

fxam

FXAM

Transcendental Instructions (Floating-Point)

The transcendental instructions perform trigonometric and logarithmic operations on floating-point operands.
TABLE 316

Transcendental Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes
x

Solaris Mnemonic

f2xm1 fcos fpatan

F2XM1 FCOS FPATAN

computes 2 1 cosine partial arctangent

Chapter 3 Instruction Set Mapping

43

Floating-Point Instructions

TABLE 316

Transcendental Instructions (Floating-Point)

Intel/AMD Mnemonic

(Continued)
Notes

Solaris Mnemonic

Description

fptan fsin fsincos fyl2x fyl2xp1

FPTAN FSIN FSINCOS FYL2X FYL2XP1

partial tangent sine sine and cosine computes y * log2x computes y * log2(x+1)

Load Constants (Floating-Point) Instructions

The load constants instructions load common constants, such as , into the floating-point registers.
TABLE 317

Load Constants Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fld1 fldl2e fldl2t fldlg2 fldln2 fldpi fldz

FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ

load +1.0 load log2e load log210 load log102 load loge2 load load +0.0

Control Instructions (Floating-Point)

The floating-point control instructions operate on the floating-point register stack and save and restore the floating-point state.
TABLE 318

Control Instructions (Floating-Point)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fclex

FCLEX

clear floating-point exception flags after checking for error conditions

44

x86 Assembly Language Reference Manual March 2010

Floating-Point Instructions

TABLE 318

Control Instructions (Floating-Point)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

fdecstp

FDECSTP

decrement floating-point register stack pointer free floating-point register increment floating-point register stack pointer initialize floating-point unit after checking error conditions load floating-point unit control word load floating-point unit environment clear floating-point exception flags without checking for error conditions initialize floating-point unit without checking error conditions floating-point no operation save floating-point unit state without checking error conditions store floating-point unit control word without checking error conditions store floating-point unit environment without checking error conditions store floating-point unit status word without checking error conditions restore floating-point unit state

ffree

FFREE

fincstp

FINCSTP

finit

FINIT

fldcw

FLDCW

fldenv

FLDENV

fnclex

FNCLEX

fninit

FNINIT

fnop

FNOP

fnsave

FNSAVE

fnstcw

FNSTCW

fnstenv

FNSTENV

fnstsw

FNSTSW

frstor

FRSTOR

Chapter 3 Instruction Set Mapping

45

SIMD State Management Instructions

TABLE 318

Control Instructions (Floating-Point)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

fsave

FSAVE

save floating-point unit state after checking error conditions store floating-point unit control word after checking error conditions store floating-point unit environment after checking error conditions store floating-point unit status word after checking error conditions wait for floating-point unit wait for floating-point unit

fstcw

FSTCW

fstenv

FSTENV

fstsw

FSTSW

fwait

FWAIT

wait

WAIT

SIMD State Management Instructions

The fxsave and fxrstor instructions save and restore the state of the floating-point unit and the MMX, XMM, and MXCSR registers.
TABLE 319

SIMD State Management Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

fxrstor

FXRSTOR

restore floating-point unit and SIMD state save floating-point unit and SIMD state

fxsave

FXSAVE

MMX Instructions
The MMX instructions enable x86 processors to perform single-instruction, multiple-data(SIMD) operations on packed byte, word, doubleword, or quadword integer operands contained in memory, in MMX registers, or in general-purpose registers.

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MMX Instructions

Data Transfer Instructions (MMX)

The data transfer instructions move doubleword and quadword operands between MMX registers and between MMX registers and memory.
TABLE 320

Data Transfer Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

movd

MOVD

move doubleword move quadword

movdq valid only under -xarch=amd64 valid only under -xarch=amd64

movq

MOVQ

Conversion Instructions (MMX)

The conversion instructions pack and unpack bytes, words, and doublewords.
TABLE 321

Conversion Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

packssdw

PACKSSDW

pack doublewords into words with signed saturation pack words into bytes with signed saturation pack words into bytes with unsigned saturation unpack high-order bytes unpack high-order doublewords unpack high-order words unpack low-order bytes unpack low-order doublewords unpack low-order words

packsswb

PACKSSWB

packuswb

PACKUSWB

punpckhbw punpckhdq

PUNPCKHBW PUNPCKHDQ

punpckhwd punpcklbw punpckldq

PUNPCKHWD PUNPCKLBW PUNPCKLDQ

punpcklwd

PUNPCKLWD

Chapter 3 Instruction Set Mapping

47

MMX Instructions

Packed Arithmetic Instructions (MMX)

The packed arithmetic instructions perform packed integer arithmetic on packed byte, word, and doubleword integers.
TABLE 322

Packed Arithmetic Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

paddb paddd

PADDB PADDD

add packed byte integers add packed doubleword integers add packed signed byte integers with signed saturation add packed signed word integers with signed saturation add packed unsigned byte integers with unsigned saturation add packed unsigned word integers with unsigned saturation add packed word integers multiply and add packed word integers multiply packed signed word integers and store high result multiply packed signed word integers and store low result subtract packed byte integers subtract packed doubleword integers subtract packed signed byte integers with signed saturation

paddsb

PADDSB

paddsw

PADDSW

paddusb

PADDUSB

paddusw

PADDUSW

paddw pmaddwd

PADDW PMADDWD

pmulhw

PMULHW

pmullw

PMULLW

psubb

PSUBB

psubd

PSUBD

psubsb

PSUBSB

48

x86 Assembly Language Reference Manual March 2010

MMX Instructions

TABLE 322

Packed Arithmetic Instructions (MMX)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

psubsw

PSUBSW

subtract packed signed word integers with signed saturation subtract packed unsigned byte integers with unsigned saturation subtract packed unsigned word integers with unsigned saturation subtract packed word integers

psubusb

PSUBUSB

psubusw

PSUBUSW

psubw

PSUBW

Comparison Instructions (MMX)

The compare instructions compare packed bytes, words, or doublewords.
TABLE 323

Comparison Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

pcmpeqb

PCMPEQB

compare packed bytes for equal compare packed doublewords for equal compare packed words for equal compare packed signed byte integers for greater than compare packed signed doubleword integers for greater than compare packed signed word integers for greater than

pcmpeqd

PCMPEQD

pcmpeqw

PCMPEQW

pcmpgtb

PCMPGTB

pcmpgtd

PCMPGTD

pcmpgtw

PCMPGTW

Logical Instructions (MMX)

The logical instructions perform logical operations on quadword operands.
Chapter 3 Instruction Set Mapping 49

MMX Instructions

TABLE 324

Logical Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

pand pandn por pxor

PAND PANDN POR PXOR

bitwise logical AND bitwise logical AND NOT bitwise logical OR bitwise logical XOR

Shift and Rotate Instructions (MMX)

The shift and rotate instructions operate on packed bytes, words, doublewords, or quadwords in 64bit operands.
TABLE 325

Shift and Rotate Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

pslld

PSLLD

shift packed doublewords left logical shift packed quadword left logical shift packed words left logical shift packed doublewords right arithmetic shift packed words right arithmetic shift packed doublewords right logical shift packed quadword right logical shift packed words right logical

psllq

PSLLQ

psllw

PSLLW

psrad

PSRAD

psraw

PSRAW

psrld

PSRLD

psrlq

PSRLQ

psrlw

PSRLW

State Management Instructions (MMX)

The emms (EMMS) instruction clears the MMX state from the MMX registers.
50 x86 Assembly Language Reference Manual March 2010

SSE Instructions

TABLE 326

State Management Instructions (MMX)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

emms

EMMS

empty MMX state

SSE Instructions
SSE instructions are an extension of the SIMD execution model introduced with the MMX technology. SSE instructions are divided into four subgroups:

SIMD single-precision floating-point instructions that operate on the XMM registers MXSCR state management instructions 64bit SIMD integer instructions that operate on the MMX registers Instructions that provide cache control, prefetch, and instruction ordering functionality

SIMD Single-Precision Floating-Point Instructions (SSE)

The SSE SIMD instructions operate on packed and scalar single-precision floating-point values located in the XMM registers or memory.

Data Transfer Instructions (SSE)

The SSE data transfer instructions move packed and scalar single-precision floating-point operands between XMM registers and between XMM registers and memory.
TABLE 327

Data Transfer Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

movaps

MOVAPS

move four aligned packed single-precision floating-point values between XMM registers or memory move two packed single-precision floating-point values from the high quadword of an XMM register to the low quadword of another XMM register

movhlps

MOVHLPS

Chapter 3 Instruction Set Mapping

51

SSE Instructions

TABLE 327

Data Transfer Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

movhps

MOVHPS

move two packed single-precision floating-point values to or from the high quadword of an XMM register or memory move two packed single-precision floating-point values from the low quadword of an XMM register to the high quadword of another XMM register move two packed single-precision floating-point values to or from the low quadword of an XMM register or memory extract sign mask from four packed single-precision floating-point values move scalar single-precision floating-point value between XMM registers or memory move four unaligned packed single-precision floating-point values between XMM registers or memory

movlhps

MOVLHPS

movlps

MOVLPS

movmskps

MOVMSKPS

movss

MOVSS

movups

MOVUPS

Packed Arithmetic Instructions (SSE)

SSE packed arithmetic instructions perform packed and scalar arithmetic operations on packed and scalar single-precision floating-point operands.

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SSE Instructions

TABLE 328

Packed Arithmetic Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

addps

ADDPS

add packed single-precision floating-point values add scalar single-precision floating-point values divide packed single-precision floating-point values divide scalar single-precision floating-point values return maximum packed single-precision floating-point values return maximum scalar single-precision floating-point values return minimum packed single-precision floating-point values return minimum scalar single-precision floating-point values. multiply packed single-precision floating-point values multiply scalar single-precision floating-point values compute reciprocals of packed single-precision floating-point values compute reciprocal of scalar single-precision floating-point values

addss

ADDSS

divps

DIVPS

divss

DIVSS

maxps

MAXPS

maxss

MAXSS

minps

MINPS

minss

MINSS

mulps

MULPS

mulss

MULSS

rcpps

RCPPS

rcpss

RCPSS

Chapter 3 Instruction Set Mapping

53

SSE Instructions

TABLE 328

Packed Arithmetic Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

rsqrtps

RSQRTPS

compute reciprocals of square roots of packed single-precision floating-point values compute reciprocal of square root of scalar single-precision floating-point values compute square roots of packed single-precision floating-point values compute square root of scalar single-precision floating-point values subtract packed single-precision floating-point values subtract scalar single-precision floating-point values

rsqrtss

RSQRTSS

sqrtps

SQRTPS

sqrtss

SQRTSS

subps

SUBPS

subss

SUBSS

Comparison Instructions (SSE)

The SEE compare instructions compare packed and scalar single-precision floating-point operands.
TABLE 329

Comparison Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cmpps

CMPPS

compare packed single-precision floating-point values compare scalar single-precision floating-point values

cmpss

CMPSS

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SSE Instructions

TABLE 329

Comparison Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

comiss

COMISS

perform ordered comparison of scalar single-precision floating-point values and set flags in EFLAGS register perform unordered comparison of scalar single-precision floating-point values and set flags in EFLAGS register

ucomiss

UCOMISS

Logical Instructions (SSE)

The SSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations on packed single-precision floating-point operands.
TABLE 330

Logical Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

andnps

ANDNPS

perform bitwise logical AND NOT of packed single-precision floating-point values perform bitwise logical AND of packed single-precision floating-point values perform bitwise logical OR of packed single-precision floating-point values perform bitwise logical XOR of packed single-precision floating-point values

andps

ANDPS

orps

ORPS

xorps

XORPS

Shuffle and Unpack Instructions (SSE)

The SSE shuffle and unpack instructions shuffle or interleave single-precision floating-point values in packed single-precision floating-point operands.
Chapter 3 Instruction Set Mapping 55

SSE Instructions

TABLE 331

Shuffle and Unpack Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

shufps

SHUFPS

shuffles values in packed single-precision floating-point operands unpacks and interleaves the two high-order values from two single-precision floating-point operands unpacks and interleaves the two low-order values from two single-precision floating-point operands

unpckhps

UNPCKHPS

unpcklps

UNPCKLPS

Conversion Instructions (SSE)

The SSE conversion instructions convert packed and individual doubleword integers into packed and scalar single-precision floating-point values.
TABLE 332

Conversion Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cvtpi2ps

CVTPI2PS

convert packed doubleword integers to packed single-precision floating-point values convert packed single-precision floating-point values to packed doubleword integers convert doubleword integer to scalar single-precision floating-point value convert scalar single-precision floating-point value to a doubleword integer

cvtps2pi

CVTPS2PI

cvtsi2ss

CVTSI2SS

cvtss2si

CVTSS2SI

56

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SSE Instructions

TABLE 332

Conversion Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

cvttps2pi

CVTTPS2PI

convert with truncation packed single-precision floating-point values to packed doubleword integers convert with truncation scalar single-precision floating-point value to scalar doubleword integer

cvttss2si

CVTTSS2SI

MXCSR State Management Instructions (SSE)

The MXCSR state management instructions save and restore the state of the MXCSR control and status register.
TABLE 333

MXCSR State Management Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

ldmxcsr stmxcsr

LDMXCSR STMXCSR

load %mxcsr register save %mxcsr register state

64Bit SIMD Integer Instructions (SSE)

The SSE 64bit SIMD integer instructions perform operations on packed bytes, words, or doublewords in MMX registers.
TABLE 334

64Bit SIMD Integer Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

pavgb

PAVGB

compute average of packed unsigned byte integers compute average of packed unsigned byte integers extract word insert word

pavgw

PAVGW

pextrw pinsrw

PEXTRW PINSRW

Chapter 3 Instruction Set Mapping

57

SSE Instructions

TABLE 334

64Bit SIMD Integer Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

pmaxsw

PMAXSW

maximum of packed signed word integers maximum of packed unsigned byte integers minimum of packed signed word integers minimum of packed unsigned byte integers move byte mask multiply packed unsigned integers and store high result compute sum of absolute differences shuffle packed integer word in MMX register

pmaxub

PMAXUB

pminsw

PMINSW

pminub

PMINUB

pmovmskb pmulhuw

PMOVMSKB PMULHUW

psadbw

PSADBW

pshufw

PSHUFW

Miscellaneous Instructions (SSE)

The following instructions control caching, prefetching, and instruction ordering.
TABLE 335

Miscellaneous Instructions (SSE)

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

maskmovq

MASKMOVQ

non-temporal store of selected bytes from an MMX register into memory non-temporal store of four packed single-precision floating-point values from an XMM register into memory non-temporal store of quadword from an MMX register into memory

movntps

MOVNTPS

movntq

MOVNTQ

58

x86 Assembly Language Reference Manual March 2010

SSE2 Instructions

TABLE 335

Miscellaneous Instructions (SSE)

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

prefetchnta

PREFETCHNTA

prefetch data into non-temporal cache structure and into a location close to the processor prefetch data into all levels of the cache hierarchy prefetch data into level 2 cache and higher prefetch data into level 2 cache and higher serialize store operations

prefetcht0

PREFETCHT0

prefetcht1

PREFETCHT1

prefetcht2

PREFETCHT2

sfence

SFENCE

SSE2 Instructions
SSE2 instructions are an extension of the SIMD execution model introduced with the MMX technology and the SSE extensions. SSE2 instructions are divided into four subgroups:

Packed and scalar double-precision floating-point instructions Packed single-precision floating-point conversion instructions 128bit SIMD integer instructions Instructions that provide cache control and instruction ordering functionality

SSE2 Packed and Scalar Double-Precision Floating-Point Instructions

The SSE2 packed and scalar double-precision floating-point instructions operate on double-precision floating-point operands.

SSE2 Data Movement Instructions

The SSE2 data movement instructions move double-precision floating-point data between XMM registers and memory.

Chapter 3 Instruction Set Mapping

59

SSE2 Instructions

TABLE 336

SSE2 Data Movement Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

movapd

MOVAPD

move two aligned packed double-precision floating-point values between XMM registers and memory move high packed double-precision floating-point value to or from the high quadword of an XMM register and memory move low packed single-precision floating-point value to or from the low quadword of an XMM register and memory extract sign mask from two packed double-precision floating-point values move scalar double-precision floating-point value between XMM registers and memory. move two unaligned packed double-precision floating-point values between XMM registers and memory

movhpd

MOVHPD

movlpd

MOVLPD

movmskpd

MOVMSKPD

movsd

MOVSD

movupd

MOVUPD

SSE2 Packed Arithmetic Instructions

The SSE2 arithmetic instructions operate on packed and scalar double-precision floating-point operands.

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SSE2 Instructions

TABLE 337

SSE2 Packed Arithmetic Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

addpd

ADDPD

add packed double-precision floating-point values add scalar double-precision floating-point values divide packed double-precision floating-point values divide scalar double-precision floating-point values return maximum packed double-precision floating-point values return maximum scalar double-precision floating-point value return minimum packed double-precision floating-point values return minimum scalar double-precision floating-point value multiply packed double-precision floating-point values multiply scalar double-precision floating-point values compute packed square roots of packed double-precision floating-point values compute scalar square root of scalar double-precision floating-point value

addsd

ADDSD

divpd

DIVPD

divsd

DIVSD

maxpd

MAXPD

maxsd

MAXSD

minpd

MINPD

minsd

MINSD

mulpd

MULPD

mulsd

MULSD

sqrtpd

SQRTPD

sqrtsd

SQRTSD

Chapter 3 Instruction Set Mapping

61

SSE2 Instructions

TABLE 337

SSE2 Packed Arithmetic Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

subpd

SUBPD

subtract packed double-precision floating-point values subtract scalar double-precision floating-point values

subsd

SUBSD

SSE2 Logical Instructions

The SSE2 logical instructions operate on packed double-precision floating-point values.
TABLE 338

SSE2 Logical Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

andnpd

ANDNPD

perform bitwise logical AND NOT of packed double-precision floating-point values perform bitwise logical AND of packed double-precision floating-point values perform bitwise logical OR of packed double-precision floating-point values perform bitwise logical XOR of packed double-precision floating-point values

andpd

ANDPD

orpd

ORPD

xorpd

XORPD

SSE2 Compare Instructions

The SSE2 compare instructions compare packed and scalar double-precision floating-point values and return the results of the comparison to either the destination operand or to the EFLAGS register.

62

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SSE2 Instructions

TABLE 339

SSE2 Compare Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cmppd

CMPPD

compare packed double-precision floating-point values compare scalar double-precision floating-point values perform ordered comparison of scalar double-precision floating-point values and set flags in EFLAGS register perform unordered comparison of scalar double-precision floating-point values and set flags in EFLAGS register

cmpsd

CMPSD

comisd

COMISD

ucomisd

UCOMISD

SSE2 Shuffle and Unpack Instructions

The SSE2 shuffle and unpack instructions operate on packed double-precision floating-point operands.
TABLE 340

SSE2 Shuffle and Unpack Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

shufpd

SHUFPD

shuffle values in packed double-precision floating-point operands unpack and interleave the high values from two packed double-precision floating-point operands unpack and interleave the low values from two packed double-precision floating-point operands

unpckhpd

UNPCKHPD

unpcklpd

UNPCKLPD

Chapter 3 Instruction Set Mapping

63

SSE2 Instructions

SSE2 Conversion Instructions

The SSE2 conversion instructions convert packed and individual doubleword integers into packed and scalar double-precision floating-point values (and vice versa). These instructions also convert between packed and scalar single-precision and double-precision floating-point values.
TABLE 341

SSE2 Conversion Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cvtdq2pd

CVTDQ2PD

convert packed doubleword integers to packed double-precision floating-point values convert packed double-precision floating-point values to packed doubleword integers convert packed double-precision floating-point values to packed doubleword integers convert packed double-precision floating-point values to packed single-precision floating-point values convert packed doubleword integers to packed double-precision floating-point values convert packed single-precision floating-point values to packed double-precision floating-point values convert scalar double-precision floating-point values to a doubleword integer

cvtpd2dq

CVTPD2DQ

cvtpd2pi

CVTPD2PI

cvtpd2ps

CVTPD2PS

cvtpi2pd

CVTPI2PD

cvtps2pd

CVTPS2PD

cvtsd2si

CVTSD2SI

64

x86 Assembly Language Reference Manual March 2010

SSE2 Instructions

TABLE 341

SSE2 Conversion Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

cvtsd2ss

CVTSD2SS

convert scalar double-precision floating-point values to scalar single-precision floating-point values convert doubleword integer to scalar double-precision floating-point value convert scalar single-precision floating-point values to scalar double-precision floating-point values convert with truncation packed double-precision floating-point values to packed doubleword integers convert with truncation packed double-precision floating-point values to packed doubleword integers convert with truncation scalar double-precision floating-point values to scalar doubleword integers

cvtsi2sd

CVTSI2SD

cvtss2sd

CVTSS2SD

cvttpd2dq

CVTTPD2DQ

cvttpd2pi

CVTTPD2PI

cvttsd2si

CVTTSD2SI

SSE2 Packed Single-Precision Floating-Point Instructions

The SSE2 packed single-precision floating-point instructions operate on single-precision floating-point and integer operands.

Chapter 3 Instruction Set Mapping

65

SSE2 Instructions

TABLE 342

SSE2 Packed Single-Precision Floating-Point Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

cvtdq2ps

CVTDQ2PS

convert packed doubleword integers to packed single-precision floating-point values convert packed single-precision floating-point values to packed doubleword integers convert with truncation packed single-precision floating-point values to packed doubleword integers

cvtps2dq

CVTPS2DQ

cvttps2dq

CVTTPS2DQ

SSE2 128Bit SIMD Integer Instructions

The SSE2 SIMD integer instructions operate on packed words, doublewords, and quadwords contained in XMM and MMX registers.
TABLE 343

SSE2 128Bit SIMD Integer Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

movdq2q

MOVDQ2Q

move quadword integer from XMM to MMX registers move aligned double quadword move unaligned double quadword move quadword integer from MMX to XMM registers add packed quadword integers multiply packed unsigned doubleword integers

movdqa

MOVDQA

movdqu

MOVDQU

movq2dq

MOVQ2DQ

paddq

PADDQ

pmuludq

PMULUDQ

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x86 Assembly Language Reference Manual March 2010

SSE2 Instructions

TABLE 343

SSE2 128Bit SIMD Integer Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

pshufd

PSHUFD

shuffle packed doublewords shuffle packed high words shuffle packed low words shift double quadword left logical shift double quadword right logical subtract packed quadword integers unpack high quadwords unpack low quadwords

pshufhw pshuflw pslldq

PSHUFHW PSHUFLW PSLLDQ

psrldq

PSRLDQ

psubq

PSUBQ

punpckhqdq punpcklqdq

PUNPCKHQDQ PUNPCKLQDQ

SSE2 Miscellaneous Instructions

The SSE2 instructions described below provide additional functionality for caching non-temporal data when storing data from XMM registers to memory, and provide additional control of instruction ordering on store operations.
TABLE 344

SSE2 Miscellaneous Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

clflush

CLFLUSH

flushes and invalidates a memory operand and its associated cache line from all levels of the processor's cache hierarchy serializes load operations non-temporal store of selected bytes from an XMM register into memory serializes load and store operations

lfence maskmovdqu

LFENCE MASKMOVDQU

mfence

MFENCE

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Operating System Support Instructions

TABLE 344

SSE2 Miscellaneous Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

movntdq

MOVNTDQ

non-temporal store of double quadword from an XMM register into memory non-temporal store of a doubleword from a general-purpose register into memory non-temporal store of two packed double-precision floating-point values from an XMM register into memory improves the performance of spin-wait loops movntiq valid only under -xarch=amd64

movnti

MOVNTI

movntpd

MOVNTPD

pause

PAUSE

Operating System Support Instructions

The operating system support instructions provide functionality for process management, performance monitoring, debugging, and other systems tasks.
TABLE 345

Operating System Support Instructions

Intel/AMD Mnemonic Description Notes

Solaris Mnemonic

arpl

ARPL

adjust requested privilege level clear the task-switched flag halt processor invalidate cache, no writeback invalidate TLB entry load access rights load global descriptor table (GDT) register larq valid only under -xarch=amd64

clts

CLTS

hlt invd

HLT INVD

invlpg lar

INVLPG LAR

lgdt

LGDT

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Operating System Support Instructions

TABLE 345

Operating System Support Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

lidt

LIDT

load interrupt descriptor table (IDT) register load local descriptor table (LDT) register load machine status word lock bus load segment limit load task register read model-specific register read performance monitoring counters read time stamp counter return from system management mode (SMM) store global descriptor table (GDT) register store interrupt descriptor table (IDT) register store local descriptor table (LDT) register sldtq valid only under -xarch=amd64 lslq valid only under -xarch=amd64

lldt

LLDT

lmsw lock lsl

LMSW LOCK LSL

ltr rdmsr

LTR RDMSR

rdpmc

RDPMC

rdtsc rsm

RDTSC RSM

sgdt

SGDT

sidt

SIDT

sldt

SLDT

smsw

SMSW

store machine status word smswq valid only under -xarch=amd64 store task register fast system call, transfers to a flat protected model kernel at CPL=0 fast system call, transfers to a flat protected mode kernal at CPL=3 verify segment for reading strq valid only under -xarch=amd64

str

STR

sysenter

SYSENTER

sysexit

SYSEXIT

verr

VERR

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69

64Bit AMD Opteron Considerations

TABLE 345

Operating System Support Instructions

Intel/AMD Mnemonic

(Continued)
Description Notes

Solaris Mnemonic

verw wbinvd

VERW WBINVD

verify segment for writing invalidate cache, with writeback write model-specific register

wrmsr

WRMSR

64Bit AMD Opteron Considerations

To assemble code for the AMD Opteron CPU, invoke the assembler with the -xarch=amd64 command line option. See the as(1) man page for additional information. The following Solaris mnemonics are only valid when the -xarch=amd64 command line option is specified: adcq addq andq bsfq bsrq bswapq btcq btq btrq btsq cltq cmovaeq cmovaq cmovbeq cmovbq cmovcq cmoveq cmovgeq cmovgq cmovleq cmovlq cmovnaeq cmovnaq cmovnbeq cmovnbq cmovncq
70

cmovneq cmovngeq cmovngq cmovnleq cmovnlq cmovnoq cmovnpq cmovnsq cmovnzq cmovoq cmovpeq cmovpoq cmovpq cmovsq cmovzq cmpq cmpsq cmpxchgq cqtd cqto decq divq idivq imulq incq larq

leaq lodsq lslq movabs movdq movntiq movq movsq movswq movzwq mulq negq notq orq popfq popq pushfq pushq rclq rcrq rolq rorq salq sarq sbbq scasq

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64Bit AMD Opteron Considerations

shldq shlq shrdq shrq sldtq

smswq stosq strq subq testq

xaddq xchgq xchgqA xorq

The following Solaris mnemonics are not valid when the -xarch=amd64 command line option is specified: aaa aad aam aas boundw daa das into jecxz ldsw lesw popa popaw pusha pushaw

Chapter 3 Instruction Set Mapping

71

72

Index

A
aaa, 30 aad, 30 aam, 31 aas, 31 adc, 29 add, 30 addpd, 61 addps, 53 addressing, 18 addsd, 61 addss, 53 .align, 20 and, 31 andnpd, 62 andnps, 55 andpd, 62 andps, 55 arpl, 68 as, 11 command line, 12 ELF object file, 11 macro processing, 11 syntax, UNIX versus Intel, 12 .ascii, 20 assembler, See as

bit instructions, 32 bound, 34 bsf, 32 bsr, 32 .bss, 20 bswap, 26 bt, 32 btc, 32 btr, 32 bts, 33 .2byte, 20 .4byte, 20 .8byte, 20 .byte, 20 byte instructions, 32

C
call, 34 cbtw, 26 clc, 38 cld, 38 clflush, 67 cli, 38 cltd, 26 cltq, 26 clts, 68 cmc, 38 cmov.a, 26 cmova, 26 cmov.ae, 26

B
.bcd, 20 binary arithmetic instructions, 29

73

Index

cmovae, 26 cmov.b, 26 cmovb, 26 cmov.be, 26 cmovbe, 26 cmov.c, 26 cmovc, 26 cmov.e, 26 cmove, 26 cmov.g, 26 cmovg, 26 cmov.ge, 27 cmovge, 27 cmov.l, 27 cmovl, 27 cmov.le, 27 cmovle, 27 cmov.na, 27 cmovna, 27 cmov.nae, 27 cmovnae, 27 cmov.nb, 27 cmovnb, 27 cmov.nbe, 27 cmovnbe, 27 cmov.nc, 27 cmovnc, 27 cmov.ne, 27 cmovne, 27 cmov.ng, 27 cmovng, 27 cmov.nge, 27 cmovnge, 27 cmov.nl, 27 cmovnl, 27 cmov.nle, 27 cmovnle, 27 cmov.no, 27 cmovno, 27 cmov.np, 27 cmovnp, 27 cmov.ns, 27 cmovns, 27 cmov.nz, 27
74

cmovnz, 27 cmov.o, 28 cmovo, 28 cmov.p, 28 cmovp, 28 cmovpe, 28 cmovpo, 28 cmovs, 28 cmovz, 28 cmp, 30 cmppd, 63 cmpps, 54 cmps, 36 cmpsb, 36 cmpsd, 63 cmpsl, 36 cmpss, 54 cmpsw, 36 cmpxchg, 28 cmpxchg8b, 28 comisd, 63 comiss, 55 .comm, 20 comment, 13 control transfer instructions, 34 cpp, 11 cpuid, 39 cqtd, 28 cqto, 28 cvtdq2pd, 64 cvtdq2ps, 66 cvtpd2dq, 64 cvtpd2pi, 64 cvtpd2ps, 64 cvtpi2pd, 64 cvtpi2ps, 56 cvtps2dq, 66 cvtps2pd, 64 cvtps2pi, 56 cvtsd2si, 64 cvtsd2ss, 65 cvtsi2sd, 65 cvtsi2ss, 56 cvtss2sd, 65
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Index

cvtss2si, 56 cvttpd2dq, 65 cvttpd2pi, 65 cvttps2dq, 66 cvttps2pi, 57 cvttsd2si, 65 cvttss2si, 57 cwtd, 28 cwtl, 28

D
daa, 31 das, 31 .data, 20 data transfer instructions, 26 dec, 30 decimal arithmetic instructions, 30 directives, 19 div, 30 divpd, 61 divps, 53 divsd, 61 divss, 53 .double, 20

E
ELF object file, 11 emms, 50 enter, 34 .even, 20 .ext, 20

F
f2xm1, 43 fabs, 41 fadd, 41 faddp, 41 fbe, See as fbld, 40

fbstp, 40 fchs, 41 fclex, 44 fcmovb, 40 fcmovbe, 40 fcmove, 40 fcmovnb, 40 fcmovnbe, 40 fcmovne, 40 fcmovnu, 40 fcmovu, 41 fcom, 42 fcomi, 42 fcomip, 43 fcomp, 43 fcompp, 43 fcos, 43 fdecstp, 45 fdiv, 41 fdivp, 41 fdivr, 41 fdivrp, 41 ffree, 45 fiadd, 41 ficom, 43 ficomp, 43 fidiv, 41 fidivr, 42 fild, 41 .file, 21 fimul, 42 fincstp, 45 finit, 45 fist, 41 fistp, 41 fisub, 42 fisubr, 42 flag control instructions, 38 fld, 41 fld1, 44 fldcw, 45 fldenv, 45 fldl2e, 44 fldl2t, 44
75

Index

fldlg2, 44 fldln2, 44 fldpi, 44 fldz, 44 .float, 21 floating-point instructions basic arithmetic, 41 comparison, 42 control, 44 data transfer, 40 load constants, 44 logarithmic See transcendental transcendental, 43 trigonometric See transcendental fmul, 42 fmulp, 42 fnclex, 45 fninit, 45 fnop, 45 fnsave, 45 fnstcw, 45 fnstenv, 45 fnstsw, 45 fpatan, 43 fprem, 42 fprem1, 42 fptan, 44 frndint, 42 frstor, 45 fsave, 46 fscale, 42 fsin, 44 fsincos, 44 fsqrt, 42 fst, 41 fstcw, 46 fstenv, 46 fstp, 41 fstsw, 46 fsub, 42 fsubp, 42 fsubr, 42
76

fsubrp, 42 ftst, 43 fucom, 43 fucomi, 43 fucomip, 43 fucomp, 43 fucompp, 43 fwait, 46 fxam, 43 fxch, 41 fxrstor, 46 fxsave, 46 fxtract, 42 fyl2x, 44 fyl2xp1, 44

G
gas, 12 .globl, 21 .group, 21

H
.hidden, 21 hlt, 68

I
I/O (input/output) instructions, 37 .ident, 21 identifier, 15 idiv, 30 imul, 30 in, 38 inc, 30 ins, 38 insb, 38 insl, 38 instruction, 17 format, 17 suffixes, 17

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Index

instructions binary arithmetic, 29 bit, 32 byte, 32 control transfer, 34 data transfer, 26 decimal arithmetic, 30 flag control, 38 floating-point, 40-46 I/O (input/output), 37 logical, 31 miscellaneous, 39 MMX, 46-51 operating system support, 68-70 Opteron, 70 rotate, 31 segment register, 39 shift, 31 SIMD state management, 46 SSE, 51-59 SSE2, 59-68 string, 36 insw, 38 int, 34 into, 34 invd, 68 invlpg, 68 iret, 34

jnae, 35 jnb, 35 jnbe, 35 jnc, 35 jne, 35 jng, 35 jnge, 35 jnl, 35 jnle, 35 jno, 35 jnp, 35 jns, 35 jnz, 35 jo, 35 jp, 35 jpe, 35 jpo, 35 js, 35 jz, 35

K
keyword, 15

L
label, 14 numeric, 14 symbolic, 14 lahf, 38 lar, 68 lcall, 36 .lcomm, 21 ldmxcsr, 57 lds, 39 lea, 39 leave, 36 les, 39 lfence, 67 lfs, 39 lgdt, 68 lgs, 39 lidt, 69
77

J
ja, 34 jae, 34 jb, 34 jbe, 34 jc, 34 jcxz, 34 je, 34 jecxz, 35 jg, 35 jge, 35 jl, 35 jle, 35 jmp, 35

Index

lldt, 69 lmsw, 69 .local, 21 lock, 69 lods, 36 lodsb, 37 lodsl, 37 lodsw, 37 logical instructions, 31 .long, 22 loop, 36 loope, 36 loopne, 36 loopnz, 36 loopz, 36 lret, 36 lsl, 69 lss, 39 ltr, 69

M
m4, 11 maskmovdqu, 67 maskmovq, 58 maxpd, 61 maxps, 53 maxsd, 61 maxss, 53 mfence, 67 minpd, 61 minps, 53 minsd, 61 minss, 53 miscellaneous instructions, 39 MMX instructions comparison, 49 conversion, 47 data transfer, 47 logical, 49 packed arithmetic, 48 rotate, 50 shift, 50 state management, 50
78

mov, 28 movabs, 28 movabsA, 29 movapd, 60 movaps, 51 movd, 47 movdq2q, 66 movdqa, 66 movdqu, 66 movhlps, 51 movhpd, 60 movhps, 52 movlhps, 52 movlpd, 60 movlps, 52 movmskpd, 60 movmskps, 52 movntdq, 68 movnti, 68 movntpd, 68 movntps, 58 movntq, 58 movq, 47 movq2dq, 66 movs, 37 movsb, 29, 37 movsd, 60 movsl, 37 movss, 52 movsw, 29, 37 movupd, 60 movups, 52 movzb, 29 movzw, 29 mul, 30 mulpd, 61 mulps, 53 mulsd, 61 mulss, 53

N
neg, 30 nop, 39

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Index

not, 31 numbers, 15 floating point, 16 integers, 15 binary, 15 decimal, 15 hexadecimal, 15 octal, 15

O
operands, 18 immediate, 18 indirect, 18 memory addressing, 18 ordering (source, destination), 18 register, 18 operating system support instructions, 68 Opteron instructions, 70 or, 31 orpd, 62 orps, 55 out, 38 outs, 38 outsb, 38 outsl, 38 outsw, 38

P
packssdw, 47 packsswb, 47 packuswb, 47 paddb, 48 paddd, 48 paddq, 66 paddsb, 48 paddsw, 48 paddusb, 48 paddusw, 48 paddw, 48 pand, 50

pandn, 50 pause, 68 pavgb, 57 pavgw, 57 pcmpeqb, 49 pcmpeqd, 49 pcmpeqw, 49 pcmpgtb, 49 pcmpgtd, 49 pcmpgtw, 49 pextrw, 57 pinsrw, 57 pmaddwd, 48 pmaxsw, 58 pmaxub, 58 pminsw, 58 pminub, 58 pmovmskb, 58 pmulhuw, 58 pmulhw, 48 pmullw, 48 pmuludq, 66 pop, 29 popa, 29 popal, 29 popaw, 29 popf, 38 popfw, 38 .popsection, 22 por, 50 prefetchnta, 59 prefetcht0, 59 prefetcht1, 59 prefetcht2, 59 .previous, 22 psadbw, 58 pshufd, 67 pshufhw, 67 pshuflw, 67 pshufw, 58 pslld, 50 pslldq, 67 psllq, 50 psllw, 50
79

Index

psrad, 50 psraw, 50 psrld, 50 psrldq, 67 psrlq, 50 psrlw, 50 psubb, 48 psubd, 48 psubq, 67 psubsb, 48 psubsw, 49 psubusb, 49 psubusw, 49 psubw, 49 punpckhbw, 47 punpckhdq, 47 punpckhqdq, 67 punpckhwd, 47 punpcklbw, 47 punpckldq, 47 punpcklqdq, 67 punpcklwd, 47 push, 29 pusha, 29 pushal, 29 pushaw, 29 pushf, 39 pushfw, 38 .pushsection, 22 pxor, 50

rdtsc, 69 .rel, 22 rep, 37 repnz, 37 repz, 37 ret, 36 rol, 32 ror, 32 rotate instructions, 31 rsm, 69 rsqrtps, 54 rsqrtss, 54

S
sahf, 39 sal, 32 sar, 32 sbb, 30 scas, 37 scasb, 37 scasl, 37 scasw, 37 .section, 22 segment register instructions, 39 .set, 22 seta, 33 setae, 33 setb, 33 setbe, 33 setc, 33 sete, 33 setg, 33 setge, 33 setl, 33 setle, 33 setna, 33 setnae, 33 setnb, 33 setnbe, 33 setnc, 33 setne, 33 setng, 33 setnge, 33
x86 Assembly Language Reference Manual March 2010

Q
.quad, 22

R
rcl, 31 rcpps, 53 rcpss, 53 rcr, 31 rdmsr, 69 rdpmc, 69
80

Index

setnl, 33 setnle, 33 setno, 33 setnp, 33 setns, 33 setnz, 33 seto, 34 setp, 34 setpe, 34 setpo, 34 sets, 34 setz, 34 sfence, 59 sgdt, 69 shift instructions, 31 shl, 32 shld, 32 shr, 32 shrd, 32 shufpd, 63 shufps, 56 sidt, 69 SIMD state management instructions, 46 .skip, 22 sldt, 69 .sleb128, 22 smovl, 37 smsw, 69 sqrtpd, 61 sqrtps, 54 sqrtsd, 61 sqrtss, 54 SSE instructions compare, 54 conversion, 56 data transfer, 51 integer (64bit SIMD), 57 logical, 55 miscellaneous, 58 MXCSR state management, 57 packed arithmetic, 52 shuffle, 55 unpack, 55

SSE2 instructions compare, 62 conversion, 64 data movement, 59 logical, 62 miscellaneous, 67 packed arithmetic, 60 packed single-precision floating-point, 65 shuffle, 63 SIMD integer instructions (128bit), 66 unpack, 63 statement, 13 empty, 13 stc, 39 std, 39 sti, 39 stmxcsr, 57 stos, 37 stosb, 37 stosl, 37 stosw, 37 str, 69 .string, 22 string, 16 string instructions, 36 sub, 30 subpd, 62 subps, 54 subsd, 62 subss, 54 .symbolic, 22 sysenter, 69 sysexit, 69

T
.tbss, 23 .tcomm, 23 .tdata, 23 test, 34 .text, 23

81

Index

U
ucomisd, 63 ucomiss, 55 ud2, 39 .uleb128, 23 unpckhpd, 63 unpckhps, 56 unpcklpd, 63 unpcklps, 56

V
.value, 23 verr, 69 verw, 70

W
wait, 46 wbinvd, 70 .weak, 23 whitespace, 13 wrmsr, 70

X
xadd, 29 xchg, 29 xchgA, 29 xlat, 39 xlatb, 39 xor, 31 xorpd, 62 xorps, 55

Z
.zero, 23

82

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