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DSP 56300

The Motorola DSP56300 family is a series of digital signal processors that features a highly parallel instruction set, on-chip memory interfaces, and hardware for debugging. It has a multiplier-accumulator unit, address generation unit, program control unit, and six-channel direct memory access controller. The processor core can achieve one million instructions per second per MHz and includes an instruction cache. External memory is divided into separate spaces for program, X data, and Y data access.

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Aneesh Raveendran
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207 views

DSP 56300

The Motorola DSP56300 family is a series of digital signal processors that features a highly parallel instruction set, on-chip memory interfaces, and hardware for debugging. It has a multiplier-accumulator unit, address generation unit, program control unit, and six-channel direct memory access controller. The processor core can achieve one million instructions per second per MHz and includes an instruction cache. External memory is divided into separate spaces for program, X data, and Y data access.

Uploaded by

Aneesh Raveendran
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Motorola DSP56300 Family

Aneesh R Broadcast and Communication Group Centre for Development of Advanced Computing Thiruvananthapuram

Aneesh R,CDAC Thiruvananthapuram

DSP56300 Family

Aneesh R,CDAC Thiruvananthapuram

Overview
One Million Instructions Per Second (MIPS) per MHz of operating speed Object code compatible with the DSP56000 core Highly parallel instruction set Data Arithmetic Logic Unit (Data ALU) Address Generation Unit (AGU) Program Control Unit (PCU) On-chip instruction cache controller
Aneesh R,CDAC Thiruvananthapuram

Overview Contd
External memory interface (Port A) Phase Locked Loop (PLL) Hardware debugging support (JTAG TAP, OnCETM module, and Address Trace Mode) Six-channel Direct Memory Access (DMA) controller Reduced power dissipation

Aneesh R,CDAC Thiruvananthapuram

Block Diagram

Aneesh R,CDAC Thiruvananthapuram

Core Busses

Aneesh R,CDAC Thiruvananthapuram

PCU Architecture

Aneesh R,CDAC Thiruvananthapuram

Data Arithmetic Logic Unit


Four 24-bit input registers A fully pipelined Multiplier-Accumulator (MAC) Two 48-bit accumulator registers Two 8-bit accumulator extension registers A Bit Field Unit (BFU) with a 56-bit barrel shifter An accumulator shifter Two data bus shifter/limiter circuits
Aneesh R,CDAC Thiruvananthapuram

Accumulator Shifter
No shift (unmodified) 24-bit right shift (arithmetic) for DMAC 16-bit right shift (arithmetic) for DMAC in Sixteen-bit Arithmetic mode Force to zero

Aneesh R,CDAC Thiruvananthapuram

Address Generation Unit

Aneesh R,CDAC Thiruvananthapuram

External Memory Interface


External memory is divided into three possible 24bit spaces: X-data, Y-data and program memory External memory is accessed through DMA and Single Move Comments An internal wait state generator can be programmed to statically insert up to 31 wait states for access to slower memory or I/O devices.

Aneesh R,CDAC Thiruvananthapuram

DMA Controller
DMA saves core MIPS because the core can operate in parallel. DMA saves power because it requires less circuitry than the core to move data. DMA saves pointers because core AGU pointer registers are not needed. DMA has no modulo block size restrictions, unlike the core AGU.
Aneesh R,CDAC Thiruvananthapuram

PLL and Clock Generator

Phase Locked Loop (PLL)


Clock input division Frequency multiplication Skew elimination

Clock Generator (CLKGEN)


Low-power division Internal and external clock generation

Aneesh R,CDAC Thiruvananthapuram

PLL Block Diagram

Aneesh R,CDAC Thiruvananthapuram

Memory Space
Program memory space X data memory space Y data memory space

Aneesh R,CDAC Thiruvananthapuram

Program Memory
Bootstrap ROM Reserved space for Program ROM External program memory Internal program memory Internal instruction cache memory

Aneesh R,CDAC Thiruvananthapuram

X Data Memory space


Internal X I/O space Switchable internal or external X I/O memory space Reserved space for X ROM or RAM External X data memory Internal X data RAM

Aneesh R,CDAC Thiruvananthapuram

Y Data Memory space


Internal/External Y I/O space Switchable internal or external Y I/O memory space Reserved space for Y ROM or RAM External Y data memory Internal Y data RAM

Aneesh R,CDAC Thiruvananthapuram

Pipeline Instruction Execution

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Pipeline Operation

Aneesh R,CDAC Thiruvananthapuram

Internal Interrupts
Stack Error Illegal Instruction Debug Request Trap DMA Peripherals

Aneesh R,CDAC Thiruvananthapuram

External Interrupts
NMI IRQA IRQB IRQC IRQD

Aneesh R,CDAC Thiruvananthapuram

Non Maskable Interrupts


Hardware Reset Illegal Instruction Interrupt (III) Stack Error TRAP NMI Debug

Aneesh R,CDAC Thiruvananthapuram

Interrupt Priority

Aneesh R,CDAC Thiruvananthapuram

Debugging Modes

Aneesh R,CDAC Thiruvananthapuram

Aneesh R Broadcast and Communication Group Centre for Development of Advanced Computing Thiruvananthapuram,kerala

Aneesh R,CDAC Thiruvananthapuram

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