DESIGN AND SIMULATION OF LOGIC GATES

OBJECTIVE: Design and simulation of Logic gates using VHDL.

AND GATE:

LOGIC SYMBOL:

TRUTH TABLE:

VHDL CODE:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AND1 is port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC); end AND1; --Dataflow model architecture behav1 of AND1 is begin Z<= x and y; --Signal Assignment Statement End behav1; -- Behavioral model architecture behav2 of AND1 is

begin process (x, y) begin if (x='1' and y='1') then -- Compare with truth table Z <= '1'; else Z <= '0'; end if; end process; end behav2; OUTPUT WAVEFORM:

OR GATE:
LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity OR2 is port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); end OR2; --Dataflow model architecture behav1 of OR2 is begin Z <= x or y; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of OR2 is begin process (x, y) begin if (x='0' and y='0') then -- Compare with truth table Z <= '0'; else Z<= '1'; end if; end process; end behav2; OUTPUT WAVEFORM:

OR GATE: LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is port( X: in STD_LOGIC; Z: out STD_LOGIC ); end not1; --Dataflow model architecture behav1 of not1 is begin Z<= not X; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of not1 is begin process (X) begin if (x='0') then -- Compare with truth table Z <= '1'; else Z<= '0'; end if; end process; end behav2;

OUTPUT WAVEFORM:

NAND GATE:
LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand2 is port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); end nand2; --Dataflow model architecture behav1 of nand2 is

begin z<= x nand y; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of nand2 is begin Process (x, y) Begin If (x='1' and y='1') then -- Compare with truth table Z <= '0'; else Z <= '1'; end if; end process; end behav2; OUTPUT WAVEFORM:

NOR GATE:
LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor2 is Port ( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC ); end nor2; --Dataflow model architecture behav1 of nor2 is begin Z<= x nor y; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of nor2 is begin process (x, y) begin If (x='0' and y='0') then -- Compare with truth table Z <= '1'; else Z <= '0'; end if; end process; end behav2; OUTPUT WAVEFORM:

XOR GATE:
LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC ); end xor2; --Dataflow model architecture behav1 of xor2 is begin Z<= x xor y; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of xor2 is begin process (x, y) begin If (x/=y) then -- Compare with truth table

Z <= '1'; else Z<= '0'; end if; end process; end behav2; OUTPUT WAVEFORM:

XNOR GATE:
LOGIC SYMBOL: TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnor2 is Port ( X: in STD_LOGIC; Y: in STD_LOGIC;

Z: out STD_LOGIC ); end xnor2; --Dataflow model architecture behav1 of xnor2 is begin Z<= x xnor y; --Signal Assignment Statement end behav1; -- Behavioral model architecture behav2 of xnor2 is begin process (x, y) begin If (x=y) then -- Compare with truth table Z <= '1'; else Z<= '0'; end if; end process; end behav2; OUTPUT WAVEFORM:

DESIGN AND SIMULATION OF ADDERS

AIM: Design and simulation of half adder and full adder using VHDL. TRUTH TABLE: HALFADDER:

INPUTS A 0 0 1 1 B 0 1 0 1

OUTPUT S Su m 0 1 1 0 Carr y 0 0 0 1

CIRCUIT DIAGRAM:

FULLADDER:

INPUTS A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

OUTPUTS Sum 0 1 1 0 1 0 0 1 Carr y 0 0 0 1 0 1 1 1

CIRCUIT DIAGRAM:

VHDL CODE:
Design and simulation of Half Adder using Data Flow Model:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder1 is Port (a: in std_logic; b: in std_logic; Sum: out std_logic; Carry: out std_logic); end halfadder1; architecture dataflow of halfadder1 is begin Sum<= a xor b; Carry<= a and b; end dataflow;

Design and simulation of Half Adder using Behavioral Model:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is Port (a, b: in std_logic; Sum: out std_logic; Carry: out std_logic); end halfadder; architecture Behavioral of halfadder is begin process (a, b) begin if a='0' and b='0' then Sum<='0'; Carry<='0'; elsif a='0' and b='1' then Sum<='1'; Carry<='0'; elsif a='1' and b='0' then Sum<='1'; Carry<='0'; elsif a='1' and b='1' then Sum<='0'; Carry<='1'; end if; end process; end Behavioral;

OUTPUT WAVEFORM FOR HALFADDER:

Design and simulation of Full Adder using Structural Model: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder3 is Port (a, b, c: in std_logic; sum: out std_logic; carry: out std_logic); end fulladder3; architecture structural of fulladder3 is component XOR1 is port (a,b,c : in std_logic; w :out std_logic); end component; component AND1 is port (l, m: in std_logic; n: out std_logic); end component; component OR1 is port (e, f, i : in std_logic; j: out std_logic); end component; signal l1, l2, l3 : std_logic; begin

X1: XOR1 port map (a, b, c, sum); A1: AND1 port map b, a, l1); A2: AND1 port map (b, c, l2); A3: AND1 port map (c, a, l3); R1: OR1 port map (l1,l2, l3, carry); end structural; i) Design and simulation of AND1:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and1 is Port (l, m: in std_logic; n: out std_logic); end and1; architecture structural of and1 is begin n<= l and m; end structural; ii) Design and simulation of OR1: ibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or1 is Port (e, f, i: in std_logic; j: out std_logic); end or1; architecture structural of or1 is begin j<=e or f; end structural; iii) design and simulation of XOR1: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor1 is Port (a, b, c: in std_logic; w: out std_logic); end xor1; architecture structural of xor1 is begin w<= (a xor b) xor c; end structural;

Design and simulation of Full Adder using Behavioral Model: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder2 is Port (a, b, c: in std_logic; Sum: out std_logic; Carry: out std_logic); end fulladder2; architecture Behavioral of fulladder2 is begin process (a, b, c) begin if a='0' and b='0' and c='0' then sum<='0' ; carry<='0'; elsif a='0' and b='0' and c='1' then sum<='1' ; carry<='0'; elsif a='0' and b='1' and c='0' then sum<='1' ; carry<='0'; elsif a='0' and b='1' and c='1' then sum<='0' ; carry<='1'; elsif a='1' and b='0' and c='0' then sum<='1' ; carry<='0'; elsif a='1' and b='0' and c='1' then

sum<='0' ; carry<='1'; elsif a='1' and b='1' and c='0' then sum<='1' ; carry<='0'; elsif a='1' and b='1' and c='1' then sum<='1'; carry<='1'; end if; end process; end Behavioral; OUTPUT WAVEFORM FOR FULL ADDER:

DESIGN AND SIMULATION OF 3 TO 8 DECODER OBJECTIVE:

CIRCUIT:

TRUTH TABLE:

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity decoder is port( input : in std_logic_vector(2 downto 0); --3 bit input

output : out std_logic_vector(7 downto 0) -- 8 bit ouput ); end decoder; --architecture of entity architecture Behavioral of decoder is begin output(0) <= (not input(2)) and (not input(1)) and (not input(0)); output(1) <= (not input(2)) and (not input(1)) and input(0); output(2) <= (not input(2)) and input(1) and (not input(0)); output(3) <= (not input(2)) and input(1) and input(0); output(4) <= input(2) and (not input(1)) and (not input(0)); output(5) <= input(2) and (not input(1)) and input(0); output(6) <= input(2) and input(1) and (not input(0)); output(7) <= input(2) and input(1) and input(0); end Behavioral;

OUTPUT WAVEFORM:

DESIGN AND SIMULATION OF 8 TO 1 MULTIPLEXER

OBJECTIVE: CIRCUIT:

TRUTH TABLE:

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Y Din0 Din1 Din2 Din3 Din4 Din5 Din6 Din7

VHDL CODE: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX8_1 IS PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC); END MUX8_1; ARCHITECTURE BEH123 OF MUX8_1 IS BEGIN PROCESS(DIN,SEL) BEGIN CASE SEL IS WHEN"000"=>DOUT<=DIN(0); WHEN"001"=>DOUT<=DIN(1); WHEN"010"=>DOUT<=DIN(2); WHEN"011"=>DOUT<=DIN(3); WHEN"100"=>DOUT<=DIN(4); WHEN"101"=>DOUT<=DIN(5); WHEN"110"=>DOUT<=DIN(6); WHEN"111"=>DOUT<=DIN(7); WHEN OTHERS=> DOUT<='Z'; END CASE; END PROCESS; END BEH123; OUTPUT WAVEFORM: