Fundamentals and Economics

In the last installment of this series on Software Defined Chips™, the story of the external forces that helped to drive a new product family unfolded. This posting takes on the economics of time and money, and compares Software Defined Chips™ to Application-Specific Standard Products (ASSPs).

Show Me the Money

Getting to revenue is a big deal. Fast designs that turn into the first products of a new generation or industry segment make a lot more money than those that come later. Not only do they make more money for you, they make more money for your customer.

This is one of the primary items of value in Software Defined Chips™. Everything you do needs to focus on how quickly a customer can get to production. Everything. You can outrun an ASSP. But you cannot easily displace it after it shows up. You can shoot ahead to hit a new market or a new niche, but your shot has to arrive when the market or niche opens. What distinguishes Software Defined Chips™ from chips with hard tooling (Application-Specific Standard Products, or ASSPs) is:

• Shorter time to completed systems design (you can verify in the real system with the real ship much sooner)
• Lead time of supply chain
• Flexibility in design customization and the ability to fix bugs and enhance functionality in hardware

These characteristics can be emulated with ASSPs, but the physics of the process are irrefutable. You can save your customer 18-24 months of development time by designing a Software Defined Chips product that meets his or her requirements. Even if you need to customize it, the time savings is at least 15 months:  an eternity in today’s markets.

Comparisons: Time and Money

Here is a fast ASSP development schedule that takes you out to your lead customer’s first revenue shipment:

Link to the underlying spreadsheet

 Using the same front-end design times and design complexities, here is a Software Defined Chip™ (SDC™) schedule:

Link to the underlying spreadsheet

Pretty different? Yes. Important to your customer? Absolutely. Remember – time to your customer’s revenue is the most important factor.

You are probably wondering – what about the capital costs to do such developments. I’ve taken some generic numbers and tried to be generous (that is, low cost) on the ASSP side and realistic on the SDC side:

Link to the underlying spreadsheet

There are dramatic differences between the two cases. Using the simpler design, it takes 85,000 units to break – much less turn a profit – on the ASSP side. The SDC side is only 11,000 units. Even more important is the time to break-even: 102 months (that’s 8.5 years for those of you who are counting), versus 13 months for the SDC.

A Long and Winding Road

The food chain of chips to consumers is often a circuitous path. On one level, it is straightforward: wafer fabs produce chips that are packaged and assembled into systems that are shipped to users (from IoT devices to data centers to teleco’s…). The transactions required to get from Point A to Point B are linear. However, in real life they are numerous and more discontinuous than you might expect. The decisions made and designs done to create this flow of ideas to reality are even more disjointed and now very complex. Consider a simple microcontroller, suitable for use in an Internet of Things device. I’m choosing this example because the average ASSP is much more complex – making the problem much worse than you see below. 

• Semiconductor company A decides a new microcontroller with 802.11 wireless interfaces is needed
• It must be low cost
• It needs a 32-bit processor, wireless radio technology, and some standard interfaces, such as I2C
• It must be incredibly low power, with power-down modes to ensure long battery life
• There must be enough memory on board to run an operating system and multiple applications
• A development board is needed for users, along with operating system (probably Linux) and sample applications, a few tools, and clean documentation
• What has to happen:
  • A product requirements document is created
  • Multiple customers are seen under non-disclosure to comment and buy-off on the requirements document
  • Gate 1: markets are sized, product cost and pricing and volume reviewed, team identified, and schedule cast. Management approves the game plan.
  • A formal spec of the product is written from the requirements document. Engineering leadership negotiates with marketing on the spec.
  • Engineering team is assembled, schedules cast, further negotiation with marketing on the schedule and deliverables
  • Review with customers as the spec settles down
  • Cries of anguish exceed yelps of joy
  • Company gets a processor and interface bus license from ARM
  • It finds a 3rd party to design the radio
  • It buys the memory cells
  • Stacks for WiFi are licensed
  • All this before the big expense of a mask set
• Finalizing the chip
  • Logic is synthesized, processor and memory embedded, and radio IP integrated
  • Verification suites are written and run
  • Power estimates done at a logic level
  • More cries of anguish
  • Fundamental trade-offs and feature subtraction
  • Chip is synthesized
  • Physical design done
  • Final verification of the completed chip design
  • A development/evaluation board is designed and built
• Design review
  • All the assumptions going in are reviewed
  • Delta’s or exceptions are agreed to, with any caveats on special actions to take
  • Project is authorized for mask making
  • Test programs are written
  • Load boards designed and fabricated
  • Eval board is tested for correctness of logic and connectivity around the chip
• The first build
  • Company writes a big check to TSMC or Global Foundries
  • Masks are made, chips diced and assembled, first tested on an IC tester, then sent to the verification and design teams for bring-up on the development board
  • Radio silence in the lab until the chip wiggles
  • Engineering releases updates in very small doses until it gets some confidence in the chip working
  • Tears of joy or more cries of anguish
• Sampling
  • Lead customers receive evaluation boards with chips on them, software, early documentation
  • Apps team hand-holds the customer’s designers
  • Everyone holds their breath as customers keep banging on it
  • Internal team continues to verify, and identified bugs are communicated to lead customers
  • As the bugs become asymptotically small in number, it’s time to make a call to release to production
• Pre-production
  • Wafers that are held in fab at pre-metal are released to move forward
  • Enough chips are built for customers, who are moving fast and for development boards for new customers
  • PR campaign, trade shows, testimonials
• Production
  • Marketing makes a call on how much inventory to build
  • Sales kicks and screams about the expectations
  • First real PO’s are booked

Note: there has not been a dime of revenue yet!

 With SDCs, the path is much shorter. You get to skip the steps after design review, get eval systems into customers’ hands, and iterate the design as needed. Customer feedback at this stage means a lot. By being able to modify both hardware and software on the fly, you will get to a better product and your customers will ship a lot sooner. And both of you will get to revenue in about a year, versus three on an average ASSP.

The bottom line: if time matters (and it should), you should seriously evaluate how long it takes to produce a new ASSP. And, don’t forget about the risk and capital cost of a mask set. If it is not right the first time, you can kiss a significant amount of your ROI goodbye.

 Next installment: how Software Defined Chips require a change of mindset, and why.

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