Bringing It All Back Home: Final Posting on Software Defined Chips(tm)

We left off in the last installment with a grim view of the fundamental structure of today’s semiconductor industry. The capital cost of developing a new complex chip has gotten so high with designs taking so long that fewer and fewer design starts can be justified. Systems companies and consumers suffer from the lack of innovation as a result…

From the point of view of the FPGA producer, it looks like more and more business coming in, if only from the decreasing number of ASSPs. The pipeline is good. I’ve asked Altera and Xilinx people about their view of Software Defined Chips™ (SDCs). Altera is happy with TPACK (which I sold to them in 2013, along with the trademark SoftSilicon™). Altera, however, has not continued its program of SoftSilicon™ with independent companies. Xilinx has had a couple of SDC programs going but they have not made much noise. Xilinx acquired a competitor of TPACK soon after I acquired TPACK and has used it largely to supplement systems customer designs. QuickLogic has been building programmable standard products of its own for some time but does not generally welcome third parties for resale at a component level. Other players exist (Lattice and MicroSemi, and Achronix, for example), but they each serve niches, also focusing on systems customers.

The duopoly of Xilinx and Altera continues to be cyclical, with the company having the most advanced process technology and fastest interfaces wins the greatest number of high-value designs in a given quarter or year. The acquisition of Altera by Intel was driven by mutual need: Intel needs to feed its small geometry fabs and Altera needs the most advanced geometries to drive margin. As a result, Altera gets to move down the cost curve of new processes and roll out big, honking, and expensive FPGAs sooner. Over the years, Xilinx and Altera have “ping-ponged” their leadership. Time will tell whether Intel/Altera will break the cycle.

But, isn’t there a limit to all this? If systems companies (even startups) cannot design breakthrough new products using architecturally fresh ASSPs, doesn’t the entire food chain suffer? If systems companies have real limits (both in terms of design capacity and unit cost) using FPGA-based designs, how much can they do? And with the extreme consolidation of larger semiconductor companies, who will be left to break out with some really fresh new stuff?

Is the word grim too forgiving?

There are alternate approaches:

• Semiconductor companies focus on 20- and 28-nm CMOS for new ASSP designs.
• Foundries continue driving the cost of a mask set and wafer costs down dramatically to extend the life of 28nm to digestible levels and get the hurdle rate down
• Systems companies recognize the structural problem in the industry and incent ASSP companies to innovate (via NRE, investment, consortia of systems companies, or all three)
• FPGA companies do more in packaging, collaborating with ASSP companies for multi-die approaches where ASSP, FPGA, and memory reside in the same package
• Software Defined Chips™ (SDCs)

The first three options above are well understand, but easier said than done. The fourth, SDC, is what I’m advocating. It’s the fastest to implement and highest potential for true design innovation. But it’s also the most difficult for the FPGA producer to comprehend and swallow. Why? For one, it creates the perception that SDCs will take away some of the family jewels, namely, Tier 1 accounts at high gross profit margins. They can be concerned that an SDC company will replace their special relationship at the top levels of engineering of their systems customers. Remember the story of TPACK in an earlier post? We did get mindshare from GMs and system architects, who viewed the FPGA selection as secondary. Interceding at this level, especially if you are a mainstream ASSP company doing the SDC, there is fear and loathing of FPGA-as-a-prototype followed by ASSP in production.

In my experience, nothing could be further from the truth. A healthy ecosystem of FPGA, SDC, and systems customers can work together for a much greater good. A good architecture and ready-to-go evaluation systems and software enables system design starts on Day 1. We had customers go from design start to production systems in as little as six months (really – one of them really did by doing a “copy exact” on our eval board and using our software to build additional functionality. How about that for a benefit: customers get new products out a year faster, generate new revenue that drives FPGA revenue, that creates profit to invest in the next design. Is something right?

So, what is the mental change required of the FPGA producer?

• Embrace 3rd party SDC partners in the same fashion as they do with top IP providers
• Create a family of products from current standard products, but which are used only for SDCs. This approach makes possible differential pricing based on the value in use of the design, not just the FPGA.
• Be generous in allocating revenue splits to the SDC producer. Remember, your SG&A line is radically reduced when your partner creates the design/application, sells it to the customer, and supports it – and you get to revenue faster
• Make the operational side easy for the SDC producer - custom part markings, short lead times, distribution and sales channel cooperation, and preferred technical support

Each of the above points is difficult for FPGA producers to swallow. It feels like “letting go”. However, a well-structured joint-marketing agreement can eliminate these fears. If you, the FPGA company, want exclusivity in a certain SDC product family, ask for it. You’ll get it or not: either way, you know exactly where you stand. Cultivate design teams at ASSP companies and learn from them. Nurture design and IP companies to move into SDCs and get off the treadmill of lifestyle businesses that are entirely dependent on the next design contract. These third parties may spot market trends before you do, and you can find out in time to modulate your product roadmap and make a difference. The Zen of it is like this: the act of letting go will bring more back to you.

It’s About Time

This will be my last posting on the topic of SDCs. The grim picture above does not need to exist. What looks like a structural problem in the industry of crushing capital costs and major consolidation can be solved, at least in part. All that’s needed is a mental shift by FPGA producers and developers of complex chips.

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