NED'25 | xIntern @DreamBig Semiconductor Inc. | xIntern @NCL | IoT | Networking | SV | RTL | Digital System Design | FPGA , RISC V, ASIC Enthusiast
🔧 Just completed an 8x3 Priority Encoder in Verilog! 🛠️ This digital circuit prioritizes eight input signals, encoding the highest-priority one into a three-bit binary output. Excited to share this project showcasing my Verilog skills! #DigitalDesign #Verilog #qurtus #HardwareDevelopment #HardwareDescriptionLanguage #Engineering
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 97/100: PWM Generator in Verilog! Today, I designed a PWM (Pulse Width Modulation) generator using Verilog! PWM is widely used for controlling power to devices like motors and LEDs by varying the duty cycle. This project helped me dive into concepts like frequency control and duty cycle adjustment. For more information, including synthesis results, you can check my GitHub link: https://lnkd.in/gumwBnH2 #100DaysRTL #VLSI #Verilog #DigitalDesign
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 2/100: Exploring Logic Gates in Verilog! 🚀 Today, I explored the fundamental logic gates using Verilog. Understanding these basic gates is crucial for digital design. Here’s a simple example that demonstrates all basic logic gates: AND, OR, NOT, NAND, NOR, XOR, and XNOR. #100DaysRTL #VLSI #Verilog #DigitalDesign #ContinuousLearning
🌟 Day 19 of #100daysofrtl 🌟 Today, I worked on designing a BCD to Seven-Segment Decoder using Verilog! The decoder converts a 4-bit BCD input into a 7-segment display output, where each segment lights up to represent digits from 0 to 9. It was fascinating to see how logic gates control each segment to display numbers correctly. Here’s to learning and improving one day at a time! 💪 #RTLDesign #Verilog #DigitalDesign #100Ddaysofrtl #VLSI #Learning
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 35/100: Implementing a D Latch Using a 2:1 Multiplexer in Verilog! 🚀 Today, I delved into designing a D latch using a 2:1 multiplexer in Verilog. A D latch is a fundamental memory element in digital circuits that stores a single bit of data. The D latch captures the value of the data input (D) when the clock signal (CLK) is high and holds that value when the clock is low. #100DaysRTL #VLSI #Verilog #DigitalDesign
|UG'25| VLSI Enthusiast|Verilog|System Verilog|Xilinx Vivado|RTL Design| Tinker Cad |Python|Analogue &Digital Circuits|Digital System design|C|
Hello Connections ✨💫 Excited to share my latest project update!🚀🚀 #day 12 I've just completed a 2-bit multiplier using Verilog. This circuit efficiently multiplies two 2-bit numbers by utilizing a combination of half adders and AND gates: - The design integrates two half adder (HA) modules for the multiplication process. - In addition, four two-input AND gates are employed to perform the necessary AND operations. This project involved designing sources based on the truth table, executing the test bench code, and simulating the sources. #VLSI #VERILOG #COMBINATIONALCIRCUITS #DIGITALSYSTEMDESIGN
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 12/100: Understanding Latches in Verilog! 🚀 Today, I delved into the fascinating world of latches in Verilog. Unlike flip-flops, latches are level-sensitive devices and are used in various digital circuits for temporary data storage and synchronization. Let's implement an SR (Set-Reset) latch to explore its functionality. #100DaysRTL #VLSI #Verilog #DigitalDesign
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 30/100: Implementing a Clock Divider in Verilog 🚀 Today, I delved into the creation of a clock divider using Verilog. The purpose of a clock divider is to take an input clock signal and produce output clock signals at lower frequencies. Specifically, I designed a module that generates clocks divided by 2, 4, 8, and 16. #100DaysRTL #VLSI #Verilog #DigitalDesign
Day 21: Decimal to BCD Encoder 🌟 Today, I explored the Decimal to BCD Encoder, a combinational logic circuit that converts a decimal input (0–9) into its 4-bit Binary Coded Decimal (BCD) equivalent. Here’s what I worked on: Designed the encoder using Verilog. Tested it with a simple testbench to verify functionality. Learned how it’s used in real-world applications like seven-segment displays and digital systems. Decimal 5 → BCD 0101 #100DaysOfRTL #Verilog #DigitalDesign #RTLDesign #LearningByDoing #VLSI
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 33/100: Implementing an N-Bit Comparator in Verilog! 🚀 Today, I explored designing an N-bit comparator in Verilog. A comparator is a digital circuit that compares two N-bit numbers and determines if one is greater than, less than, or equal to the other. Here’s how I implemented it in Verilog #100DaysRTL #VLSI #Verilog #DigitalDesign
Pre-final Year Electronics and Communication Engineering Student at R.M.K College Of Engineering And Technology | VLSI Enthusiast | Digital Design |Verilog
🚀 Day 25/100: Understanding and Synthesizing a Priority Encoder in Verilog! 🚀 Today, I focused on the concept of priority encoders, a vital component in digital electronics used for managing multiple input lines with priority levels. A priority encoder outputs the binary code of the highest-priority active input. #100DaysRTL #VLSI #Verilog #DigitalDesign
