Simr (formerly UberCloud)’s Post

HPCwire reports on DIMON, a groundbreaking #artificialintelligence framework capable of solving complex equations at speeds that rival supercomputers — without requiring HPC infrastructure. #machinelearning #deeplearning #quantumphysics #HPCwire https://ow.ly/q13S50UGmsb

NEW BLOG! KIOXIA Product Line Manager Paul Wu discusses the future of edge computing and the role E1.S SSDs will play in that future. Check it out! https://lnkd.in/gEtvErJ #SSD #edgecomputing

Let's take a close look on how the All-New #Forlinx Rockchip #RK3576 SoM can power your #AIoT projects with its high performance, robust computing capabilities, and low power consumption!

High-performance computing will never be the same again! With NextSilicon launching its new Maverick 2 chips focused on HPC, I sat down with CEO Elad Raz to discuss how their approach is different. We discuss through the utility of accelerating standard and non-standard HPC codes, the value of this market (over AI/ML), and if I can bring my own regular C++ or Fortran code to this new hardware. Spoiler: yes I can. https://lnkd.in/ecN5QBGK

Whitepaper: New Performance Boost: COM Express mini with 13th Generation Intel Core Technology- this paper provides a detailed look at the COMe-mRP10 (E2) module, engineered for applications where space is at a premium, yet high computational power is essential. Kontron Learn more. https://lnkd.in/g3GGYrQZ

KIOXIA BLOG! KIOXIA Product Line Manager Paul Wu discusses the future of edge computing and the role E1.S SSDs will play in that future. Check it out! https://lnkd.in/gEtvErJ #SSD #edgecomputing

Join us on 11 July 2024, from 3:30 – 4:30 PM (CET) for a live webinar where we’ll take you through a step-by-step plan to accelerate your simulations. What You’ll Learn: -> Maintain control over your data and models while eliminating repetitive tasks with our High Performance Computing (HPC) technology. -> Run complex simulations simultaneously with advanced cloud-based GPU technology. -> Seamlessly integrate with your favorite tools using open standards and enhance collaboration. -> Build detailed digital twins in minutes with integrated GIS data. Why Attend? -> Accelerate your simulations. -> Integrate diverse data sets effortlessly. -> Stay at the forefront of engineering innovation. Don’t miss this chance to see the Tygron Platform in action and discover how it can transform your projects! 📅 When? Date: 11 July 2024 Time: 3:30 – 4:30 PM (CET) 👉 Yes, sign me up! https://lnkd.in/ercxWzXu

#TCAD #DTCO #TransportModeling #Nanosheet #DeviceSimulation #CMOS #AdvancedLogic #SubBandBoltzmann #DriftDiffusion #RingOscillator #Calibration #HierarchicalModeling #PathFinding #TransistorPerformance #GTS "Hierarchical Transport Modeling for Path-Finding DTCO: A New Approach to Predictive TCAD Device Simulation" This research introduces a novel hierarchical flow for predictive TCAD device simulation in Design Technology Co-Optimization (DTCO) applications. The methodology combines the accuracy of sub-band Boltzmann transport equation (SBTE) solvers with the efficiency of SPICE simulations, addressing the critical need for accurate transport modeling in active transistors for path-finding DTCO. The proposed calibration flow consists of three main phases: 1. Advanced Transport Simulation using SBTE 2. TCAD Device Simulation with drift-diffusion (DD) model 3. Full-cell DTCO simulation Key innovations of this research include: - Automated generation of TCAD device simulation parameters using a calibrated SBTE solver - Hierarchical calibration procedure utilizing characterization data and intermediate phases - Demonstration on an A14 nanosheet technology with detailed calibration steps - Significant improvement in ring-oscillator performance prediction accuracy The study addresses the challenges of accurate performance prediction in path-finding DTCO, particularly for upcoming process nodes with increasing diversity. It emphasizes the importance of thorough calibration for precise performance metrics, showing deviations of up to 76% in ring oscillator key performance indicators between uncalibrated and calibrated cases. Limitations of the study include: - Specific focus on A14 nanosheet technology, which may limit generalizability - Reliance on particular models (e.g., density gradient, Philips mobility) that may not be universally applicable - Potential computational intensity of the full calibration process, which is not explicitly discussed The research demonstrates the potential for substantial improvements in the accuracy of TCAD simulations while maintaining acceptable turn-around-times. This approach could significantly impact semiconductor industry R&D processes, enabling more precise performance predictions in DTCO. https://lnkd.in/gd5MvMVG

I am happy to share that our paper, "Transfer Learning Framework for Impedance Characterization of Modular Multilevel Converters," has been published in IEEE Transactions on Industry Applications (early access). Available: https://lnkd.in/e6qqw8g5. This paper addresses the challenges posed by the nonlinear impedance characteristics of modular multilevel converters (MMCs) in modern power grids. It proposes a transfer learning framework that uses system-level parameters to predict both AC and DC side impedances simultaneously. The framework combines linear time-invariant state-space modeling, black-box impedance measurements, and machine learning to achieve accurate MMC impedance estimation. The proposed approach has been validated using a practical converter from the CIGRE B4 DC grid test system across various controller configurations and scenarios involving unknown control parameters. RTDS simulators with hardware-in-the-loop and software-in-the-loop setups were utilized to conduct the impedance measurements. I thank my co-author, Azadeh Kermansaravi, Ph.D., and my supervisors, Pedro P. Vergara and Aleksandra Lekić, for their invaluable assistance throughout this work. #HVDC #MMC #RTDS #IEEE #MachineLearning

Hexagonal magnetic defects could lead to energy-efficient neuromorphic computing Hexagonal defect ASI with vortex. Credit score: Communications Supplies (20... See more https://lnkd.in/gXbmy-_e