Compilers Lab’s Post

Michael Canesche's paper, which describes the new kernel fusion algorithm used in the Cadence XNNC Tensor Compiler, has been accepted at the International Conference on Compiler Construction. Tensor compilers like XLA, TVM, and TensorRT operate on computational graphs, where vertices represent operations, and edges denote data flow between these operations. Operator fusion is an optimization technique that combines multiple operators into a single, more efficient operation. The paper "Fusion of Operators of Computational Graphs via Greedy Clustering: The XNNC Experience" introduces the operator fusion algorithm recently implemented in the Xtensa Neural Network Compiler (XNNC). XNNC is a toolchain designed for deploying machine learning models on Cadence's Tensilica processors. These edge-device processors are widely used in applications such as automotive systems, consumer electronics, communications, LiDAR, and radar technologies. First released in 2017 to complement Tensilica’s Vision 7 processors, XNNC has since evolved significantly. Now in version 3.0, its codebase spans hundreds of thousands of lines of C++ code. XNNC has been used to compile thousands of neural networks for a broad range of Xtensa architectures, and its design and implementation continue to advance, as this paper demonstrates. Read the paper: https://lnkd.in/dsQJtSkz #compilers #research #university #education #gradschool

  • Michael Canesche's paper, which describes the new kernel fusion algorithm used in the Cadence XNNC Tensor Compiler, has been accepted at the International Conference on Compiler Construction.

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