Zhicheng Xu

#hotRequirement Role- Data Engineer with Gen AI and Machine Learning  Location- San Jose, CA Hybrid JD- Build large-scale production systems utilizing advanced machine learning and big data technologies. Develop and optimize data processing workflows for chunking, indexing, ingestion, and vectorization for both text and non-text data Benchmark and implement various vector stores, embedding techniques, and retrieval methods Create a flexible pipeline supporting multiple embedding algorithms, vector stores, search types (vector search, hybrid search, etc.) and search ranking Implement and maintain auto-tagging systems and data preparation processes for LLMs Develop tools and pipelines for text and image data cleaning, and refinement Integrate and optimize workflows using Azure AI Search, Azure AI Services, Azure PostgreSQL and various vector store technologies Use advanced prompting techniques to develop and optimize prompts for LLM to ensure model performance, responses quality and accuracy of the Gen AI platform. Contribute to automated model testing and evaluation infrastructure Build automations to create and select the best prompts for any given task What we need to see: Demonstrated expertise in AI/ML and LLM technologies, including generative AI, Natural Language Processing, and computer vision. Hands-on experience with multimodal AI systems, integrating data from various sources such as text and images to build comprehensive and effective AI solutions. Extensive experience in designing and deploying AI models and systems in production environments. Ability to translate business needs into technical solutions. Proficiency in Python and related tools Strong understanding of LLM architectures, training processes, and data requirements Experience with RAG systems, knowledge base construction, and vector databases Familiarity with embedding techniques, similarity search algorithms, and information retrieval concepts Hands-on experience with data cleaning, tagging, and annotation processes (both manual and automated) Strong problem-solving skills and ability to work in a fast-paced, innovative environment Familiarity with MS Azure and its integration in AI/ML pipelines Experience with various vector store technologies and their applications in AI Experience building LLMs pipeline using framework like AutoGen, LangChain, Semantic Kernel, LlamaIndex, Azure AI Studio, OpenAI functions and models. Share resume at [email protected]

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To my friends in India who are asking where they can get a copy of “Next Level Testbenches: Design Patterns in SystemVerilog and UVM:” My understanding is that KDP (Kindle Direct Publishing, the publishing arm of Amazon) does not have a print on demand plant in India. Instead, Amazon India buys books from distributors in the US and the UK and resells them in India. However, they only buy paperback books, not hardcover books. So, I put together a paperback edition with identical content as the hardcover edition. The paperback edition launched this week on Amazon with “extended distribution,” which gives permission to be sold through international distributors. I don’t know when it will reach the Indian market. The KDP website says it could take up to eight weeks to get through the distribution network. In the meantime, it’s available on amazon.com, amazon.uk, and other European markets. I’m still learning how the international publishing market works. Thank you for your patience. P.S. Ebooks were not in my original plans. There are some challenges converting a book formatted for print into an ebook. I’ll look into it, but cannot promise an ebook edition will be available.

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On Day 45 of my 100 Days of RTL Coding, I focused on converting an SR flip-flop into a T flip-flop using Verilog. This conversion required reconfiguring the logic to achieve the toggling functionality of the T flip-flop while ensuring the Set and Reset inputs were appropriately utilized. Through this process, I deepened my understanding of flip-flop functionality and the relationships between different types of sequential circuits. Looking forward to more challenges and learning ahead! #RTL #Verilog #DigitalDesign #FlipFlop #100DaysOfRTL #Day45 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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🚨 Calling all Graduates! NVIDIA released its New Grad ASIC Verification Engineer role. Here's what you need to know: ⚙ Located in Santa Clara, CA ⚙ Full-time pay is ~$92,000-$180,000/yr ⚙ Full-time(40hrs/week) So if you have And have experience in SystemVerilog, C and/or C++, Python and/or Perl Then consider applying to NVIDIA now! Here's the link 👇 https://lnkd.in/gK7MNtDW You got this! ＿＿ Found this useful? Consider re-sharing 🔁 and following me Mark Benliyan for more content like this! #newgrad #nvidia #coding #softwareengineering

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𝐄𝐧𝐡𝐚𝐧𝐜𝐞 𝐘𝐨𝐮𝐫 𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐒𝐤𝐢𝐥𝐥𝐬 𝐰𝐢𝐭𝐡 𝐓𝐡𝐞𝐬𝐞 𝐓𝐨𝐩 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞𝐬! Embarking on the journey to master Verilog? Here are some excellent resources to guide you: 1. HDLBits (Link: https://lnkd.in/gkPTvT4h) 2. Chip Verify (Link: https://lnkd.in/gkE8KtgQ) 3. ChipEdge 4. Infosys Springboard (Only one is avalible. Link: https://lnkd.in/ge-geXkw. If the link do not open try to search, VLSI Digital Design - Chip Design and Verilog Programming) 5. Udemy 𝗡𝗼𝘁𝗲: 𝗜𝗳 𝘁𝗵𝗲 𝗹𝗶𝗻𝗸 𝗱𝗼 𝗻𝗼𝘁 𝘄𝗼𝗿𝗸 𝘁𝗵𝗲𝗿𝗲 𝗺𝗶𝗴𝗵𝘁 𝗯𝗲 𝘀𝗶𝘁𝗲 𝗶𝘀𝘀𝘂𝗲𝘀. 𝗦𝗼, 𝘀𝗲𝗮𝗿𝗰𝗵 𝗯𝘆 𝗻𝗮𝗺𝗲 𝗮𝘁 𝘁𝗵𝗮𝘁 𝗽𝗼𝗶𝗻𝘁. 𝑭𝒐𝒓 𝒎𝒐𝒓𝒆 𝒕𝒊𝒑𝒔 𝒇𝒐𝒍𝒍𝒐𝒘 Values #Values #GetvaluesfromValues #resources #VLSI #VLSIPrep

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GPU Kernel and memory management: 👉 What is a GPU Kernel? 1️⃣ A GPU kernel is a function that runs on the GPU and is executed in parallel by many threads. It is the core unit of execution in GPU programming. Kernels are written to perform a specific computation or operation on large datasets, leveraging the GPU's massive parallel processing capabilities. 2️⃣ Execution Model: When a kernel is launched, it is executed by a grid of thread blocks. Each block contains a group of threads that can execute the kernel function concurrently. The GPU schedules and manages these threads to perform the computations in parallel, significantly speeding up operations compared to sequential CPU execution. 👉 Memory Types in a Kernel: 1️⃣ Global Memory: The primary memory space on the GPU, accessible by all threads across different blocks. It is used to store large datasets and results that need to be read and written by multiple threads or across kernel invocations. 2️⃣ Shared Memory: An on-chip memory space shared among threads within the same block. It provides much lower latency compared to global memory and is used for inter-thread communication and temporary storage during kernel execution. 3️⃣ Local Memory: Memory that is private to each thread, used for storing per-thread data such as local variables or dynamically allocated memory. Local memory is often backed by global memory and has similar latency characteristics. 👉 Memory Management Responsibilities: 1️⃣ Data Allocation and Initialization: Before launching a kernel, data must be allocated and initialized in GPU memory. This involves transferring data from the CPU (host) to the GPU (device) and setting up the necessary memory structures for the kernel to operate on. 2️⃣ Memory Access Patterns: Efficient memory access patterns are crucial for performance. Proper alignment and coalescing of memory accesses help minimize latency and maximize throughput. Kernels must be designed to access memory in a manner that reduces contention and makes efficient use of available bandwidth. 3️⃣ Synchronization: When using shared memory, synchronization is necessary to ensure that all threads within a block have consistent views of the shared data. Functions like __syncthreads() in CUDA help manage this synchronization to prevent race conditions and ensure data integrity. 4️⃣ Resource Management: Effective management of memory resources involves optimizing the usage of different memory types, minimizing data transfers between host and device, and handling large datasets that may not fit entirely in GPU memory. Techniques such as data chunking, paging, and streaming can help manage these challenges. #gpu #cuda #memory #kernel #learning #embedded #systemdesign

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Verilog Meetup + Gowin + eFabless + Tiny Tapeout is the winning combination to prepare EE and CS students for the industry, RTL, DV and uArch positions. First students practice systemverilog-homework and basics-graphics-music examples using simulation, then they learn how to balance microarchitecture and timing on FPGA boards, then they get the basics of ASIC flow and PD layout with friendly TinyTapeout infrustructure based on Open Lane, as a precursor to Synopsys and Cadence flows, and finally they use eFabless manufacture their own silicon. Verilog Meetup examples are compatible with more than 30 boards from multiple vendors (Xilinx, Altera, Gowin, Lattice), however we particularly like Gowin for fast synthesis speed which makes the process of learning more interactive. One of the examples we demonstrate on Maker Faire in Vallejo, California is Sea Battle game, which we prototyped on FPGA board and implemented in ASIC using Tiny Tapeot. Thank you Andrea Vedanayagam / Efabless Corporation and Gowin Semiconductor Corp Andrew Dudaronek and Matt Venn from Tiny Tapeout for helping us on this exiting project and we welcome you to join Verilog Meetup at http://verilog-meetup.com

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Today's focus was on implementing a Single-Port RAM in Verilog. This memory module allows for either a read or write operation at a given time, using a single port for addressing and data transfer. The design includes features such as address decoding, write enable control, and synchronous operation with a clock signal. Single-Port RAM is a fundamental building block in digital systems, widely used for temporary data storage in embedded systems and processors. Pleased to see the seamless integration of memory design into my RTL journey! #RTL #Verilog #SinglePortRAM #MemoryDesign #DigitalDesign #100DaysOfRTL #Day80 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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🌟 Exploring LLMs: Cost and Context Window Comparison 🌟 When it comes to leveraging Large Language Models (LLMs), the cost and context window size play a pivotal role in decision-making. Here's a quick snapshot comparing various LLMs for 1 MILLION tokens—a scale so massive, it's equivalent to processing entire books or in-depth datasets in a single interaction! 📚🤖 Such a context size is a game-changer for applications like detailed analytics, long-form content creation, or enterprise-level conversations. Take a closer look at the numbers, and let's discuss—how would you harness the power of 1M tokens? #AI #LLMs #CostEfficiency #Innovation #AIApplications

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UVM Based Test Bench Environment for Verification of APB Protocol Yet another project I had undertaken to enhance my skills in understanding and building effective UVM test bench environments from scratch. APB (Advanced Peripheral Bus) is part of the ARM AMBA (Advanced Microcontroller Bus Architecture) protocol family, designed for low-power, low-bandwidth communication with peripherals in a system-on-chip (SoC). APB is typically used for connecting to peripherals that do not require high-speed access, such as UARTs, timers, GPIOs, and other registers. About my project: 1. Designed an APB RAM in SystemVerilog capable of storing and sending a total of 32 data elements each having a size of 32-bits 2. Built UVM test bench components and the entire Verification Environment from scratch to verify functionality of APB protocol. 3. Generated sequences for Write and Read operations in valid and invalid address ranges each having 15 transactions. Successfully verified functionality through behavioral simulation in Xilinx Vivado. Link for my project: https://lnkd.in/gVCkaNWF #rtldesign #rtlverification #vlsi #uvm #systemverilog #apb

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The other day I was pondering on the possibility of developing custom chips / Asics for bitnet. Didnt have a pleasant conclusion though When I was going through the required skills for the same. Learning the skillet could be done in say ~6 months (to learn FPGA programming and to simulate a chip in a FPGA board) and develop a FPGA program (which is just a virtual representation of a circuit to frankly speaking) to run the bitnet with high performance. I was all excited and decided to take on the surmountable project only to discover that the process of converting a FPGA program to ASIC is expensive af (costs easily between 100k to 1M usd+). Such high costs explain why we don't have Asics for AI systems while we already have Asics for crypto (as the operations in crypto is fixed, but in AI it changes with DL research so investing such a huge amount in asic for a fixed architecture only for the architecture to go out of date next year doesn't make sense) Hope a day comes in the distant future where I could have an asic printer at home just like a 3D printer (It would be extremely fun)🤞

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🕰 Exciting News: Introducing the Clock Alarm Project Report! 🎉 I'm thrilled to announce the release of the Clock Alarm Project Report, a collaborative effort between Abhiraj Ghose and Pallav Sharma(me), under the guidance of Dr. Ashutosh Srivastava, showcasing our innovative Verilog-based Clock Alarm system developed using Verilog and Vivado Simulator! 🌟 *Project Overview:* The Clock Alarm project is a versatile system that allows users to set alarms, stopwatches, and more, all implemented using Verilog and Vivado. With features like setting a time for the alarm, stopping the alarm, and functioning like a stopwatch, our project offers a user-friendly and practical solution for time management. 🔍 *Key Features:* - Set Alarm Time: Users can easily set the desired time for the alarm to ring. - Alarm Functionality: Once the set time is reached, the alarm rings to alert the user. - Stop Alarm: Users can stop the alarm manually once it starts ringing. - Stopwatch Mode: The system also functions as a stopwatch, allowing users to track time intervals as needed. 🛠 *Tools Used:* Our project was developed using Verilog, a hardware description language, and Vivado, a comprehensive design suite provided by Xilinx. 🚀 *Next Steps:* Excited to share our findings and insights from this project with the community! Stay tuned for more updates and future projects as we continue to explore new opportunities and innovations in hardware design. 🙏 *Gratitude:* A special thank you to Bennett University, School of CSET Bennett University, India, Prof. (Dr. ) Abhay Bansal, Dr. Ashutosh Srivastava and everyone who has supported us throughout this project, including mentors and peers. Your encouragement and guidance have been invaluable to our success. Let's continue pushing the boundaries of innovation together! ⏰💡 #ClockAlarm #Verilog #Vivado #HardwareDesign #ProjectReport #Innovation

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Recently I took up the R&D activity of Mode Merge technology.    Since it was only an evaluation my Lead suggested to take an IP which has been taped out.   I took SERDES 64Gbps chip. I started my Mode merging journey by manually adding all the necessary inputs. We had 2 Func modes both high speed and low speed which I wanted to merge into Single mode. Once I generated Merged SDC and ran STA to my surprise I saw timing was 100% correlated with original run. But when I saw the analysis coverage report it showed 100% untested, since it was a tapeout database both global timing reports were clean. Once I opened the merged SDC We saw some case analysis missing.   Upon investigation I see 2 more issues in the EDA tools that the Analog library that I took for reading had 5 modes ( 2 func + 3 scan ) even after giving func modes for merging I see the Merged Scenario is enabling all the modes due to which wrong Library setup time arc is being picked up, - for time being I manually added set_disable_timing to block scan related arcs to get picked by EDA tools.    In my evaluation I am able to achieve Timing correlation when I merge 2 func modes into 1 func mode.   Now I wanted to enable Mode merge technology in SERDES 112Gbps which was a production chip. My strategy was simple I wanted to merge 2 func modes ( high speed+low speed) into 1 mode and 3 scan modes ( at_speed, shift, capture) into 1 mode. Imagine our signoff strategy is every mode takes 10 scenarios ( 4 setup corners + 6 hold corners ). The target was to reduce 50 Scenarios to 20 Scenarios.   When I enable ECO tool report generation inside STA flow the runs are getting crashed. The main culprit was the set_sense command which gets dumped inside Merged SDC. To avoid tool crashes I tried to experiment with latest Tool version, However STA runtime is huge how are we going to reduce STA runtime? We came up with one more variable that can reduce set_sense arc size collection this helped us in dumping more set_sense commands due to which the number of lines increased in the file which is fine because STA tool has a multi threading feature to take care of.   We are able to achieve Merged STA Runtime on par with original SDC run and ECO tool runtime reduced 50% which is expected since reading 20 timing window files is more faster than reading 50 timing window files. Overall Disk space savings per Run was 50%. Mode merge technology helped us reduce 50 scenarios to just 20 scenarios.    Real time deployment took me 4 months of Hard Work and long hours of debugging helped us improve the Productivity of STA engineers.   Happy Learning.. 😊 #onemarvell#vlsi#sta#learnings

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NVIDIA is seeking best-in-class ASIC Verification Engineer to verify the world’s leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position will be working across many #NVIDIA teams from software, to architecture, design, methodology, and more. The GPU is used in applications from consumer graphics, through self-driving cars, to artificial intelligence, all of which you will be involved in and learn about. #electricalengineering #computerengineering #computerarchitecture #asic #verification #systemverilog #testbench #debugging #uvm

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On Day 25 of my 100 Days of RTL Coding, I focused on implementing a tri-state buffer using Verilog. This component allows control over the signal flow, enabling it to be in one of three states: logic high, logic low, or high-impedance (Z), making it essential for bus systems where multiple devices need to share the same data lines. The design was simulated to ensure its correct functionality in various conditions. Looking forward to continuing this journey with more complex digital circuits! #RTL #Verilog #DigitalDesign #TriStateBuffer #100DaysOfRTL #Day25 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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