Srini Srinivasan

Srini Srinivasan

San Jose, California, United States
2K followers 500+ connections

About

Srini Srinivasan has over 35 years of experience in developing and managing early stage…

Articles by Srini

  • Component Stress Characterization

    Component Stress Characterization

    When hardware or software architectural components are stressed to their limit under carefully controlled test…

  • Stress Testing

    Stress Testing

    Modern mobility platforms – such as automobiles, aircraft, drones, ships and spacecraft – have very complex computing…

Activity

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Experience

  • nHansa Graphic

    nHansa

    San Jose, CA

  • -

    Palo Alto, CA

  • -

    San Jose, CA

  • -

    Greater Pittsburgh Area

  • -

    Greater Pittsburgh Area

Education

  • The Wharton School Graphic

    University of Pennsylvania - The Wharton School

    -

    - Finalist, Kauffman Fellows Program in Venture Capital
    - Won Regional Championship in the national Venture Capital Investment Competition, evaluating investments with issue identification, risk mitigation and term sheet presentation

  • Application of Finite Element Modeling to Computational Fluid Dynamics to study Bifurcation and Chaos development in a closed flow system

Volunteer Experience

  • SVForum Graphic

    Co-Chair, Emerging Technology SIG

    SVForum

    Science and Technology

    SVForum fosters innovation, entrepreneurship and leadership within the San Francisco/Silicon Valley ecosystem of individuals/businesses participating in emerging technologies

Publications

  • Architecture Modeling for Resource Margin Estimation

    High Confidence Software and Systems Conference (HCSS)

    Rate Monotonic Analysis (RMA), ARINC 653, or similar schedulability analyses have been traditionally used to guarantee that all real-time tasks have sufficient computing resources to meet mission requirements. Schedulability analysis provides critical evidence for most safety or airworthiness certification processes. We illustrate an architecture model, inspire by AADL, that has been used to conduct RMA and also illustrate that it can be augmented to study interference effects due to shared…

    Rate Monotonic Analysis (RMA), ARINC 653, or similar schedulability analyses have been traditionally used to guarantee that all real-time tasks have sufficient computing resources to meet mission requirements. Schedulability analysis provides critical evidence for most safety or airworthiness certification processes. We illustrate an architecture model, inspire by AADL, that has been used to conduct RMA and also illustrate that it can be augmented to study interference effects due to shared computing resources.

    The architecture model describes the system hardware architecture, software architecture and the mapping between the two. Thus this model captures one or more deployment scenarios from a resource usage perspective when populated with relevant design data in design databases/code and the profiling data captured from tests in the lab. RMA can then be used to mathematically guarantee schedulability, and calculate available resource margins.

    We demonstrate that such a model can be augmented to empirically estimate resource margins available when using modern multicore processors with shared cache. To study the effect of interference due to shared hardware resources, we augmented the RMA deployment architecture model with the ability to automatically create, deploy, execute and analyze multiple deployment models, or tests. Each test represents a point in a high-dimension parameter space that describes a combination of application characteristics that may affect performance in the presence of shared cache. The model is used to automatically execute the tests and collect profiling data, and extract the inflated execution times due to cache interference. This methodology and automated tool can thus be used for empirically establishing a reasonable, high-confidence upper bound for cache interference effects, and estimate available resource margins in the context of engineering practices commonly used in certifiable real-time systems.

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  • Empirical Bounds of Multicore Cache Interference for Real-Time Schedulability Analysis

    2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC), San Diego, CA, USA, 2019

    Multicore processors offer significant advantages of weight, power, and space to embedded real-time developers, making their adoption almost inevitable. Also, system sustainability and economies of scale will increasingly make multicore devices indispensable. However, predictability of performance, specifically, establishing realistic upper bounds on execution time for schedulability analysis is a significant challenge to certification. This paper describes a methodology for empirically…

    Multicore processors offer significant advantages of weight, power, and space to embedded real-time developers, making their adoption almost inevitable. Also, system sustainability and economies of scale will increasingly make multicore devices indispensable. However, predictability of performance, specifically, establishing realistic upper bounds on execution time for schedulability analysis is a significant challenge to certification. This paper describes a methodology for empirically establishing a reasonable, high-confidence upper bound for cache interference effects in the context of engineering practices commonly used in certifiable real-time systems.

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  • SPRUCE: Systems and Software Producibility Collaboration and Evaluation Environment

    Proceedings of the 2009 International Symposium on Collaborative Technologies and Systems

    Proceedings of the 2009 International Symposium on Collaborative Technologies and Systems, Page xlv IEEE Computer Society Washington, DC, USA

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  • NAOMI - An Experimental Platform for Multi-modeling

    Proceedings of the 11th international conference on Model Driven Engineering Languages and Systems

    ISBN: 978-3-540-87874-2

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  • Temporal Models in UML

    Dr. Dobb's Journal

    Timeliness and performance in real-time object design, By Bruce Powel Douglass and Srini Vasan

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Patents

  • Method for representing multi-models

    Issued US 8,620,960

  • System and method for constructing and editing multi-models

    Issued US 8,620,959

Languages

  • Tamil

    Native or bilingual proficiency

Organizations

  • First Lego League

    Coach

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