Gary Oliverio

The unsung heroes of this 5G narrative are time and phase synchronization. These critical functions are what make TDD truly shine. By meticulously coordinating the timing of transmissions, we can optimize spectrum utilization like never before. This precision avoids the risk of cross-slot interference, ensuring that downlink and uplink channels coexist harmoniously, paving the way for a seamless flow of data. Read the blog on our website. #5G #TDD #Telecommunications #NetworkSynchronization

2

When working with a PCBA supplier, communication is key. For your supplier to meet your needs, it's crucial that they understand your project's design goals and specifications, and can easily reach out to you. By choosing a reliable supplier and communicating effectively, you should have no problem achieving your desired end result. Here are some helpful tips and suggestions for improving communication with your PCBA supplier.

2

1 Comment

7 best practices for designing vias in #RFPCBs ♦️1. Design the via to maintain low return loss at the input, especially when dealing with wide bandwidths extending into the GHz range. ♦️2. Ensure the presence of vias does not negatively impact the insertion loss. While insertion loss is not usually the focal point for vias, it is still a critical factor. ♦️3. Maintain a minimum spacing of  λ/10 between the ground vias. For instance, at 2.4 GHz, the clearance should be 6 mm. ♦️4. Place ground-connected vias near the PCB edges to reduce RF losses through the laminate. The EMFs are less confined near the edges. However, avoid placing them too close to the edge to prevent mechanical issues. ♦️5. For mmWave PCBs, implement a via fence around grounded coplanar waveguides to enhance high-frequency isolation. This technique also suppresses frequencies below a cut-off and prevents mmWave interference with other signals. ♦️6. Avoid return or stitching vias for slow-speed signals with rise times higher than 20 ns (e.g., GPIOs, I2C, and control signals) because such signals are less sensitive to impedance discontinuities. ♦️7. Prioritize transition methods and the implementation of return paths (e.g., stitching vias) for higher-frequency signals or those with fast rise times to minimize radiation or crosstalk. 💡Read the blog to learn 4 RF PCB via design challenges: https://lnkd.in/gTvqcWZr #HighFrequencyDesign #PCBDesign #ViaDesign #ElectricalEngineering

36

2 Comments

For #CostModelMonday, here's a chart that started out focused on #HybridBonding, but really just came to be about lots of #chiplets versus a few. I ran a design that has the same total area of silicon coming in, but it's four 4x4mm chips versus sixteen 2x2mm chiplets. The bonding method is hybrid bonding, and the assumption is that placing lots of chiplets takes longer (a truth more than an assumption...), but there may be a yield benefit to handling and placing the smaller die. I found a crossover point by adjusting yields; in the chart below, the total cost is the same, but the two designs have different costs in different categories.

20

2 Comments

Still some spots left for the #ASIC workshop where I'll be tomorrow (Nov 7th) with Matt Venn to help you get from chip design theory to taping out an actual digital design! If you're in #SanDiego, join Tiny Tapeout, UC San Diego and IEEE Region 6 to get in on the #opensource #ASIC action and make it happen :) https://lnkd.in/eXZRE9e4

22

5 Comments

Passive elements are integral to a multitude of electronic devices, ranging from mobile phones and computers to healthcare apparatus and industrial equipment. Their subtle yet essential function in influencing circuit performance is of great importance. In PCB design, these elements are carefully positioned and linked to produce specific results.

2

In this blog, we talk about the need to verify analog/mixed-signal blocks using a UVM-MS-based testbench and explore how to verify analog/mixed-signal blocks using the features of MS-MDV and UVM-MS. Read more and see helpful videos and training materials. https://ow.ly/zgBV50RpO1n

12

If you're navigating the challenge of connecting a CMOS camera sensor with a parallel output or a CCD sensor with an ADC parallel output to your NVidia board with MIPI CSI2, here are two implementation options to consider: - Option 1: Utilize the Toshiba TC358748XBG(EL). It comes with limitations such as being restricted to a single resolution without features like multistreaming and ROI. - Option 2: Opt for the Lattice CrossLinkPlus FPGA. This choice offers all the capabilities you need, but it comes with a higher price tag. You decide how we will design it for you.

7

Big WiFi performance gains are available to those that are willing to take a few extra (easy) steps when planning and deploying their network. This is how you do it with Alta Labs

10

Power consumption was the main topic at OFC 2024 in San Diego, CA. The g.metro discussion has laid out many things including the idea of providing telemetry data. What this can do and how transceiver customization in access networks can optimize power consumption is the topic of this week's article. Enjoy the read. #tranceiver #access #photonics #gmetro #power #energysavings

14

The total market for Power Converters will exceed $164 BILLION by 2029 💡 As the #electricvehicle (#EV) market continues growing (followed by DC charging infrastructure), the need for #greenenergy sources becomes more critical to sustain the environmental benefits of #EVs. This drives the demand for #photovoltaic (PV) and #battery energy storage systems (BESS) to help balance the grid. The increasing synergy between these segments (EVs, DC charging, BESS, and PV) is boosting the demand for power converters. These four segments are projected to account for more than half of the total market, which is expected to reach $164.1 billion by 2029. At the same time, HVDC is increasingly being considered for grid upgrades. HVDC #technology is also driven by the increasing number of offshore wind installations. The HVDC power converter market will reach $3.8 billion by 2029 with a CAGR2023-2029 of 12.8%. Thanks again to Yole Group for the full article with more background, insights and charts via the link below 💡🙏👇 https://lnkd.in/emVR8tA4 #semiconductorindustry #automotiveindustry #tech #innovation #chips #automotivetechnology #batterytechnology #SiC #renewableenergy #it

30

Micron’s team delivered a record revenue quarter for our fiscal Q1, which represented an 84% increase from our year-ago revenue results. Our data center revenue reached a record high, making up more than half of our revenue for the first time, with revenue growing 400% year-over-year. Our shipments of HBM — a critical product for #AI data center servers — were ahead of plan and we doubled HBM revenue from the previous quarter. Customer inventory reductions in consumer-oriented segments and seasonality are slowing near-term bit shipment estimates. That said, we expect this adjustment period to be relatively brief and anticipate customer inventories reaching healthier levels by spring, enabling stronger bit shipments in the second half of fiscal and calendar 2025. Longer term, we see particularly robust growth ahead for HBM, with the total addressable market growing from $16 billion in 2024 to greater than $100 billion in 2030 (bigger than the entire combined DRAM/HBM market today). We continue to apply our technology leadership to create leading-edge products — from high-capacity server modules to SSDs, low-power DRAM and mobile memory — that address the high-growth segments of multiple markets, putting Micron in the strongest competitive position in our 46-year history.

2,011

66 Comments

Pulse Electronics Corporation TLVR Dual Winding Inductors. These inductors feature TLVR topology that enables faster transient response and utilizes a dual-winding power bead inductor. https://lnkd.in/gnYMdzbY

1

When adding stitching vias to a PCB, strategic placement is crucial. It's essential to position them around the edges of critical components, high-speed signal traces, and ground planes. This ensures effective shielding and enhanced signal integrity. The appropriate size and spacing of stitching vias are chosen based on your application's specific requirements and the PCB's material. #PCBdesign

5

Check out this very interesting webinar demonstrating how Peraso Inc.'s novel mmWave technology can be used in a variety of applications!

2

🎙️ Listen to Kirsch Mackey as he discusses the mission of #JITX and its revolutionary impact on #electricalengineers, #PCBdesigners, and #softwareengineers. Kirsch talks about how JITX is leveraging #AI to streamline tedious tasks and accelerate the design process, saving engineers hours of valuable time. Learn about the key advantages of JITX's programmatic approach, from component selection to auto routing, and how it's transforming the way engineers work. Kirsch explains their seamless integration of real-time data sourcing and constraint management, allowing #engineers to focus on design validation rather than manual calculations. Don't miss this in-depth discussion on the future of #PCB design and the paradigm shift towards automated solutions. Tune in for this second episode of Trace Talks! Watch on YouTube: https://lnkd.in/g8nZ3pec Listen on Spotify: https://lnkd.in/gjX745zw https://lnkd.in/gGwuaFMa

7

I recently had the opportunity to offer my thoughts on where the industry is headed with All About Circuits. There is incredible pressure on companies as they work to keep up with current trends, but with the right tools and resources, companies can leverage T&M to reduce complexity, embrace new technologies, and drive innovation.

85

2 Comments