Chan Nam Tieu

Accessing state-of-the-art engineering equipment without ever leaving home? University of Washington, Department of Electrical & Computer Engineering professor Rania Hussein founded the Remote Hub Lab to make engineering education more accessible – regardless of their geographic location. 🌍🖥️ The Remote Hub Lab uses virtual reality and other tools to let students access physical engineering equipment from anywhere in the world. The Lab also employs a process called “digital twinning” to create virtual models that mirror real-world systems, which enable students to experiment, learn and innovate in a risk-free, cost-effective environment. “It prepares students for the demands of modern engineering, where they need to work seamlessly between digital and physical systems. This hybrid approach ensures that students are not only gaining technical knowledge, but also learning how to innovate in real-world settings, which is crucial for the future of engineering education,” says Hussein. Learn more in our latest Q&A: https://bit.ly/4h9Iipt

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🚨 Calling all Graduates! NVIDIA released its New Grad ASIC Verification Engineer role. Here's what you need to know: ⚙ Located in Santa Clara, CA ⚙ Full-time pay is ~$92,000-$180,000/yr ⚙ Full-time(40hrs/week) So if you have And have experience in SystemVerilog, C and/or C++, Python and/or Perl Then consider applying to NVIDIA now! Here's the link 👇 https://lnkd.in/gK7MNtDW You got this! ＿＿ Found this useful? Consider re-sharing 🔁 and following me Mark Benliyan for more content like this! #newgrad #nvidia #coding #softwareengineering

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I recently worked on implementing a palindrome constraint in SystemVerilog, and I’m excited to share my experience with the community! Palindromes are sequences that read the same backward as forward, and crafting a randomized test constraint to generate such sequences was both challenging and rewarding. This exercise not only reinforced my understanding of randomization in SystemVerilog but also showcased how effectively constraints can be applied to solve unique verification challenges. Here’s a snippet of the code I developed: ✅ How constraints can be applied for specific patterns ✅ Importance of verifying the logic using randomized simulations ✅ Fun in merging algorithms with hardware verification I’d love to hear your thoughts or approaches to similar constraints! Feel free to connect or share your ideas in the comments. 😊 #SystemVerilog #HardwareVerification #Coding #PalindromeConstraint

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I'm beyond thrilled to share that I’ve completed all 182 Verilog HDL problems on HDLBits and currently hold the #1 rank! 🎉 This journey has been nothing short of transformative. From basic concepts to more complex designs, each problem pushed me to think critically and increase my skills in Verilog. It’s been an incredible way to strengthen my foundation in digital design and gain a deeper appreciation for the nuances of hardware description languages. What stood out the most was how these challenges bridged the gap between theory and practical implementation. They’ve given me a new perspective on how digital systems are designed, optimized, and brought to life. Completing this milestone has fueled my passion for hardware design even further. I'm eager to take on more advanced projects, dive deeper into fields like FPGA design, system-on-chip (SoC) architecture, and VLSI, and continue growing in this exciting domain. I want to express my heartfelt gratitude to everyone who supported and encouraged me along the way. Your motivation played a big role in helping me stay focused and persistent. Here’s to more milestones, more learning, and more growth in this fascinating field! #Verilog #HDL #DigitalDesign #FPGA #VLSI #HardwareDesign #LearningJourney #AchievementUnlocked

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Dive into Karl Freund's article on the rise of physical AI in robotics. Learn how leading companies are leveraging NVIDIA technologies to transform the industry, along with recent advancements and breakthroughs.

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Dive into Karl Freund's article on the rise of physical AI in robotics. Learn how leading companies are leveraging NVIDIA technologies to transform the industry, along with recent advancements and breakthroughs.

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Dive into Karl Freund's article on the rise of physical AI in robotics. Learn how leading companies are leveraging NVIDIA technologies to transform the industry, along with recent advancements and breakthroughs.

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The other day I was pondering on the possibility of developing custom chips / Asics for bitnet. Didnt have a pleasant conclusion though When I was going through the required skills for the same. Learning the skillet could be done in say ~6 months (to learn FPGA programming and to simulate a chip in a FPGA board) and develop a FPGA program (which is just a virtual representation of a circuit to frankly speaking) to run the bitnet with high performance. I was all excited and decided to take on the surmountable project only to discover that the process of converting a FPGA program to ASIC is expensive af (costs easily between 100k to 1M usd+). Such high costs explain why we don't have Asics for AI systems while we already have Asics for crypto (as the operations in crypto is fixed, but in AI it changes with DL research so investing such a huge amount in asic for a fixed architecture only for the architecture to go out of date next year doesn't make sense) Hope a day comes in the distant future where I could have an asic printer at home just like a 3D printer (It would be extremely fun)🤞

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🚀Day 51/100: Implementing Booth's Multiplier in Verilog! 🚀 Today, I explored the implementation of Booth's multiplier in Verilog. Booth's multiplier is an efficient algorithm for multiplying binary numbers, which reduces the number of addition operations needed by encoding the operands differently. This makes it a powerful tool for digital arithmetic operations.For more information, including synthesis results, you can check my GitHub link: https://lnkd.in/gumwBnH2 #100DaysRTL #VLSI #Verilog #DigitalDesign

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🚀 Excited to Share My 13th YouTube #techshort! 🚀 In this tech short, learn how to write a constraint to randomly generate 0, 1, x, and z states in SystemVerilog. Perfect for anyone looking to enhance their design verification skills and understanding of constraints in SystemVerilog. 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #staytuned 📚

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𝐄𝐧𝐡𝐚𝐧𝐜𝐞 𝐘𝐨𝐮𝐫 𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐒𝐤𝐢𝐥𝐥𝐬 𝐰𝐢𝐭𝐡 𝐓𝐡𝐞𝐬𝐞 𝐓𝐨𝐩 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞𝐬! Embarking on the journey to master Verilog? Here are some excellent resources to guide you: 1. HDLBits (Link: https://lnkd.in/gkPTvT4h) 2. Chip Verify (Link: https://lnkd.in/gkE8KtgQ) 3. ChipEdge 4. Infosys Springboard (Only one is avalible. Link: https://lnkd.in/ge-geXkw. If the link do not open try to search, VLSI Digital Design - Chip Design and Verilog Programming) 5. Udemy 𝗡𝗼𝘁𝗲: 𝗜𝗳 𝘁𝗵𝗲 𝗹𝗶𝗻𝗸 𝗱𝗼 𝗻𝗼𝘁 𝘄𝗼𝗿𝗸 𝘁𝗵𝗲𝗿𝗲 𝗺𝗶𝗴𝗵𝘁 𝗯𝗲 𝘀𝗶𝘁𝗲 𝗶𝘀𝘀𝘂𝗲𝘀. 𝗦𝗼, 𝘀𝗲𝗮𝗿𝗰𝗵 𝗯𝘆 𝗻𝗮𝗺𝗲 𝗮𝘁 𝘁𝗵𝗮𝘁 𝗽𝗼𝗶𝗻𝘁. 𝑭𝒐𝒓 𝒎𝒐𝒓𝒆 𝒕𝒊𝒑𝒔 𝒇𝒐𝒍𝒍𝒐𝒘 Values #Values #GetvaluesfromValues #resources #VLSI #VLSIPrep

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🚀 Exploring Object-Oriented Programming in SystemVerilog 🚀 Today, I worked on creating a custom class in SystemVerilog to simulate memory transactions! Here’s a breakdown of my recent work: 🔹 MemTrans Class Design: I designed a class MemTrans that simulates memory transaction operations. The class contains: An 8-bit data input (data_in) to represent data being written to memory. A 4-bit address (address) to represent the memory location. A print() function to display the values of data_in and address. 🔹 Custom Constructor: The constructor initializes both data_in and address to zero upon object creation, ensuring a clean start for the simulation. 🔹 Waveform Generation: I also incorporated waveform generation using $dumpfile and $dumpvars to generate a VCD (Value Change Dump) file, which can be visualized using tools like GTKWave. This provides a clear visualization of signal transitions during simulation. 🔹 Simulation Output: Here’s the output I received from running the simulation: data_in: 00, address: 0 This shows that both the data_in and address are initialized to zero, and the waveform reflects this with consistent low values throughout. 🔹 Next Steps: I am excited to explore more advanced features like memory operations and handling different data states in future simulations! Feel free to check out my code on EDA Playground for further insights into SystemVerilog object-oriented programming and simulation techniques. #SystemVerilog #ChipDesign #EDA #WaveformAnalysis #OOP #Simulation #Verilog #HardwareDesign #ICDesign #Verification #VLSI #Semiconductor #DigitalDesign #DigitalElectronics #LearningJourney #KeepLearning #HappyLearning

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I am excited to announce that I have completed my summer internship in VLSI design on the topic of "Comparative Analysis of CAM cells" Here is a brief overview of my project: A CAM (Content Addressable Memory) takes the input as a reference data, searches through the stored data in the memory and returns the memory address of the matched data with the input as the output This project is a comparison based Research paper in which we have made comparison between different CAM cells consisting of different no. of transistors, varying in area and characteristics like 9T TCAM, 10T BCAM, 11T TCAM and 11T p_xor_n_pdn CAM cells. The comparison is done for different parameters like Read access time i.e. Read Delay, Write access time i.e. Write Delay and Match Delay as well as characteristics like average current, average power, Power Delay Product (PDP), Energy Delay Product (EDP), Read Static Noise Margin (RSNM) and Combined Word Line Margin(CWLM) have also been compared by calculating their mean, standard deviation and variability. Greatful for the support and guidance by our Teachers and mentors. Will continue exploring the exciting world of VLSI. #VLSI #PowerTechnology #Electronics

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🚀 Day 7 of my 30-Day RTL Coding Challenge in Verilog! 🚀 Today, I took a deep dive into designing a 32-bit adder using two 16-bit adders, each composed of 16 full adders. This journey has been incredibly rewarding, and I'm excited to continue pushing my boundaries and expanding my knowledge in digital design. Stay tuned for more updates as I progress through this challenge! 💻🔧 #RTL #Verilog #DigitalDesign #CodingChallenge #LearningJourney

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On Day 45 of my 100 Days of RTL Coding, I focused on converting an SR flip-flop into a T flip-flop using Verilog. This conversion required reconfiguring the logic to achieve the toggling functionality of the T flip-flop while ensuring the Set and Reset inputs were appropriately utilized. Through this process, I deepened my understanding of flip-flop functionality and the relationships between different types of sequential circuits. Looking forward to more challenges and learning ahead! #RTL #Verilog #DigitalDesign #FlipFlop #100DaysOfRTL #Day45 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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🔧 Just completed an 8x3 Priority Encoder in Verilog! 🛠️ This digital circuit prioritizes eight input signals, encoding the highest-priority one into a three-bit binary output. Excited to share this project showcasing my Verilog skills! #DigitalDesign #Verilog #qurtus #HardwareDevelopment #HardwareDescriptionLanguage #Engineering

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NEW YORK: Qualcomm has explored the likelihood of <!-- -->acquiring<!-- --> parts of <!-- -->Intel<!-- -->‘s <!-- -->design enterprise<!-- --> to spice up the corporate’s product portfolio, in keeping with two sources aware of the matter. The cell chipmaker has examined acquiring totally different pieces of Intel, which is struggling to generate money and seeking to shed <!-- -->enterprise<!-- --> models and unload different property, the folks stated. Intel’s shopper PC design enterprise is of important curiosity to Qualcomm executives, one of the sources stated, however they’re all of the corporate’s design models. Other pieces of Intel such because the server phase would make much less sense for Qualcomm to amass, one other supply with data of Qualcomm’s operations stated. Qualcomm has not approached Intel a couple of potential acquisition, an Intel spokesperson stated. Intel is “deeply committed to our PC business,” the spokesperson stated. Qualcomm declined to remark. Shares of Qualcomm slid as a lot as 1.3 per cent and Intel rose 1 per cent in US pre-market buying and selling on Friday. The $184 billion Qualcomm, which is thought for chips present in smartphones and counts Apple as a buyer, has been engaged on plans to purchase pieces of Intel for months. Qualcomm’s curiosity and plans haven’t been finalized and will change, in keeping with the sources. The two sources declined to be named as they weren’t licensed to debate the matter publicly. Intel reported a disastrous second quarter final month, which included a 15 per cent discount in its employees and a pause on paying dividends. Executives are grappling with how you can proceed to fund the corporate’s manufacturing plans and generate money. Its PC shopper enterprise income dropped 8 per cent to $29.3 billion final yr, amid total weak spot within the PC market. Once identified for its “Intel Inside” advertising marketing campaign, Intel’s shopper group makes laptop computer and desktop chips utilized in machines all over the world. Executives have stated the introduction of synthetic intelligence PCs will drive shoppers to improve their computer systems and generate extra gross sales. Qualcomm generated $35.82 billion in total income in its final fiscal yr. Earlier this week, Intel launched a brand new PC <!-- -->chip<!-- --> referred to as Lunar Lake that its executives stated presents superior efficiency for AI functions. Taiwan Semiconductor Manufacturing Co. fabricated important parts of the chips, which Intel traditionally did in-house. Intel’s board is about to satisfy subsequent week to weigh a proposal from Intel CEO Pat Gelsinger and different executives on how you can trim its operations in an try to avoid wasting money. Potential choices embrace a sale of its programmable chip unit, Altera, Reuters reported.

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