Aditya Bansal

Aditya Bansal

White Plains, New York, United States
979 followers 500+ connections

About

I am an electronics engineer at heart who loves building physical products which simplify…

Activity

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Experience

  • KINETIC Graphic

    KINETIC

    New York

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    New York, NY

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    New York

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    Yorktown Heights, NY

Education

  • Purdue University

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    Activities and Societies: IEEE, ECE Graduate Student Association

    - Graduate Research Assistant (2004-2007) under Prof. Kaushik Roy, Nanoelectronics Research Laboratory.
    - Represented School of ECE in Peer Mentoring Program organized by Graduate School of Purdue University, 2006-07.
    - President of Electrical and Computer Engineering Graduate Student Association (ECEGSA), 2005-2006.

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    - Graduate Research Assistant, Dr. Kaushik Roy, Nanoelectronics Research Laboratory, Summer 2003.
    - Teaching Assistant, ‘Microprocessor Systems and Interfacing’ EE362, from Fall 2002 to Spring 2004, Purdue University.
    - Teaching Assistant, ‘Introduction to Digital System Design’ EE270, in Summer 2003, Purdue University.
    - Teaching Assistant, ‘Linear Circuit Analysis II’ EE202, Spring 2002, Purdue University.
    - Teaching Assistant, ‘Electronic Measurement Techniques’ EE207, Fall 2001,…

    - Graduate Research Assistant, Dr. Kaushik Roy, Nanoelectronics Research Laboratory, Summer 2003.
    - Teaching Assistant, ‘Microprocessor Systems and Interfacing’ EE362, from Fall 2002 to Spring 2004, Purdue University.
    - Teaching Assistant, ‘Introduction to Digital System Design’ EE270, in Summer 2003, Purdue University.
    - Teaching Assistant, ‘Linear Circuit Analysis II’ EE202, Spring 2002, Purdue University.
    - Teaching Assistant, ‘Electronic Measurement Techniques’ EE207, Fall 2001, Purdue University.

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    Activities and Societies: Chairman of Electrical Engineering Society (EES) at IT-BHU, India, 2000-2001. Convener of IEE (UK), Students’ Chapter at IT-BHU, India, 2000-2001.

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Patents

  • Estimating delay deterioration due to device degradation in integrated circuits

    Issued USPTO

    A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the…

    A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.

    See patent

Languages

  • Hindi

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