Aaron Costa

Great to see attention on the high-bandwidth memory systems, which have the critical role of keeping high-performance AI processors supplied with data. 

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Dive into the difference between #CPU, #GPU, and #NPU. We explore what are Central Processing Units, Graphics Processing Units, and Neural Processing Units. https://lnkd.in/e3Xy-MyP

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Dynamic load balancing. Built-in. The latest #IntelXeon processors include the Intel Dynamic Load Balancer (Intel DLB) accelerator. Learn how this can help you optimize network performance. https://intel.ly/3Yg8SEH

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When designing with SSD's one must consider how temperature affects the SSD's ability to store and retain data. Learn how temperature impacts NAND data retention in this Virtium white paper: https://lnkd.in/e5xwZscJ

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When designing with SSD's one must consider how temperature affects the SSD's ability to store and retain data. Learn how temperature impacts NAND data retention in this Virtium white paper: https://lnkd.in/e5xwZscJ

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Last chance to register! https://lnkd.in/ekseYECp Don't miss your opportunity to learn about the functions of the AMD Versal Network on Chip. #amd #xilinx #networkonchip #systemonchip #versal #hardwaredesign #hardwareengineering #programmablelogic

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#RISCV is revolutionizing hardware design through unprecedented collaboration, bridging academia and the broader industry. This flexible architecture is filling a critical need and driving innovation. Learn more about the open standard’s momentum and ecosystem via Semiconductor Engineering: https://hubs.la/Q02y_7dk0

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thinking about the r10k - mipspro was amazing. just look at the verbose output from the software pipelining pass. i think there's pldi paper on a showdown between this algorithm and some ILP-based scheme. i should read again. .BB16.naive_matmuli: # 0xb6c  #<loop> Loop body line 263, nesting depth: 3, estimated iterations: 256  #<loop> Not unrolled: estimated schedule improvement < 10%  #<loop> Not unrolled: disable analysis w/-CG:unroll_analysis=off  #<swps>   #<swps> Pipelined loop line 263 steady state  #<swps>   #<swps>  512 iterations before pipelining  #<swps>    Not unrolled before pipelining  #<swps>  18 cycles per iteration  #<swps>   3 mem refs   ( 16% of peak)  #<swps>   7 integer ops ( 19% of peak)  #<swps>  10 instructions ( 13% of peak)  #<swps>   1 short trip threshold  #<swps>   8 integer registers used.  #<swps>   #<swps>   6 min cycles required for resources  #<swps>  17 cycles required for recurrence(s)  #<swps>   6 operations in largest recurrence  #<swps>  18 cycles in minimum schedule found  #<swps>  #<swp>   #<swp> Pipelined loop line 263 replication 0  #<swp>   #<freq>  #<freq> BB:16 frequency = 56481544.00000 (heuristic)  #<freq> BB:16 => BB:15 probability = 0.99610  #<freq> BB:16 => BB:18 probability = 0.00390

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Do closures like the #Intel Shannon facility signal consolidation or selectivity in site location? What's unclear is how Intel will treat the remote employees. Does anybody know what will happen to those who are fully remote? Does anybody know if there are other planned facility closures modeled on the same pattern? #softwareengineering #itnews #technews #research #programming #devops #itcareers #techcareers

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I have been reading my copy of “The RISC-V Reader” by David Patterson and Andrew Waterman. They compare their architecture with MIPS, ARM and the x86. They point out that it is a newer architecture so that they can avoid making the mistakes of the past. Back in my mind I hear Ian Malcolm of Jurassic Park fame responding with “yeah...and you're making all new ones.” Truth be told, many of the “mistakes” they are referring to are not really mistakes. They are just features that come from a particular mind set. They actually used the BCD math features of the x86 as their example of what is obsolete. I can see that BCD encoding will always be useful for applications that want to minimize rounding errors in our decimal biased writing system. Indeed, it is our decimal bias that should be considered to be obsolete. But I seriously doubt that these two authors are going to be successful at coercing the world's population to start writing our numbers (including scientific notation!) in base 16 instead of base ten. Chapter 2 compares the four architectures using an algorithm called “Insert Sort”. Just for fun I wrote one for the newest version of ϕEng32 and hand assembled it. The sizes of each of the assembly language routines were: RISC-V32: 76 ARM32:   76 MIPS32:  96 x86−32:  45 ϕEng32:  53 I was impressed that the x86 had the best code density of all five. It is not surprising since it uses a variable length instruction format and has only 16 general purpose registers which saves on code space. The newest variant of ϕEng32/64 has 16 Address Registers alone. Besides those they have 16 Integer Registers if you view them as Working 64-bit registers. This puts it on par with RISC-V and ARM64. I would call ϕEng32/64 a MISC (For Moderate Instruction Set Computer) architecture because it really isn't minimal and it isn't maximal either. The instructions are all fairly simple. For most operations, one operand can be in a register or memory. They contain built-in features that are lacking in true RISC processors like zero and sign extension for operands that are either in registers or memory. The encoding technique was included for the first time in some instructions that assist in array indexing. Element sizes are not just limited to the common ones like 1, 2, 4 and 8 as in the x86 address modes used. #RISC #programming #electronics #assembly

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Read Dan Wakefield's latest article on Shattering the Memory Wall and we can help you with how next gen processors can solve your organizations memory capacity. https://lnkd.in/gJDHxpHe

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Are you considering using open source tools to teach #FPGA, #VLSI, chip design, #verification? If so you've probably wondered how stable they are, how the students respond. What are the pros and cons? In this article Dustin R. shares his experiences of using the open source tools for teaching at University of California, Santa Cruz https://lnkd.in/ddNRZwpX

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What are your thoughts on Risc-V? Do you know what it is used for? Does RISC-V have a future? Check out the article below and learn more about the function, benefits, and future of RISC-V. https://buff.ly/3Bcsr9c

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[Press Release] QCT is exhibiting a rich portfolio of accelerated products and solutions powered by #IntelXeon processors at #SC24, as we continue to empower researchers and scientists with high-performance, cost-efficient infrastructures. Learn more: https://bit.ly/3OgslRi

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What do oxide transistors, ferroelectrics, 2-dimensional channel layers, CFETS, #advancedPackaging, #AI, and tradewinds have in common? They were all topics at the June IEEE 2024 VLSI Conference, which took place in Hawaii. Our own Dean Freeman was there, and in his latest blog post, he reports from the panel discussion with the provocative title: Will AI Bite the Industry that Feeds it? Will it indeed? read on to find out 👉 👉 https://lnkd.in/guP9H_JK

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In the last post I wrote about how the authors of “The RISC-V Reader” posed the BCD (Binary Coded Decimal) operations of the x86 as a mistake of the past. I countered this supposition and argued that it is a useful feature for certain applications. But I didn't want to leave the reader with the impression that I thought that there were no features that I would regard as design mistakes. That is certainly not the case. The 8051 was an early design by Intel and was copied by many other manufacturers. It has features that are truly design mistakes that should never have happened. It is an architecture which should have been left to die an early death but was perpetuated by hardware people who are deficient in their software capabilities. One of its design mistakes is its upward-growing stack. What this does is to reverse the order of the bytes so that they don't appear like they should in memory. They are useless as local variables. Advanced programming languages like C heavily use variables stored in the stack for active temporary storage. But because of the deficiency of the 8051's stack-relative address modes, it is a moot point. It is akin to a blind person finding himself without binoculars when they would be useful for identifying birds for example. The Motorola HC08 has a downward-growing stack and it has good stack relative addressing modes. But even this architecture has a minor design mistake. It uses post-decrement instead of pre-decrement for pushes and pre-increment instead of post-increment for pulls. This flaw was corrected in the HC12. But Motorola decided to keep the flaw in the HC08 to maintain software compatibility. All-in-all, the HC08 is still far superior to the 8051. The x86 got it right when it comes to push and pull stack operations. Intel just used the wrong key word for "pull". RISC-V doesn't have built-in push and pull operations. It is a raw primitive architecture like IBM's mainframes. #Intel8051 #ISA #assembly #programming #computers #microcontrollers

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