Movellus Inc.

WHITEPAPER ALERT: How do you determine the goodness-of-fit for droop mitigation solutions? Our recently released whitepaper will walk you through a quantitative analysis for voltage droop and mitigation techniques! Some of the highlights include: ⚡ 𝗖𝗼𝗺𝗽𝗿𝗲𝗵𝗲𝗻𝘀𝗶𝘃𝗲 𝗔𝗻𝗮𝗹𝘆𝘀𝗶𝘀 - Detailed examination of voltage droop and its impact on high-performance SoCs, including mitigation techniques and adaptive clocking solutions. ⚡ 𝗜𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗲𝗱 𝗦𝗼𝗹𝘂𝘁𝗶𝗼𝗻𝘀 - Introduction to an integrated (detection + mitigation) solution to maximize power savings and functional reliability in the face of unpredictable droops. ⚡𝗧𝘂𝗻𝗶𝗻𝗴 𝗠𝗶𝘁𝗶𝗴𝗮𝘁𝗶𝗼𝗻 𝗦𝗼𝗹𝘂𝘁𝗶𝗼𝗻𝘀 - Understanding what contributes to your total adaptation time and how to minimize this key metric ⚡𝗛𝗲𝗮𝗱 𝘁𝗼 𝗛𝗲𝗮𝗱 𝗖𝗼𝗺𝗽𝗮𝗿𝗶𝘀𝗼𝗻𝘀 - Let's quantify how an integrated solution stacks up against traditional clock muxing! Download our whitepaper today to learn more about vorlage droop characterization and analyzing mitigation techniques! Link -> https://lnkd.in/gwjGKfcq

⚡Not all droop response systems are created the same!   This short clip explores the key differences between a clock mux (two PLLs connected via a mux) and an adaptive clock. When it comes to handling rapid voltage droop rates, a clock mux system often falls short—either offering minimal Vmin savings or simply responding too slowly to mitigate the impact. In contrast, the adaptive clock consistently delivers greater savings across all droop rate scenarios, thanks to its superior response speed.   In our recently released white-paper we go through a more in-depth analysis of how design teams can compare droop mitigation systems.   In the below example, we simulated the Vmin savings for a 100mV droop with a multiple droop rates. The system uses an integrated droop response system that operates at 2GHz and features an adaptation time of 4 clock cycles. Download our whitepaper here -> https://lnkd.in/gwjGKfcq

⚡ How does droop rate affect your potential Vmin savings when mitigating droop? Droop rate is how fast your droop is occurring. For those who still remember differential calculus it is the derivative of your voltage with respect to time. As droop rates increase, your ability to mitigate in time decreases, which also leads to less and less Vmin savings. In our recently released white-paper we go through a more in-depth analysis of how design teams can estimate their Vmin savings with adaptive clock systems, while accounting for differing droop rates. In the below example, we simulated the Vmin savings for a 100mV droop with a multiple droop rates. The system uses an integrated droop response system that operates at 2GHz and features an adaptation time of 4 clock cycles. Download our whitepaper here -> https://lnkd.in/gwjGKfcq

How much Vmin can you expect to save with an adaptive clock system? The answer isn't as clear-cut as you may expect. Your Vmin savings are a function of the maximum expected droop, the detection threshold, and the worst-case scenario for your droop. In our recently released white-paper we go through a more in-depth analysis of how design teams can estimate their Vmin savings with adaptive clock systems. In the below example, we simulated the Vmin savings for a 100mV droop with a 6mV/ns droop rate. The system uses an integrated droop response system that operates at 2GHz and features an adaptation time of 4 clock cycles. To learn more and see our step-by-step analysis download the whitepaper here -> https://lnkd.in/gwjGKfcq

Catch up on your semiconductor + system power news: ⚡ High-Reliability Power Crucial for Aerospace, Defense and Space Missions - Maurizio Di Paolo Emilio: https://lnkd.in/eKjFSJg4 ⚡Power Budgets Optimized By Managing Glitch Power - Adam Kovac: https://lnkd.in/gMrkKVPq ⚡Solving AI’s Power Struggle - Mark Rushworth: https://lnkd.in/ebhnydAm As SoC power demands increase in the AI era, let Movellus Inc. be your trusted partner to help reduce your next chip's power consumption with performance and energy-optimized IP solutions. https://www.movellus.com/

🔎Managing kW Power Budgets   Scroll through to hear from some of the industry's best and brightest!   The experts: Joseph C. Davis, Senior Director for Calibre interfaces and EM/IR product management at Design with Calibre Mo Faisal, CEO of Movellus Inc. Trey Roessig, CTO and Senior Vice President of Engineering at Empower Semiconductor Hans Yeager, Senior Principal Engineer, Architecture, at Tenstorrent       Original Article by Semiconductor Engineering by Ed Sperling –> https://lnkd.in/gGReSfvw   To help reduce your SoC's power through foundational IP solutions, check out our website here -> (https://www.movellus.com/)

Catch up on your semiconductor + system power news: ⚡ Hidden Cost of AI: Why Data Center Strategies Need a Rethink - Lauro Rizzatti: https://lnkd.in/eusfzwXR ⚡ NXP Semiconductors launches first MCX microcontrollers with dual power domains - Nick Flaherty: https://lnkd.in/gAmXNcQF ⚡ Reversible Computing Escapes the Lab in 2025 (Vaire Computing) - Dina Genkina: https://lnkd.in/gDQG6U-C As SoC power demands increase in the AI era, let Movellus Inc. be your trusted partner to help reduce your next chip's power consumption with performance and energy-optimized IP solutions. https://www.movellus.com/

🔎 SLM Evolves Into Critical Aspect Of Chip Design And Operation Scroll through to hear from some of the industry's best and brightest! The experts: Lee Vick, Vice President of Strategic Marketing at Movellus Inc. Randy Fish, Product Line Director for SLM at Synopsys Inc Adam Cron, Distinguished Architect at Synopsys Inc Marc Hutner, Director of Product Management for Tessent Yield Learning at Siemens Digital Industries Software Original Article by Semiconductor Engineering by Ann Mutschler –> https://lnkd.in/gX8Wmnst To help reduce your SoC's power through foundational IP solutions, check out our website here -> (https://lnkd.in/g-WMx_X4)

What chip industry engineers watched in 2024. Hot topics included challenges involving chiplets and heterogeneous integration, AI, data management, MCUs, power semis, software-defined vehicles, sensors, adaptive test, yield tracking, safety monitoring, security, and much more. https://lnkd.in/gP8s4mty #semiconductor #RISCV #DRAM #chiplets #semiconductormanufacturing #AI #automotive #EDA Onto Innovation Keith Best Rambus Steven Woo Winbond Andy Nightingale Arteris Frank Schirrmeister Dick Otte Promex Industries Inc. Eli Roth Teradyne Bryan Schackmuth Nordson Corporation Yang Zhang Andy Heinig Fraunhofer IIS, Division Engineering of Adaptive Systems EAS Roland Jancke Nir Sever proteanTecs PDF Solutions Sivaram Trikutam Infineon Technologies Kevin Brand Synopsys Inc Jayson Bethurem Pulin Desai Cadence Kajetan Nürnberger Guy Ben-Haim🎗 Lee Vick Movellus Inc. Alphawave Semi Archana P Cheruliyil Ashish Darbari Axiomise Letizia Giuliano Ronen Perets Siemens Digital Industries Software

Happy Holidays from Movellus to our customers, partners, and supporters! May your season be filled with comfort, joy, and relaxation!