Representing Instructions in Computer
Last Updated :
14 Mar, 2022
An instruction is an order given to a computer processor by a computer program. Each instruction is a sequence of 0s and 1s. They help in describing the physical operation that the computer should perform. Registers are used for storing the data temporarily and performing the operations that the instruction is aimed at.
Description of ARM Fields:
1. Opcode represents the basic operation of the instruction.
2. Rd represents the register destination operand. The result obtained by performing the operation is stored here.
3. Rn represents the first register source operand.
4. Operand2 represents the second source operand (In case of Data Processing Instructions) and offset(address) in case of Data Transfer Instructions.
5. I represent the Immediate, if
- I = 0, then the second source operand registers.
- I = 1,then second source operand is 12 bit immediate(constant).
6. S represents the Set condition code. It is related to conditional branch instruction.
7. The condition represents the Condition. It is related to conditional branch instruction.
8. F represents the Instruction format, if
- F = 0,then it is Data Processing Format
- F = 1,then it is Data Transfer Format
Different Instruction Formats:
1. Data Processing(DP): Includes general arithmetic operations (Ex: Addition, Subtraction, etc.)
| Condition | F | I | Opcode | S | Rn | Rd | Operand2 |
|---|
| 4 bits | 2 bits | 1 bit | 4 bits | 1 bit | 4 bits | 4 bits | 12 bits |
2. Data Transfer(DT): Includes data transfer operations (Ex: Load, Store)
| Condition | F | Opcode | Rn | Rd | Offset2 |
|---|
| 4 bits | 2 bits | 6 bits | 4 bits | 4 bits | 12 bits |
Representation of ARM Field:
Each instruction is 32 bits long. In the figure, the above information is represented in a tabulated format. Here,
Reg refers to the Register numbers between 0 and 15.
Constant: 12 bit constant
Address: 12 bit address
ARM Instruction Encoding is also represented in the below figure.
ARM Instruction Encoding:
| Instruction | Format | Condition | F | I | Opcode | S | Rn | Rd | Operand |
|---|
| ADD | DP | 14 | 0 | 0 | 4 | 0 | Register | Register | Register |
|---|
| SUB | DP | 14 | 0 | 0 | 2 | 0 | Register | Register | Register |
|---|
| ADD WITH IMMEDIATE | DP | 14 | 0 | 1 | 4 | 0 | Register | Register | Constant |
|---|
| LDR(LOAD) | DT | 14 | 1 | - | 24 | - | Register | Register | Address |
|---|
| STR(STORE) | DT | 14 | 1 | - | 25 | - | Register | Register | Address |
|---|
Each of the segments of instruction is called a field. Opcode containing 4 bits(for DP) and 6 bits(for DT) indicates the type of operation that the instruction performs. (Ex: Addition, Subtraction, etc. in case of DP and Load or Store in case of DT). Rn containing 4 bits gives the number of the register which is the first source operand. Operand2 containing 12 bits gives the other source operand for the operation that is to be performed by the instruction. Rd containing 4 bits gives the number of the register that is to receive the sum and is called as Destination Register.
Note :
- Even though multiple formats(DP and DT) complicate the hardware, the complexity is reduced by keeping the formats similar.
- The first two fields and last three fields of the two formats are the same sizes and four of them have the same names.
- The length of the opcode field in DT format(6 bits) is equal to the sum of the lengths of three fields of DP format(Opcode, S, I: 4+1+1 bits).
- In the figures, the numbers are represented in a decimal number system but they are actually stored as binaries(0 and 1)
Translating ARM Instructions into Machine Instructions :
Example 1: Consider this ARM instruction.
ADD r3,r1,r2
| Condition | F | I | Opcode | S | Rn | Rd | Operand2 |
|---|
| 14 | 0 | 0 | 4 | 0 | 1 | 3 | 2 |
The values of the fields are represented in the table. The numbers are stored in the form of binary.
I = 0 because here the second source operand is a register but not a constant.
Opcode = 4(0100) corresponds to the Addition operation.
Since, it is an arithmetic operation, F = 0.
The value in,
Rn field is 1. (Because r1 is the first source operand)
Operand2 is 2. (Because r2 is the second source operand)
Rd field is 3. (Because r3 is destination register in which result achieved by
adding contents of registers r1 and r2 is stored)
Example 2: Consider this ARM instruction.
SUB r2,r2,#6
| Condition | F | I | Opcode | S | Rn | Rd | Operand2 |
|---|
| 14 | 0 | 1 | 2 | 0 | 2 | 2 | 6 |
I = 1 because here the second source operand is a constant.
Opcode = 2(0010) corresponds to the Subtraction operation.
Since, it is an arithmetic operation, F = 0.
The value in,
Rn field is 2. (Because r2 is first source operand)
Operand2 is 6. (Constant)
Rd field is 2. (Because r2 is destination register in which result achieved by subtracting 6 from r2 is stored).
Example-3: Consider this ARM Instruction.
LDR r4,[r3,#24]
| Condition | F | Opcode | Rn | Rd | Offset2 |
|---|
| 14 | 1 | 24 | 3 | 4 | 24 |
Opcode = 24(011000) corresponds to the Load operation.
Since,it is a data transfer operation, F = 1.
The value in,
Rn field is 3. (Because r3 is first source operand).
Address is 32. (offset to be added to the base register r3)
Rd field is 4.
In this way, ARM assembly instructions are translated into machine instructions.
Instruction Completeness:
The set of instructions are said to be complete if the instructions have each of the below categories:
- Arithmetic, logic, and shift instructions.
- Data Transfer Instructions (i.e., Load and Store).
- I/O instructions.
- Program control instructions include the instructions that check status conditions with the help of flags.
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