GATE | CS | 2011 | Digital Logic | Sequential Circuit | Question 50

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Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. 

 

If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?

000

001

010

011

This question is part of this quiz :

GATE CS 2011,Digital Logic & Number representation,Sequential circuits,Digital Logic GATE CS PYQ Quiz,Sequential circuit PYQ QUIZ GATE CS
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GATE
Computer Organization and Architecture
Digital Logic
GATE CS
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