Design Asynchronous Up/Down Counter

Asynchronous counters are a kind of digital circuitry which may count either upwards or downwards while not adhering to the timing pulses from an oscillator. As a result, state transitions are determined by extra inputs rather than by time frames at fixed intervals. The flip-flops and logic gates are utilized for designing the asynchronous counter in order to get counting sequence control based on input signals. With such characteristics they offer flexibility in counting and can be applied in many situations that demands an asynchronous action.

In asynchronous/ripple counter output of the first flip-flop is provided as the clock to the second flip-flop i.e., flip-flop(FF) are not clocked simultaneously. Circuit is simpler, but speed is slow.

Asynchronous Counter Basics

When -ve edge clock pulse is applied and input is given to FF logic 1 then the output state of FF will toggle for every falling edge. The output frequency will be f/2 (If f is clock frequency). It is known as binary or mod -2 counter or bit ripple counter.
It has 2 unique output states (0 and 1).

When two FFs are connected in series and output of one FF is act as clock for 2nd FF. So the state of 2nd FF will change only when output and 1st FF is logic 1 and falling edge occur. The output frequency of Q₁ is f/4(if f is clock frequency). 
It can generate 4 different unique states. This is known as divide by 4 circuits or mod 4 ripple counter. 
Here output is taken as Q₁(MSB) Q₀(LSB).

By this, we can conclude that-

If there are n FFs then the output frequency will be divide by 2ⁿ. ​Also generate 2n unique states.

So the frequency division basically forms counting state. 
Here we are seeing that the output of the 1st FF act as clock for 2nd FF. Suppose the FF takes 30ns for generating output(i.e. propagation delay because of gates). Therefore, the output of second FF will be obtained after 60 ns. So the propagation delay is ripples through the FFs and becomes more when the number of FFs increases.
Therefore, asynchronous counter are too slow for generating big counting.  

• As we know, when the output state (i.e. Q) of previous FF is feed as clock to next FF then the counter will perform up counting as you seen above(i.e. 0 1 2 3). 
  After 4th -ve edge clock pulse the sequence will repeat.
• When the complemented output state (i.e. Q') of previous FF is feed as clock to next FF then the counter will perform down counting as you seen below(i.e. 3 2 1 0). 
  After 4th -ve edge clock pulse the sequence will repeat.

Now we are designing Up/Down counter.
Up/Down counter is the combination of both the counters in which we can perform up or down counting by changing the Mode control input. 

Design of 3 Bit Asynchronous UP/DOWN Counter 

It is used more than separate up or down counter.

1. In this a mode control input (say M) is used for selecting up and down mode.
2. A combinational circuit is required between each pair of flip-flop to decide whether to do up or do down counting.

For n = 3, i.e for 3 bit counter -
Maximum count = 2ⁿ -1 and number of states are 2ⁿ.

Steps involve in design are :
Step 1 : Decision for Mode control input -

When M = 0, then Y= Q, therefore it will perform Up counting (As discussed above).
When M = 1, then Y= Q' therefore it will perform Down counting (As discussed above).
Combinational circuit is required for deciding mode control(i.e., whether counter will perform Up counting or Down counting).
So the all possible combinations are -

K-map for finding output Y that will be given as clock to next FF.

Step 2 : Insertion of Combinational logic between every pair of FFs -

Timing diagram

Initially Q₃ = 0, Q₂ = 0, Q₁ = 0.

Case 1 - When M=0, then M' =1.
Put this in Y= M'Q + MQ'= Q So Q is acting as clock for next FFs. 
Therefore, the counter will act as Up counter.

Explanation of Up counter

• The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
• The 2nd FF input is connected to Q₁.Therefore it changes its state when Q₁= 1 and there is falling edge of clock.
• Similarly, 3rd FF is connected to Q₂. Therefore, it changes its state when Q₂= 1 and there is falling edge of clock.
• By this we can generate counting states of Up counter.
• After every 8th falling edge the counter is again reaching to state 0 0 0.
  Therefore, it is also known as divide by 8 circuit or mod 8 counter.

Case 2 - When M=1, then M' =0.
Put this in Y= M'Q + MQ'= Q'.  So Q' is acting as clock for next FFs. 
Therefore, the counter will act as Down counter.

Explanation of Down counter

• The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
• The 2nd FF input is connected to Q'₁.Therefore it changes its state when Q'₁= 1 and there is falling edge of clock.
• Similarly, 3rd FF is connected to Q'₂. Therefore, it changes its state when Q'₂= 1 and there is falling edge of clock.
• By this we can generate counting states of down counter.
• After every 8th falling edge the counter is again reaching to state 0 0 0.
• Therefore, it is also known as divide by 8 circuit or mod 8 counter.

Up and Down Falling State

In the asynchronous up/down counter design, up and down falling states are called specific conditions that cause the counter to either increment (up) or decrement (down).

Up Falling State : This state results when the counter goes up, incremented by one count. In an asynchronous counter, the up falling state is normally caused by some specific input signal or by some certain condition. On the occurrence of this kind of condition, the counter proceeds to the next count.

Down Falling State : The down falling state is when the counter decrements, going down by one count. Much like the up falling state, this state also starts with some input signal or condition which will prompt the counter to advance to the previous count.

​These states are very critical to an asynchronous up/down counter since it decides on the direction in which the counter progresses. If these states have been effectively controlled, then according to the input signals, the counter will count up or down accurately.

Advantages

Designing an up/down counter asynchronously has several benefits.

• Flexibility : An up/down counter that is not synchronous provides flexible counting up and down. This flexibility can be important for cases when the counting direction must change dynamically based on some conditions or inputs.
• Simplicity : Compared to synchronized counters, asynchronous counters are relatively easy to build. They operate without using clock signals, enabling them to be simpler than others in certain cases.
• ​Speed : Asynchronous counters can count at hh speeds because they do not depend on the clock signal for counting.
• ​Simple Installation : Timing-critical system whose requirements suit the functioning of an asynchronous counter can find it easy to incorporate such devices.
• ​Decreased Energy Usage : The asynchronous counters have a lower power consumption than synchronous ones because in their operation they do not need a continuous clocking signal. This can be advantageous for applications that are sensitive to power supply.

Generally speaking, some of the advantages associated with designing an asynchronous Up/Down counter include flexibility, simplicity, speed, lower power consumption and easy integration in different digital circuits.

Disadvantages

Here's what you should know about designing asynchronous Up/Down counters.

• Timing analysis can be complex : With more complex timing compared to synchronous circuits; these make them harder to analyze and debug. Timing will always be an important aspect at the design stage since hazards or race conditions may read more.
• ​Glitches possibility : Glitches are temporary and unwanted output signals that occur as a result of changes in signal propagation delays in all sorts of digital circuits but are usually very common among asynchronous types. Hence managing these types of signals becomes one major problem when designing asynchronies.
• ​Propagation delay variations : In the case of an asynchronous counter delay variability can be rather uneven signal travelling times in different routes that cause timing uncertainties or possible unreliability. Thus, proper synchronization and timing constraints must be ensured.
• Limited scalability : Synchronously, this kind of design could have limitations in terms of scalability and complexity. As a result, building large and intricate circuits using asynchronous counters becomes much more difficult because there are additional design considerations to be considered.
• Increased Complexity of Design : Certain aspects of asynchronous clocks are simple given their higher design complexities like the ability to maintain proper timing, signal integrity among others. Non synchronous circuit design is complicated than any other circuit and this calls for a well thought out design by an expert who understands what he is doing.

Asynchronous UP/DOWN counters have some disadvantages that show they are difficult to design and need careful consideration before going ahead with their actual implementation. Hence such challenges emphasize the need for thorough testing and careful design practices so as to prevent possible problems at the end.

Conclusion

The circuit implementation is the last step in designing an asynchronous up/down counter according to required features. The control inputs should allow for both counting modes (up or down) by the counter. Using flip-flops and suitable logic gates, the counter can be designed so that it changes its state with respect to clock signal and control inputs.