Booth's Algorithm

Last Updated : 23 Sep, 2025

Booth’s algorithm is a method for multiplying signed binary numbers in two’s complement representation. It improves efficiency by minimizing the number of required arithmetic operations.

The method works by examining pairs of adjacent bits in the multiplier and deciding whether to add, subtract, or do nothing with the multiplicand, followed by an arithmetic shift.
This approach simplifies handling of consecutive sequences of 1s or 0s, making multiplication faster and more effective than the standard binary method.

Hardware Implementation of Booth's Algorithm

The hardware implementation of the booth algorithm requires the register configuration shown in the figure below:

Booth's Algorithm Flowchart

We name the registers as A, B and Q, AC, BR and QR, respectively. Qn designates the least significant bit of the multiplier in the register QR. An extra flip-flop Qn+1is appended to QR to facilitate a double inspection of the multiplier. The flowchart for the booth algorithm is shown below:

Booth’s Algorithm Steps

Initialize AC = 0, Qn+1 = 0, and set SC = n (number of multiplier bits).
Check the two least significant bits (Qn and Qn+1).
If bits = 10 → Subtract multiplicand (M) from AC (first 1 in a sequence).
If bits = 01 → Add multiplicand (M) to AC (first 0 after ones).
If bits = 00 or 11 → No change in AC (partial product unchanged).
Perform an Arithmetic Shift Right (ashr) on [AC, QR, Qn+1] (sign bit in AC remains).
Decrement sequence counter (SC).
Repeat steps until SC = 0 (n iterations complete).
Handle negative numbers: if multiplicand/multiplier is negative, take its 2’s complement to simplify operations.
Final product obtained in [AC, QR] after all steps.

Example - A numerical example of booth's algorithm is shown below for n = 4. It shows the step by step multiplication of -5 and -7.

BR = -5 = 1011,
BR' = 0100, <-- 1's Complement (change the values 0 to 1 and 1 to 0)
BR'+1 = 0101 <-- 2's Complement (add 1 to the Binary value obtained after 1's complement)
QR = -7 = 1001 <-- 2's Complement of 0111 (7 = 0111 in Binary)
The explanation of first step is as follows: Qn+1
AC = 0000, QR = 1001, Qn+1 = 0, SC = 4
Qn Qn+1 = 10
So, we do AC + (BR)'+1, which gives AC = 0101
On right shifting AC and QR, we get
AC = 0010, QR = 1100 and Qn+1 = 1

Product is calculated as follows:

Product = AC QR
Product = 0010 0011 = 35

Application of Booth's Algorithm

Processors and ALUs: Booth’s Algorithm enables efficient signed multiplication inside microchips and processors by reducing the number of additions/subtractions, leading to faster arithmetic logic unit (ALU) operations essential for computing, graphics, and cryptography.
Digital Signal Processing (DSP): It accelerates multiplication tasks in DSP applications such as filtering and convolution for real-time audio, video, and signal processing.
Hardware Accelerators: Specialized hardware for image processing, neural networks, and AI use Booth’s Algorithm to speed up multiplication operations.
Cryptography: Cryptographic operations involving large-number exponentiation benefit from faster multiplication with Booth’s Algorithm, improving encryption and signature processes.
High-Performance Computing (HPC): Large-scale scientific and mathematical computations employ Booth’s Algorithm for optimized multiplication, enhancing overall system performance.
Embedded Systems: Resource-limited embedded devices improve multiplication efficiency and power consumption by using Booth’s Algorithm.
Network Packet Processing: Booth’s Algorithm helps efficient multiplication in network devices for operations on packet headers and payloads.

Basically, Corner's Calculation finds its application any place productive paired duplication is required, particularly in situations where speed, power proficiency, and equipment streamlining are significant elements.

Best Case and Worst Case : Best case is when there is a large block of consecutive 1's and 0's in the multipliers, so that there is minimum number of logical operations taking place, as in addition and subtraction. Worst case is when there are pairs of alternate 0's and 1's, either 01 or 10 in the multipliers, so that maximum number of additions and subtractions are required. GATE Practice Questions -