NEAT chipset
The NEAT chipset (the acronym standing for "New Enhanced AT") was a 3-chip chipset for IBM PC compatible computers. It was developed by Chips and Technologies.
History
The NEAT chipset descended from the first chipset that C&T had developed for IBM XT-compatible systems, which was based around the 82C100 "XT controller" chip. This chip incorporated the functionality of what had been, until its invention, discrete TTL chips on the XT's mainboard, namely:
the 8284 clock generator
the 8288 bus controller
the 8254 Programmable Interval Timer
the 8255 parallel I/O interface
the 8259 Programmable Interrupt Controller
the 8237 DMA controller
The central chip of the NEAT chipset was C&T's 82C206 chip, introduced by C&T in 1986. This chip, like its predecessor the 82C100, provided equivalent functionality to the TTL chips on the PC/AT's mainboard, namely:
the 82284 clock generator
the 82288 bus controller
the 8254 Programmable Interval Timer
the two 8259 Programmable Interrupt Controllers
the two 8237 DMA controllers