Vineesh V S

UVM SEQUENCER UVM Sequencer acts as a mediator between Sequence & Driver. It sends the transaction to the driver. The driver then converts this transaction into the pin wiggles to drive the DUT. Let's deep dive into this interesting component - Sequencer. What we will learn? - Purpose of Sequencer - Sequencer class hierarchy - Sequencer methods - Flow of transaction from sequence to driver - Steps to code a sequencer - Sequencer code - Sequencer handles: m_sequencer, p_sequencer Here is the diagram I created to represent the class hierarchy of UVM Sequencer Detailed Video on UVM Sequencer - Link in COMMENT #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #tcl #scipting #puzzles #problemsolving #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial #memories #memory #register #ram #rom #cache

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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A newspaper clipping that brings back memories of Texas Instruments Educators' Conference held in 2013 at Nimhans Convention Center. The highlight of the conference was the exhibition of projects which were carried out by students across India, who had enrolled in the TI Analog Design Contest. After a modest beginning with ten institutions and 20 projects, year after year, we saw the number of submissions growing at a rate higher than Moore's law! Executing the contest was a massive effort. It included distribution of electronic components to the participants, receiving periodic updates on the progress of the projects, finding help for students who were facing difficulties, arranging the exhibition, having the contests judged and declaring the prizes in the Educators' Conference. We tried some interesting ideas in the 2013 conference. As part of the inauguration, we invited students of IISc who worked with Prof Jamadagni to enact small technoskits to bring out the innovation in the projects. Back in 2013, when IoT was still a new idea, a project was carried out by Prof Jamadagni's students, based on the idea of the Infinite Coffee Cup by Gene Frantz. This project was demo-enacted on the stage. The infinite coffee cup has built in electronics to sense when the cup is empty and signals to the waiter for a refill. The conference also had paper presentation sessions where the demoed projects were presented as papers . We brought out the conference proceedings as a book which published by Chitkara University thanks to help from Prof Rajnish Sharma. We had invited Prof Dhananjay Gadre to make a special inaugural lamp for the inauguration. Steve Lyle and Brad Ruziska from TI Dallas and Bobby Mitra and Sanjay Bhan from TI India inaugurated the conference by lighting an electronic lamp with a remote controller. Prof Gadre went on to create multiple versions of the inaugural lamp with more technology integration. My former colleagues Sagar Juneja and Vaibhav Agarwal were helping me in organising the conference. My former colleague Narahari helped in getting press coverage for the conference. I have not mentioned the names of several colleagues from TI and many University Professors who played a role in the success of the conference. #texasinstruments #education #embeddedsystems #iot #contest #conference #university

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Recently I took up the R&D activity of Mode Merge technology.    Since it was only an evaluation my Lead suggested to take an IP which has been taped out.   I took SERDES 64Gbps chip. I started my Mode merging journey by manually adding all the necessary inputs. We had 2 Func modes both high speed and low speed which I wanted to merge into Single mode. Once I generated Merged SDC and ran STA to my surprise I saw timing was 100% correlated with original run. But when I saw the analysis coverage report it showed 100% untested, since it was a tapeout database both global timing reports were clean. Once I opened the merged SDC We saw some case analysis missing.   Upon investigation I see 2 more issues in the EDA tools that the Analog library that I took for reading had 5 modes ( 2 func + 3 scan ) even after giving func modes for merging I see the Merged Scenario is enabling all the modes due to which wrong Library setup time arc is being picked up, - for time being I manually added set_disable_timing to block scan related arcs to get picked by EDA tools.    In my evaluation I am able to achieve Timing correlation when I merge 2 func modes into 1 func mode.   Now I wanted to enable Mode merge technology in SERDES 112Gbps which was a production chip. My strategy was simple I wanted to merge 2 func modes ( high speed+low speed) into 1 mode and 3 scan modes ( at_speed, shift, capture) into 1 mode. Imagine our signoff strategy is every mode takes 10 scenarios ( 4 setup corners + 6 hold corners ). The target was to reduce 50 Scenarios to 20 Scenarios.   When I enable ECO tool report generation inside STA flow the runs are getting crashed. The main culprit was the set_sense command which gets dumped inside Merged SDC. To avoid tool crashes I tried to experiment with latest Tool version, However STA runtime is huge how are we going to reduce STA runtime? We came up with one more variable that can reduce set_sense arc size collection this helped us in dumping more set_sense commands due to which the number of lines increased in the file which is fine because STA tool has a multi threading feature to take care of.   We are able to achieve Merged STA Runtime on par with original SDC run and ECO tool runtime reduced 50% which is expected since reading 20 timing window files is more faster than reading 50 timing window files. Overall Disk space savings per Run was 50%. Mode merge technology helped us reduce 50 scenarios to just 20 scenarios.    Real time deployment took me 4 months of Hard Work and long hours of debugging helped us improve the Productivity of STA engineers.   Happy Learning.. 😊 #onemarvell#vlsi#sta#learnings

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#fundamentalseries UVM Monitor Classes 7. uvm_monitor * Observes DUT signals and converts them into transactions. * Sends transactions to other components like scoreboards and coverage collectors. * Passive component, does not drive signals. Environment Classes 8. uvm_env * Container class for grouping related UVM components (e.g., agents, scoreboards). * Typically represents a complete verification environment for a specific DUT. Agent Classes 9. uvm_agent * Groups related driver, sequencer, and monitor components. * Can be active (contains a driver and sequencer) or passive (contains only a monitor). Reporting Classes 10. uvm_report_object * Provides reporting utilities for printing messages, warnings, and errors. * Base class for components that need reporting capabilities. 11. uvm_report_server * Centralized reporting mechanism. * Collects and processes messages from uvm_report_object instances. Scoreboard and Analysis Classes 12. uvm_scoreboard * Analyzes DUT outputs and compares them with expected results. * Receives transactions from monitors via analysis ports. 13. uvm_analysis_port * Used for broadcasting transactions to one or more analysis components. * Example: uvm_analysis_port #(T)where T is the transaction type. 14. uvm_analysis_imp * Implements the analysis export interface. * Used to connect analysis ports to scoreboards or other analysis components. #uvm #uvmmethodology #fundamentalseries #uvmconcepts #uvmsyntax #verification #testbenches #verificationengineer #training #mirafratechnologies

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Will I be able to learn anything in VLSI if I finish my second year Isn't it too early ? For all those who ask the answer is the video shared here created by second year graduate student Rajat Maurya an intern at VLSI EXPERT Let's recapitulate your fundamentals from industry point of view on "Synopsys Tools" "If it's never too late t to follow your dream Then it's also not very early to start following your dreams" Start early Get ahead of your time & rest will follow #hspice #simulation

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Why does someone need to visit an offline training centre for embedded system training ? I am not sure which is the best course because this year six students joined Embedkari who had already done training from various institutes. Many students are looking for jobs even after one year. One should select any learning option based on the following factors : 1: Time budget: If you are capable , will you be able to finish the course ahead of schedule and focus on applying for a job? If the course material is not available in advance, you can't. 2: Total cost : It includes the following a: Training cost + GST - Generally around 65k b: Living cost - 1Lakh because most of the students spend min 9 months c: Travel cost - Depends on your native place d: Career path cost - You will lose almost 1yr in training and finding a job. That can be considered 3lakh. If you get stuck in the wrong job such as lab assistant, servicing, maintenance, testing etc. You may not get a good salary even after switching job. I have seen many professionals getting just 5LPA even after 5yrs. So there you may lose upto 10lakh assuming that 3LPA x5 = 15 LPA after 5 yrs. So one can lose 5 to 10lakh with a simple wrong decision. What is the solution ? Embedded system learning is a combination of proper guidance and self efforts. Create your own setup at home. It should include following: a: ARM based evaluation board with few low cost modules. b: low cost USB analyzer c: Multimeter, breadboard and electronics components d: Good internet connection e: Any online training with a provision of recorded and live sessions for doubt clarification. If you are targeting Embedded hardware design, find an experienced person in the hardware domain. If you are targeting Embedded software, find an experienced person with the software domain. BTW you already found 😊 Answer to How long is an embedded system course and which institute offers it in Hyderabad? by Sanjay Kumar https://lnkd.in/gWr7-E26 #embedded #opentowork #freshers #salarybadhao

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Insightful Expert Talks on VLSI

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How will AI impact and enable the semiconductor industry and what jobs exist in semiconductor industry ? Listen to this brief chat with Data &AI expert Lekhana Reddy on salaries and more.. Where do you see AI impacting the semiconductor industry...would love to hear your thoughts below 👇🏾 https://lnkd.in/gb7rhvFH #semiconductorindustry #semiconductorsalaries #data hashtag #ai hashtag #genai

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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Quantum Computing is an exciting upcoming field in VLSI. Have you wondered what the fuss is about? Well head over to Tutorials at VLSI Design Conference 2025 on 4th and 5th January 2025 at Bangalore and hear it from subject matter experts

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Emulation is an important method for verifying designs at SoCs often with both software and hardware. It can accelerate verification cycle as well. Head over to Gaurav G 's Tutorial at VLSI Design Conference 2025 on 4th-5th Jan 2025. Register Today

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the capacitor makes this circuit a low pass filter, as the author suggested the then reduces noise but even if one doesn't necessarily need a low pass filter, it improves phase margin of the feedback configuration (or is high pass in feedback) - very useful for marginally stable designs

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#SV Constraint Interview questions: 1. Write a constraint for walking 1’s. please find EDA link below: https://lnkd.in/gaTz-nmB 2. Write a constraint to generate multiples of power 2 without using power. please find EDA link below: https://lnkd.in/g7T-sQtF   3. Write a constraint for 32 bit where every randomization would only allow 2 bits to differ from the previous randomization. please find EDA link below: https://lnkd.in/gzrScMzC #dvengineer #semiconductors #semiconductorindustry #semiconductor #electronicsengineering #electricalengineering #ipverification #semiconductorjobs #asicverification #linkedin

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Here is the overview by Harry Foster chief scientist verification Siemens And here is how the growth and need of VLSI engineers in the next few years . His vision talk and the glimpse of the vision on 2030 DVCon India 2024 #DVConIndia2024 Mirafra Technologies #vlsi #verification #asicverification #ece #electronicsandcommunication #electronicsengineer

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🚀 Analog VLSI: The Silent Powerhouse Driving Quantum Computing 🧑‍💻 In the rapidly evolving landscape of Quantum Computing 🌐, where qubits, entanglement, and superposition are the buzzwords, there's an unsung hero that's playing a pivotal role—Analog VLSI. Let's delve into how Analog VLSI is contributing to this cutting-edge technology and why it's indispensable! 🔍 #1️⃣ The Foundation of Precision Quantum computing relies on the manipulation of quantum states, which demands ultra-precise control over signals. 🎛️ Analog VLSI circuits excel in generating and processing continuous signals with high fidelity, enabling the precise control needed to manipulate qubits effectively. Without this precision, the delicate quantum states could easily be disrupted, leading to computational errors. ⚠️ #2️⃣ Bridging the Classical-Quantum Divide One of the challenges in quantum computing is the interface between classical and quantum domains. Analog VLSI provides a seamless bridge 🌉 by enabling efficient data conversion and signal processing. Through high-speed Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), it translates quantum information into classical data formats, allowing for effective monitoring, control, and error correction in quantum systems. 🖥️ #3️⃣ Power Efficiency at Its Best In quantum computing, maintaining qubit coherence requires low temperatures, often near absolute zero ❄️. This poses significant challenges in power management. Analog VLSI circuits are inherently power-efficient, ensuring minimal thermal noise and heat generation. This efficiency is crucial in maintaining the delicate balance required for qubits to function properly over extended periods. 🕒 #4️⃣ Real-Time Signal Processing Quantum computers require real-time signal processing to maintain qubit coherence and perform operations swiftly. Analog VLSI, with its fast response times and low-latency signal processing capabilities ⏱️, is key to ensuring that quantum operations are executed with the speed and accuracy required for practical applications. #5️⃣ Scalability and Integration As quantum computing scales up, the integration of numerous qubits and control circuits becomes complex. Analog VLSI offers high-density integration capabilities, allowing for the compact design of quantum processors. This integration is critical in developing scalable quantum systems that can handle more qubits and deliver higher computational power. 📈 #6️⃣ The Future Outlook The fusion of Analog VLSI with quantum computing technology is paving the way for new frontiers in computing power and efficiency. As we advance toward practical quantum computers, the role of Analog VLSI will only grow more prominent, becoming the backbone that supports the next wave of technological breakthroughs 🌍. Follow Soumick Majumdar for more such technical content. Happy Connecting !!! #QuantumComputing #AnalogVLSI #VLSI #iiitb #gate #gate2025 #innovation

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View my verified achievement from Intel Corporation. Earners of this badge have shown a thorough comprehension and understanding of the lifecycle of AI projects, spanning from fundamental AI concepts and problem definition to creating and implementing value-adding solutions. They have developed proficiencies to increase their success rate in generating high-value AI capabilities to address actual business challenges and have gained actionable insights into the requirements for discovering, exploring, and deploying AI solutions.

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