Ivan Teterevkov

Is C++ the Ultimate Solution for Performance Issues? 🚀 We had a discussion with Barnabás Bágyi at the latest Budapest C++ Meetup (big thanks to Shapr3D for hosting us!). We explored this question and other exciting topics in the world of C++ programming. 🎥 Watch the full interview through the link in the comments below!

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New job opening in Flow. https://lnkd.in/d9v__9HM #LLVM #FlowComputing #PPU #CPUTechnology #CPUtech #ParallelProcessing #SuperCPU #Computing #Seriousperformance #Deeptech

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One of the ways our engineers stay up to date on trends impacting the RF ecosystem is by experimenting with open-source RF modeling and analysis tools. Here, the team uses the Phyton Scipy.signal Toolbox to explore the theory behind poles and zeros and shares their findings. White Paper | RF Tools to Understand How Poles and Zeros Relate to Q Factor https://bit.ly/3xQQSrB

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How is running AI locally different from using the cloud? Listen to this episode of the Technically Speaking podcast with Intel’s Robert Hallock to discover the added benefits of the Intel #AIPC with #IntelCoreUltra. #Intel #IntelvPro https://bit.ly/3yjbQzD

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Exciting news coming from AWS today. F2 is now officially available! The much awaited refresh to the EC2 F1 instances is here. It features: 1️⃣ Bigger FPGAs (Xilinx VU47P) compared to the VU9P available on F1 2️⃣ Ubuntu based AMI compared to the archaic CentOS based AMI for F1 3️⃣ 3rd generation AMD EPYC (Milan) processors that offer up to 3x as many processor cores and up to twice as much system memory compared to F1 VeriFire on F1 was ground breaking. F2 will super-charge VeriFire by enabling: 1️⃣ Verification of Bigger DUTs 2️⃣ Faster FPGA build times 3️⃣ Richer IDEs Read the announcement here: https://lnkd.in/eAET37de #aws #semiconductor #eda

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A good read how to do performance tuning for serving AI models. “To summarize, the performance bottleneck of vLLM is mainly caused by the CPU overhead that blocks the GPU execution.” If we can model everything beforehand, we should not wait for one year to locate the bottleneck. There are still a lot of cross-layer optimization opportunity for AI model serving. With hardware software co-design, there are more rooms for improving efficiency.

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CppCon, The C++ Conference 2024 - Andrei Alexandrescu: "C++ Reflection Is Not Contemplation" youtu.be/H3IdVM4xoCU The C++ community has long been interested in reflection, and we have made significant progress in adding core reflection capabilities to the language. While there is emerging clarity on the querying side of reflection—inspecting existing code artifacts programmatically—there is considerably less consensus on the generative aspect: using reflection insights to emit new code. As a result, current proposals showcase a stark contrast between well-polished reflection query capabilities and limited code generation capabilities. Reifying only the reflection of preexisting code in an Ouroboros manner leads to a curious circularity that hinders the synthesis of new artifacts. This talk provides examples that demonstrate the necessity of generative capabilities in reflection and discusses current and upcoming proposals for generative extensions in C++ reflection. --- Andrei Alexandrescu is a Principal Research Scientist at NVIDIA. He wrote three best-selling books on programming (Modern C++ Design, C++ Coding Standards, and The D Programming Language) and numerous articles and papers on wide-ranging topics from programming to language design to Machine Learning to Natural Language Processing to fundamental algorithms. Andrei holds a PhD in Computer Science from the University of Washington and a BSc in Electrical Engineering from University "Politehnica" Bucharest. He is the Vice President of the D Language Foundation.

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C++Now 2024 - David Sankel: "C++ Should Be C++" youtu.be/qTw0q3WfdNs Between memory safety legislation, calls for C++ successors, and Rust's rising popularity, many conclude C++ is going through rough times. Are complaints of fundamental insecurity, over-complexity, and committee dysfunction overblown? Either way, what's to be done? This talk pragmatically evaluates these developments and makes the case that a focus on improving people's lives is the ideal response. We'll see how this outlook leads to guidance on the libraries we build, the talks we give, the features we add, and how we conceptualize C++'s role in humanity. --- David Sankel is a Principal Scientist in Adobe's Software Technology Lab and an active member of the C++ Standardization Committee. His experience spans microservice architectures, CAD/CAM, computer graphics, visual programming languages, web applications, computer vision, and cryptography. He is a frequent speaker at C++ conferences and specializes in large-scale software engineering and advanced C++ topics. David’s interests include dependently typed languages, semantic domains, EDSLs, and functional reactive programming. He was the project editor of the C++ Reflection TS, is the Executive Director of the Boost Foundation, and an author of several C++ proposals including pattern matching and language variants.

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#LatestNews NXP announced the release of Debian 12 (based on the Linux® kernel 6.6.3) available fo select i.MX series SoCs. This is the first release of a planned semiannual release cadence. Debian is widely used in the embedded market for its stability (based on rigorous testing), its choice and control of a vast software repository with over 30,000 packages, long-term support with security updates for at least 5 years and high customizability for users who require closer control over their system. https://lnkd.in/ggV5Wpt4

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Curious about the future of open computing? Catch Krste Asanovic’s RISC-V State of the Union from the recent RISC-V Summit! Krste dives into adoption trends across markets, ecosystem programs fueling growth, and new extensions advancing AI applications. Watch the full keynote here: https://hubs.la/Q02XY9Tc0

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Krste Asanovic, Chief Architect at RISC-V International and SVP Global Engineering at SiFive, presented the RISC-V State of the Union at RISC-V Summit Europe last month. During his presentation he discussed the current state of RISC-V (spoiler alert: it’s dominating the embedded space), where the architecture is headed, how the adoption of new features will make it more competitive, and more. Watch the presentation at bit.ly/3xMPTZy. 

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Crafting a modern memory store. What makes our cache unique? Part 3 - Topology-Aware Routing Momento Cache incorporates a novel two-tiered architecture in which an independently-scalable gateway layer provides stable low-latency fan out to millions of direct connections. Internal cache topology updates are propagated to the gateway layer, which gracefully re-routes requests as cache nodes change due to scaling redeployments. This intelligent routing also enables AZ-aware connections to improve network costs and latency. Curious? Read more here about our #serverless cache! https://buff.ly/4ghc0bq

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Yield learning and silicon debug have evolved in the era of high complexity SoCs and multi-die systems. Marc Hutner, Director, Product Management, Tessent explains how in this podcast with https://sie.ag/2rknRN. Marc discusses improving Yield Insights through AI, ML and other techniques that can result in millions of dollars of savings. Listen to the full podcast to learn more. https://sie.ag/648qE2 #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

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🚀 Meet the Revolutionaries 🚀 Meet Orr Mazor, our resident Llama whisperer, at #SC24 this week. He's unleashing #LLM Llama 3 on our 7nm NR1 SoCs paired with Qualcomm Cloud AI 100 Ultra cards. Witness him squeeze every ounce of performance out of those AI accelerators, achieving 100% utilization, linear scalability and the lowest cost per token in real-world, high-load AI inference environments. Forget the paltry <30-50% utilization you're stuck with using traditional CPU/NIC architecture. Isn't it time to upgrade your infrastructure to handle #GenAI at scale? #GPUSuperBooster #AIInference #Atlanta #Booth411 #MadScientist

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I wrote an IRQ tracer for the Linux Kernel. I call it "intrace". intrace hooks into the IRQ subsystem of the Linux Kernel and maintains a ring buffer which records necessary information about IRQs. This is then exposed to the userspace thought the debugFS filesystem using the seq_file interface. YES IT WORKS ON SMP SYSTEMS TOO ;) I made a blogpost going into MUCH detail and I am sure you will find it very interesting. => https://lnkd.in/grJc_kTK The source code can be found here: https://lnkd.in/gYrTHQzA Please let me know your suggestions :) Note: This is not part of the mainline. #linux #kernel #computer #science #pesuniversity #c #assembly #embedded #lowlevel #development

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Can AI be used to generate fully functional Linux kernel schedulers in Rust? Here some details of a silly experiment that I've done to showcase the usability of the scx_rustland_core framework and the potential of sched_ext. https://lnkd.in/dGJ9Baur

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Here is a module which extends the 1-to-N Differential Deserializer by packing two consecutive differential N-bit deserialized words into one differential 2N-bit word and extending the bitslip word-alignment logic to support this double-width word. Why do it this way? Because the system this was designed for required a word length that was not supported by either single SERDES blocks, or by width-extension from chaining two SERDES blocks. We can instead just deserialize consecutive half-words and add some half-word permutation logic to allow the half-word-length bitslip to find a correct word alignment (since the offset can now be as much as twice as big as a single SERDES bitslip can adjust for). https://lnkd.in/gm4uMv7K

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