Surinder Sood

the capacitor makes this circuit a low pass filter, as the author suggested the then reduces noise but even if one doesn't necessarily need a low pass filter, it improves phase margin of the feedback configuration (or is high pass in feedback) - very useful for marginally stable designs

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total power will need to include power of digital layers also but PHY power is impressive

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This month's safety matters #EZBlog series is about the requirement for on chip separation to allow a claim of HFT=1. So, if you are looking for a blog on IEC 61508-2:2010 Annex E, this is for you!

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Can integrating application-specific properties into the design of approximate operators (AxOs) enhance their application-level output accuracy beyond that of traditional accurate operators while maintaining comparable PPA metrics? Together with Dr. Siva Satyendra Sahoo and Dr. Akash Kumar , I am excited to announce our recent work "AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design", accepted at https://esweek.org/cases/ 2024, where we explore this question with Spiking Neural Networks (SNNs) as a test case application. Unlike traditional, application-agnostic approaches, we propose an application-driven strategy for AxOs design. By embedding application-specific properties directly into operator modeling, we achieve superior accuracy-PPA tradeoffs, outperforming conventional circuit pruning techniques and even surpassing accurate operators in AI workloads. If you're attending #ESWEEK 2024, join us tomorrow for our presentation.

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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𝙒𝙝𝙖𝙩 𝙞𝙨 𝙮𝙤𝙪𝙧 𝙘𝙪𝙧𝙧𝙚𝙣𝙩 𝙨𝙩𝙖𝙩𝙪𝙨 ? When we talk about embedded systems, machine status registers are fundamental to managing and monitoring the processor’s state during program execution. These registers control critical aspects like the status of operations, privilege levels, and interrupt management. Let’s take a look at how different architectures implement these registers, including Cortex-M, PowerPC and 8051 𝑨𝑹𝑴 (𝑺𝑻𝑴32 𝑪𝒐𝒓𝒕𝒆𝒙-𝑴) - 𝑷𝒓𝒐𝒈𝒓𝒂𝒎 𝑺𝒕𝒂𝒕𝒖𝒔 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 (𝑷𝑺𝑹) N (Negative), Z (Zero), C (Carry), and V (Overflow) flags indicate the results of the latest operations. IPSR (Interrupt Status) and EPSR (Execution Status) help manage interrupt handling and the current execution state. 𝑷𝒐𝒘𝒆𝒓𝑷𝑪 - 𝑴𝒂𝒄𝒉𝒊𝒏𝒆 𝑺𝒕𝒂𝒕𝒆 𝑹𝒆𝒈𝒊𝒔𝒕𝒆𝒓 (𝑴𝑺𝑹) EE (External Interrupt Enable), ME (Machine Check Enable), and RI (Recoverable Interrupt) flags manage interrupts. Privilege Level (PR) and Memory Translation (DR/IR) provide memory access control and protection. 8051 - 𝑷𝒓𝒐𝒈𝒓𝒂𝒎 𝑺𝒕𝒂𝒕𝒖𝒔 𝑾𝒐𝒓𝒅 (𝑷𝑺𝑾) Flags like CY (Carry), AC (Auxiliary Carry), and OV (Overflow) manage arithmetic and logical operation results. The RS1 and RS0 bits select working register banks, allowing flexibility with limited resources. Machine status registers play an essential role in every architecture, regardless of complexity. They enable processors to: - Track the outcomes of operations (arithmetic flags), - Control interrupt behavior, - Manage privilege and memory access levels. Understanding these status registers is key for anyone working in embedded systems ! Which architecture do you work with most often? #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #devicedriver #softwareengineers #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers

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Why does someone need to visit an offline training centre for embedded system training ? I am not sure which is the best course because this year six students joined Embedkari who had already done training from various institutes. Many students are looking for jobs even after one year. One should select any learning option based on the following factors : 1: Time budget: If you are capable , will you be able to finish the course ahead of schedule and focus on applying for a job? If the course material is not available in advance, you can't. 2: Total cost : It includes the following a: Training cost + GST - Generally around 65k b: Living cost - 1Lakh because most of the students spend min 9 months c: Travel cost - Depends on your native place d: Career path cost - You will lose almost 1yr in training and finding a job. That can be considered 3lakh. If you get stuck in the wrong job such as lab assistant, servicing, maintenance, testing etc. You may not get a good salary even after switching job. I have seen many professionals getting just 5LPA even after 5yrs. So there you may lose upto 10lakh assuming that 3LPA x5 = 15 LPA after 5 yrs. So one can lose 5 to 10lakh with a simple wrong decision. What is the solution ? Embedded system learning is a combination of proper guidance and self efforts. Create your own setup at home. It should include following: a: ARM based evaluation board with few low cost modules. b: low cost USB analyzer c: Multimeter, breadboard and electronics components d: Good internet connection e: Any online training with a provision of recorded and live sessions for doubt clarification. If you are targeting Embedded hardware design, find an experienced person in the hardware domain. If you are targeting Embedded software, find an experienced person with the software domain. BTW you already found 😊 Answer to How long is an embedded system course and which institute offers it in Hyderabad? by Sanjay Kumar https://lnkd.in/gWr7-E26 #embedded #opentowork #freshers #salarybadhao

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🚀 Reachability Matrix verification in Network-on-Chip (NoC) 🔍 In a Network-on-Chip (NoC) system, the reachability matrix plays a critical role in defining communication paths between initiators (processors, IP cores) and targets (memory blocks, peripherals). Ensuring its correctness is no small feat. 🔑 The Challenge: Traditional methods like simulation fall short due to their inherent limitations. The complexity of NoC systems makes exhaustive testing impractical, leaving corner cases and rare conditions undetected. ⚙️ The Solution: ✅ Formal and Static Verification: These methods leverage mathematical models to ensure complete coverage, identifying corner cases and rare scenarios that simulations often miss. ✅ Static Signoff for Negative Scenarios: When it comes to verifying what shouldn’t happen—absence cases—static signoff shines. It provides a robust and efficient solution for validating scenarios that traditional methods struggle to address. By adopting these advanced verification techniques, we can ensure the robustness, reliability, and security of complex NoC designs. 💡 #Semiconductors #NetworkOnChip #NoC #Verification #StaticSignoff #FormalVerification #TechInnovation #VLSI #ChipDesign #techtips

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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Will I be able to learn anything in VLSI if I finish my second year Isn't it too early ? For all those who ask the answer is the video shared here created by second year graduate student Rajat Maurya an intern at VLSI EXPERT Let's recapitulate your fundamentals from industry point of view on "Synopsys Tools" "If it's never too late t to follow your dream Then it's also not very early to start following your dreams" Start early Get ahead of your time & rest will follow #hspice #simulation

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Dual-core ARM Cortex-A55 SoM starting from $34 https://lnkd.in/eC4M4PUa

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🚀 Analog VLSI: The Silent Powerhouse Driving Quantum Computing 🧑‍💻 In the rapidly evolving landscape of Quantum Computing 🌐, where qubits, entanglement, and superposition are the buzzwords, there's an unsung hero that's playing a pivotal role—Analog VLSI. Let's delve into how Analog VLSI is contributing to this cutting-edge technology and why it's indispensable! 🔍 #1️⃣ The Foundation of Precision Quantum computing relies on the manipulation of quantum states, which demands ultra-precise control over signals. 🎛️ Analog VLSI circuits excel in generating and processing continuous signals with high fidelity, enabling the precise control needed to manipulate qubits effectively. Without this precision, the delicate quantum states could easily be disrupted, leading to computational errors. ⚠️ #2️⃣ Bridging the Classical-Quantum Divide One of the challenges in quantum computing is the interface between classical and quantum domains. Analog VLSI provides a seamless bridge 🌉 by enabling efficient data conversion and signal processing. Through high-speed Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), it translates quantum information into classical data formats, allowing for effective monitoring, control, and error correction in quantum systems. 🖥️ #3️⃣ Power Efficiency at Its Best In quantum computing, maintaining qubit coherence requires low temperatures, often near absolute zero ❄️. This poses significant challenges in power management. Analog VLSI circuits are inherently power-efficient, ensuring minimal thermal noise and heat generation. This efficiency is crucial in maintaining the delicate balance required for qubits to function properly over extended periods. 🕒 #4️⃣ Real-Time Signal Processing Quantum computers require real-time signal processing to maintain qubit coherence and perform operations swiftly. Analog VLSI, with its fast response times and low-latency signal processing capabilities ⏱️, is key to ensuring that quantum operations are executed with the speed and accuracy required for practical applications. #5️⃣ Scalability and Integration As quantum computing scales up, the integration of numerous qubits and control circuits becomes complex. Analog VLSI offers high-density integration capabilities, allowing for the compact design of quantum processors. This integration is critical in developing scalable quantum systems that can handle more qubits and deliver higher computational power. 📈 #6️⃣ The Future Outlook The fusion of Analog VLSI with quantum computing technology is paving the way for new frontiers in computing power and efficiency. As we advance toward practical quantum computers, the role of Analog VLSI will only grow more prominent, becoming the backbone that supports the next wave of technological breakthroughs 🌍. Follow Soumick Majumdar for more such technical content. Happy Connecting !!! #QuantumComputing #AnalogVLSI #VLSI #iiitb #gate #gate2025 #innovation

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"Chiplets also allow a more flexible design process, enabling the integration of diverse functionalities tailored to specific applications without the need for entirely new chip designs. This flexibility not only reduces development time and costs but also allows for rapid adaptation to evolving technological demands" #semiconductorindustry #chiplet https://lnkd.in/eNwRb52m

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If you are new to Formal Verification, I have 3 articles on systemverilog.io to get you started. 1. 𝗦𝗩𝗔 𝗯𝗮𝘀𝗶𝗰𝘀 - Will build the necessary foundation in SVA, with lots of examples 2. 𝗔 𝗴𝗲𝗻𝘁𝗹𝗲 𝗶𝗻𝘁𝗿𝗼𝗱𝘂𝗰𝘁𝗶𝗼𝗻 𝘁𝗼 𝗙𝗼𝗿𝗺𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 - What is Formal, how is it different from Functional Verification. 3. 𝗔 𝗯𝗹𝘂𝗲𝗽𝗿𝗶𝗻𝘁 𝗳𝗼𝗿 𝗙𝗼𝗿𝗺𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 - End-to-end strategy for someone new to Formal Link: https://lnkd.in/gZTBX46K These were written in 2019, but is still a good place to start. If you have a Synopsys SolvNet account, you can also watch a talk I gave in SNUG 2019. ~~~ Join 1500+ readers in my upcoming newsletter: svio.link/newsletter #verilog #systemverilog #formalverification #asic

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Important methods in Digital Design to optimize Boolean logic in VLSI: To minimise or optimise the Boolean expression of digital logic theorems and laws related to digital logic or K-map, reduction techniques should be adopted as per the need. When the number of variables are four in a sop or pos expression, k map can able to reduce them easily. Even upto five variable and maximum upto 6 variables K map can able to perform quite efficiently. For 5 variable(ABCDE), 32 combinations are possible so two blocks of 4 variable k map are built from (0 to 15) and (16 to 31) and for BCDE, A is taken for both 0 and 1. For 6 variables, 64 combinations are possible, so mapping is done on the basis of four, four variable k map. But beyond that k map technique fails to meet the demand. So here comes the tabulation method. ✓ Tabulation method: Tabulation method in digital logic is necessary to optimise the Boolean expression when the number of variables are large, to be more precise more than six. There are two approaches to this. [1] Variable Entered Mapping (VEM) : VEM is just an extension of the K map approach where a dummy variable is AND ed with each of the minterm or the maxterm of the expression for either assertion or de assertion. That particular dummy variable can be customised according to needs and can be either on and off . Instead of filling up the mappings with corresponding 1's and 0's, VEM contain function of variables. [2] Quine-McCluskey Method: This is a another tabular method and is particularly used when both K map and VEM approach fails. The concept behind Quine-McCluskey method is the combining method approach where AB(bar) + AB = A(B + B(bar)) = A. ✓ Combine all the minterm of the expression into a common group and to first find the prime implicants of the Boolean logic. ✓ Group the prime implications and from that deduce the essential prime implicants by constructing table. ✓ Further from the essential prime implicants reduce it further to another set of essential prime implicants. ✓ Remove the earlier prime implicants where it only remained with the rows and columns with maximum number of minterm and maxterm. Drawbacks of QM method: a] Prime Implicants grows very huge making the solution space quite large. b] Difficult to generate all PI. [3] Petrick's method: It eliminates the problem of QM method, by reducing or eliminating the EPI rows and columns. [4] Espresso: It produces a minimized table which is very useful for Synthesis of the digital logic. ✓ Other important methods: [1] Consensus theorem: It helps to reduce the redundant terms from the Boolean description. [2] Binary Decision Diagram (BDD): Optimises an expression by factoring into either 0/1 and then decide which path to move. [3] Flattening / Factoring: They are the method to optimise an unoptimized RTL description. #vlsi #asic #electronics #electricalengineering

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Explore the top tools for Design for Testability (DFT) in VLSI! Compare Synopsys DFTMAX, Cadence Modus, and Mentor Tessent to enhance your chip testing efficiency and reliability. Read More : https://lnkd.in/gnXZ2QMz #VLSI #DesignForTestability #DFT #Synopsys #Cadence #MentorGraphics #ChipDesign #Semiconductor #TechInnovation #HardwareDesign #EmbeddedSystems #EDA #IntegratedCircuits #CircuitDesign #TechTools #Engineering #TechTrends #Electronics #ChipTesting #TechReview

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MosChip® selects Cadence tools for the design of HPC Processor “AUM” for C-DAC 💡👇 Hyderabad, India -- December 11, 2024 — MosChip® Technologies selects Cadence 5nm EDA tools for the design of the High-Performance Computing (HPC) Processor “AUM” for C-DAC.   MosChip® Technologies is the first fabless semiconductor company publicly traded in India. It has over twenty-five years of experience designing products and SoCs with a vision to be a preferred partner for technology and excellence throughout the SoC development cycle. MosChip® also provides Turnkey ASIC solutions using advanced EDA tools and proven design flow. Supported by a focused team of domain experts, MosChip® delivers technologically advanced solutions for various applications spanning Computing, Automotive, Consumer Electronics, Telecommunications, Industrial Automation, Healthcare, etc.   As India’s demand for data processing and high-speed computing increases, the AUM processor represents a significant milestone in supporting next-generation applications across industries. MosChip® will utilize Cadence EDA tools for linting, verification, synthesis, PNR implementation, timing, and PNR signoff in the AUM processor project. Moreover, MosChip® has used the Cadence tool suite on multiple customer SoCs that progressed to volume production. Read more here: https://lnkd.in/dSZESK5m Mustaqh Ali Shaik Yash Dhagat Srilakshmi Simhadri Jayashankar Narayanankutty

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𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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To cater to the ever increasing demand for high speed computing, ingenuity is needed in the design of digital VLSI circuits (processors) running those high speed applications. We recently explored approximate computing paradigm, wherein power consumption, propagation delay, and switching activity of the circuit has been reduced at an expense of producing some erroneous outputs. Carried out using 32nm CNTFET technology at Chitkara University, our study has been published in the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (Wiley) The paper has been co-authored by Kulbhushan Sharma and  M. Elangovan You can access the paper from this link - https://lnkd.in/euEPuDHi #VLSI #Publication #Research #Computing #ChitkaraU #Wiley Chitkara University

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