Kishan Mushar

In your view, what factors are contributing to the scarcity of FPGA engineers? FPGA engineers require a specialised skill, combining hardware, digital logic, and programming languages like Verilog or VHDL, which can be discouragingly complex and challenging to learn. Many engineering degrees may not even offer extensive coursework specifically focused on FPGA design.  FPGAs are also significantly more expensive than microcontrollers. ASICs are expensive to produce in small quantities but are also more cost-effective than FPGAs when it comes to mass production. Despite this, industries like aerospace, defence, automotive and telecoms have a high demand for FPGA engineers, intensifying competition. What do you think? 🤔 #FPGA #FPGAEngineers #SkillsShortage

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Common Resource Block (CRB) in 5G-NR 1. CRBs are set of RBs which occupy channel bandwidth and they are defined for each subcarrier spacing. 2. CRBs provide the RB numbering throughout the carrier bandwidth while PRBs provide RB numbering within each BWP. 3. They are numbered from 0 in upward direction where CRB 0 is located at lower side of Channel Bandwidth. 4. The CRBs associated with each and every SCS are aligned at Point A  i.e., the center of subcarrier 0 of CRB 0 for each subcarrier spacing coincides with Point A. 5. From figure, the CRB edges for different SCS are not aligned. The CRB edge with SCS = 2∆f is shifted by ∆f kHz as compared to CRB edge with SCS= ∆f. For example, the CRB edge with SCS= 30kHz is shifted by 7.5kHz as compared to CRB edge with SCS= 15kHz. 6. UE determines the position of 'Point A' using ARFCN provided by SIB1 or dedicated signalling from gNB. SIB1 provides the FrequencyInfoDL-SIB parameter including IE "offset to carrier value" specifying the number of RBs between 'Point A' and subcarrier 0 and also IE 'carrierBandwidth' that specifics the number of RBs which are available.  #5g #5gnetwork #5gnr #communication #5gtechnology

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Semiconductors are the backbone of modern technology, but have you heard about VLSI? Prepare to be amazed by the evolution of telecom industry with #TechFacts⚡️ Department of Telecommunications ( DOT ) #didyouknowfacts #facts #semiconductors #vlsi #telecom

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Choosing the best country to settle as an Indian VLSI (Very-Large-Scale Integration) design engineer depends on factors like job market demand, work-life balance, visa policies, cost of living, and long-term career growth. Here's an analysis of the countries you listed: Countries with Strong Semiconductor/VLSI Prospects 1. Spain and Portugal Why? Semiconductor Expansion: Both countries are benefiting from the EU's focus on strengthening the semiconductor supply chain. Work-Life Balance: Exceptional quality of life with moderate working hours. Challenges: Limited English-speaking roles; knowledge of Spanish/Portuguese may be required. 2. Poland and Romania Why? Emerging Tech Hubs: Growth in tech outsourcing, semiconductor R&D, and embedded systems. Cost-Effective: Lower living costs compared to Western Europe. Challenges: Lower salary scales compared to Western European countries. 3. Italy and Greece Why? Academic-Industry Ties: Good opportunities for research-oriented engineers. Lifestyle Appeal: Excellent for work-life balance. Challenges: Limited industrial semiconductor focus; may suit niche roles. 4. UAE Why? Tech Innovation Push: The UAE is investing heavily in technology and AI sectors. Tax-Free Income: High salaries and tax-free earnings are appealing. Challenges: Fewer semiconductor-specific roles; high cost of living. Countries with Growing Potential 5. Thailand and Malaysia Why? Established Manufacturing Base: Both countries are integral to the global semiconductor supply chain. Low Cost of Living: Affordable for Indian engineers. Challenges: Manufacturing-focused roles may dominate over design or R&D. 6. Mexico Why? Proximity to the U.S. Market: Growing demand for skilled engineers due to the North American semiconductor boom. Affordable Lifestyle: Low cost of living. Challenges: Limited advanced design roles; mostly production-oriented jobs. 7. Uruguay Why? Quality of Life: Known for safety and high living standards in Latin America. Challenges: Limited semiconductor industry; more focused on IT and software. Niche Markets with Limited Scope 8. El Salvador, Panama, Costa Rica, Serbia, and Montenegro Why? Smaller Economies: Less focus on high-tech industries. Opportunities: IT outsourcing rather than VLSI design. Challenges: Limited career growth in semiconductor design. Key Recommendations 1. For Immediate Career Growth: Spain, Portugal, Poland, Romania, UAE are the best for VLSI engineers looking for design/R&D roles and a blend of lifestyle and career opportunities. 2. For Manufacturing and Support Roles: Malaysia, Thailand, and Mexico offer better opportunities for production-related roles with future scope in advanced semiconductor processes. 3. For Research and Academic Growth: Italy and Greece may be suitable for research-oriented engineers. 4. Long-Term Viability: Spain, Portugal, UAE, and Poland stand out for future scope, government investment in tech, and global connectivity.

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Hi my people🌷, Keep moving on. Let’s chat something today📝one more interesting topic 📍 Please check ,I mentioned below and read understand,thank you . There are several ways to fix an ASIC-based design. >From easiest to most extreme: RTL Fix -> Gate Fix -> Metal Fix -> FIB Fix First, let's review fundementals. A standard-cell ASIC consists of at least 2 dozen manufactured layers/masks. Lower layers conists of materialsmaking up the actual CMOS transistors and gates of the design. The upper 3-6 layers are metal layers used ti connect everything together. ASICs, of course, are not intended to be flexible like an FPGA, however, important "fixes" can be made during the manufacturing process. The progression of possible fixes in the manufacturing life cycle is as listed above. An RTL fix means you change the Verilog/VHDL code and you resynthesize. This usually implies a new Plance&Route. RTL fixes would also imply new masks, etc. etc. In other words - start from scratch. A Gate Fix means that a select number of gates and their interconections may be added or subtracted from the design (netlist). This avoids resynthesis. Gate fixes preserve the previous synthesis effort and involve manually editing a gate-level netlist - adding gates, removing gates, etc. Gate level fixes affect ALL layers of the chip and all masks. A Metal Fix means that only the upper metal interconnect layers are affected. Connections may be broken or made, but new cells may not be added. A Sewing Kit is a means of adding a new gate into the design while only affecting the metal layers. Sewing Kits are typically added into the initial design either at the RTL level or during synthesis by the customer and are part of the netlist. A Metal Fix affects only the top layers of the wafers and does not affect the "base" layers. Sewing Kits are modules that contain an unused mix of gates, flip-flops or any other cells considered potentially useful for an unforseen metal fix. A Sewing Kit may be specified in RTL by instantiating the literal cells from the vendor library. The cells in the kit are usually connected such that each cell's output is unconnected and the inputs are tied to ground. Clocks and resets may be wired into the larger design's signals, or not. A FIB Fix is only performed on a completed chip. FIB is a somewhat exotic technology where a particle beam is able to make and break connections on a completed die. FIB fixes are done on individual chips and would only be done as a last resort to repair an otherwise defective prototype chip. Masks are not affected since it is the final chip that is intrusively repaired. Clearly, these sorts of fixes are tricky and risky. They are available to the ASIC developer, but must be negotiated and coordinated with the foundry. ASIC designers who have been through enough of these fixes appreciate the value of adding test and fault- tolerant design features into the RTL code so that Software Fixes can correct mior silicon problems.

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UVM SEQUENCER UVM Sequencer acts as a mediator between Sequence & Driver. It sends the transaction to the driver. The driver then converts this transaction into the pin wiggles to drive the DUT. Let's deep dive into this interesting component - Sequencer. What we will learn? - Purpose of Sequencer - Sequencer class hierarchy - Sequencer methods - Flow of transaction from sequence to driver - Steps to code a sequencer - Sequencer code - Sequencer handles: m_sequencer, p_sequencer Here is the diagram I created to represent the class hierarchy of UVM Sequencer Detailed Video on UVM Sequencer - Link in COMMENT #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #tcl #scipting #puzzles #problemsolving #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial #memories #memory #register #ram #rom #cache

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1.This Verilog module FA_case implements a 1-bit full adder. It has three inputs (a, b, c) and two outputs (sum, cout). 2.Module Definition: Declares inputs and outputs, with sum and cout as reg type. 3.Always Block: Triggers on changes to any input (a, b, c). Case Statement: Evaluates a 3-bit vector {a, b, c} representing all possible input combinations 4.Each Line: Corresponds to a specific combination of the inputs (a, b, and c), and defines the resulting values of sum and cout. 3'b000: When all inputs are 0 (a=0, b=0, c=0), both sum and cout are set to 0. 3'b001: When a=0, b=0, c=1, the sum is 1, and carry-out (cout) is 0. 3'b010: When a=0, b=1, c=0, the sum is 1, and carry-out is 0. 3'b011: When a=0, b=1, c=1, the sum is 0, and carry-out is 1. 3'b100: When a=1, b=0, c=0, the sum is 1, and carry-out is 0. 3'b101: When a=1, b=0, c=1, the sum is 0, and carry-out is 1. 3'b110: When a=1, b=1, c=0, the sum is 0, and carry-out is 1. 3'b111: When a=1, b=1, c=1, the sum is 1, and carry-out is 1. 5.Summary -The module is a 1-bit full adder that computes the sum and carry-out based on the three input bits. -The case statement provides a straightforward way to define the output for each possible combination of the inputs. -The always block ensures that the output is updated whenever the inputs change, and the case statement efficiently encodes the logic of the full adder.

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The Significance of VLSI in Advancing Career Opportunities and its Technological Impact. #WhyVLSI #CareerGrowth #TechCareers #Semiconductors #Innovation #AI #5G #IoT #ChipDesign #VerificationEngineer #SystemVerilog

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Advanced High-performance Bus (AHB) is a part of AMBA bus which is used as a communication and Interface protocol in Subsystem / IP / SOC based design and is essential for both RTL and ASIC Verification in VLSI. Below are the important concepts that are needed to learn AHB protocol. [1] Role of Arbiter and Decoder in AMBA AHB. [2] Different arbitration mechanism in AHB. (Ex: Round Robin, Priority access, etc) [3] Multi Master - Slave interconnection scheme in AHB. [4] Difference between Incrementing and Wrapping Burst. [5] What is an address and data phase in AHB. Why data phase can accomodate multiple cycle. Waveform for Basic transfer operation. [6] Total maximum No. Of wait states can be inserted as a delay in AHB cycles. [7] Difference between Sequential and Non-seqiential transfer. Role of Idle cycle. [8] What is the role of default Slave and when it is needed. [9] How the address decoding operation execute in AHB. [10] Early Burst termination mechanism. [11] What are the different response mechanism scheme in AHB. Role of HreadyIn and HreadyOut signal. [12] What is the difference between Split and Retry operation. Why OK response execute in single cycle and Error, Retry and Split need at least two cycles. [13] How the arbiter decide which Master to grant access to the bus. Role of HGRANTx and HBUSREQx signal. [14] Role of default master and why it only execute Idle cycle. [15] Locked transfer operation in AHB. [16] How to prevent deadlock when multiple master try to access the bus. How AHB handles multiple split transfer. [17] Operation of AHB bridge in AHB to APB interface. [18] Limit of boundary access in AHB. What will happen if the slave try to access out of bound address range. [19] No. of channels in AHB and it's pipelined architecture. [20] What is the role of dummy master in AHB. #vlsi #asic #semiconductorindustry #electricalengineering

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Ever wonder how 2 state variable will work in Systemverilog? Find out more on my new blog where I have explained with it's usage in associative array. #verification #ASIC #Systemverilog #UVM

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Project 13: Serial Adder (108 Advanced RTL Projects) 1. Project Overview A serial adder processes binary numbers sequentially, performing bit-by-bit addition over multiple clock cycles. 2. Teammates Gati Goyal Ayush Jain NIKUNJ AGRAWAL 3. Low Area & Power Efficiency Consumes fewer hardware resources (gates, flip-flops) compared to parallel adders, making it ideal for low-power designs. 4. Operation Utilizes a full adder with shift registers and a clock signal to sequentially add operands and propagate carry. 5. SystemVerilog Design RTL design implemented in SystemVerilog, leveraging modular components like full adders and registers. 6. Test Bench Testbench validates the serial adder's functionality with various binary inputs and tests for correct carry propagation. 7. Simulation Results Simulation waveforms demonstrate bitwise addition and the sequential carry-forward mechanism. 8. Synthesis The synthesized design shows optimized resource usage, highlighting minimal gate count and power consumption. 9. Applications Commonly used in embedded systems, signal processing units, and low-cost IoT devices. 10. Industry Use Widely adopted by companies such as Intel Corporation , Arm , Texas Instruments Silicon Labs , and AMD for power-sensitive designs. Tags: #SerialAdder #RTLDesign #SystemVerilog #DigitalLogic #LowPowerDesign #EmbeddedSystems #VLSIDesign #FPGA #Synthesis

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🚨 **Ensuring Proper PG Bias Off State in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, managing power gating bias off states correctly is crucial for optimizing power efficiency and ensuring reliable operation. The Synopsys VSLP tool is essential for detecting and resolving pg_biasoff_state issues. Here’s a concise overview of what pg_biasoff_state entails and its importance. ### **What is PG Bias Off State?** **PG Bias Off State** refers to the condition where biasing of power-gated domains is correctly turned off to save power. Ensuring this state is properly managed is vital for achieving power efficiency and maintaining functional integrity. ### **Importance of Addressing PG Bias Off State Violations** - **Power Efficiency**: Proper management of bias off states reduces power consumption, enhancing the overall energy efficiency of the IC. - **Functional Integrity**: Correctly handling bias off states ensures that power-gated domains are fully powered down without unintended leakage or partial functionality. - **Reliability**: Ensuring proper bias off states enhances the reliability and stability of the IC, preventing potential issues from partial biasing. - **Thermal Management**: Reducing power consumption through effective bias off state management helps in thermal management by lowering heat generation. ### **Detecting and Addressing PG Bias Off State Violations with Synopsys VSLP** The Synopsys VSLP tool provides advanced capabilities to detect and rectify issues related to PG bias off states, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Bias Off State Checks**: Analyze the design to ensure that power-gated domains are correctly biased off when required. - **State Transition Verification**: Verify that transitions to and from the bias off state are managed correctly, preventing unintended power leakage. #### **2. Dynamic Simulation** - **Power Down Scenarios**: Simulate various power down scenarios to assess the impact on system functionality and ensure proper bias off state management. - **Power Consumption Analysis**: Monitor power consumption during bias off states to identify any irregularities or inefficiencies. ### **Best Practices for Managing PG Bias Off States** 1. **Clear Power Management Strategy**: Develop a clear strategy for managing bias off states, including guidelines for when and how components should enter and exit these states. 2. **Continuous Validation**: Regularly validate bias off state implementation throughout the design process to catch and address issues early. 3. **Collaborative Approach**: Work closely with power management and system design teams to ensure that bias off states are integrated seamlessly into the overall design. 4. **Advanced Tool Utilization**: Use advanced tools like Synopsys VSLP for automated detection and correction of bias off state issues. #workwithuppula #synopsys #VSLPTool #powerefficiency Thanks, Vishnu

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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Important Content!!!!! These days training institutions are stealing money in the name of training. Training feedback needs to be given by candidates not by placements officials or mentors. Training quality can be judged by how well the candidates are trained. Nowadays few #training institutions are only focusing on money/ strength. IndiaTaxGov.com / #incometax dept should have eye on the training institutions where their is lot of loop hole in paying tax by institutions.

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What are the reasons for routing congestion 📢 Inefficient floorplan 📢 Macro placement or macro channels is not proper. 📢 Placement blockages not given 📢 No Macro to Macro channel space given. 📢 High cell density 📢 High local utilization 📢 High number of complex cells like AOI/OAI cells which has more pin count are placed together. 📢 Placement of std cells near macros 📢 Logic optimization is not properly done. 📢 Pin density is more on edge of block 📢 Buffers added too many while optimization 📢 IO ports are crisscrossed, it needs to be properly aligned in order. What are the different methods to reduce congestion. 📢 Review the floorplan/macro placements according to the block size and 📢 port placement. 📢 Add proper placement blockages in channels and around the macro boundaries. 📢 Reduce the local density using the percentage utilization/density screens. 📢 Cell padding is applied for high pin density cells, like AOI/OAI. 📢 Check and reorder scan chain if needed. 📢 Run the congestion driven placement with high effort. 📢 Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

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© Topic: VLSI Glossary © ⏭ ⏭⏭ ⏭ GrowVLSI ⏮ ⏮ ⏮ ⏮ (A-S posted few days back) T: TB- Tera Byte TN- Technology Node TG- Transmission Gate TTL- Transistor Transistor Logic TT- Typical Typical (TT is the corner where both NMOS and PMOS are typical, when this corner is enabled the processing parameters may be typical/hard because corner analysis does include all the process variation possiblities ) TCL- Tool Command Language TF- Technology File 😍It is an ASCII file in which information about all the metal layers, vias and their design rules are available😍 TLU+: Timing Library Update/Table LookUp 😍 TLU+ file provides RC parasitic information of metal per unit length which is used to calculate the net delay. All TLU+ file data is completely technology dependent and is given by Foundry 😍 TNS- Total Negative Slack U: ULVT- Ultra Low Threshold Voltage UPF- Unified Power Format ULSI- Ultra Large Scale Integration V: VLSI- Very Large Scale Integration VHDL- VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language W: WNS- Worst Negative Slack X, Y, Z: Didnot find anything Content Writer B. Lokeshwar

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Are you an Electronics or Electrical Engineering graduate ready to dive into the exciting world of VLSI? 🚀 Future-proof your career with Futurewiz's Super 50 VLSI Training Program 🌐 ✅ 100% Industry Ready Trainings ✅ Real-Time Project Experience ✅ 100% Placement Guaranteed Don't miss your #CareerInTech part of this transformative journey. Apply Now #Futurewiz #FuturewizCourses #VLSI #Placement #VLSTraining #Electronics #ComputerScience #ComputerScienceEngineering #ComputerSoftware #ElectronicsEngineer #ElectronicsIndustry #CareerinVLSI #careerintech

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Hi Everyone Today we will discuss about Crosstalk Crosstalk: It occurs when there are parallel running nets of same metal layer for long distance. When a signal on a net switches very fast then, the wires in its surroundings tends to switch too and their logical values or transition can be affected. This is called cross talk. It causes noise bumps in non-switching nets and advancing/delaying of transition in switching nets. They are 2 different types of crosstalk 1)Crosstalk Noise: -->It is undesired change in the logical values of victim due to switching in the input of aggressor. -->If one net is switching and other is at a constant value, the switching net may cause voltage spikes on other net.This is called as cross talk noise. -->Cross talk noise is evolving as a key source in degrading performance and reliability of high speed integrated circuits. 2)Crosstalk Delay: When there is some delay or advancement in output transition of victim due to input transition of aggressor, it is called as cross talk delay. It occurs when some transition is happening in both the nets.Cross talk delay depends on the switching direction of the aggressor and victim nets. # If input transitions in aggressor and victim occur in same direction then output transition of victim becomes faster and it is earlier. It may cause hold violations. ## If input transitions occur in opposite directions then output transition of victim becomes slower and it is delayed, which may cause setup violations. • Ways to fix Crosstalk effects -->Assign Non default routing (NDR) rules by Increasing the spacing. -->Insert buffer to split the long nets -->Jump to different metal layers -->Shielding - Ground lines run in between the signal lines so that they form coupling capacitance with ground. -->By up-sizing the driver of victim net or downsizing driver of aggressor net. Thank you Everyone #Happy learning #Physical Design #VLSI #Semiconductor.

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