Kazu Itoi

High density system in package (SiP) is required for system miniaturization in various applications and each high-density semiconductor packaging technology has capable area like 3D integration, high power, low cost etc. This presentation describes various types of high density semiconductor packaging technologies and introduces embedded die technology, Chip-stack WABE Package®, which multiple dies are embedded vertically in polyimide film. This embedded die technology is comprised of thin die… さらに表示

High density system in package (SiP) is required for system miniaturization in various applications and each high-density semiconductor packaging technology has capable area like 3D integration, high power, low cost etc. This presentation describes various types of high density semiconductor packaging technologies and introduces embedded die technology, Chip-stack WABE Package®, which multiple dies are embedded vertically in polyimide film. This embedded die technology is comprised of thin die embedded in polyimide film with connecting conductive paste and has been developed to enable ultra-miniaturization SiP form factor for small level system and low to middle power application. 部分表示

We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring… さらに表示

We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides.
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We have developed a polyimide-based embedded wiring board in which multiple dies are embedded in a 3D stacked configuration based on WABE (Wafer and Board level device Embedded) technology.
Test vehicle included two embedding dies (3 mm x 3 mm x 0.085 mm) with 7 PI/9 wiring layers. The measured thickness of fabricated vehicle was 0.45 mm which was about the same size as that of a conventional non-embedded build-up substrate. Electrical connections between circuit layers including embedded… さらに表示

We have developed a polyimide-based embedded wiring board in which multiple dies are embedded in a 3D stacked configuration based on WABE (Wafer and Board level device Embedded) technology.
Test vehicle included two embedding dies (3 mm x 3 mm x 0.085 mm) with 7 PI/9 wiring layers. The measured thickness of fabricated vehicle was 0.45 mm which was about the same size as that of a conventional non-embedded build-up substrate. Electrical connections between circuit layers including embedded dies were established by a reliable conductive paste. We have performed moisture soak reflow tests on test vehicles and verified that they endured the conditions compliant with JEDEC level2.
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We have developed active and passive devices embedded multilayer board utilizing our
laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit-formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures highly reliable connection… さらに表示

We have developed active and passive devices embedded multilayer board utilizing our
laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit-formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures highly reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor and/or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between devices and board’s circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded board of its kind in the world.

To confirm the reliability of the embedded board, we have performed several reliability tests on the
WLCSP and resistors embedded TEG board of 4 polyimide / 5 copper circuit layers. As
environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a
thermal cycling test (-55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/ high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the embedded portion. The embedded device never broke and the circuit resistance change was also within acceptable range. 部分表示

A novel flex board based fan-out embedded die and system in package technology has been developed. The features of this package include a flex based multilayer substrate utilizing polyimide film to reduce its total thickness, thin embedded die with redistributed layers for pitch conversion by wafer level chip scale packaging processing and a cost-effective co-lamination process with conductive paste filled vias for z-axis electrical interlayer connections.

The fabricated package is… さらに表示

A novel flex board based fan-out embedded die and system in package technology has been developed. The features of this package include a flex based multilayer substrate utilizing polyimide film to reduce its total thickness, thin embedded die with redistributed layers for pitch conversion by wafer level chip scale packaging processing and a cost-effective co-lamination process with conductive paste filled vias for z-axis electrical interlayer connections.

The fabricated package is composed of 4 polyimide flex layers and 1 embedded die having a 100 I/O, 4 mm x 4 mm daisy chain device. The body profile without bump and footprint includes a 220 m package thickness and 5.25 x 5.25 mm body size, respectively. The resultant multilayer flex package showed high reliability.

Thermal performance of the package was simulated with and without thermal vias on the backside of the embedded die for both face up and face down configurations of the die. The simulated results showed that the thermal via on the backside of the embedded die reduced thermal resistance parameters, ja and jc. The face down embedded die with thermal via was particularly effective in reducing jc to 5.9 oC/W, compared to that without thermal via was 20.4 oC/W. This technology provides ultra-thin Fan-Out embedded packages with cost-effective panel sized fabrication processing.
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On-chip high-Q spiral inductors on Si substrate embedded in WLP have been fabricated. These inductors consisted of a thick Cu electroplated rerouting to reduce electrical resistance and a thick resin layer to separate the inductors typically 20 m from Si substrate. The inductance L of 5.0 and 4.9 nH with the quality factor Q of 28.4 and 42.9 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz on the Si substrate, which had a resistivity of 4-6, 1kcm, respectively. The RSi in the… さらに表示

On-chip high-Q spiral inductors on Si substrate embedded in WLP have been fabricated. These inductors consisted of a thick Cu electroplated rerouting to reduce electrical resistance and a thick resin layer to separate the inductors typically 20 m from Si substrate. The inductance L of 5.0 and 4.9 nH with the quality factor Q of 28.4 and 42.9 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz on the Si substrate, which had a resistivity of 4-6, 1kcm, respectively. The RSi in the assignment parameters for lumped RLC equivalent circuit by ADS denoted more than 5 k in a 3.5 turn. In addition, the measured results of Q, L and fres corresponded well with the simulated values by HFSS and Sonnet. This technology realizes embedded high quality inductors in WLP. 部分表示

On-chip Cu solenoid inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by double Cu electroplating layers and separated more than 10 m from Si substrate by thick resin layer. The self-resonance frequency of 17.7 and 19.3 GHz with peak Q factor of 18.0 and 20.0 were obtained for a 5 turn solenoid inductor in  of 4, 1kcm, respec-tively. This technology realizes that high performance inductors are embedded in wafer-level chip-scale packag-es.

On-chip high-Q spiral inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by a thick Cu electroplated rerouting and separated more than 10 m from Si substrate by thick resin layer. The inductance L of 5.2 and 4.9 nH with the quality factor Q of 18.1 and 27.5 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz in  of 4-6, 1k ohm-cm, respectively. This technology is favorable for Si RF application to minimize the stray inductance… さらに表示

On-chip high-Q spiral inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by a thick Cu electroplated rerouting and separated more than 10 m from Si substrate by thick resin layer. The inductance L of 5.2 and 4.9 nH with the quality factor Q of 18.1 and 27.5 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz in  of 4-6, 1k ohm-cm, respectively. This technology is favorable for Si RF application to minimize the stray inductance from wire-bonding and reducing circuit resistance. 部分表示

This paper describes the fabrication process of a Si interposer with high-density electrical feedthroughs that go through a Si substrate. We made the interposer by using Deep-RIE (Reactive Ion Etching), PE-CVD (Plasma-Enhanced Chemical Vapour Deposition) and Molten Metal Suction Method (MMSM). In addition, we evaluated the structural and electrical properties of this interposer. This Si interposer has excellent performances concerning the insulation voltage, the electrical resistivity of the… さらに表示

This paper describes the fabrication process of a Si interposer with high-density electrical feedthroughs that go through a Si substrate. We made the interposer by using Deep-RIE (Reactive Ion Etching), PE-CVD (Plasma-Enhanced Chemical Vapour Deposition) and Molten Metal Suction Method (MMSM). In addition, we evaluated the structural and electrical properties of this interposer. This Si interposer has excellent performances concerning the insulation voltage, the electrical resistivity of the individual feedthroughs and the leakage between the front and the back of the interposer. This interposer can be applied in Si terraces for MOEMS device, Si Optical Bench (SiOB), 3D-stacked IC packaging or other System In Package (SIP) to minimize the size and reduce the cost. 部分表示

Two key technologies, Optical Excitation Electro-polishing Method (OEEM) and Molten Metal Suctioned Method (MMSM), to form metal filled Through-Holes (THs) from the front to the back of thick Si wafer (~500μm), have been developed. The OEEM is a wet-etching technology that has the capability to produce very high aspect ratio (more than 100) THs in Si substrate. The MMSM is a technique of filling the TH with molten metal in vacuum. The conductive interconnections formed by the both technologies… さらに表示

Two key technologies, Optical Excitation Electro-polishing Method (OEEM) and Molten Metal Suctioned Method (MMSM), to form metal filled Through-Holes (THs) from the front to the back of thick Si wafer (~500μm), have been developed. The OEEM is a wet-etching technology that has the capability to produce very high aspect ratio (more than 100) THs in Si substrate. The MMSM is a technique of filling the TH with molten metal in vacuum. The conductive interconnections formed by the both technologies have very good performances of individual insulation (more than 300V dielectric breakdown voltage) and leakage free structure between the front and the back of the substrate. We experimentally made 500THs/cm2 in a thick Si substrate, each of which has an opening 15μm in the diameter and the aspect ratio of 35. These THs were filled with several different kinds of metal after the formation of insulation layers. Both technologies can be applied in Si terraces for MOEMS device, Si Optical Bench (SiOB), 3D-stacked IC packaging or other System In Package (SIP) to minimize the size or the cost. 部分表示