Michele Bologna

1200V 900A Hybrid module. With SiC SBD diode inside，the turn on switching loss is reduced to a very low level.

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<<Within just a week! >> Wafer fabs like Clas-Sic Wafer Fab in the UK are the latest type of customer to see the impact of yieldHUB on their operations. We normally have fabless customers. How do we make such an impact in a new area for us? Imagine removing silos of information across your company. Imagine if your data was suddenly centralized and available and <<all linked up>> in another tab of the browser you are now using? And you could search for anything and see quickly everything that happened with the material and wafers, irrepsective of volume? All setup within a few days? It's hard to get through all the noise to get in front of potential customers. But you have to see it to believe it.

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I really enjoyed this talk with Nitin Dahad of EE Times | Electronic Engineering Times. We walked about the different steps in my career, my management philosophy, and other interesting things. See https://lnkd.in/dAgc_adg

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Teledyne LeCroy PCIe 6.0 M616 Exerciser / Analyzer Demo - Flit mode traffic generation at 64.0 GT/s with PAM-4 signaling. https://lnkd.in/g_GBp-yp

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Part 1: The Hidden Giants of the Semiconductor Industry: OSATs in a Changing Market   Published in 2023, Edward Choi’s book on Outsourced Semiconductor Assembly and Test (OSAT) describes the challenges, competitive landscape, and evolutionary history of these hidden giants that drive much of today’s technological innovation.   The OSAT’s Role in the Semiconductor Market   The global semiconductor market, currently valued at around $600 billion, does not include two major sectors: the foundry market, which stands at nearly $130 billion, and the OSAT market, valued at $50 billion in 2022. OSATs are integral to the semiconductor value chain, specializing in assembly, packaging, and testing of semiconductor chips. While foundries manufacture the chips, OSATs ensure those chips are functional and durable, ready for the integration into electronic devices.   OSATs: The Key to Surviving in a Cyclical Market   Similar to foundries, OSATs must scale to survive in the highly competitive and cyclical semiconductor market. Their long-term success hinges on their ability to handle high-end semiconductors and develop proprietary advanced packaging technologies that can compete with IDMs (Integrated Device Manufacturers). Leading names like ASE (Taiwan), Amkor (USA), JCET (China), and SPIL (Taiwan) have mastered these skills. During an upturn in the semiconductor cycle, having sufficient inventory allows OSATs to quickly fulfill rising demand. However, during a downturn—like in 2022 following the COVID-19 pandemic—large inventory stocks become burdensome, leading to financial strain. Such downturns are often felt late by OSATs due to the inertia of production and demand.   Taiwan: The Global OSAT Powerhouse   According to Choi, a major factor in Taiwan’s dominance is the strong relationship between fabless companies (which design chips but don’t manufacture them) and local foundries, like TSMC, as well as OSATs. Companies such as ASE and SPIL form close alliances with Taiwanese foundries, facilitating a horizontal partnership that enables both foundries and OSATs to serve the same customers. These Taiwanese giants also diversify their portfolios by offering both, high-end and low-end products, helping to mitigate risks. Taiwanese OSATs cater to global customers and have developed their own advanced packaging technologies, allowing them to compete directly with IDMs. #semiconductor #FutureTech #OSAT #AdvancedPackaging

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Personally, High-level synthesis is a great tool to reduce the time to design for FPGA or ASIC, so I decided to learn the concept and knowledge of HLS and HLV. I researched industry and academic HLS tools for a few months and I decided to learn Catapult HLS from Siemens EDA gives free content or On-demand. I think it is a more powerful tool than others because Catapult HLS teams are not only eager to collaborate with big tech such as Google, NVIDIA, and They give free open sources, like AC math, and ML libraries. Those activities and services will occupy HLS software markets in VLSI. Now, let me see what I learned about HLS by doing these labs. To begin with, I learned HLS, and HLV overall flows with Machine learning applications that HLS libs give ML application inferences from open sources. Moreover, Bit accurate is very important to decide on hardware performance for Machine learning or 5G/6G, etc. This lab gave me to learn the concept of bit-accurate types for high-level synthesis and Cataputl HLS gives some AC datatypes. Secondly, object detection with machine learning labs gave me creative ideas to build more efficiently. Normally RTL engineers design the hardware accelators by using RTL. However, RTL codes are more complex in ML applications. Using the HLS can reduce overall the number of codes and reduce time to markets. (HLS to GDS). Thus, I realized that companies will choose these HLS tools to meet customers' needs. All in all, the Catapult Basic C++ and High-Level Synthesis program gave me a great opportunity to learn what is high-level synthesis and how to use Catapult HLS but also give resources about Machine learning training modules by using the cloud-based lab. This is a huge career upgrade opportunity for High-level ASIC designers or High-level verification engineers who work in company or academy areas. Anyway, Thank you so much Siemens EDA for building this step-by-step labs for students. Best regard, JINSUK LEE. #SiemensEDA

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Food for thought given the global shifts and challenges we face within the sector and the expectations that AI could drive better business productivity which is a key ingredient for much needed growth in the economy. https://lnkd.in/euH8dQdu

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TSMC MPW cybershuttle for N2 starting in April 2025 https://lnkd.in/gWYGXHeU this tells that the process is mature and risk production of customers such as Apple is just round the corner

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SK hynix wins large order for #HBM from Broadcom 💡 US #chip firm set to compete with NVIDIA South Korean memory chip giant SK Hynix has won a large order to supply high-bandwidth memory (HBM) to #Broadcom, TheElec has learned. The US #chip giant will procure the #memory #chips from #SKHynix to install on the #AIcomputing chip of a #BigTech company, sources said. SK Hynix is expected to supply the chip in the second half of next year. Broadcom actively approached the South Korean memory chip giant, the largest #HBM supplier in the world, to procure verified HBMs, the sources also said.SK Hynix will now surely adjust its #DRAM production capacity projection as it now suppliers HBM to both Nvidia and Broadcom. It is currently supplies the majority of HBM used by Nvidia for their AI accelerators. The South Korean firm aimed to expand its 1b DRAM, which is used as the core die in its HBM, production capacity to 140,000 to 150,000 300mm wafers next year. But with the new Broadcom deal, this is expected to increase to 160,000 to 170,000 300mm #wafers. Thanks again to Seonhaeng Lee and TheElec for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/et6E4wxF #semiconductorindustry #semiconductormanufacturing #tech #it #ic #computer #datacenter #computer #computing #hpc #chip #server

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ASMPT Ltd Reportedly Provided Demo TC Bonder to Micron Technology for #HBM Production 💡 Driven by #memory giants ramping up high-bandwidth #memory (HBM) production, according to a report from Korean media outlet TheElec, ASMPT, a back-end equipment maker, has supplied a demo thermal compression (TC) bonder for #Micron's HBM production. TC bonders play a pivotal role in HBM production by employing thermal compression to bond and stack #chips on processed wafers, thereby significantly influencing HBM yield. #ASMPT is reportedly collaborating with the #USA memory giant to co-develop a TC bonder for use in #HBM4 production. Notably, ASMPT has supplied TC bonders to SK hynix as well and plans to deliver more units later in the year. Thanks again to TrendForce Corporation for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eUcjevBU #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #chip #ic #icdesign #dram #ai #innovation #southkorea #usa #it

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Licensing customizable multi-process analog IP - Chris Morrison, Director of Product Marketing, Agile Analog For many years analog IP integration has been known to be complex, time-consuming and costly. In this Agile Analog blog post, we outline how licensing our customizable multi-process analog IP can enable chip design engineers to take back control of the work, time and expense involved. There are two key questions that Agile Analog can answer that will help explain this. Why is our customizable analog IP superior to standard off-the-shelf IP? Why is licensing our analog IP solutions better for your business than trying to develop analog IP internally? https://lnkd.in/gaU-M5-g

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Numemory reinvents Optane storage-class #memory 💡 Chinese fabless #semiconductor startup Numemory is developing storage-class memory (SCM) #chips using Optane-like phase change memory and crossbar #technology. Numemory, a business unit of Xincun Technology (#Wuhan), has launched the NM101, a storage-class memory #chip with 10x faster read and write speeds and 5x longer endurance than #NAND #chips. Xincun Technology was established in July 2022 and has developed a 3D selector-only memory (SOM) #technology using phase-change memory and a crossbar structure, which is remarkably similar to Intel Corporation and Micron Technology’s failed Optane #memory technology. Numemory’s website states: “The new memory is a type of SCM (storage-class memory) that can increase #storage capacity, reduce costs, and thus greatly improve the overall performance of the storage system. The new memory is considered to be a next-generation non-volatile storage technology that is very promising for large-scale mass production, and has become a hot topic of international concern in recent years.” Thanks again to Chris Mellor and Blocks and Files for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/emUECvnU #semiconductorindustry #semiconductormanufacturing #technology #ai #tech #innovation #dram #nand #nandflash #flashmemory #server #computer #datacenter #foundry #it #computing #computer #ic

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If you try to be objective. AMD started with Su and Papermaster. They promised ryzen to be on par with lower tier intel. They kept promising and delivering. It is not rocket science, ppl are accustomed to announcements then delays and then barely matching the amd cpu that is at least 9 months old. To the outside the problem is very clear.

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Proud to share that @Lattice Semiconductor introduced the new Lattice Nexus 2 FPGA platform and the first FPGA based in the new platform – Certus-N2, new mid-range FPGA devices based on Lattice Avant, and enhanced capabilities for our application-specific solution stacks and design software tools. Learn more: https://bit.ly/3ONyXad

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Joe RoReg, A principal DV engineer as SiliconHole LTD announced today he was suing Accellera, author and maintainer of UVM for 1M, for "irreparable financial losses and damage to his and his company reputation". According to Joe's attorney his client was misled by UVM's register bit bash sequence assuming that it was, in his customer words "really bashing the hell out of those damn registers". This turned out, according to the plaintiff, to be utterly false. "This, so called bashing is always done in the order in which the registers are arranged in the map, and hence has very slim chance of catching any register aliasing issues. A true bashing would bash the registers in random order, and reduce at list some of this risk". Unfortunately, according to the claim, Joe and SiliconHole found out about that limitation the hard way, when a customer exposed those issues in Silicon. "We lost a big contract and a ton of money, but the worst part was it made us look damn stupid" said Joe in tears. "If this case could save one DV engineer from hearing a customer ask: but didn't you ever %^$&-ing check access to register 5 before register 1? maybe it hadn't been in vain. #uvm #verification

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