Add custom naming to VIO probes #2483
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A design with VIO probes is inspected (through the GUI of the synthesis tool) when programmed on an FPGA. It therefore makes sense to give each individual probe a logical name. The names of in- and output ports should be given as two `Vec`tor of `Strings`, where the length should match the number of probes.
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Clone of #2478. See #2478 (comment).