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-fclash-force-undefined produces invalid values for BitVector with undefined bits. #2360

@lmbollen

Description

@lmbollen

Title says it all I think.

Reproducer:

module Example.Project where

import Clash.Prelude

topEntity ::(BitVector 8)
topEntity = deepErrorX "broken"

compiled with cabal run -- clash --verilog Example.Project -fclash-force-undefined=0, produces:

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.6.4. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module topEntity
    ( // No inputs

      // Outputs
      output wire [7:0] result
    );


  assign result = 8'b'0''0''0''0''0''0''0''0'; // invalid value


endmodule

HDL was generated with 1.6.4, but the problem was encountered with 1.7.0.
Problem also exists for systemverilog and vhdl.

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