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compiled with cabal run -- clash --verilog Example.Project -fclash-force-undefined=0, produces:
/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.** GENERATED BY CLASH 1.6.4. DO NOT MODIFY.*/`timescale 100fs/100fs
moduletopEntity
( // No inputs// Outputsoutputwire [7:0] result
);
assign result =8'b'0''0''0''0''0''0''0''0'; // invalid valueendmodule
HDL was generated with 1.6.4, but the problem was encountered with 1.7.0.
Problem also exists for systemverilog and vhdl.