Uhlig, B. et al. (2018) Challenges and Progress on Carbon Nanotube Integration for BEOL Interconnects. In: 2018 IEEE International Interconnect Technology Conference (IITC), Santa Clara, CA, USA, 4-7 Jun 2018, pp. 16-18. ISBN 9781538643372 (doi: 10.1109/IITC.2018.8430411)
Uhlig, B. et al. (2018) Progress on Carbon Nanotube BEOL Interconnects. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 19-23 Mar 2018, pp. 937-942. ISBN 9783981926309 (doi: 10.23919/DATE.2018.8342144)
Lee, J. et al. (2017) Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, pp. 153-156. (doi: 10.23919/SISPAD.2017.8085287)
Sadi, T., Wang, L. and Asenov, A. (2017) Multi-Scale Electrothermal Simulation and Modelling of Resistive Random Access Memory Devices. In: 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), Bremen, Germany, 21-23 Sept 2016, pp. 33-37. ISBN 9781509007332 (doi: 10.1109/PATMOS.2016.7833422)
Sadi, T., Towie, E., Nedjalkov, M., Riddet, C., Alexander, C., Wang, L., Georgiev, V. , Brown, A., Millar, C. and Asenov, A. (2016) One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors. In: SISPAD 2016: International Conference on Simulation of Semiconductor Processes and Devices, Nuremberg, Germany, 6-8 Sept 2016, pp. 23-26. ISBN 9781509008186 (doi: 10.1109/SISPAD.2016.7605139)
Sadi, T., Wang, L. and Asenov, A. (2016) Advanced Simulation of Resistance Switching in Si-rich Silica RRAM Devices. 2016 IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, 12-13 Jun 2016. ISBN 9781509007264 (doi: 10.1109/SNW.2016.7578049)
Sadi, T., Wang, L., Gao, D., Mehonic, A., Montesi, L., Buckwell, M., Kenyon, A., Shluger, A. and Asenov, A. (2016) Advanced physical modeling of SiOx resistive random access memories. In: International Conference on Simulation of Semiconductor Processes and Devices, Nuremberg, Germany, 06-08 Sep 2016, pp. 149-152. ISBN 9781509008186 (doi: 10.1109/SISPAD.2016.7605169)
Wang, L., Sadi, T., Brown, A.R., Nedjalkov, M., Alexander, C., Cheng, B., Millar, C. and Asenov, A. (2016) Simulation Analysis of the Electro-Thermal Performance of SOI FinFETs. In: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2016), Vienna, Austria, 25-27 Jan 2016, pp. 56-59. ISBN 9781467386098 (doi: 10.1109/ULIS.2016.7440051)
Wang, L., Brown, A. R., Nedjalkov, M., Alexander, C., Cheng, B., Millar, C. and Asenov, A. (2015) Impact of self-heating on the statistical variability in bulk and SOI FinFETs. IEEE Transactions on Electron Devices, 62(7), pp. 2106-2112. (doi: 10.1109/TED.2015.2436351)
Sadi, T., Wang, L., Gerrer, L. and Asenov, A. (2015) Physical Simulation of Si-Based Resistive Random-Access Memory Devices. In: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, USA, 9-11 Sep 2015, pp. 385-388. ISBN 9781467378581 (doi: 10.1109/SISPAD.2015.7292340)
Sadi, T., Wang, L., Gerrer, L., Georgiev, V. and Asenov, A. (2015) Self-consistent physical modeling of SiOx-based RRAM structures. In: International Workshop on Computational Electronics (IWCE), West Lafayette, IN, USA, 2-4 Sep 2015, pp. 1-4. ISBN 978069251523515 (doi: 10.1109/IWCE.2015.7301981)
Wang, L., Sadi, T., Nedjalkov, M., Brown, A.R., Alexander, C., Cheng, B., Millar, C. and Asenov, A. (2015) An Advanced Electro-Thermal Simulation Methodology for Nanoscale Device. In: International Workshop on Computational Electronics (IWCE), West Lafayette, USA, 2-4 Sep 2015, pp. 1-4. (doi: 10.1109/IWCE.2015.7301989)
Wang, X., Reid, D., Wang, L., Burenkov, A., Millar, C., Lorenz, J. and Asenov, A. (2015) Hierarchical Variability-Aware Compact Models of 20nm Bulk CMOS. In: 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington D.C.,USA, 09-11 Sep 2015, pp. 325-328. ISBN 9781467378598
Wang, X., Reid, D., Wang, L., Burenkov, A., Millar, C., Cheng, B., Lange, A., Lorenz, J., Baer, E. and Asenov, A. (2014) Variability-aware compact model strategy for 20-nm bulk MOSFETs. In: 19th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama Japan, 8-11 Sep 2014, pp. 293-296. ISBN 9781479952878
Lorenz, J., Bar, E., Burenkov, A., Evanschitzky, P., Asenov, A. , Wang, L., Wang, X., Brown, A. R., Millar, C. and Reid, D. (2014) Simultaneous simulation of systematic and stochastic process variations. In: Proceedings of the 19th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama Japan, 8-11 Sept. 2014. IEEE, pp. 289-292. ISBN 9781479952878 (doi: 10.1109/SISPAD.2014.6931620)
Wang, L., Brown, A.R., Nedjalkov, M., Alexander, C., Cheng, B., Millar, C. and Asenov, A. (2014) 3D coupled electro-thermal FinFET simulations including the fin shape dependence of the thermal conductivity. In: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014), Yokohama, Japan, 9-11 Sept. 2014, pp. 269-272. (doi: 10.1109/SISPAD.2014.6931615)
Wang, L., Brown, A.R., Nedjalkov, M., Alexander, C., Cheng, B., Millar, C. and Asenov, A. (2014) 3D coupled electro-thermal simulations for SOI FinFET with statistical variations including the fin shape dependence of the thermal conductivity. In: 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014), Guilin, China, 28-31 Oct 2014,
Wang, L., Brown, A., Cheng, B. and Asenov, A. (2014) Simulation of 3D FinFET doping profiles introduced by ion implantation and the impact on device performance. In: The 20th International Conference on Ion Implantation Technology (IIT 2014), Portland, OR, USA, 26 June - 4 July 2014, pp. 1-4. (doi: 10.1109/IIT.2014.6940008)
Wang, L., Brown, A. R., Millar, C., Burenkov, A., Wang, X., Asenov, A. and Lorenz, J. (2014) Simulation for statistical variability in realistic 20nm MOSFET. In: 15th International Conference On Ultimate Integration On Silicon (ULIS2014), Stockholm, Sweden, 7-9 April 2014, pp. 5-8. (doi: 10.1109/ULIS.2014.6813892)
Wang, L., Brown, A. R., Cheng, B. and Asenov, A. (2013) Analytical models for three-dimensional ion implantation profiles in FinFETs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), pp. 2004-2008. (doi: 10.1109/TCAD.2013.2277975)
Wang, J., Wang, L., Li, C. , Cumming, D. and Wasige, E. (2013) Novel resonant tunnelling diode oscillator with high output power. In: UK Semiconductors 2013, Sheffield, UK, 3 - 4 Jul 2013,
Wang, L., Brown, A. R., Cheng, B. and Asenov, A. (2012) Simulation of 3D FinFET doping profiles by ion implantation. In: 19th International Conference on Ion Implantation Technology, Valladolid, Spain, 25-29 June 2012, pp. 217-220. (doi: 10.1063/1.4766527)
Gawthrop, P. and Wang, L. (2011) The system-matched hold and the intermittent control separation principle. International Journal of Control, 84(12), pp. 1965-1974. (doi: 10.1080/00207179.2011.630759)
Wang, L., Figueiredo, J.M.L., Ironside, C.N. and Wasige, E. (2011) DC characterisation of tunnel diodes under stable non-oscillatory circuit conditions. IEEE Transactions on Electron Devices, 58(2), pp. 343-347. (doi: 10.1109/TED.2010.2091507)
Wang, L.D., Ye, P., Zhai, C.R. and Zhang, Y.H. (2008) High Performance Strapdown Inertial Navigation System Algorithms for Space Flight. In: 2008 2nd International Symposium on Systems and Control in Aerospace and Astronautics, Vols 1 and 2. IEEE: New York, pp. 832-836. ISBN 978-1-4244-3908-9
Beeley, J.M., Mills, C., Hammond, P.A., Glidle, A., Cooper, J.M. , Wang, L. and Cumming, D.R.S. (2004) All-digital interface ASIC for a QCM-based electronic nose. Sensors and Actuators B: Chemical, 103(1-2), pp. 31-36. (doi: 10.1016/j.snb.2004.02.059)
Gawthrop, P. and Wang, L. (2002) Transfer function and frequency response estimation using resonant filters. Proceedings of the Institution of Mechanical Engineers Part I: Journal of Systems and Control Engineering, 216(I6), pp. 441-453. (doi: 10.1177/095965180221600601)
![[up]](/https/eprints.gla.ac.uk/style/images/multi_up.png)
Up a level