Tessent
Creating a TDR inside the IJTAG Network using
DftSpecification editing commands.
更新于 2022年8月06日
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摘要
This Support Kitshows how to create a TDR using DftSpecification editing commands.
This is part of the parent Support KitMG619991:Three different methodologies to create a TDR (Test
Data Register) inside the IJTAG Network using the DftSpecification.
By the end of this Support Kit you should be able to do the following:
Create a TDR to control or monitor the PLL instrument signals described above using DftSpecification
editing commands add_config_element and set_config_value
Set up the PLL by programming the TDR through a PDL and an iCall in a pattern set
详细信息
Consider a PLL instrument in a design, for which a Test data register(TDR) needs to be added to:
Program the PLL using the CTRL[7:0] inputs
Reset the PLL using the RESET input
Check the PLL lock on the LOCK output
This TDR is to be accessed through an SRI (Scan Resource Instrument) SIB, since the contents are not to
be disturbed during scan test.
Note that ifa PLL instrument ICL and PDL are read in, as in this test case, set the attribute
tessent_use_in_dft_specification on these PLL DataInPorts and PLL DataOutPorts to false in the ICL.
For example: DataInPort RESET {Attribute tessent_use_in_dft_specification = "false";}
This prevents a TDR for these ports from being automatically inferredto the DftSpecification.
An SRI SIB is added with the create_dft_specification command:
set spec [create_dft_specification -sri_sib_list {sri_tdr_pll} ]
The TDR is added using add_config_element below the SRI SIB created above:
add_config_element
DftSpecification(top,gate)/IjtagNetwork/HostScanInterface(tap)/Tap(main)/HostIjtag(1)/Sib(sri)/Sib(sri_tdr_pll)/Tdr(pll)
Next the DataInPorts and DataOutPorts are added to the TDR:
add_config_element
DftSpecification(top,gate)/IjtagNetwork/HostScanInterface(tap)/Tap(main)/HostIjtag(1)/Sib(sri)/Sib(sri_tdr_pll)/Tdr(pll)/DataInPorts
add_config_element
DftSpecification(top,gate)/IjtagNetwork/HostScanInterface(tap)/Tap(main)/HostIjtag(1)/Sib(sri)/Sib(sri_tdr_pll)/Tdr(pll)/DataOutPorts
Now the connections are made fromthese TDR DataOutPorts tothe PLL CTRL[7:0] and RESET inputs and
to the TDR DataInPortsfromthe PLL LOCK output as follows:
add_config_element
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