davinci_emac--.rar_davinci_emac

/* * DaVinci Ethernet Medium Access Controller * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * --------------------------------------------------------------------------- * History: * 0-5 A number of folks worked on this driver in bits and pieces but the major * contribution came from Suraj Iyer and Anant Gole * 6.0 Anant Gole - rewrote the driver as per Linux conventions * 6.1 Chaithrika U S - added support for Gigabit and RMII features, * PHY layer usage */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/string.h> #include <linux/timer.h> #include <linux/errno.h> #include <linux/in.h> #include <linux/ioport.h> #include <linux/slab.h> #include <linux/mm.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/ethtool.h> #include <linux/highmem.h> #include <linux/proc_fs.h> #include <linux/ctype.h> #include <linux/version.h> #include <linux/spinlock.h> #include <linux/dma-mapping.h> #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/semaphore.h> #include <linux/phy.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/uaccess.h> #include <linux/davinci_emac.h> #include <asm/irq.h> #include <asm/page.h> #include "davinci_cpdma.h" static int debug_level; module_param(debug_level, int, 0); MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); /* Netif debug messages possible */ #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ NETIF_MSG_PROBE | \ NETIF_MSG_LINK | \ NETIF_MSG_TIMER | \ NETIF_MSG_IFDOWN | \ NETIF_MSG_IFUP | \ NETIF_MSG_RX_ERR | \ NETIF_MSG_TX_ERR | \ NETIF_MSG_TX_QUEUED | \ NETIF_MSG_INTR | \ NETIF_MSG_TX_DONE | \ NETIF_MSG_RX_STATUS | \ NETIF_MSG_PKTDATA | \ NETIF_MSG_HW | \ NETIF_MSG_WOL) /* version info */ #define EMAC_MAJOR_VERSION 6 #define EMAC_MINOR_VERSION 1 #define EMAC_MODULE_VERSION "6.1" MODULE_VERSION(EMAC_MODULE_VERSION); static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; /* Configuration items */ #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ #define EMAC_DEF_RX_NUM_DESC (128) #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ /* Buffer descriptor parameters */ #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ /* EMAC register related defines */ #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) #define EMAC_NUM_MULTICAST_BITS (64) #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) #define EMAC_INT_MASK_CLEAR (0xFF) /* RX MBP register bit positions */ #define EMAC_RXMBP_PASSCRC_MASK BIT(30) #define EMAC_RXMBP_QOSEN_MASK BIT(29) #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) #define EMAC_RXMBP_CMFEN_MASK BIT(24) #define EMAC_RXMBP_CSFEN_MASK BIT(23) #define EMAC_RXMBP_CEFEN_MASK BIT(22) #define EMAC_RXMBP_CAFEN_MASK BIT(21) #define EMAC_RXMBP_PROMCH_SHIFT (16) #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) #define EMAC_RXMBP_BROADEN_MASK BIT(13) #define EMAC_RXMBP_BROADCH_SHIFT (8) #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) #define EMAC_RXMBP_MULTIEN_MASK BIT(5) #define EMAC_RXMBP_MULTICH_SHIFT (0) #define EMAC_RXMBP_MULTICH_MASK (0x7) #define EMAC_RXMBP_CHMASK (0x7) /* EMAC register definitions/bit maps used */ # define EMAC_MBP_RXPROMISC (0x00200000) # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) # define EMAC_MBP_RXBCAST (0x00002000) # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) # define EMAC_MBP_RXMCAST (0x00000020) # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) /* EMAC mac_control register */ #define EMAC_MACCONTROL_TXPTYPE BIT(9) #define EMAC_MACCONTROL_TXPACEEN BIT(6) #define EMAC_MACCONTROL_GMIIEN BIT(5) #define EMAC_MACCONTROL_GIGABITEN BIT(7) #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) /* GIGABIT MODE related bits */ #define EMAC_DM646X_MACCONTORL_GIG BIT(7) #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) /* EMAC mac_status register */ #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) /* EMAC RX register masks */ #define EMAC_RX_MAX_LEN_MASK (0xFFFF) #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) /* MAC_IN_VECTOR (0x180) register bit fields */ #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) /** NOTE:: For DM646x the IN_VECTOR has changed */ #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) /* CPPI bit positions */ #define EMAC_CPPI_SOP_BIT BIT(31) #define EMAC_CPPI_EOP_BIT BIT(30) #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) #define EMAC_CPPI_EOQ_BIT BIT(28) #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) #define EMAC_CPPI_PASS_CRC_BIT BIT(26) #define EMAC_RX_BD_BUF_SIZE (0xFFFF) #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) /* Max hardware defines */ #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ /* EMAC Peripheral Device Register Memory Layout structure */ #define EMAC_MACINVECTOR 0x90 #define EMAC_DM646X_MACEOIVECTOR 0x94 #define EMAC_MACINTSTATRAW 0xB0 #define EMAC_MACINTSTATMASKED 0xB4 #define EMAC_MACINTMASKSET 0xB8 #define EMAC_MACINTMASKCLEAR 0xBC #define EMAC_RXMBPENABLE 0x100 #define EMAC_RXUNICASTSET 0x104 #define EMAC_RXUNICASTCLEAR 0x108 #define EMAC_RXMAXLEN 0x10C #define EMAC_RXBUFFEROFFSET 0x110 #define EMAC_RXFILTERLOWTHRESH 0x114 #define EMAC_MACCONTROL 0x160 #define EMAC_MACSTATUS 0x164 #define EMAC_EMCONTROL 0x168 #define EMAC_FIFOCONTROL 0x16C #define EMAC_MACCONFIG 0x170 #define EMAC_SOFTRESET 0x174 #define EMAC_MACSRCADDRLO 0x1D0 #define EMAC_MACSRCADDRHI 0x1D4 #define EMAC_MACHASH1 0x1D8 #define EMAC_MACHASH2 0x1DC #define EMAC_MACADDRLO 0x500 #define EMAC_MACADDRHI 0x504 #define EMAC_MACINDEX 0x508 /*