International Cadence Users Group 2002 Fundamentals of Efficient Synthesizable FSM
Rev 1.2 Design using NC-Verilog and BuildGates
5
design, not the state encodings. This means that if an engineer wants to experiment with different state
encodings, only the parameter values need to be modified while the rest of the Verilog code remains
unchanged.
• Declarations are made for
state and next (next state) after the parameter assignments.
• The sequential always block is coded using nonblocking assignments.
• The combinational always block sensitivity list is sensitive to changes on the
state variable and all of
the inputs referenced in the combinational always block.
• Assignments within the combinational always block are made using Verilog blocking assignments.
• The combinational always block has a default
next state assignment at the top of the always block
(see section 5.3 for details about making default-X assignments).
• Default output assignments are made before coding the
case statement (this eliminates latches and
reduces the amount of code required to code the rest of the outputs in the
case statement and
highlights in the
case statement exactly in which states the individual output(s) change).
• In the states where the output assignment is not the default value assigned at the top of the always
block, the output assignment is only made once for each state.
• There is an
if-statement, an else-if-statement or an else statement for each transition arc in the
FSM state diagram. The number of transition arcs between states in the FSM state diagram should
equal the number of
if-else-type statements in the combinational always block.
• For ease of scanning and debug, all of the
next assignments have been placed in a single column, as
opposed to finding
next assignments following the contour of the RTL code.
5.2 The unfounded fear of transitions to erroneous states
In engineering school, we were all cautioned about "what happens if you FSM gets into an erroneous
state?" In general, this concern is both invalid or poorly developed.
I do not worry about most of my FSM designs going to an erroneous state any more than I worry about any
other register in my design spontaneously changing value. It just does not occur!
There are exceptions, such as satellites (subject to alpha particle bombardment) or medical implants
(subject to radiation and requiring extra robust design), plus other examples. In these situations, one does
have to worry about FSMs going to an erroneous state, but most engineering schools fail to note that
getting back to a known state is typically not good enough! Even though the FSM is now in a known state,
the rest of the hardware is still expecting activity related to another state. It is possible for the design to
lockup waiting for signals that will never arrive because the FSM changed states without resetting the rest
of the design. At the very least, the FSM should transition to an error state that communicates to the rest of
the design that resetting will occur on the next state transition, "get ready!"
5.3 Making default next equal all X's assignment
Placing a default next state assignment on the line immediately following the always block sensitivity list is
a very efficient coding style. This default assignment is updated by next-state assignments inside the case
statement. There are three types of default next-state assignments that are commonly used: (1) next is set to
all X's, (2) next is set to a predetermined recovery state such as IDLE, or (3) next is just set to the value of
the state register.
By making a default next state assignment of X's, pre-synthesis simulation models will cause the state
machine outputs to go unknown if not all state transitions have been explicitly assigned in the case
statement. This is a useful technique to debug state machine designs, plus the X's will be treated as "don't
cares" by the synthesis tool.
Some designs require an assignment to a known state as opposed to assigning X's. Examples include:
satellite applications, medical applications, designs that use the FSM flip-flops as part of a diagnostic scan
